1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef ATH12K_CORE_H 8 #define ATH12K_CORE_H 9 10 #include <linux/types.h> 11 #include <linux/interrupt.h> 12 #include <linux/irq.h> 13 #include <linux/bitfield.h> 14 #include <linux/dmi.h> 15 #include <linux/ctype.h> 16 #include <linux/firmware.h> 17 #include <linux/panic_notifier.h> 18 #include "qmi.h" 19 #include "htc.h" 20 #include "wmi.h" 21 #include "hal.h" 22 #include "dp.h" 23 #include "ce.h" 24 #include "mac.h" 25 #include "hw.h" 26 #include "hal_rx.h" 27 #include "reg.h" 28 #include "dbring.h" 29 #include "fw.h" 30 #include "acpi.h" 31 32 #define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK) 33 34 #define ATH12K_TX_MGMT_NUM_PENDING_MAX 512 35 36 #define ATH12K_TX_MGMT_TARGET_MAX_SUPPORT_WMI 64 37 38 /* Pending management packets threshold for dropping probe responses */ 39 #define ATH12K_PRB_RSP_DROP_THRESHOLD ((ATH12K_TX_MGMT_TARGET_MAX_SUPPORT_WMI * 3) / 4) 40 41 /* SMBIOS type containing Board Data File Name Extension */ 42 #define ATH12K_SMBIOS_BDF_EXT_TYPE 0xF8 43 44 /* SMBIOS type structure length (excluding strings-set) */ 45 #define ATH12K_SMBIOS_BDF_EXT_LENGTH 0x9 46 47 /* The magic used by QCA spec */ 48 #define ATH12K_SMBIOS_BDF_EXT_MAGIC "BDF_" 49 50 #define ATH12K_INVALID_HW_MAC_ID 0xFF 51 #define ATH12K_CONNECTION_LOSS_HZ (3 * HZ) 52 #define ATH12K_RX_RATE_TABLE_NUM 320 53 #define ATH12K_RX_RATE_TABLE_11AX_NUM 576 54 55 #define ATH12K_MON_TIMER_INTERVAL 10 56 #define ATH12K_RESET_TIMEOUT_HZ (20 * HZ) 57 #define ATH12K_RESET_MAX_FAIL_COUNT_FIRST 3 58 #define ATH12K_RESET_MAX_FAIL_COUNT_FINAL 5 59 #define ATH12K_RESET_FAIL_TIMEOUT_HZ (20 * HZ) 60 #define ATH12K_RECONFIGURE_TIMEOUT_HZ (10 * HZ) 61 #define ATH12K_RECOVER_START_TIMEOUT_HZ (20 * HZ) 62 63 enum ath12k_bdf_search { 64 ATH12K_BDF_SEARCH_DEFAULT, 65 ATH12K_BDF_SEARCH_BUS_AND_BOARD, 66 }; 67 68 enum wme_ac { 69 WME_AC_BE, 70 WME_AC_BK, 71 WME_AC_VI, 72 WME_AC_VO, 73 WME_NUM_AC 74 }; 75 76 #define ATH12K_HT_MCS_MAX 7 77 #define ATH12K_VHT_MCS_MAX 9 78 #define ATH12K_HE_MCS_MAX 11 79 80 enum ath12k_crypt_mode { 81 /* Only use hardware crypto engine */ 82 ATH12K_CRYPT_MODE_HW, 83 /* Only use software crypto */ 84 ATH12K_CRYPT_MODE_SW, 85 }; 86 87 static inline enum wme_ac ath12k_tid_to_ac(u32 tid) 88 { 89 return (((tid == 0) || (tid == 3)) ? WME_AC_BE : 90 ((tid == 1) || (tid == 2)) ? WME_AC_BK : 91 ((tid == 4) || (tid == 5)) ? WME_AC_VI : 92 WME_AC_VO); 93 } 94 95 enum ath12k_skb_flags { 96 ATH12K_SKB_HW_80211_ENCAP = BIT(0), 97 ATH12K_SKB_CIPHER_SET = BIT(1), 98 }; 99 100 struct ath12k_skb_cb { 101 dma_addr_t paddr; 102 struct ath12k *ar; 103 struct ieee80211_vif *vif; 104 dma_addr_t paddr_ext_desc; 105 u32 cipher; 106 u8 flags; 107 }; 108 109 struct ath12k_skb_rxcb { 110 dma_addr_t paddr; 111 bool is_first_msdu; 112 bool is_last_msdu; 113 bool is_continuation; 114 bool is_mcbc; 115 bool is_eapol; 116 struct hal_rx_desc *rx_desc; 117 u8 err_rel_src; 118 u8 err_code; 119 u8 mac_id; 120 u8 unmapped; 121 u8 is_frag; 122 u8 tid; 123 u16 peer_id; 124 }; 125 126 enum ath12k_hw_rev { 127 ATH12K_HW_QCN9274_HW10, 128 ATH12K_HW_QCN9274_HW20, 129 ATH12K_HW_WCN7850_HW20 130 }; 131 132 enum ath12k_firmware_mode { 133 /* the default mode, standard 802.11 functionality */ 134 ATH12K_FIRMWARE_MODE_NORMAL, 135 136 /* factory tests etc */ 137 ATH12K_FIRMWARE_MODE_FTM, 138 }; 139 140 #define ATH12K_IRQ_NUM_MAX 57 141 #define ATH12K_EXT_IRQ_NUM_MAX 16 142 143 struct ath12k_ext_irq_grp { 144 struct ath12k_base *ab; 145 u32 irqs[ATH12K_EXT_IRQ_NUM_MAX]; 146 u32 num_irq; 147 u32 grp_id; 148 u64 timestamp; 149 struct napi_struct napi; 150 struct net_device *napi_ndev; 151 }; 152 153 struct ath12k_smbios_bdf { 154 struct dmi_header hdr; 155 u32 padding; 156 u8 bdf_enabled; 157 u8 bdf_ext[]; 158 } __packed; 159 160 #define HEHANDLE_CAP_PHYINFO_SIZE 3 161 #define HECAP_PHYINFO_SIZE 9 162 #define HECAP_MACINFO_SIZE 5 163 #define HECAP_TXRX_MCS_NSS_SIZE 2 164 #define HECAP_PPET16_PPET8_MAX_SIZE 25 165 166 #define HE_PPET16_PPET8_SIZE 8 167 168 /* 802.11ax PPE (PPDU packet Extension) threshold */ 169 struct he_ppe_threshold { 170 u32 numss_m1; 171 u32 ru_mask; 172 u32 ppet16_ppet8_ru3_ru0[HE_PPET16_PPET8_SIZE]; 173 }; 174 175 struct ath12k_he { 176 u8 hecap_macinfo[HECAP_MACINFO_SIZE]; 177 u32 hecap_rxmcsnssmap; 178 u32 hecap_txmcsnssmap; 179 u32 hecap_phyinfo[HEHANDLE_CAP_PHYINFO_SIZE]; 180 struct he_ppe_threshold hecap_ppet; 181 u32 heop_param; 182 }; 183 184 enum { 185 WMI_HOST_TP_SCALE_MAX = 0, 186 WMI_HOST_TP_SCALE_50 = 1, 187 WMI_HOST_TP_SCALE_25 = 2, 188 WMI_HOST_TP_SCALE_12 = 3, 189 WMI_HOST_TP_SCALE_MIN = 4, 190 WMI_HOST_TP_SCALE_SIZE = 5, 191 }; 192 193 enum ath12k_scan_state { 194 ATH12K_SCAN_IDLE, 195 ATH12K_SCAN_STARTING, 196 ATH12K_SCAN_RUNNING, 197 ATH12K_SCAN_ABORTING, 198 }; 199 200 enum ath12k_dev_flags { 201 ATH12K_CAC_RUNNING, 202 ATH12K_FLAG_CRASH_FLUSH, 203 ATH12K_FLAG_RAW_MODE, 204 ATH12K_FLAG_HW_CRYPTO_DISABLED, 205 ATH12K_FLAG_RECOVERY, 206 ATH12K_FLAG_UNREGISTERING, 207 ATH12K_FLAG_REGISTERED, 208 ATH12K_FLAG_QMI_FAIL, 209 ATH12K_FLAG_HTC_SUSPEND_COMPLETE, 210 ATH12K_FLAG_CE_IRQ_ENABLED, 211 ATH12K_FLAG_EXT_IRQ_ENABLED, 212 }; 213 214 struct ath12k_tx_conf { 215 bool changed; 216 u16 ac; 217 struct ieee80211_tx_queue_params tx_queue_params; 218 }; 219 220 struct ath12k_key_conf { 221 bool changed; 222 enum set_key_cmd cmd; 223 struct ieee80211_key_conf *key; 224 }; 225 226 struct ath12k_vif_cache { 227 struct ath12k_tx_conf tx_conf; 228 struct ath12k_key_conf key_conf; 229 u32 bss_conf_changed; 230 }; 231 232 struct ath12k_vif { 233 u32 vdev_id; 234 enum wmi_vdev_type vdev_type; 235 enum wmi_vdev_subtype vdev_subtype; 236 u32 beacon_interval; 237 u32 dtim_period; 238 u16 ast_hash; 239 u16 ast_idx; 240 u16 tcl_metadata; 241 u8 hal_addr_search_flags; 242 u8 search_type; 243 244 struct ath12k *ar; 245 struct ieee80211_vif *vif; 246 247 int bank_id; 248 u8 vdev_id_check_en; 249 250 struct wmi_wmm_params_all_arg wmm_params; 251 struct list_head list; 252 union { 253 struct { 254 u32 uapsd; 255 } sta; 256 struct { 257 /* 127 stations; wmi limit */ 258 u8 tim_bitmap[16]; 259 u8 tim_len; 260 u32 ssid_len; 261 u8 ssid[IEEE80211_MAX_SSID_LEN]; 262 bool hidden_ssid; 263 /* P2P_IE with NoA attribute for P2P_GO case */ 264 u32 noa_len; 265 u8 *noa_data; 266 } ap; 267 } u; 268 269 bool is_created; 270 bool is_started; 271 bool is_up; 272 u32 aid; 273 u8 bssid[ETH_ALEN]; 274 struct cfg80211_bitrate_mask bitrate_mask; 275 struct delayed_work connection_loss_work; 276 int num_legacy_stations; 277 int rtscts_prot_mode; 278 int txpower; 279 bool rsnie_present; 280 bool wpaie_present; 281 struct ieee80211_chanctx_conf chanctx; 282 u32 key_cipher; 283 u8 tx_encap_type; 284 u8 vdev_stats_id; 285 u32 punct_bitmap; 286 bool ps; 287 struct ath12k_vif_cache *cache; 288 }; 289 290 struct ath12k_vif_iter { 291 u32 vdev_id; 292 struct ath12k *ar; 293 struct ath12k_vif *arvif; 294 }; 295 296 #define HAL_AST_IDX_INVALID 0xFFFF 297 #define HAL_RX_MAX_MCS 12 298 #define HAL_RX_MAX_MCS_HT 31 299 #define HAL_RX_MAX_MCS_VHT 9 300 #define HAL_RX_MAX_MCS_HE 11 301 #define HAL_RX_MAX_NSS 8 302 #define HAL_RX_MAX_NUM_LEGACY_RATES 12 303 #define ATH12K_RX_RATE_TABLE_11AX_NUM 576 304 #define ATH12K_RX_RATE_TABLE_NUM 320 305 306 struct ath12k_rx_peer_rate_stats { 307 u64 ht_mcs_count[HAL_RX_MAX_MCS_HT + 1]; 308 u64 vht_mcs_count[HAL_RX_MAX_MCS_VHT + 1]; 309 u64 he_mcs_count[HAL_RX_MAX_MCS_HE + 1]; 310 u64 nss_count[HAL_RX_MAX_NSS]; 311 u64 bw_count[HAL_RX_BW_MAX]; 312 u64 gi_count[HAL_RX_GI_MAX]; 313 u64 legacy_count[HAL_RX_MAX_NUM_LEGACY_RATES]; 314 u64 rx_rate[ATH12K_RX_RATE_TABLE_11AX_NUM]; 315 }; 316 317 struct ath12k_rx_peer_stats { 318 u64 num_msdu; 319 u64 num_mpdu_fcs_ok; 320 u64 num_mpdu_fcs_err; 321 u64 tcp_msdu_count; 322 u64 udp_msdu_count; 323 u64 other_msdu_count; 324 u64 ampdu_msdu_count; 325 u64 non_ampdu_msdu_count; 326 u64 stbc_count; 327 u64 beamformed_count; 328 u64 mcs_count[HAL_RX_MAX_MCS + 1]; 329 u64 nss_count[HAL_RX_MAX_NSS]; 330 u64 bw_count[HAL_RX_BW_MAX]; 331 u64 gi_count[HAL_RX_GI_MAX]; 332 u64 coding_count[HAL_RX_SU_MU_CODING_MAX]; 333 u64 tid_count[IEEE80211_NUM_TIDS + 1]; 334 u64 pream_cnt[HAL_RX_PREAMBLE_MAX]; 335 u64 reception_type[HAL_RX_RECEPTION_TYPE_MAX]; 336 u64 rx_duration; 337 u64 dcm_count; 338 u64 ru_alloc_cnt[HAL_RX_RU_ALLOC_TYPE_MAX]; 339 struct ath12k_rx_peer_rate_stats pkt_stats; 340 struct ath12k_rx_peer_rate_stats byte_stats; 341 }; 342 343 #define ATH12K_HE_MCS_NUM 12 344 #define ATH12K_VHT_MCS_NUM 10 345 #define ATH12K_BW_NUM 5 346 #define ATH12K_NSS_NUM 4 347 #define ATH12K_LEGACY_NUM 12 348 #define ATH12K_GI_NUM 4 349 #define ATH12K_HT_MCS_NUM 32 350 351 enum ath12k_pkt_rx_err { 352 ATH12K_PKT_RX_ERR_FCS, 353 ATH12K_PKT_RX_ERR_TKIP, 354 ATH12K_PKT_RX_ERR_CRYPT, 355 ATH12K_PKT_RX_ERR_PEER_IDX_INVAL, 356 ATH12K_PKT_RX_ERR_MAX, 357 }; 358 359 enum ath12k_ampdu_subfrm_num { 360 ATH12K_AMPDU_SUBFRM_NUM_10, 361 ATH12K_AMPDU_SUBFRM_NUM_20, 362 ATH12K_AMPDU_SUBFRM_NUM_30, 363 ATH12K_AMPDU_SUBFRM_NUM_40, 364 ATH12K_AMPDU_SUBFRM_NUM_50, 365 ATH12K_AMPDU_SUBFRM_NUM_60, 366 ATH12K_AMPDU_SUBFRM_NUM_MORE, 367 ATH12K_AMPDU_SUBFRM_NUM_MAX, 368 }; 369 370 enum ath12k_amsdu_subfrm_num { 371 ATH12K_AMSDU_SUBFRM_NUM_1, 372 ATH12K_AMSDU_SUBFRM_NUM_2, 373 ATH12K_AMSDU_SUBFRM_NUM_3, 374 ATH12K_AMSDU_SUBFRM_NUM_4, 375 ATH12K_AMSDU_SUBFRM_NUM_MORE, 376 ATH12K_AMSDU_SUBFRM_NUM_MAX, 377 }; 378 379 enum ath12k_counter_type { 380 ATH12K_COUNTER_TYPE_BYTES, 381 ATH12K_COUNTER_TYPE_PKTS, 382 ATH12K_COUNTER_TYPE_MAX, 383 }; 384 385 enum ath12k_stats_type { 386 ATH12K_STATS_TYPE_SUCC, 387 ATH12K_STATS_TYPE_FAIL, 388 ATH12K_STATS_TYPE_RETRY, 389 ATH12K_STATS_TYPE_AMPDU, 390 ATH12K_STATS_TYPE_MAX, 391 }; 392 393 struct ath12k_htt_data_stats { 394 u64 legacy[ATH12K_COUNTER_TYPE_MAX][ATH12K_LEGACY_NUM]; 395 u64 ht[ATH12K_COUNTER_TYPE_MAX][ATH12K_HT_MCS_NUM]; 396 u64 vht[ATH12K_COUNTER_TYPE_MAX][ATH12K_VHT_MCS_NUM]; 397 u64 he[ATH12K_COUNTER_TYPE_MAX][ATH12K_HE_MCS_NUM]; 398 u64 bw[ATH12K_COUNTER_TYPE_MAX][ATH12K_BW_NUM]; 399 u64 nss[ATH12K_COUNTER_TYPE_MAX][ATH12K_NSS_NUM]; 400 u64 gi[ATH12K_COUNTER_TYPE_MAX][ATH12K_GI_NUM]; 401 u64 transmit_type[ATH12K_COUNTER_TYPE_MAX][HAL_RX_RECEPTION_TYPE_MAX]; 402 u64 ru_loc[ATH12K_COUNTER_TYPE_MAX][HAL_RX_RU_ALLOC_TYPE_MAX]; 403 }; 404 405 struct ath12k_htt_tx_stats { 406 struct ath12k_htt_data_stats stats[ATH12K_STATS_TYPE_MAX]; 407 u64 tx_duration; 408 u64 ba_fails; 409 u64 ack_fails; 410 u16 ru_start; 411 u16 ru_tones; 412 u32 mu_group[MAX_MU_GROUP_ID]; 413 }; 414 415 struct ath12k_per_ppdu_tx_stats { 416 u16 succ_pkts; 417 u16 failed_pkts; 418 u16 retry_pkts; 419 u32 succ_bytes; 420 u32 failed_bytes; 421 u32 retry_bytes; 422 }; 423 424 struct ath12k_wbm_tx_stats { 425 u64 wbm_tx_comp_stats[HAL_WBM_REL_HTT_TX_COMP_STATUS_MAX]; 426 }; 427 428 struct ath12k_sta { 429 struct ath12k_vif *arvif; 430 431 /* the following are protected by ar->data_lock */ 432 u32 changed; /* IEEE80211_RC_* */ 433 u32 bw; 434 u32 nss; 435 u32 smps; 436 enum hal_pn_type pn_type; 437 438 struct work_struct update_wk; 439 struct rate_info txrate; 440 struct rate_info last_txrate; 441 u64 rx_duration; 442 u64 tx_duration; 443 u8 rssi_comb; 444 struct ath12k_rx_peer_stats *rx_stats; 445 struct ath12k_wbm_tx_stats *wbm_tx_stats; 446 u32 bw_prev; 447 }; 448 449 #define ATH12K_MIN_5G_FREQ 4150 450 #define ATH12K_MIN_6G_FREQ 5925 451 #define ATH12K_MAX_6G_FREQ 7115 452 #define ATH12K_NUM_CHANS 101 453 #define ATH12K_MAX_5G_CHAN 173 454 455 enum ath12k_hw_state { 456 ATH12K_HW_STATE_OFF, 457 ATH12K_HW_STATE_ON, 458 ATH12K_HW_STATE_RESTARTING, 459 ATH12K_HW_STATE_RESTARTED, 460 ATH12K_HW_STATE_WEDGED, 461 /* Add other states as required */ 462 }; 463 464 /* Antenna noise floor */ 465 #define ATH12K_DEFAULT_NOISE_FLOOR -95 466 467 struct ath12k_fw_stats { 468 u32 pdev_id; 469 u32 stats_id; 470 struct list_head pdevs; 471 struct list_head vdevs; 472 struct list_head bcn; 473 }; 474 475 struct ath12k_debug { 476 struct dentry *debugfs_pdev; 477 }; 478 479 struct ath12k_per_peer_tx_stats { 480 u32 succ_bytes; 481 u32 retry_bytes; 482 u32 failed_bytes; 483 u32 duration; 484 u16 succ_pkts; 485 u16 retry_pkts; 486 u16 failed_pkts; 487 u16 ru_start; 488 u16 ru_tones; 489 u8 ba_fails; 490 u8 ppdu_type; 491 u32 mu_grpid; 492 u32 mu_pos; 493 bool is_ampdu; 494 }; 495 496 #define ATH12K_FLUSH_TIMEOUT (5 * HZ) 497 #define ATH12K_VDEV_DELETE_TIMEOUT_HZ (5 * HZ) 498 499 struct ath12k { 500 struct ath12k_base *ab; 501 struct ath12k_pdev *pdev; 502 struct ath12k_hw *ah; 503 struct ath12k_wmi_pdev *wmi; 504 struct ath12k_pdev_dp dp; 505 u8 mac_addr[ETH_ALEN]; 506 u32 ht_cap_info; 507 u32 vht_cap_info; 508 struct ath12k_he ar_he; 509 bool supports_6ghz; 510 struct { 511 struct completion started; 512 struct completion completed; 513 struct completion on_channel; 514 struct delayed_work timeout; 515 enum ath12k_scan_state state; 516 bool is_roc; 517 int vdev_id; 518 int roc_freq; 519 bool roc_notify; 520 } scan; 521 522 struct { 523 struct ieee80211_supported_band sbands[NUM_NL80211_BANDS]; 524 struct ieee80211_sband_iftype_data 525 iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES]; 526 } mac; 527 528 unsigned long dev_flags; 529 unsigned int filter_flags; 530 u32 min_tx_power; 531 u32 max_tx_power; 532 u32 txpower_limit_2g; 533 u32 txpower_limit_5g; 534 u32 txpower_scale; 535 u32 power_scale; 536 u32 chan_tx_pwr; 537 u32 num_stations; 538 u32 max_num_stations; 539 bool monitor_present; 540 /* To synchronize concurrent synchronous mac80211 callback operations, 541 * concurrent debugfs configuration and concurrent FW statistics events. 542 */ 543 struct mutex conf_mutex; 544 /* protects the radio specific data like debug stats, ppdu_stats_info stats, 545 * vdev_stop_status info, scan data, ath12k_sta info, ath12k_vif info, 546 * channel context data, survey info, test mode data. 547 */ 548 spinlock_t data_lock; 549 550 struct list_head arvifs; 551 /* should never be NULL; needed for regular htt rx */ 552 struct ieee80211_channel *rx_channel; 553 554 /* valid during scan; needed for mgmt rx during scan */ 555 struct ieee80211_channel *scan_channel; 556 557 u8 cfg_tx_chainmask; 558 u8 cfg_rx_chainmask; 559 u8 num_rx_chains; 560 u8 num_tx_chains; 561 /* pdev_idx starts from 0 whereas pdev->pdev_id starts with 1 */ 562 u8 pdev_idx; 563 u8 lmac_id; 564 u8 hw_link_id; 565 566 struct completion peer_assoc_done; 567 struct completion peer_delete_done; 568 569 int install_key_status; 570 struct completion install_key_done; 571 572 int last_wmi_vdev_start_status; 573 struct completion vdev_setup_done; 574 struct completion vdev_delete_done; 575 576 int num_peers; 577 int max_num_peers; 578 u32 num_started_vdevs; 579 u32 num_created_vdevs; 580 unsigned long long allocated_vdev_map; 581 582 struct idr txmgmt_idr; 583 /* protects txmgmt_idr data */ 584 spinlock_t txmgmt_idr_lock; 585 atomic_t num_pending_mgmt_tx; 586 wait_queue_head_t txmgmt_empty_waitq; 587 588 /* cycle count is reported twice for each visited channel during scan. 589 * access protected by data_lock 590 */ 591 u32 survey_last_rx_clear_count; 592 u32 survey_last_cycle_count; 593 594 /* Channel info events are expected to come in pairs without and with 595 * COMPLETE flag set respectively for each channel visit during scan. 596 * 597 * However there are deviations from this rule. This flag is used to 598 * avoid reporting garbage data. 599 */ 600 bool ch_info_can_report_survey; 601 struct survey_info survey[ATH12K_NUM_CHANS]; 602 struct completion bss_survey_done; 603 604 struct work_struct regd_update_work; 605 606 struct work_struct wmi_mgmt_tx_work; 607 struct sk_buff_head wmi_mgmt_tx_queue; 608 609 struct ath12k_per_peer_tx_stats peer_tx_stats; 610 struct list_head ppdu_stats_info; 611 u32 ppdu_stat_list_depth; 612 613 struct ath12k_per_peer_tx_stats cached_stats; 614 u32 last_ppdu_id; 615 u32 cached_ppdu_id; 616 #ifdef CONFIG_ATH12K_DEBUGFS 617 struct ath12k_debug debug; 618 #endif 619 620 bool dfs_block_radar_events; 621 bool monitor_conf_enabled; 622 bool monitor_vdev_created; 623 bool monitor_started; 624 int monitor_vdev_id; 625 626 u32 freq_low; 627 u32 freq_high; 628 }; 629 630 struct ath12k_hw { 631 struct ieee80211_hw *hw; 632 struct ath12k_base *ab; 633 634 /* Protect the write operation of the hardware state ath12k_hw::state 635 * between hardware start<=>reconfigure<=>stop transitions. 636 */ 637 struct mutex hw_mutex; 638 enum ath12k_hw_state state; 639 bool regd_updated; 640 bool use_6ghz_regd; 641 u8 num_radio; 642 643 /* Keep last */ 644 struct ath12k radio[] __aligned(sizeof(void *)); 645 }; 646 647 struct ath12k_band_cap { 648 u32 phy_id; 649 u32 max_bw_supported; 650 u32 ht_cap_info; 651 u32 he_cap_info[2]; 652 u32 he_mcs; 653 u32 he_cap_phy_info[PSOC_HOST_MAX_PHY_SIZE]; 654 struct ath12k_wmi_ppe_threshold_arg he_ppet; 655 u16 he_6ghz_capa; 656 u32 eht_cap_mac_info[WMI_MAX_EHTCAP_MAC_SIZE]; 657 u32 eht_cap_phy_info[WMI_MAX_EHTCAP_PHY_SIZE]; 658 u32 eht_mcs_20_only; 659 u32 eht_mcs_80; 660 u32 eht_mcs_160; 661 u32 eht_mcs_320; 662 struct ath12k_wmi_ppe_threshold_arg eht_ppet; 663 u32 eht_cap_info_internal; 664 }; 665 666 struct ath12k_pdev_cap { 667 u32 supported_bands; 668 u32 ampdu_density; 669 u32 vht_cap; 670 u32 vht_mcs; 671 u32 he_mcs; 672 u32 tx_chain_mask; 673 u32 rx_chain_mask; 674 u32 tx_chain_mask_shift; 675 u32 rx_chain_mask_shift; 676 struct ath12k_band_cap band[NUM_NL80211_BANDS]; 677 }; 678 679 struct mlo_timestamp { 680 u32 info; 681 u32 sync_timestamp_lo_us; 682 u32 sync_timestamp_hi_us; 683 u32 mlo_offset_lo; 684 u32 mlo_offset_hi; 685 u32 mlo_offset_clks; 686 u32 mlo_comp_clks; 687 u32 mlo_comp_timer; 688 }; 689 690 struct ath12k_pdev { 691 struct ath12k *ar; 692 u32 pdev_id; 693 u32 hw_link_id; 694 struct ath12k_pdev_cap cap; 695 u8 mac_addr[ETH_ALEN]; 696 struct mlo_timestamp timestamp; 697 }; 698 699 struct ath12k_fw_pdev { 700 u32 pdev_id; 701 u32 phy_id; 702 u32 supported_bands; 703 }; 704 705 struct ath12k_board_data { 706 const struct firmware *fw; 707 const void *data; 708 size_t len; 709 }; 710 711 struct ath12k_soc_dp_tx_err_stats { 712 /* TCL Ring Descriptor unavailable */ 713 u32 desc_na[DP_TCL_NUM_RING_MAX]; 714 /* Other failures during dp_tx due to mem allocation failure 715 * idr unavailable etc. 716 */ 717 atomic_t misc_fail; 718 }; 719 720 struct ath12k_soc_dp_stats { 721 u32 err_ring_pkts; 722 u32 invalid_rbm; 723 u32 rxdma_error[HAL_REO_ENTR_RING_RXDMA_ECODE_MAX]; 724 u32 reo_error[HAL_REO_DEST_RING_ERROR_CODE_MAX]; 725 u32 hal_reo_error[DP_REO_DST_RING_MAX]; 726 struct ath12k_soc_dp_tx_err_stats tx_err; 727 }; 728 729 /** 730 * enum ath12k_link_capable_flags - link capable flags 731 * 732 * Single/Multi link capability information 733 * 734 * @ATH12K_INTRA_DEVICE_MLO_SUPPORT: SLO/MLO form between the radio, where all 735 * the links (radios) present within a device. 736 * @ATH12K_INTER_DEVICE_MLO_SUPPORT: SLO/MLO form between the radio, where all 737 * the links (radios) present across the devices. 738 */ 739 enum ath12k_link_capable_flags { 740 ATH12K_INTRA_DEVICE_MLO_SUPPORT = BIT(0), 741 ATH12K_INTER_DEVICE_MLO_SUPPORT = BIT(1), 742 }; 743 744 /* Master structure to hold the hw data which may be used in core module */ 745 struct ath12k_base { 746 enum ath12k_hw_rev hw_rev; 747 struct platform_device *pdev; 748 struct device *dev; 749 struct ath12k_qmi qmi; 750 struct ath12k_wmi_base wmi_ab; 751 struct completion fw_ready; 752 u8 device_id; 753 int num_radios; 754 /* HW channel counters frequency value in hertz common to all MACs */ 755 u32 cc_freq_hz; 756 757 struct ath12k_htc htc; 758 759 struct ath12k_dp dp; 760 761 void __iomem *mem; 762 unsigned long mem_len; 763 764 struct { 765 enum ath12k_bus bus; 766 const struct ath12k_hif_ops *ops; 767 } hif; 768 769 struct ath12k_ce ce; 770 struct timer_list rx_replenish_retry; 771 struct ath12k_hal hal; 772 /* To synchronize core_start/core_stop */ 773 struct mutex core_lock; 774 /* Protects data like peers */ 775 spinlock_t base_lock; 776 777 /* Single pdev device (struct ath12k_hw_params::single_pdev_only): 778 * 779 * Firmware maintains data for all bands but advertises a single 780 * phy to the host which is stored as a single element in this 781 * array. 782 * 783 * Other devices: 784 * 785 * This array will contain as many elements as the number of 786 * radios. 787 */ 788 struct ath12k_pdev pdevs[MAX_RADIOS]; 789 790 /* struct ath12k_hw_params::single_pdev_only devices use this to 791 * store phy specific data 792 */ 793 struct ath12k_fw_pdev fw_pdev[MAX_RADIOS]; 794 u8 fw_pdev_count; 795 796 struct ath12k_pdev __rcu *pdevs_active[MAX_RADIOS]; 797 798 /* Holds information of wiphy (hw) registration. 799 * 800 * In Multi/Single Link Operation case, all pdevs are registered as 801 * a single wiphy. In other (legacy/Non-MLO) cases, each pdev is 802 * registered as separate wiphys. 803 */ 804 struct ath12k_hw *ah[MAX_RADIOS]; 805 u8 num_hw; 806 807 struct ath12k_wmi_hal_reg_capabilities_ext_arg hal_reg_cap[MAX_RADIOS]; 808 unsigned long long free_vdev_map; 809 unsigned long long free_vdev_stats_id_map; 810 struct list_head peers; 811 wait_queue_head_t peer_mapping_wq; 812 u8 mac_addr[ETH_ALEN]; 813 bool wmi_ready; 814 u32 wlan_init_status; 815 int irq_num[ATH12K_IRQ_NUM_MAX]; 816 struct ath12k_ext_irq_grp ext_irq_grp[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 817 struct napi_struct *napi; 818 struct ath12k_wmi_target_cap_arg target_caps; 819 u32 ext_service_bitmap[WMI_SERVICE_EXT_BM_SIZE]; 820 bool pdevs_macaddr_valid; 821 822 const struct ath12k_hw_params *hw_params; 823 824 const struct firmware *cal_file; 825 826 /* Below regd's are protected by ab->data_lock */ 827 /* This is the regd set for every radio 828 * by the firmware during initialization 829 */ 830 struct ieee80211_regdomain *default_regd[MAX_RADIOS]; 831 /* This regd is set during dynamic country setting 832 * This may or may not be used during the runtime 833 */ 834 struct ieee80211_regdomain *new_regd[MAX_RADIOS]; 835 836 /* Current DFS Regulatory */ 837 enum ath12k_dfs_region dfs_region; 838 struct ath12k_soc_dp_stats soc_stats; 839 #ifdef CONFIG_ATH12K_DEBUGFS 840 struct dentry *debugfs_soc; 841 #endif 842 843 unsigned long dev_flags; 844 struct completion driver_recovery; 845 struct workqueue_struct *workqueue; 846 struct work_struct restart_work; 847 struct workqueue_struct *workqueue_aux; 848 struct work_struct reset_work; 849 atomic_t reset_count; 850 atomic_t recovery_count; 851 atomic_t recovery_start_count; 852 bool is_reset; 853 struct completion reset_complete; 854 struct completion reconfigure_complete; 855 struct completion recovery_start; 856 /* continuous recovery fail count */ 857 atomic_t fail_cont_count; 858 unsigned long reset_fail_timeout; 859 struct { 860 /* protected by data_lock */ 861 u32 fw_crash_counter; 862 } stats; 863 u32 pktlog_defs_checksum; 864 865 struct ath12k_dbring_cap *db_caps; 866 u32 num_db_cap; 867 868 struct timer_list mon_reap_timer; 869 870 struct completion htc_suspend; 871 872 u64 fw_soc_drop_count; 873 bool static_window_map; 874 875 struct work_struct rfkill_work; 876 /* true means radio is on */ 877 bool rfkill_radio_on; 878 879 struct { 880 enum ath12k_bdf_search bdf_search; 881 u32 vendor; 882 u32 device; 883 u32 subsystem_vendor; 884 u32 subsystem_device; 885 } id; 886 887 struct { 888 u32 api_version; 889 890 const struct firmware *fw; 891 const u8 *amss_data; 892 size_t amss_len; 893 const u8 *amss_dualmac_data; 894 size_t amss_dualmac_len; 895 const u8 *m3_data; 896 size_t m3_len; 897 898 DECLARE_BITMAP(fw_features, ATH12K_FW_FEATURE_COUNT); 899 } fw; 900 901 const struct hal_rx_ops *hal_rx_ops; 902 903 /* mlo_capable_flags denotes the single/multi link operation 904 * capabilities of the Device. 905 * 906 * See enum ath12k_link_capable_flags 907 */ 908 u8 mlo_capable_flags; 909 910 struct completion restart_completed; 911 912 #ifdef CONFIG_ACPI 913 914 struct { 915 bool started; 916 u32 func_bit; 917 bool acpi_tas_enable; 918 bool acpi_bios_sar_enable; 919 u8 tas_cfg[ATH12K_ACPI_DSM_TAS_CFG_SIZE]; 920 u8 tas_sar_power_table[ATH12K_ACPI_DSM_TAS_DATA_SIZE]; 921 u8 bios_sar_data[ATH12K_ACPI_DSM_BIOS_SAR_DATA_SIZE]; 922 u8 geo_offset_data[ATH12K_ACPI_DSM_GEO_OFFSET_DATA_SIZE]; 923 u8 cca_data[ATH12K_ACPI_DSM_CCA_DATA_SIZE]; 924 u8 band_edge_power[ATH12K_ACPI_DSM_BAND_EDGE_DATA_SIZE]; 925 } acpi; 926 927 #endif /* CONFIG_ACPI */ 928 929 struct notifier_block panic_nb; 930 931 /* must be last */ 932 u8 drv_priv[] __aligned(sizeof(void *)); 933 }; 934 935 struct ath12k_pdev_map { 936 struct ath12k_base *ab; 937 u8 pdev_idx; 938 }; 939 940 int ath12k_core_qmi_firmware_ready(struct ath12k_base *ab); 941 int ath12k_core_pre_init(struct ath12k_base *ab); 942 int ath12k_core_init(struct ath12k_base *ath12k); 943 void ath12k_core_deinit(struct ath12k_base *ath12k); 944 struct ath12k_base *ath12k_core_alloc(struct device *dev, size_t priv_size, 945 enum ath12k_bus bus); 946 void ath12k_core_free(struct ath12k_base *ath12k); 947 int ath12k_core_fetch_board_data_api_1(struct ath12k_base *ab, 948 struct ath12k_board_data *bd, 949 char *filename); 950 int ath12k_core_fetch_bdf(struct ath12k_base *ath12k, 951 struct ath12k_board_data *bd); 952 void ath12k_core_free_bdf(struct ath12k_base *ab, struct ath12k_board_data *bd); 953 int ath12k_core_fetch_regdb(struct ath12k_base *ab, struct ath12k_board_data *bd); 954 int ath12k_core_check_dt(struct ath12k_base *ath12k); 955 int ath12k_core_check_smbios(struct ath12k_base *ab); 956 void ath12k_core_halt(struct ath12k *ar); 957 int ath12k_core_resume_early(struct ath12k_base *ab); 958 int ath12k_core_resume(struct ath12k_base *ab); 959 int ath12k_core_suspend(struct ath12k_base *ab); 960 int ath12k_core_suspend_late(struct ath12k_base *ab); 961 962 const struct firmware *ath12k_core_firmware_request(struct ath12k_base *ab, 963 const char *filename); 964 u32 ath12k_core_get_max_station_per_radio(struct ath12k_base *ab); 965 u32 ath12k_core_get_max_peers_per_radio(struct ath12k_base *ab); 966 u32 ath12k_core_get_max_num_tids(struct ath12k_base *ab); 967 968 static inline const char *ath12k_scan_state_str(enum ath12k_scan_state state) 969 { 970 switch (state) { 971 case ATH12K_SCAN_IDLE: 972 return "idle"; 973 case ATH12K_SCAN_STARTING: 974 return "starting"; 975 case ATH12K_SCAN_RUNNING: 976 return "running"; 977 case ATH12K_SCAN_ABORTING: 978 return "aborting"; 979 } 980 981 return "unknown"; 982 } 983 984 static inline struct ath12k_skb_cb *ATH12K_SKB_CB(struct sk_buff *skb) 985 { 986 BUILD_BUG_ON(sizeof(struct ath12k_skb_cb) > 987 IEEE80211_TX_INFO_DRIVER_DATA_SIZE); 988 return (struct ath12k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data; 989 } 990 991 static inline struct ath12k_skb_rxcb *ATH12K_SKB_RXCB(struct sk_buff *skb) 992 { 993 BUILD_BUG_ON(sizeof(struct ath12k_skb_rxcb) > sizeof(skb->cb)); 994 return (struct ath12k_skb_rxcb *)skb->cb; 995 } 996 997 static inline struct ath12k_vif *ath12k_vif_to_arvif(struct ieee80211_vif *vif) 998 { 999 return (struct ath12k_vif *)vif->drv_priv; 1000 } 1001 1002 static inline struct ath12k_sta *ath12k_sta_to_arsta(struct ieee80211_sta *sta) 1003 { 1004 return (struct ath12k_sta *)sta->drv_priv; 1005 } 1006 1007 static inline struct ath12k *ath12k_ab_to_ar(struct ath12k_base *ab, 1008 int mac_id) 1009 { 1010 return ab->pdevs[ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id)].ar; 1011 } 1012 1013 static inline void ath12k_core_create_firmware_path(struct ath12k_base *ab, 1014 const char *filename, 1015 void *buf, size_t buf_len) 1016 { 1017 snprintf(buf, buf_len, "%s/%s/%s", ATH12K_FW_DIR, 1018 ab->hw_params->fw.dir, filename); 1019 } 1020 1021 static inline const char *ath12k_bus_str(enum ath12k_bus bus) 1022 { 1023 switch (bus) { 1024 case ATH12K_BUS_PCI: 1025 return "pci"; 1026 } 1027 1028 return "unknown"; 1029 } 1030 1031 static inline struct ath12k_hw *ath12k_hw_to_ah(struct ieee80211_hw *hw) 1032 { 1033 return hw->priv; 1034 } 1035 1036 static inline struct ath12k *ath12k_ah_to_ar(struct ath12k_hw *ah, u8 hw_link_id) 1037 { 1038 if (WARN(hw_link_id >= ah->num_radio, 1039 "bad hw link id %d, so switch to default link\n", hw_link_id)) 1040 hw_link_id = 0; 1041 1042 return &ah->radio[hw_link_id]; 1043 } 1044 1045 static inline struct ath12k_hw *ath12k_ar_to_ah(struct ath12k *ar) 1046 { 1047 return ar->ah; 1048 } 1049 1050 static inline struct ieee80211_hw *ath12k_ar_to_hw(struct ath12k *ar) 1051 { 1052 return ar->ah->hw; 1053 } 1054 1055 #define for_each_ar(ah, ar, index) \ 1056 for ((index) = 0; ((index) < (ah)->num_radio && \ 1057 ((ar) = &(ah)->radio[(index)])); (index)++) 1058 #endif /* _CORE_H_ */ 1059