1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 5 */ 6 7 #ifndef ATH12K_CORE_H 8 #define ATH12K_CORE_H 9 10 #include <linux/types.h> 11 #include <linux/interrupt.h> 12 #include <linux/irq.h> 13 #include <linux/bitfield.h> 14 #include <linux/dmi.h> 15 #include <linux/ctype.h> 16 #include <linux/firmware.h> 17 #include <linux/of_reserved_mem.h> 18 #include <linux/panic_notifier.h> 19 #include <linux/average.h> 20 #include <linux/of.h> 21 #include "qmi.h" 22 #include "htc.h" 23 #include "wmi.h" 24 #include "hal.h" 25 #include "dp.h" 26 #include "ce.h" 27 #include "mac.h" 28 #include "hw.h" 29 #include "hal_rx.h" 30 #include "reg.h" 31 #include "dbring.h" 32 #include "fw.h" 33 #include "acpi.h" 34 #include "wow.h" 35 #include "debugfs_htt_stats.h" 36 #include "coredump.h" 37 38 #define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK) 39 40 #define ATH12K_TX_MGMT_NUM_PENDING_MAX 512 41 42 #define ATH12K_TX_MGMT_TARGET_MAX_SUPPORT_WMI 64 43 44 /* Pending management packets threshold for dropping probe responses */ 45 #define ATH12K_PRB_RSP_DROP_THRESHOLD ((ATH12K_TX_MGMT_TARGET_MAX_SUPPORT_WMI * 3) / 4) 46 47 /* SMBIOS type containing Board Data File Name Extension */ 48 #define ATH12K_SMBIOS_BDF_EXT_TYPE 0xF8 49 50 /* SMBIOS type structure length (excluding strings-set) */ 51 #define ATH12K_SMBIOS_BDF_EXT_LENGTH 0x9 52 53 /* The magic used by QCA spec */ 54 #define ATH12K_SMBIOS_BDF_EXT_MAGIC "BDF_" 55 56 #define ATH12K_INVALID_HW_MAC_ID 0xFF 57 #define ATH12K_CONNECTION_LOSS_HZ (3 * HZ) 58 59 #define ATH12K_MON_TIMER_INTERVAL 10 60 #define ATH12K_RESET_TIMEOUT_HZ (20 * HZ) 61 #define ATH12K_RESET_MAX_FAIL_COUNT_FIRST 3 62 #define ATH12K_RESET_MAX_FAIL_COUNT_FINAL 5 63 #define ATH12K_RESET_FAIL_TIMEOUT_HZ (20 * HZ) 64 #define ATH12K_RECONFIGURE_TIMEOUT_HZ (10 * HZ) 65 #define ATH12K_RECOVER_START_TIMEOUT_HZ (20 * HZ) 66 67 #define ATH12K_MAX_DEVICES 3 68 #define ATH12K_GROUP_MAX_RADIO (ATH12K_MAX_DEVICES * MAX_RADIOS) 69 #define ATH12K_INVALID_GROUP_ID 0xFF 70 #define ATH12K_INVALID_DEVICE_ID 0xFF 71 72 #define ATH12K_MAX_MLO_PEERS 256 73 #define ATH12K_MLO_PEER_ID_INVALID 0xFFFF 74 75 #define ATH12K_INVALID_RSSI_FULL -1 76 #define ATH12K_INVALID_RSSI_EMPTY -128 77 78 enum ath12k_bdf_search { 79 ATH12K_BDF_SEARCH_DEFAULT, 80 ATH12K_BDF_SEARCH_BUS_AND_BOARD, 81 }; 82 83 enum wme_ac { 84 WME_AC_BE, 85 WME_AC_BK, 86 WME_AC_VI, 87 WME_AC_VO, 88 WME_NUM_AC 89 }; 90 91 #define ATH12K_HT_MCS_MAX 7 92 #define ATH12K_VHT_MCS_MAX 9 93 #define ATH12K_HE_MCS_MAX 11 94 #define ATH12K_EHT_MCS_MAX 15 95 96 enum ath12k_crypt_mode { 97 /* Only use hardware crypto engine */ 98 ATH12K_CRYPT_MODE_HW, 99 /* Only use software crypto */ 100 ATH12K_CRYPT_MODE_SW, 101 }; 102 103 static inline enum wme_ac ath12k_tid_to_ac(u32 tid) 104 { 105 return (((tid == 0) || (tid == 3)) ? WME_AC_BE : 106 ((tid == 1) || (tid == 2)) ? WME_AC_BK : 107 ((tid == 4) || (tid == 5)) ? WME_AC_VI : 108 WME_AC_VO); 109 } 110 111 static inline u64 ath12k_le32hilo_to_u64(__le32 hi, __le32 lo) 112 { 113 u64 hi64 = le32_to_cpu(hi); 114 u64 lo64 = le32_to_cpu(lo); 115 116 return (hi64 << 32) | lo64; 117 } 118 119 enum ath12k_skb_flags { 120 ATH12K_SKB_HW_80211_ENCAP = BIT(0), 121 ATH12K_SKB_CIPHER_SET = BIT(1), 122 ATH12K_SKB_MLO_STA = BIT(2), 123 }; 124 125 struct ath12k_skb_cb { 126 dma_addr_t paddr; 127 struct ath12k *ar; 128 struct ieee80211_vif *vif; 129 dma_addr_t paddr_ext_desc; 130 u32 cipher; 131 u8 flags; 132 u8 link_id; 133 }; 134 135 struct ath12k_skb_rxcb { 136 dma_addr_t paddr; 137 bool is_first_msdu; 138 bool is_last_msdu; 139 bool is_continuation; 140 bool is_mcbc; 141 bool is_eapol; 142 struct hal_rx_desc *rx_desc; 143 u8 err_rel_src; 144 u8 err_code; 145 u8 hw_link_id; 146 u8 unmapped; 147 u8 is_frag; 148 u8 tid; 149 u16 peer_id; 150 bool is_end_of_ppdu; 151 }; 152 153 enum ath12k_hw_rev { 154 ATH12K_HW_QCN9274_HW10, 155 ATH12K_HW_QCN9274_HW20, 156 ATH12K_HW_WCN7850_HW20, 157 ATH12K_HW_IPQ5332_HW10, 158 }; 159 160 enum ath12k_firmware_mode { 161 /* the default mode, standard 802.11 functionality */ 162 ATH12K_FIRMWARE_MODE_NORMAL, 163 164 /* factory tests etc */ 165 ATH12K_FIRMWARE_MODE_FTM, 166 }; 167 168 #define ATH12K_IRQ_NUM_MAX 57 169 #define ATH12K_EXT_IRQ_NUM_MAX 16 170 #define ATH12K_MAX_TCL_RING_NUM 3 171 172 struct ath12k_ext_irq_grp { 173 struct ath12k_base *ab; 174 u32 irqs[ATH12K_EXT_IRQ_NUM_MAX]; 175 u32 num_irq; 176 u32 grp_id; 177 u64 timestamp; 178 bool napi_enabled; 179 struct napi_struct napi; 180 struct net_device *napi_ndev; 181 }; 182 183 enum ath12k_smbios_cc_type { 184 /* disable country code setting from SMBIOS */ 185 ATH12K_SMBIOS_CC_DISABLE = 0, 186 187 /* set country code by ANSI country name, based on ISO3166-1 alpha2 */ 188 ATH12K_SMBIOS_CC_ISO = 1, 189 190 /* worldwide regdomain */ 191 ATH12K_SMBIOS_CC_WW = 2, 192 }; 193 194 struct ath12k_smbios_bdf { 195 struct dmi_header hdr; 196 u8 features_disabled; 197 198 /* enum ath12k_smbios_cc_type */ 199 u8 country_code_flag; 200 201 /* To set specific country, you need to set country code 202 * flag=ATH12K_SMBIOS_CC_ISO first, then if country is United 203 * States, then country code value = 0x5553 ("US",'U' = 0x55, 'S'= 204 * 0x53). To set country to INDONESIA, then country code value = 205 * 0x4944 ("IN", 'I'=0x49, 'D'=0x44). If country code flag = 206 * ATH12K_SMBIOS_CC_WW, then you can use worldwide regulatory 207 * setting. 208 */ 209 u16 cc_code; 210 211 u8 bdf_enabled; 212 u8 bdf_ext[]; 213 } __packed; 214 215 #define HEHANDLE_CAP_PHYINFO_SIZE 3 216 #define HECAP_PHYINFO_SIZE 9 217 #define HECAP_MACINFO_SIZE 5 218 #define HECAP_TXRX_MCS_NSS_SIZE 2 219 #define HECAP_PPET16_PPET8_MAX_SIZE 25 220 221 #define HE_PPET16_PPET8_SIZE 8 222 223 /* 802.11ax PPE (PPDU packet Extension) threshold */ 224 struct he_ppe_threshold { 225 u32 numss_m1; 226 u32 ru_mask; 227 u32 ppet16_ppet8_ru3_ru0[HE_PPET16_PPET8_SIZE]; 228 }; 229 230 struct ath12k_he { 231 u8 hecap_macinfo[HECAP_MACINFO_SIZE]; 232 u32 hecap_rxmcsnssmap; 233 u32 hecap_txmcsnssmap; 234 u32 hecap_phyinfo[HEHANDLE_CAP_PHYINFO_SIZE]; 235 struct he_ppe_threshold hecap_ppet; 236 u32 heop_param; 237 }; 238 239 enum { 240 WMI_HOST_TP_SCALE_MAX = 0, 241 WMI_HOST_TP_SCALE_50 = 1, 242 WMI_HOST_TP_SCALE_25 = 2, 243 WMI_HOST_TP_SCALE_12 = 3, 244 WMI_HOST_TP_SCALE_MIN = 4, 245 WMI_HOST_TP_SCALE_SIZE = 5, 246 }; 247 248 enum ath12k_scan_state { 249 ATH12K_SCAN_IDLE, 250 ATH12K_SCAN_STARTING, 251 ATH12K_SCAN_RUNNING, 252 ATH12K_SCAN_ABORTING, 253 }; 254 255 enum ath12k_11d_state { 256 ATH12K_11D_IDLE, 257 ATH12K_11D_PREPARING, 258 ATH12K_11D_RUNNING, 259 }; 260 261 enum ath12k_hw_group_flags { 262 ATH12K_GROUP_FLAG_REGISTERED, 263 ATH12K_GROUP_FLAG_UNREGISTER, 264 }; 265 266 enum ath12k_dev_flags { 267 ATH12K_FLAG_CAC_RUNNING, 268 ATH12K_FLAG_CRASH_FLUSH, 269 ATH12K_FLAG_RAW_MODE, 270 ATH12K_FLAG_HW_CRYPTO_DISABLED, 271 ATH12K_FLAG_RECOVERY, 272 ATH12K_FLAG_UNREGISTERING, 273 ATH12K_FLAG_REGISTERED, 274 ATH12K_FLAG_QMI_FAIL, 275 ATH12K_FLAG_HTC_SUSPEND_COMPLETE, 276 ATH12K_FLAG_CE_IRQ_ENABLED, 277 ATH12K_FLAG_EXT_IRQ_ENABLED, 278 ATH12K_FLAG_QMI_FW_READY_COMPLETE, 279 ATH12K_FLAG_FTM_SEGMENTED, 280 ATH12K_FLAG_FIXED_MEM_REGION, 281 }; 282 283 struct ath12k_tx_conf { 284 bool changed; 285 u16 ac; 286 struct ieee80211_tx_queue_params tx_queue_params; 287 }; 288 289 struct ath12k_key_conf { 290 enum set_key_cmd cmd; 291 struct list_head list; 292 struct ieee80211_sta *sta; 293 struct ieee80211_key_conf *key; 294 }; 295 296 struct ath12k_vif_cache { 297 struct ath12k_tx_conf tx_conf; 298 struct ath12k_key_conf key_conf; 299 u32 bss_conf_changed; 300 }; 301 302 struct ath12k_rekey_data { 303 u8 kck[NL80211_KCK_LEN]; 304 u8 kek[NL80211_KCK_LEN]; 305 u64 replay_ctr; 306 bool enable_offload; 307 }; 308 309 struct ath12k_link_vif { 310 u32 vdev_id; 311 u32 beacon_interval; 312 u32 dtim_period; 313 u16 ast_hash; 314 u16 ast_idx; 315 u16 tcl_metadata; 316 u8 hal_addr_search_flags; 317 u8 search_type; 318 319 struct ath12k *ar; 320 321 int bank_id; 322 u8 vdev_id_check_en; 323 bool beacon_prot; 324 325 struct wmi_wmm_params_all_arg wmm_params; 326 struct list_head list; 327 328 bool is_created; 329 bool is_started; 330 bool is_up; 331 u8 bssid[ETH_ALEN]; 332 struct cfg80211_bitrate_mask bitrate_mask; 333 struct delayed_work connection_loss_work; 334 int num_legacy_stations; 335 int rtscts_prot_mode; 336 int txpower; 337 bool rsnie_present; 338 bool wpaie_present; 339 u8 vdev_stats_id; 340 u32 punct_bitmap; 341 u8 link_id; 342 struct ath12k_vif *ahvif; 343 struct ath12k_rekey_data rekey_data; 344 struct ath12k_link_stats link_stats; 345 spinlock_t link_stats_lock; /* Protects updates to link_stats */ 346 347 u8 current_cntdown_counter; 348 349 /* only used in station mode */ 350 bool is_sta_assoc_link; 351 352 struct ath12k_reg_tpc_power_info reg_tpc_info; 353 354 bool group_key_valid; 355 struct wmi_vdev_install_key_arg group_key; 356 bool pairwise_key_done; 357 u16 num_stations; 358 }; 359 360 struct ath12k_vif { 361 enum wmi_vdev_type vdev_type; 362 enum wmi_vdev_subtype vdev_subtype; 363 struct ieee80211_vif *vif; 364 struct ath12k_hw *ah; 365 366 union { 367 struct { 368 u32 uapsd; 369 } sta; 370 struct { 371 /* 127 stations; wmi limit */ 372 u8 tim_bitmap[16]; 373 u8 tim_len; 374 u32 ssid_len; 375 u8 ssid[IEEE80211_MAX_SSID_LEN]; 376 bool hidden_ssid; 377 /* P2P_IE with NoA attribute for P2P_GO case */ 378 u32 noa_len; 379 u8 *noa_data; 380 } ap; 381 } u; 382 383 u32 aid; 384 u32 key_cipher; 385 u8 tx_encap_type; 386 bool ps; 387 atomic_t mcbc_gsn; 388 389 struct ath12k_link_vif deflink; 390 struct ath12k_link_vif __rcu *link[ATH12K_NUM_MAX_LINKS]; 391 struct ath12k_vif_cache *cache[IEEE80211_MLD_MAX_NUM_LINKS]; 392 /* indicates bitmap of link vif created in FW */ 393 u32 links_map; 394 /* Must be last - ends in a flexible-array member. 395 * 396 * FIXME: Driver should not copy struct ieee80211_chanctx_conf, 397 * especially because it has a flexible array. Find a better way. 398 */ 399 struct ieee80211_chanctx_conf chanctx; 400 }; 401 402 struct ath12k_vif_iter { 403 u32 vdev_id; 404 struct ath12k *ar; 405 struct ath12k_link_vif *arvif; 406 }; 407 408 #define HAL_AST_IDX_INVALID 0xFFFF 409 #define HAL_RX_MAX_MCS 12 410 #define HAL_RX_MAX_MCS_HT 31 411 #define HAL_RX_MAX_MCS_VHT 9 412 #define HAL_RX_MAX_MCS_HE 11 413 #define HAL_RX_MAX_MCS_BE 15 414 #define HAL_RX_MAX_NSS 8 415 #define HAL_RX_MAX_NUM_LEGACY_RATES 12 416 417 #define ATH12K_SCAN_TIMEOUT_HZ (20 * HZ) 418 419 struct ath12k_rx_peer_rate_stats { 420 u64 ht_mcs_count[HAL_RX_MAX_MCS_HT + 1]; 421 u64 vht_mcs_count[HAL_RX_MAX_MCS_VHT + 1]; 422 u64 he_mcs_count[HAL_RX_MAX_MCS_HE + 1]; 423 u64 be_mcs_count[HAL_RX_MAX_MCS_BE + 1]; 424 u64 nss_count[HAL_RX_MAX_NSS]; 425 u64 bw_count[HAL_RX_BW_MAX]; 426 u64 gi_count[HAL_RX_GI_MAX]; 427 u64 legacy_count[HAL_RX_MAX_NUM_LEGACY_RATES]; 428 u64 rx_rate[HAL_RX_BW_MAX][HAL_RX_GI_MAX][HAL_RX_MAX_NSS][HAL_RX_MAX_MCS_HT + 1]; 429 }; 430 431 struct ath12k_rx_peer_stats { 432 u64 num_msdu; 433 u64 num_mpdu_fcs_ok; 434 u64 num_mpdu_fcs_err; 435 u64 tcp_msdu_count; 436 u64 udp_msdu_count; 437 u64 other_msdu_count; 438 u64 ampdu_msdu_count; 439 u64 non_ampdu_msdu_count; 440 u64 stbc_count; 441 u64 beamformed_count; 442 u64 coding_count[HAL_RX_SU_MU_CODING_MAX]; 443 u64 tid_count[IEEE80211_NUM_TIDS + 1]; 444 u64 pream_cnt[HAL_RX_PREAMBLE_MAX]; 445 u64 reception_type[HAL_RX_RECEPTION_TYPE_MAX]; 446 u64 rx_duration; 447 u64 dcm_count; 448 u64 ru_alloc_cnt[HAL_RX_RU_ALLOC_TYPE_MAX]; 449 struct ath12k_rx_peer_rate_stats pkt_stats; 450 struct ath12k_rx_peer_rate_stats byte_stats; 451 }; 452 453 #define ATH12K_HE_MCS_NUM 12 454 #define ATH12K_VHT_MCS_NUM 10 455 #define ATH12K_BW_NUM 5 456 #define ATH12K_NSS_NUM 4 457 #define ATH12K_LEGACY_NUM 12 458 #define ATH12K_GI_NUM 4 459 #define ATH12K_HT_MCS_NUM 32 460 461 enum ath12k_pkt_rx_err { 462 ATH12K_PKT_RX_ERR_FCS, 463 ATH12K_PKT_RX_ERR_TKIP, 464 ATH12K_PKT_RX_ERR_CRYPT, 465 ATH12K_PKT_RX_ERR_PEER_IDX_INVAL, 466 ATH12K_PKT_RX_ERR_MAX, 467 }; 468 469 enum ath12k_ampdu_subfrm_num { 470 ATH12K_AMPDU_SUBFRM_NUM_10, 471 ATH12K_AMPDU_SUBFRM_NUM_20, 472 ATH12K_AMPDU_SUBFRM_NUM_30, 473 ATH12K_AMPDU_SUBFRM_NUM_40, 474 ATH12K_AMPDU_SUBFRM_NUM_50, 475 ATH12K_AMPDU_SUBFRM_NUM_60, 476 ATH12K_AMPDU_SUBFRM_NUM_MORE, 477 ATH12K_AMPDU_SUBFRM_NUM_MAX, 478 }; 479 480 enum ath12k_amsdu_subfrm_num { 481 ATH12K_AMSDU_SUBFRM_NUM_1, 482 ATH12K_AMSDU_SUBFRM_NUM_2, 483 ATH12K_AMSDU_SUBFRM_NUM_3, 484 ATH12K_AMSDU_SUBFRM_NUM_4, 485 ATH12K_AMSDU_SUBFRM_NUM_MORE, 486 ATH12K_AMSDU_SUBFRM_NUM_MAX, 487 }; 488 489 enum ath12k_counter_type { 490 ATH12K_COUNTER_TYPE_BYTES, 491 ATH12K_COUNTER_TYPE_PKTS, 492 ATH12K_COUNTER_TYPE_MAX, 493 }; 494 495 enum ath12k_stats_type { 496 ATH12K_STATS_TYPE_SUCC, 497 ATH12K_STATS_TYPE_FAIL, 498 ATH12K_STATS_TYPE_RETRY, 499 ATH12K_STATS_TYPE_AMPDU, 500 ATH12K_STATS_TYPE_MAX, 501 }; 502 503 struct ath12k_htt_data_stats { 504 u64 legacy[ATH12K_COUNTER_TYPE_MAX][ATH12K_LEGACY_NUM]; 505 u64 ht[ATH12K_COUNTER_TYPE_MAX][ATH12K_HT_MCS_NUM]; 506 u64 vht[ATH12K_COUNTER_TYPE_MAX][ATH12K_VHT_MCS_NUM]; 507 u64 he[ATH12K_COUNTER_TYPE_MAX][ATH12K_HE_MCS_NUM]; 508 u64 bw[ATH12K_COUNTER_TYPE_MAX][ATH12K_BW_NUM]; 509 u64 nss[ATH12K_COUNTER_TYPE_MAX][ATH12K_NSS_NUM]; 510 u64 gi[ATH12K_COUNTER_TYPE_MAX][ATH12K_GI_NUM]; 511 u64 transmit_type[ATH12K_COUNTER_TYPE_MAX][HAL_RX_RECEPTION_TYPE_MAX]; 512 u64 ru_loc[ATH12K_COUNTER_TYPE_MAX][HAL_RX_RU_ALLOC_TYPE_MAX]; 513 }; 514 515 struct ath12k_htt_tx_stats { 516 struct ath12k_htt_data_stats stats[ATH12K_STATS_TYPE_MAX]; 517 u64 tx_duration; 518 u64 ba_fails; 519 u64 ack_fails; 520 u16 ru_start; 521 u16 ru_tones; 522 u32 mu_group[MAX_MU_GROUP_ID]; 523 }; 524 525 struct ath12k_per_ppdu_tx_stats { 526 u16 succ_pkts; 527 u16 failed_pkts; 528 u16 retry_pkts; 529 u32 succ_bytes; 530 u32 failed_bytes; 531 u32 retry_bytes; 532 }; 533 534 struct ath12k_wbm_tx_stats { 535 u64 wbm_tx_comp_stats[HAL_WBM_REL_HTT_TX_COMP_STATUS_MAX]; 536 }; 537 538 DECLARE_EWMA(avg_rssi, 10, 8) 539 540 struct ath12k_link_sta { 541 struct ath12k_link_vif *arvif; 542 struct ath12k_sta *ahsta; 543 544 /* link address similar to ieee80211_link_sta */ 545 u8 addr[ETH_ALEN]; 546 547 /* the following are protected by ar->data_lock */ 548 u32 changed; /* IEEE80211_RC_* */ 549 u32 bw; 550 u32 nss; 551 u32 smps; 552 553 struct wiphy_work update_wk; 554 struct rate_info txrate; 555 struct rate_info last_txrate; 556 u64 rx_duration; 557 u64 tx_duration; 558 u8 rssi_comb; 559 struct ewma_avg_rssi avg_rssi; 560 u8 link_id; 561 struct ath12k_rx_peer_stats *rx_stats; 562 struct ath12k_wbm_tx_stats *wbm_tx_stats; 563 u32 bw_prev; 564 u32 peer_nss; 565 s8 rssi_beacon; 566 s8 chain_signal[IEEE80211_MAX_CHAINS]; 567 568 /* For now the assoc link will be considered primary */ 569 bool is_assoc_link; 570 571 /* for firmware use only */ 572 u8 link_idx; 573 u32 tx_retry_failed; 574 u32 tx_retry_count; 575 }; 576 577 struct ath12k_reoq_buf { 578 void *vaddr; 579 dma_addr_t paddr_aligned; 580 u32 size; 581 }; 582 583 struct ath12k_sta { 584 struct ath12k_vif *ahvif; 585 enum hal_pn_type pn_type; 586 struct ath12k_link_sta deflink; 587 struct ath12k_link_sta __rcu *link[IEEE80211_MLD_MAX_NUM_LINKS]; 588 /* indicates bitmap of link sta created in FW */ 589 u16 links_map; 590 u8 assoc_link_id; 591 u16 ml_peer_id; 592 u8 num_peer; 593 594 enum ieee80211_sta_state state; 595 596 struct ath12k_reoq_buf reoq_bufs[IEEE80211_NUM_TIDS + 1]; 597 }; 598 599 #define ATH12K_HALF_20MHZ_BW 10 600 #define ATH12K_2GHZ_MIN_CENTER 2412 601 #define ATH12K_2GHZ_MAX_CENTER 2484 602 #define ATH12K_5GHZ_MIN_CENTER 4900 603 #define ATH12K_5GHZ_MAX_CENTER 5920 604 #define ATH12K_6GHZ_MIN_CENTER 5935 605 #define ATH12K_6GHZ_MAX_CENTER 7115 606 #define ATH12K_MIN_2GHZ_FREQ (ATH12K_2GHZ_MIN_CENTER - ATH12K_HALF_20MHZ_BW - 1) 607 #define ATH12K_MAX_2GHZ_FREQ (ATH12K_2GHZ_MAX_CENTER + ATH12K_HALF_20MHZ_BW + 1) 608 #define ATH12K_MIN_5GHZ_FREQ (ATH12K_5GHZ_MIN_CENTER - ATH12K_HALF_20MHZ_BW) 609 #define ATH12K_MAX_5GHZ_FREQ (ATH12K_5GHZ_MAX_CENTER + ATH12K_HALF_20MHZ_BW) 610 #define ATH12K_MIN_6GHZ_FREQ (ATH12K_6GHZ_MIN_CENTER - ATH12K_HALF_20MHZ_BW) 611 #define ATH12K_MAX_6GHZ_FREQ (ATH12K_6GHZ_MAX_CENTER + ATH12K_HALF_20MHZ_BW) 612 #define ATH12K_NUM_CHANS 101 613 #define ATH12K_MAX_5GHZ_CHAN 173 614 615 static inline bool ath12k_is_2ghz_channel_freq(u32 freq) 616 { 617 return freq >= ATH12K_MIN_2GHZ_FREQ && 618 freq <= ATH12K_MAX_2GHZ_FREQ; 619 } 620 621 enum ath12k_hw_state { 622 ATH12K_HW_STATE_OFF, 623 ATH12K_HW_STATE_ON, 624 ATH12K_HW_STATE_RESTARTING, 625 ATH12K_HW_STATE_RESTARTED, 626 ATH12K_HW_STATE_WEDGED, 627 ATH12K_HW_STATE_TM, 628 /* Add other states as required */ 629 }; 630 631 /* Antenna noise floor */ 632 #define ATH12K_DEFAULT_NOISE_FLOOR -95 633 634 struct ath12k_ftm_event_obj { 635 u32 data_pos; 636 u32 expected_seq; 637 u8 *eventdata; 638 }; 639 640 struct ath12k_fw_stats { 641 u32 pdev_id; 642 u32 stats_id; 643 struct list_head pdevs; 644 struct list_head vdevs; 645 struct list_head bcn; 646 u32 num_vdev_recvd; 647 u32 num_bcn_recvd; 648 }; 649 650 struct ath12k_dbg_htt_stats { 651 enum ath12k_dbg_htt_ext_stats_type type; 652 u32 cfg_param[4]; 653 u8 reset; 654 struct debug_htt_stats_req *stats_req; 655 }; 656 657 struct ath12k_debug { 658 struct dentry *debugfs_pdev; 659 struct dentry *debugfs_pdev_symlink; 660 struct ath12k_dbg_htt_stats htt_stats; 661 enum wmi_halphy_ctrl_path_stats_id tpc_stats_type; 662 bool tpc_request; 663 struct completion tpc_complete; 664 struct wmi_tpc_stats_arg *tpc_stats; 665 u32 rx_filter; 666 bool extd_rx_stats; 667 }; 668 669 struct ath12k_per_peer_tx_stats { 670 u32 succ_bytes; 671 u32 retry_bytes; 672 u32 failed_bytes; 673 u32 duration; 674 u16 succ_pkts; 675 u16 retry_pkts; 676 u16 failed_pkts; 677 u16 ru_start; 678 u16 ru_tones; 679 u8 ba_fails; 680 u8 ppdu_type; 681 u32 mu_grpid; 682 u32 mu_pos; 683 bool is_ampdu; 684 }; 685 686 struct ath12k_pdev_rssi_offsets { 687 s32 temp_offset; 688 s8 min_nf_dbm; 689 /* Cache the sum here to avoid calculating it every time in hot path 690 * noise_floor = min_nf_dbm + temp_offset 691 */ 692 s32 noise_floor; 693 }; 694 695 #define ATH12K_FLUSH_TIMEOUT (5 * HZ) 696 #define ATH12K_VDEV_DELETE_TIMEOUT_HZ (5 * HZ) 697 698 struct ath12k { 699 struct ath12k_base *ab; 700 struct ath12k_pdev *pdev; 701 struct ath12k_hw *ah; 702 struct ath12k_wmi_pdev *wmi; 703 struct ath12k_pdev_dp dp; 704 u8 mac_addr[ETH_ALEN]; 705 u32 ht_cap_info; 706 u32 vht_cap_info; 707 struct ath12k_he ar_he; 708 bool supports_6ghz; 709 struct { 710 struct completion started; 711 struct completion completed; 712 struct completion on_channel; 713 struct delayed_work timeout; 714 enum ath12k_scan_state state; 715 bool is_roc; 716 int roc_freq; 717 bool roc_notify; 718 struct wiphy_work vdev_clean_wk; 719 struct ath12k_link_vif *arvif; 720 } scan; 721 722 struct { 723 struct ieee80211_supported_band sbands[NUM_NL80211_BANDS]; 724 struct ieee80211_sband_iftype_data 725 iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES]; 726 } mac; 727 728 unsigned long dev_flags; 729 unsigned int filter_flags; 730 u32 min_tx_power; 731 u32 max_tx_power; 732 u32 txpower_limit_2g; 733 u32 txpower_limit_5g; 734 u32 txpower_scale; 735 u32 power_scale; 736 u32 chan_tx_pwr; 737 u32 rts_threshold; 738 u32 num_stations; 739 u32 max_num_stations; 740 741 /* protects the radio specific data like debug stats, ppdu_stats_info stats, 742 * vdev_stop_status info, scan data, ath12k_sta info, ath12k_link_vif info, 743 * channel context data, survey info, test mode data, regd_channel_update_queue. 744 */ 745 spinlock_t data_lock; 746 747 struct list_head arvifs; 748 /* should never be NULL; needed for regular htt rx */ 749 struct ieee80211_channel *rx_channel; 750 751 /* valid during scan; needed for mgmt rx during scan */ 752 struct ieee80211_channel *scan_channel; 753 754 u8 cfg_tx_chainmask; 755 u8 cfg_rx_chainmask; 756 u8 num_rx_chains; 757 u8 num_tx_chains; 758 /* pdev_idx starts from 0 whereas pdev->pdev_id starts with 1 */ 759 u8 pdev_idx; 760 u8 lmac_id; 761 u8 hw_link_id; 762 763 struct completion peer_assoc_done; 764 struct completion peer_delete_done; 765 766 int install_key_status; 767 struct completion install_key_done; 768 769 int last_wmi_vdev_start_status; 770 struct completion vdev_setup_done; 771 struct completion vdev_delete_done; 772 773 int num_peers; 774 int max_num_peers; 775 u32 num_started_vdevs; 776 u32 num_created_vdevs; 777 unsigned long long allocated_vdev_map; 778 779 struct idr txmgmt_idr; 780 /* protects txmgmt_idr data */ 781 spinlock_t txmgmt_idr_lock; 782 atomic_t num_pending_mgmt_tx; 783 wait_queue_head_t txmgmt_empty_waitq; 784 785 /* cycle count is reported twice for each visited channel during scan. 786 * access protected by data_lock 787 */ 788 u32 survey_last_rx_clear_count; 789 u32 survey_last_cycle_count; 790 791 /* Channel info events are expected to come in pairs without and with 792 * COMPLETE flag set respectively for each channel visit during scan. 793 * 794 * However there are deviations from this rule. This flag is used to 795 * avoid reporting garbage data. 796 */ 797 bool ch_info_can_report_survey; 798 struct survey_info survey[ATH12K_NUM_CHANS]; 799 struct completion bss_survey_done; 800 801 struct work_struct regd_update_work; 802 struct work_struct regd_channel_update_work; 803 struct list_head regd_channel_update_queue; 804 805 struct wiphy_work wmi_mgmt_tx_work; 806 struct sk_buff_head wmi_mgmt_tx_queue; 807 808 struct ath12k_wow wow; 809 struct completion target_suspend; 810 bool target_suspend_ack; 811 struct ath12k_per_peer_tx_stats peer_tx_stats; 812 struct list_head ppdu_stats_info; 813 u32 ppdu_stat_list_depth; 814 815 struct ath12k_per_peer_tx_stats cached_stats; 816 u32 last_ppdu_id; 817 u32 cached_ppdu_id; 818 #ifdef CONFIG_ATH12K_DEBUGFS 819 struct ath12k_debug debug; 820 #endif 821 822 bool dfs_block_radar_events; 823 bool monitor_vdev_created; 824 bool monitor_started; 825 int monitor_vdev_id; 826 827 struct wiphy_radio_freq_range freq_range; 828 829 bool nlo_enabled; 830 831 /* Protected by wiphy::mtx lock. */ 832 u32 vdev_id_11d_scan; 833 struct completion completed_11d_scan; 834 enum ath12k_11d_state state_11d; 835 u8 alpha2[REG_ALPHA2_LEN]; 836 bool regdom_set_by_user; 837 struct completion regd_update_completed; 838 839 struct completion fw_stats_complete; 840 struct completion fw_stats_done; 841 842 struct completion mlo_setup_done; 843 u32 mlo_setup_status; 844 u8 ftm_msgref; 845 struct ath12k_fw_stats fw_stats; 846 unsigned long last_tx_power_update; 847 848 s8 max_allowed_tx_power; 849 struct ath12k_pdev_rssi_offsets rssi_info; 850 }; 851 852 struct ath12k_hw { 853 struct ieee80211_hw *hw; 854 struct device *dev; 855 856 /* Protect the write operation of the hardware state ath12k_hw::state 857 * between hardware start<=>reconfigure<=>stop transitions. 858 */ 859 struct mutex hw_mutex; 860 enum ath12k_hw_state state; 861 bool regd_updated; 862 bool use_6ghz_regd; 863 864 u8 num_radio; 865 866 DECLARE_BITMAP(free_ml_peer_id_map, ATH12K_MAX_MLO_PEERS); 867 868 /* protected by wiphy_lock() */ 869 struct list_head ml_peers; 870 871 /* Keep last */ 872 struct ath12k radio[] __aligned(sizeof(void *)); 873 }; 874 875 struct ath12k_band_cap { 876 u32 phy_id; 877 u32 max_bw_supported; 878 u32 ht_cap_info; 879 u32 he_cap_info[2]; 880 u32 he_mcs; 881 u32 he_cap_phy_info[PSOC_HOST_MAX_PHY_SIZE]; 882 struct ath12k_wmi_ppe_threshold_arg he_ppet; 883 u16 he_6ghz_capa; 884 u32 eht_cap_mac_info[WMI_MAX_EHTCAP_MAC_SIZE]; 885 u32 eht_cap_phy_info[WMI_MAX_EHTCAP_PHY_SIZE]; 886 u32 eht_mcs_20_only; 887 u32 eht_mcs_80; 888 u32 eht_mcs_160; 889 u32 eht_mcs_320; 890 struct ath12k_wmi_ppe_threshold_arg eht_ppet; 891 u32 eht_cap_info_internal; 892 }; 893 894 struct ath12k_pdev_cap { 895 u32 supported_bands; 896 u32 ampdu_density; 897 u32 vht_cap; 898 u32 vht_mcs; 899 u32 he_mcs; 900 u32 tx_chain_mask; 901 u32 rx_chain_mask; 902 u32 tx_chain_mask_shift; 903 u32 rx_chain_mask_shift; 904 struct ath12k_band_cap band[NUM_NL80211_BANDS]; 905 u32 eml_cap; 906 u32 mld_cap; 907 bool nss_ratio_enabled; 908 u8 nss_ratio_info; 909 }; 910 911 struct mlo_timestamp { 912 u32 info; 913 u32 sync_timestamp_lo_us; 914 u32 sync_timestamp_hi_us; 915 u32 mlo_offset_lo; 916 u32 mlo_offset_hi; 917 u32 mlo_offset_clks; 918 u32 mlo_comp_clks; 919 u32 mlo_comp_timer; 920 }; 921 922 struct ath12k_pdev { 923 struct ath12k *ar; 924 u32 pdev_id; 925 u32 hw_link_id; 926 struct ath12k_pdev_cap cap; 927 u8 mac_addr[ETH_ALEN]; 928 struct mlo_timestamp timestamp; 929 }; 930 931 struct ath12k_fw_pdev { 932 u32 pdev_id; 933 u32 phy_id; 934 u32 supported_bands; 935 }; 936 937 struct ath12k_board_data { 938 const struct firmware *fw; 939 const void *data; 940 size_t len; 941 }; 942 943 struct ath12k_device_dp_tx_err_stats { 944 /* TCL Ring Descriptor unavailable */ 945 u32 desc_na[DP_TCL_NUM_RING_MAX]; 946 /* Other failures during dp_tx due to mem allocation failure 947 * idr unavailable etc. 948 */ 949 atomic_t misc_fail; 950 }; 951 952 struct ath12k_device_dp_stats { 953 u32 err_ring_pkts; 954 u32 invalid_rbm; 955 u32 rxdma_error[HAL_REO_ENTR_RING_RXDMA_ECODE_MAX]; 956 u32 reo_error[HAL_REO_DEST_RING_ERROR_CODE_MAX]; 957 u32 hal_reo_error[DP_REO_DST_RING_MAX]; 958 struct ath12k_device_dp_tx_err_stats tx_err; 959 u32 reo_rx[DP_REO_DST_RING_MAX][ATH12K_MAX_DEVICES]; 960 u32 rx_wbm_rel_source[HAL_WBM_REL_SRC_MODULE_MAX][ATH12K_MAX_DEVICES]; 961 u32 tqm_rel_reason[MAX_TQM_RELEASE_REASON]; 962 u32 fw_tx_status[MAX_FW_TX_STATUS]; 963 u32 tx_wbm_rel_source[HAL_WBM_REL_SRC_MODULE_MAX]; 964 u32 tx_enqueued[DP_TCL_NUM_RING_MAX]; 965 u32 tx_completed[DP_TCL_NUM_RING_MAX]; 966 }; 967 968 struct ath12k_reg_freq { 969 u32 start_freq; 970 u32 end_freq; 971 }; 972 973 struct ath12k_mlo_memory { 974 struct target_mem_chunk chunk[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 975 int mlo_mem_size; 976 bool init_done; 977 }; 978 979 struct ath12k_hw_link { 980 u8 device_id; 981 u8 pdev_idx; 982 }; 983 984 /* Holds info on the group of devices that are registered as a single 985 * wiphy, protected with struct ath12k_hw_group::mutex. 986 */ 987 struct ath12k_hw_group { 988 struct list_head list; 989 u8 id; 990 u8 num_devices; 991 u8 num_probed; 992 u8 num_started; 993 unsigned long flags; 994 struct ath12k_base *ab[ATH12K_MAX_DEVICES]; 995 996 /* protects access to this struct */ 997 struct mutex mutex; 998 999 /* Holds information of wiphy (hw) registration. 1000 * 1001 * In Multi/Single Link Operation case, all pdevs are registered as 1002 * a single wiphy. In other (legacy/Non-MLO) cases, each pdev is 1003 * registered as separate wiphys. 1004 */ 1005 struct ath12k_hw *ah[ATH12K_GROUP_MAX_RADIO]; 1006 u8 num_hw; 1007 bool mlo_capable; 1008 struct device_node *wsi_node[ATH12K_MAX_DEVICES]; 1009 struct ath12k_mlo_memory mlo_mem; 1010 struct ath12k_hw_link hw_links[ATH12K_GROUP_MAX_RADIO]; 1011 bool hw_link_id_init_done; 1012 }; 1013 1014 /* Holds WSI info specific to each device, excluding WSI group info */ 1015 struct ath12k_wsi_info { 1016 u32 index; 1017 u32 hw_link_id_base; 1018 }; 1019 1020 struct ath12k_dp_profile_params { 1021 u32 tx_comp_ring_size; 1022 u32 rxdma_monitor_buf_ring_size; 1023 u32 rxdma_monitor_dst_ring_size; 1024 u32 num_pool_tx_desc; 1025 u32 rx_desc_count; 1026 }; 1027 1028 struct ath12k_mem_profile_based_param { 1029 u32 num_vdevs; 1030 u32 max_client_single; 1031 u32 max_client_dbs; 1032 u32 max_client_dbs_sbs; 1033 struct ath12k_dp_profile_params dp_params; 1034 }; 1035 1036 /* Master structure to hold the hw data which may be used in core module */ 1037 struct ath12k_base { 1038 enum ath12k_hw_rev hw_rev; 1039 struct platform_device *pdev; 1040 struct device *dev; 1041 struct ath12k_qmi qmi; 1042 struct ath12k_wmi_base wmi_ab; 1043 struct completion fw_ready; 1044 u8 device_id; 1045 int num_radios; 1046 /* HW channel counters frequency value in hertz common to all MACs */ 1047 u32 cc_freq_hz; 1048 1049 struct ath12k_dump_file_data *dump_data; 1050 size_t ath12k_coredump_len; 1051 struct work_struct dump_work; 1052 1053 struct ath12k_htc htc; 1054 1055 struct ath12k_dp dp; 1056 1057 void __iomem *mem; 1058 unsigned long mem_len; 1059 1060 void __iomem *mem_ce; 1061 u32 ce_remap_base_addr; 1062 bool ce_remap; 1063 1064 struct { 1065 enum ath12k_bus bus; 1066 const struct ath12k_hif_ops *ops; 1067 } hif; 1068 1069 struct { 1070 struct completion wakeup_completed; 1071 u32 wmi_conf_rx_decap_mode; 1072 } wow; 1073 1074 struct ath12k_ce ce; 1075 struct timer_list rx_replenish_retry; 1076 struct ath12k_hal hal; 1077 /* To synchronize core_start/core_stop */ 1078 struct mutex core_lock; 1079 /* Protects data like peers */ 1080 spinlock_t base_lock; 1081 1082 /* Single pdev device (struct ath12k_hw_params::single_pdev_only): 1083 * 1084 * Firmware maintains data for all bands but advertises a single 1085 * phy to the host which is stored as a single element in this 1086 * array. 1087 * 1088 * Other devices: 1089 * 1090 * This array will contain as many elements as the number of 1091 * radios. 1092 */ 1093 struct ath12k_pdev pdevs[MAX_RADIOS]; 1094 1095 /* struct ath12k_hw_params::single_pdev_only devices use this to 1096 * store phy specific data 1097 */ 1098 struct ath12k_fw_pdev fw_pdev[MAX_RADIOS]; 1099 u8 fw_pdev_count; 1100 1101 struct ath12k_pdev __rcu *pdevs_active[MAX_RADIOS]; 1102 1103 struct ath12k_wmi_hal_reg_capabilities_ext_arg hal_reg_cap[MAX_RADIOS]; 1104 unsigned long long free_vdev_map; 1105 unsigned long long free_vdev_stats_id_map; 1106 struct list_head peers; 1107 wait_queue_head_t peer_mapping_wq; 1108 u8 mac_addr[ETH_ALEN]; 1109 bool wmi_ready; 1110 u32 wlan_init_status; 1111 int irq_num[ATH12K_IRQ_NUM_MAX]; 1112 struct ath12k_ext_irq_grp ext_irq_grp[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 1113 struct napi_struct *napi; 1114 struct ath12k_wmi_target_cap_arg target_caps; 1115 u32 ext_service_bitmap[WMI_SERVICE_EXT_BM_SIZE]; 1116 bool pdevs_macaddr_valid; 1117 1118 const struct ath12k_hw_params *hw_params; 1119 1120 const struct firmware *cal_file; 1121 1122 /* Below regd's are protected by ab->data_lock */ 1123 /* This is the regd set for every radio 1124 * by the firmware during initialization 1125 */ 1126 struct ieee80211_regdomain *default_regd[MAX_RADIOS]; 1127 /* This regd is set during dynamic country setting 1128 * This may or may not be used during the runtime 1129 */ 1130 struct ieee80211_regdomain *new_regd[MAX_RADIOS]; 1131 1132 struct ath12k_reg_info *reg_info[MAX_RADIOS]; 1133 1134 /* Current DFS Regulatory */ 1135 enum ath12k_dfs_region dfs_region; 1136 struct ath12k_device_dp_stats device_stats; 1137 #ifdef CONFIG_ATH12K_DEBUGFS 1138 struct dentry *debugfs_soc; 1139 #endif 1140 1141 unsigned long dev_flags; 1142 struct completion driver_recovery; 1143 struct workqueue_struct *workqueue; 1144 struct work_struct restart_work; 1145 struct workqueue_struct *workqueue_aux; 1146 struct work_struct reset_work; 1147 atomic_t reset_count; 1148 atomic_t recovery_count; 1149 bool is_reset; 1150 struct completion reset_complete; 1151 /* continuous recovery fail count */ 1152 atomic_t fail_cont_count; 1153 unsigned long reset_fail_timeout; 1154 struct work_struct update_11d_work; 1155 u8 new_alpha2[2]; 1156 struct { 1157 /* protected by data_lock */ 1158 u32 fw_crash_counter; 1159 } stats; 1160 u32 pktlog_defs_checksum; 1161 1162 struct ath12k_dbring_cap *db_caps; 1163 u32 num_db_cap; 1164 1165 struct completion htc_suspend; 1166 1167 u64 fw_soc_drop_count; 1168 bool static_window_map; 1169 1170 struct work_struct rfkill_work; 1171 /* true means radio is on */ 1172 bool rfkill_radio_on; 1173 1174 struct { 1175 enum ath12k_bdf_search bdf_search; 1176 u32 vendor; 1177 u32 device; 1178 u32 subsystem_vendor; 1179 u32 subsystem_device; 1180 } id; 1181 1182 struct { 1183 u32 api_version; 1184 1185 const struct firmware *fw; 1186 const u8 *amss_data; 1187 size_t amss_len; 1188 const u8 *amss_dualmac_data; 1189 size_t amss_dualmac_len; 1190 const u8 *m3_data; 1191 size_t m3_len; 1192 1193 DECLARE_BITMAP(fw_features, ATH12K_FW_FEATURE_COUNT); 1194 bool fw_features_valid; 1195 } fw; 1196 1197 const struct hal_rx_ops *hal_rx_ops; 1198 1199 struct completion restart_completed; 1200 1201 #ifdef CONFIG_ACPI 1202 1203 struct { 1204 bool started; 1205 u32 func_bit; 1206 bool acpi_tas_enable; 1207 bool acpi_bios_sar_enable; 1208 bool acpi_disable_11be; 1209 bool acpi_disable_rfkill; 1210 bool acpi_cca_enable; 1211 bool acpi_band_edge_enable; 1212 bool acpi_enable_bdf; 1213 u32 bit_flag; 1214 char bdf_string[ATH12K_ACPI_BDF_MAX_LEN]; 1215 u8 tas_cfg[ATH12K_ACPI_DSM_TAS_CFG_SIZE]; 1216 u8 tas_sar_power_table[ATH12K_ACPI_DSM_TAS_DATA_SIZE]; 1217 u8 bios_sar_data[ATH12K_ACPI_DSM_BIOS_SAR_DATA_SIZE]; 1218 u8 geo_offset_data[ATH12K_ACPI_DSM_GEO_OFFSET_DATA_SIZE]; 1219 u8 cca_data[ATH12K_ACPI_DSM_CCA_DATA_SIZE]; 1220 u8 band_edge_power[ATH12K_ACPI_DSM_BAND_EDGE_DATA_SIZE]; 1221 } acpi; 1222 1223 #endif /* CONFIG_ACPI */ 1224 1225 struct notifier_block panic_nb; 1226 1227 struct ath12k_hw_group *ag; 1228 struct ath12k_wsi_info wsi_info; 1229 enum ath12k_firmware_mode fw_mode; 1230 struct ath12k_ftm_event_obj ftm_event_obj; 1231 bool hw_group_ref; 1232 1233 /* Denote whether MLO is possible within the device */ 1234 bool single_chip_mlo_support; 1235 1236 struct ath12k_reg_freq reg_freq_2ghz; 1237 struct ath12k_reg_freq reg_freq_5ghz; 1238 struct ath12k_reg_freq reg_freq_6ghz; 1239 const struct ath12k_mem_profile_based_param *profile_param; 1240 enum ath12k_qmi_mem_mode target_mem_mode; 1241 1242 /* must be last */ 1243 u8 drv_priv[] __aligned(sizeof(void *)); 1244 }; 1245 1246 struct ath12k_pdev_map { 1247 struct ath12k_base *ab; 1248 u8 pdev_idx; 1249 }; 1250 1251 struct ath12k_fw_stats_vdev { 1252 struct list_head list; 1253 1254 u32 vdev_id; 1255 u32 beacon_snr; 1256 u32 data_snr; 1257 u32 num_tx_frames[WLAN_MAX_AC]; 1258 u32 num_rx_frames; 1259 u32 num_tx_frames_retries[WLAN_MAX_AC]; 1260 u32 num_tx_frames_failures[WLAN_MAX_AC]; 1261 u32 num_rts_fail; 1262 u32 num_rts_success; 1263 u32 num_rx_err; 1264 u32 num_rx_discard; 1265 u32 num_tx_not_acked; 1266 u32 tx_rate_history[MAX_TX_RATE_VALUES]; 1267 u32 beacon_rssi_history[MAX_TX_RATE_VALUES]; 1268 }; 1269 1270 struct ath12k_fw_stats_bcn { 1271 struct list_head list; 1272 1273 u32 vdev_id; 1274 u32 tx_bcn_succ_cnt; 1275 u32 tx_bcn_outage_cnt; 1276 }; 1277 1278 struct ath12k_fw_stats_pdev { 1279 struct list_head list; 1280 1281 /* PDEV stats */ 1282 s32 ch_noise_floor; 1283 u32 tx_frame_count; 1284 u32 rx_frame_count; 1285 u32 rx_clear_count; 1286 u32 cycle_count; 1287 u32 phy_err_count; 1288 u32 chan_tx_power; 1289 u32 ack_rx_bad; 1290 u32 rts_bad; 1291 u32 rts_good; 1292 u32 fcs_bad; 1293 u32 no_beacons; 1294 u32 mib_int_count; 1295 1296 /* PDEV TX stats */ 1297 s32 comp_queued; 1298 s32 comp_delivered; 1299 s32 msdu_enqued; 1300 s32 mpdu_enqued; 1301 s32 wmm_drop; 1302 s32 local_enqued; 1303 s32 local_freed; 1304 s32 hw_queued; 1305 s32 hw_reaped; 1306 s32 underrun; 1307 s32 tx_abort; 1308 s32 mpdus_requed; 1309 u32 tx_ko; 1310 u32 data_rc; 1311 u32 self_triggers; 1312 u32 sw_retry_failure; 1313 u32 illgl_rate_phy_err; 1314 u32 pdev_cont_xretry; 1315 u32 pdev_tx_timeout; 1316 u32 pdev_resets; 1317 u32 stateless_tid_alloc_failure; 1318 u32 phy_underrun; 1319 u32 txop_ovf; 1320 1321 /* PDEV RX stats */ 1322 s32 mid_ppdu_route_change; 1323 s32 status_rcvd; 1324 s32 r0_frags; 1325 s32 r1_frags; 1326 s32 r2_frags; 1327 s32 r3_frags; 1328 s32 htt_msdus; 1329 s32 htt_mpdus; 1330 s32 loc_msdus; 1331 s32 loc_mpdus; 1332 s32 oversize_amsdu; 1333 s32 phy_errs; 1334 s32 phy_err_drop; 1335 s32 mpdu_errs; 1336 }; 1337 1338 int ath12k_core_qmi_firmware_ready(struct ath12k_base *ab); 1339 void ath12k_core_hw_group_cleanup(struct ath12k_hw_group *ag); 1340 int ath12k_core_pre_init(struct ath12k_base *ab); 1341 int ath12k_core_init(struct ath12k_base *ath12k); 1342 void ath12k_core_deinit(struct ath12k_base *ath12k); 1343 struct ath12k_base *ath12k_core_alloc(struct device *dev, size_t priv_size, 1344 enum ath12k_bus bus); 1345 void ath12k_core_free(struct ath12k_base *ath12k); 1346 int ath12k_core_fetch_board_data_api_1(struct ath12k_base *ab, 1347 struct ath12k_board_data *bd, 1348 char *filename); 1349 int ath12k_core_fetch_bdf(struct ath12k_base *ath12k, 1350 struct ath12k_board_data *bd); 1351 void ath12k_core_free_bdf(struct ath12k_base *ab, struct ath12k_board_data *bd); 1352 int ath12k_core_fetch_regdb(struct ath12k_base *ab, struct ath12k_board_data *bd); 1353 int ath12k_core_check_dt(struct ath12k_base *ath12k); 1354 int ath12k_core_check_smbios(struct ath12k_base *ab); 1355 void ath12k_core_halt(struct ath12k *ar); 1356 int ath12k_core_resume_early(struct ath12k_base *ab); 1357 int ath12k_core_resume(struct ath12k_base *ab); 1358 int ath12k_core_suspend(struct ath12k_base *ab); 1359 int ath12k_core_suspend_late(struct ath12k_base *ab); 1360 void ath12k_core_hw_group_unassign(struct ath12k_base *ab); 1361 u8 ath12k_get_num_partner_link(struct ath12k *ar); 1362 1363 const struct firmware *ath12k_core_firmware_request(struct ath12k_base *ab, 1364 const char *filename); 1365 u32 ath12k_core_get_max_station_per_radio(struct ath12k_base *ab); 1366 u32 ath12k_core_get_max_peers_per_radio(struct ath12k_base *ab); 1367 1368 void ath12k_core_hw_group_set_mlo_capable(struct ath12k_hw_group *ag); 1369 void ath12k_fw_stats_init(struct ath12k *ar); 1370 void ath12k_fw_stats_bcn_free(struct list_head *head); 1371 void ath12k_fw_stats_free(struct ath12k_fw_stats *stats); 1372 void ath12k_fw_stats_reset(struct ath12k *ar); 1373 struct reserved_mem *ath12k_core_get_reserved_mem(struct ath12k_base *ab, 1374 int index); 1375 enum ath12k_qmi_mem_mode ath12k_core_get_memory_mode(struct ath12k_base *ab); 1376 1377 static inline const char *ath12k_scan_state_str(enum ath12k_scan_state state) 1378 { 1379 switch (state) { 1380 case ATH12K_SCAN_IDLE: 1381 return "idle"; 1382 case ATH12K_SCAN_STARTING: 1383 return "starting"; 1384 case ATH12K_SCAN_RUNNING: 1385 return "running"; 1386 case ATH12K_SCAN_ABORTING: 1387 return "aborting"; 1388 } 1389 1390 return "unknown"; 1391 } 1392 1393 static inline struct ath12k_skb_cb *ATH12K_SKB_CB(struct sk_buff *skb) 1394 { 1395 BUILD_BUG_ON(sizeof(struct ath12k_skb_cb) > 1396 IEEE80211_TX_INFO_DRIVER_DATA_SIZE); 1397 return (struct ath12k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data; 1398 } 1399 1400 static inline struct ath12k_skb_rxcb *ATH12K_SKB_RXCB(struct sk_buff *skb) 1401 { 1402 BUILD_BUG_ON(sizeof(struct ath12k_skb_rxcb) > sizeof(skb->cb)); 1403 return (struct ath12k_skb_rxcb *)skb->cb; 1404 } 1405 1406 static inline struct ath12k_vif *ath12k_vif_to_ahvif(struct ieee80211_vif *vif) 1407 { 1408 return (struct ath12k_vif *)vif->drv_priv; 1409 } 1410 1411 static inline struct ath12k_sta *ath12k_sta_to_ahsta(struct ieee80211_sta *sta) 1412 { 1413 return (struct ath12k_sta *)sta->drv_priv; 1414 } 1415 1416 static inline struct ieee80211_sta *ath12k_ahsta_to_sta(struct ath12k_sta *ahsta) 1417 { 1418 return container_of((void *)ahsta, struct ieee80211_sta, drv_priv); 1419 } 1420 1421 static inline struct ieee80211_vif *ath12k_ahvif_to_vif(struct ath12k_vif *ahvif) 1422 { 1423 return container_of((void *)ahvif, struct ieee80211_vif, drv_priv); 1424 } 1425 1426 static inline struct ath12k *ath12k_ab_to_ar(struct ath12k_base *ab, 1427 int mac_id) 1428 { 1429 return ab->pdevs[ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id)].ar; 1430 } 1431 1432 static inline void ath12k_core_create_firmware_path(struct ath12k_base *ab, 1433 const char *filename, 1434 void *buf, size_t buf_len) 1435 { 1436 const char *fw_name = NULL; 1437 1438 of_property_read_string(ab->dev->of_node, "firmware-name", &fw_name); 1439 1440 if (fw_name && strncmp(filename, "board", 5)) 1441 snprintf(buf, buf_len, "%s/%s/%s/%s", ATH12K_FW_DIR, 1442 ab->hw_params->fw.dir, fw_name, filename); 1443 else 1444 snprintf(buf, buf_len, "%s/%s/%s", ATH12K_FW_DIR, 1445 ab->hw_params->fw.dir, filename); 1446 } 1447 1448 static inline const char *ath12k_bus_str(enum ath12k_bus bus) 1449 { 1450 switch (bus) { 1451 case ATH12K_BUS_PCI: 1452 return "pci"; 1453 case ATH12K_BUS_AHB: 1454 return "ahb"; 1455 } 1456 1457 return "unknown"; 1458 } 1459 1460 static inline struct ath12k_hw *ath12k_hw_to_ah(struct ieee80211_hw *hw) 1461 { 1462 return hw->priv; 1463 } 1464 1465 static inline struct ath12k *ath12k_ah_to_ar(struct ath12k_hw *ah, u8 hw_link_id) 1466 { 1467 if (WARN(hw_link_id >= ah->num_radio, 1468 "bad hw link id %d, so switch to default link\n", hw_link_id)) 1469 hw_link_id = 0; 1470 1471 return &ah->radio[hw_link_id]; 1472 } 1473 1474 static inline struct ath12k_hw *ath12k_ar_to_ah(struct ath12k *ar) 1475 { 1476 return ar->ah; 1477 } 1478 1479 static inline struct ieee80211_hw *ath12k_ar_to_hw(struct ath12k *ar) 1480 { 1481 return ar->ah->hw; 1482 } 1483 1484 #define for_each_ar(ah, ar, index) \ 1485 for ((index) = 0; ((index) < (ah)->num_radio && \ 1486 ((ar) = &(ah)->radio[(index)])); (index)++) 1487 1488 static inline struct ath12k_hw *ath12k_ag_to_ah(struct ath12k_hw_group *ag, int idx) 1489 { 1490 return ag->ah[idx]; 1491 } 1492 1493 static inline void ath12k_ag_set_ah(struct ath12k_hw_group *ag, int idx, 1494 struct ath12k_hw *ah) 1495 { 1496 ag->ah[idx] = ah; 1497 } 1498 1499 static inline struct ath12k_hw_group *ath12k_ab_to_ag(struct ath12k_base *ab) 1500 { 1501 return ab->ag; 1502 } 1503 1504 static inline struct ath12k_base *ath12k_ag_to_ab(struct ath12k_hw_group *ag, 1505 u8 device_id) 1506 { 1507 return ag->ab[device_id]; 1508 } 1509 1510 static inline s32 ath12k_pdev_get_noise_floor(struct ath12k *ar) 1511 { 1512 lockdep_assert_held(&ar->data_lock); 1513 1514 return ar->rssi_info.noise_floor; 1515 } 1516 1517 #endif /* _CORE_H_ */ 1518