1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef ATH12K_CORE_H 8 #define ATH12K_CORE_H 9 10 #include <linux/types.h> 11 #include <linux/interrupt.h> 12 #include <linux/irq.h> 13 #include <linux/bitfield.h> 14 #include <linux/dmi.h> 15 #include <linux/ctype.h> 16 #include "qmi.h" 17 #include "htc.h" 18 #include "wmi.h" 19 #include "hal.h" 20 #include "dp.h" 21 #include "ce.h" 22 #include "mac.h" 23 #include "hw.h" 24 #include "hal_rx.h" 25 #include "reg.h" 26 #include "dbring.h" 27 28 #define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK) 29 30 #define ATH12K_TX_MGMT_NUM_PENDING_MAX 512 31 32 #define ATH12K_TX_MGMT_TARGET_MAX_SUPPORT_WMI 64 33 34 /* Pending management packets threshold for dropping probe responses */ 35 #define ATH12K_PRB_RSP_DROP_THRESHOLD ((ATH12K_TX_MGMT_TARGET_MAX_SUPPORT_WMI * 3) / 4) 36 37 /* SMBIOS type containing Board Data File Name Extension */ 38 #define ATH12K_SMBIOS_BDF_EXT_TYPE 0xF8 39 40 /* SMBIOS type structure length (excluding strings-set) */ 41 #define ATH12K_SMBIOS_BDF_EXT_LENGTH 0x9 42 43 /* The magic used by QCA spec */ 44 #define ATH12K_SMBIOS_BDF_EXT_MAGIC "BDF_" 45 46 #define ATH12K_INVALID_HW_MAC_ID 0xFF 47 #define ATH12K_RX_RATE_TABLE_NUM 320 48 #define ATH12K_RX_RATE_TABLE_11AX_NUM 576 49 50 #define ATH12K_MON_TIMER_INTERVAL 10 51 #define ATH12K_RESET_TIMEOUT_HZ (20 * HZ) 52 #define ATH12K_RESET_MAX_FAIL_COUNT_FIRST 3 53 #define ATH12K_RESET_MAX_FAIL_COUNT_FINAL 5 54 #define ATH12K_RESET_FAIL_TIMEOUT_HZ (20 * HZ) 55 #define ATH12K_RECONFIGURE_TIMEOUT_HZ (10 * HZ) 56 #define ATH12K_RECOVER_START_TIMEOUT_HZ (20 * HZ) 57 58 enum wme_ac { 59 WME_AC_BE, 60 WME_AC_BK, 61 WME_AC_VI, 62 WME_AC_VO, 63 WME_NUM_AC 64 }; 65 66 #define ATH12K_HT_MCS_MAX 7 67 #define ATH12K_VHT_MCS_MAX 9 68 #define ATH12K_HE_MCS_MAX 11 69 70 enum ath12k_crypt_mode { 71 /* Only use hardware crypto engine */ 72 ATH12K_CRYPT_MODE_HW, 73 /* Only use software crypto */ 74 ATH12K_CRYPT_MODE_SW, 75 }; 76 77 static inline enum wme_ac ath12k_tid_to_ac(u32 tid) 78 { 79 return (((tid == 0) || (tid == 3)) ? WME_AC_BE : 80 ((tid == 1) || (tid == 2)) ? WME_AC_BK : 81 ((tid == 4) || (tid == 5)) ? WME_AC_VI : 82 WME_AC_VO); 83 } 84 85 enum ath12k_skb_flags { 86 ATH12K_SKB_HW_80211_ENCAP = BIT(0), 87 ATH12K_SKB_CIPHER_SET = BIT(1), 88 }; 89 90 struct ath12k_skb_cb { 91 dma_addr_t paddr; 92 struct ath12k *ar; 93 struct ieee80211_vif *vif; 94 dma_addr_t paddr_ext_desc; 95 u32 cipher; 96 u8 flags; 97 }; 98 99 struct ath12k_skb_rxcb { 100 dma_addr_t paddr; 101 bool is_first_msdu; 102 bool is_last_msdu; 103 bool is_continuation; 104 bool is_mcbc; 105 bool is_eapol; 106 struct hal_rx_desc *rx_desc; 107 u8 err_rel_src; 108 u8 err_code; 109 u8 mac_id; 110 u8 unmapped; 111 u8 is_frag; 112 u8 tid; 113 u16 peer_id; 114 }; 115 116 enum ath12k_hw_rev { 117 ATH12K_HW_QCN9274_HW10, 118 ATH12K_HW_QCN9274_HW20, 119 ATH12K_HW_WCN7850_HW20 120 }; 121 122 enum ath12k_firmware_mode { 123 /* the default mode, standard 802.11 functionality */ 124 ATH12K_FIRMWARE_MODE_NORMAL, 125 126 /* factory tests etc */ 127 ATH12K_FIRMWARE_MODE_FTM, 128 }; 129 130 #define ATH12K_IRQ_NUM_MAX 57 131 #define ATH12K_EXT_IRQ_NUM_MAX 16 132 133 struct ath12k_ext_irq_grp { 134 struct ath12k_base *ab; 135 u32 irqs[ATH12K_EXT_IRQ_NUM_MAX]; 136 u32 num_irq; 137 u32 grp_id; 138 u64 timestamp; 139 struct napi_struct napi; 140 struct net_device napi_ndev; 141 }; 142 143 struct ath12k_smbios_bdf { 144 struct dmi_header hdr; 145 u32 padding; 146 u8 bdf_enabled; 147 u8 bdf_ext[]; 148 } __packed; 149 150 #define HEHANDLE_CAP_PHYINFO_SIZE 3 151 #define HECAP_PHYINFO_SIZE 9 152 #define HECAP_MACINFO_SIZE 5 153 #define HECAP_TXRX_MCS_NSS_SIZE 2 154 #define HECAP_PPET16_PPET8_MAX_SIZE 25 155 156 #define HE_PPET16_PPET8_SIZE 8 157 158 /* 802.11ax PPE (PPDU packet Extension) threshold */ 159 struct he_ppe_threshold { 160 u32 numss_m1; 161 u32 ru_mask; 162 u32 ppet16_ppet8_ru3_ru0[HE_PPET16_PPET8_SIZE]; 163 }; 164 165 struct ath12k_he { 166 u8 hecap_macinfo[HECAP_MACINFO_SIZE]; 167 u32 hecap_rxmcsnssmap; 168 u32 hecap_txmcsnssmap; 169 u32 hecap_phyinfo[HEHANDLE_CAP_PHYINFO_SIZE]; 170 struct he_ppe_threshold hecap_ppet; 171 u32 heop_param; 172 }; 173 174 #define MAX_RADIOS 3 175 176 enum { 177 WMI_HOST_TP_SCALE_MAX = 0, 178 WMI_HOST_TP_SCALE_50 = 1, 179 WMI_HOST_TP_SCALE_25 = 2, 180 WMI_HOST_TP_SCALE_12 = 3, 181 WMI_HOST_TP_SCALE_MIN = 4, 182 WMI_HOST_TP_SCALE_SIZE = 5, 183 }; 184 185 enum ath12k_scan_state { 186 ATH12K_SCAN_IDLE, 187 ATH12K_SCAN_STARTING, 188 ATH12K_SCAN_RUNNING, 189 ATH12K_SCAN_ABORTING, 190 }; 191 192 enum ath12k_dev_flags { 193 ATH12K_CAC_RUNNING, 194 ATH12K_FLAG_CRASH_FLUSH, 195 ATH12K_FLAG_RAW_MODE, 196 ATH12K_FLAG_HW_CRYPTO_DISABLED, 197 ATH12K_FLAG_RECOVERY, 198 ATH12K_FLAG_UNREGISTERING, 199 ATH12K_FLAG_REGISTERED, 200 ATH12K_FLAG_QMI_FAIL, 201 ATH12K_FLAG_HTC_SUSPEND_COMPLETE, 202 }; 203 204 enum ath12k_monitor_flags { 205 ATH12K_FLAG_MONITOR_ENABLED, 206 }; 207 208 struct ath12k_vif { 209 u32 vdev_id; 210 enum wmi_vdev_type vdev_type; 211 enum wmi_vdev_subtype vdev_subtype; 212 u32 beacon_interval; 213 u32 dtim_period; 214 u16 ast_hash; 215 u16 ast_idx; 216 u16 tcl_metadata; 217 u8 hal_addr_search_flags; 218 u8 search_type; 219 220 struct ath12k *ar; 221 struct ieee80211_vif *vif; 222 223 int bank_id; 224 u8 vdev_id_check_en; 225 226 struct wmi_wmm_params_all_arg wmm_params; 227 struct list_head list; 228 union { 229 struct { 230 u32 uapsd; 231 } sta; 232 struct { 233 /* 127 stations; wmi limit */ 234 u8 tim_bitmap[16]; 235 u8 tim_len; 236 u32 ssid_len; 237 u8 ssid[IEEE80211_MAX_SSID_LEN]; 238 bool hidden_ssid; 239 /* P2P_IE with NoA attribute for P2P_GO case */ 240 u32 noa_len; 241 u8 *noa_data; 242 } ap; 243 } u; 244 245 bool is_started; 246 bool is_up; 247 u32 aid; 248 u8 bssid[ETH_ALEN]; 249 struct cfg80211_bitrate_mask bitrate_mask; 250 int num_legacy_stations; 251 int rtscts_prot_mode; 252 int txpower; 253 bool rsnie_present; 254 bool wpaie_present; 255 struct ieee80211_chanctx_conf chanctx; 256 u32 key_cipher; 257 u8 tx_encap_type; 258 u8 vdev_stats_id; 259 u32 punct_bitmap; 260 }; 261 262 struct ath12k_vif_iter { 263 u32 vdev_id; 264 struct ath12k_vif *arvif; 265 }; 266 267 #define HAL_AST_IDX_INVALID 0xFFFF 268 #define HAL_RX_MAX_MCS 12 269 #define HAL_RX_MAX_MCS_HT 31 270 #define HAL_RX_MAX_MCS_VHT 9 271 #define HAL_RX_MAX_MCS_HE 11 272 #define HAL_RX_MAX_NSS 8 273 #define HAL_RX_MAX_NUM_LEGACY_RATES 12 274 #define ATH12K_RX_RATE_TABLE_11AX_NUM 576 275 #define ATH12K_RX_RATE_TABLE_NUM 320 276 277 struct ath12k_rx_peer_rate_stats { 278 u64 ht_mcs_count[HAL_RX_MAX_MCS_HT + 1]; 279 u64 vht_mcs_count[HAL_RX_MAX_MCS_VHT + 1]; 280 u64 he_mcs_count[HAL_RX_MAX_MCS_HE + 1]; 281 u64 nss_count[HAL_RX_MAX_NSS]; 282 u64 bw_count[HAL_RX_BW_MAX]; 283 u64 gi_count[HAL_RX_GI_MAX]; 284 u64 legacy_count[HAL_RX_MAX_NUM_LEGACY_RATES]; 285 u64 rx_rate[ATH12K_RX_RATE_TABLE_11AX_NUM]; 286 }; 287 288 struct ath12k_rx_peer_stats { 289 u64 num_msdu; 290 u64 num_mpdu_fcs_ok; 291 u64 num_mpdu_fcs_err; 292 u64 tcp_msdu_count; 293 u64 udp_msdu_count; 294 u64 other_msdu_count; 295 u64 ampdu_msdu_count; 296 u64 non_ampdu_msdu_count; 297 u64 stbc_count; 298 u64 beamformed_count; 299 u64 mcs_count[HAL_RX_MAX_MCS + 1]; 300 u64 nss_count[HAL_RX_MAX_NSS]; 301 u64 bw_count[HAL_RX_BW_MAX]; 302 u64 gi_count[HAL_RX_GI_MAX]; 303 u64 coding_count[HAL_RX_SU_MU_CODING_MAX]; 304 u64 tid_count[IEEE80211_NUM_TIDS + 1]; 305 u64 pream_cnt[HAL_RX_PREAMBLE_MAX]; 306 u64 reception_type[HAL_RX_RECEPTION_TYPE_MAX]; 307 u64 rx_duration; 308 u64 dcm_count; 309 u64 ru_alloc_cnt[HAL_RX_RU_ALLOC_TYPE_MAX]; 310 struct ath12k_rx_peer_rate_stats pkt_stats; 311 struct ath12k_rx_peer_rate_stats byte_stats; 312 }; 313 314 #define ATH12K_HE_MCS_NUM 12 315 #define ATH12K_VHT_MCS_NUM 10 316 #define ATH12K_BW_NUM 5 317 #define ATH12K_NSS_NUM 4 318 #define ATH12K_LEGACY_NUM 12 319 #define ATH12K_GI_NUM 4 320 #define ATH12K_HT_MCS_NUM 32 321 322 enum ath12k_pkt_rx_err { 323 ATH12K_PKT_RX_ERR_FCS, 324 ATH12K_PKT_RX_ERR_TKIP, 325 ATH12K_PKT_RX_ERR_CRYPT, 326 ATH12K_PKT_RX_ERR_PEER_IDX_INVAL, 327 ATH12K_PKT_RX_ERR_MAX, 328 }; 329 330 enum ath12k_ampdu_subfrm_num { 331 ATH12K_AMPDU_SUBFRM_NUM_10, 332 ATH12K_AMPDU_SUBFRM_NUM_20, 333 ATH12K_AMPDU_SUBFRM_NUM_30, 334 ATH12K_AMPDU_SUBFRM_NUM_40, 335 ATH12K_AMPDU_SUBFRM_NUM_50, 336 ATH12K_AMPDU_SUBFRM_NUM_60, 337 ATH12K_AMPDU_SUBFRM_NUM_MORE, 338 ATH12K_AMPDU_SUBFRM_NUM_MAX, 339 }; 340 341 enum ath12k_amsdu_subfrm_num { 342 ATH12K_AMSDU_SUBFRM_NUM_1, 343 ATH12K_AMSDU_SUBFRM_NUM_2, 344 ATH12K_AMSDU_SUBFRM_NUM_3, 345 ATH12K_AMSDU_SUBFRM_NUM_4, 346 ATH12K_AMSDU_SUBFRM_NUM_MORE, 347 ATH12K_AMSDU_SUBFRM_NUM_MAX, 348 }; 349 350 enum ath12k_counter_type { 351 ATH12K_COUNTER_TYPE_BYTES, 352 ATH12K_COUNTER_TYPE_PKTS, 353 ATH12K_COUNTER_TYPE_MAX, 354 }; 355 356 enum ath12k_stats_type { 357 ATH12K_STATS_TYPE_SUCC, 358 ATH12K_STATS_TYPE_FAIL, 359 ATH12K_STATS_TYPE_RETRY, 360 ATH12K_STATS_TYPE_AMPDU, 361 ATH12K_STATS_TYPE_MAX, 362 }; 363 364 struct ath12k_htt_data_stats { 365 u64 legacy[ATH12K_COUNTER_TYPE_MAX][ATH12K_LEGACY_NUM]; 366 u64 ht[ATH12K_COUNTER_TYPE_MAX][ATH12K_HT_MCS_NUM]; 367 u64 vht[ATH12K_COUNTER_TYPE_MAX][ATH12K_VHT_MCS_NUM]; 368 u64 he[ATH12K_COUNTER_TYPE_MAX][ATH12K_HE_MCS_NUM]; 369 u64 bw[ATH12K_COUNTER_TYPE_MAX][ATH12K_BW_NUM]; 370 u64 nss[ATH12K_COUNTER_TYPE_MAX][ATH12K_NSS_NUM]; 371 u64 gi[ATH12K_COUNTER_TYPE_MAX][ATH12K_GI_NUM]; 372 u64 transmit_type[ATH12K_COUNTER_TYPE_MAX][HAL_RX_RECEPTION_TYPE_MAX]; 373 u64 ru_loc[ATH12K_COUNTER_TYPE_MAX][HAL_RX_RU_ALLOC_TYPE_MAX]; 374 }; 375 376 struct ath12k_htt_tx_stats { 377 struct ath12k_htt_data_stats stats[ATH12K_STATS_TYPE_MAX]; 378 u64 tx_duration; 379 u64 ba_fails; 380 u64 ack_fails; 381 u16 ru_start; 382 u16 ru_tones; 383 u32 mu_group[MAX_MU_GROUP_ID]; 384 }; 385 386 struct ath12k_per_ppdu_tx_stats { 387 u16 succ_pkts; 388 u16 failed_pkts; 389 u16 retry_pkts; 390 u32 succ_bytes; 391 u32 failed_bytes; 392 u32 retry_bytes; 393 }; 394 395 struct ath12k_wbm_tx_stats { 396 u64 wbm_tx_comp_stats[HAL_WBM_REL_HTT_TX_COMP_STATUS_MAX]; 397 }; 398 399 struct ath12k_sta { 400 struct ath12k_vif *arvif; 401 402 /* the following are protected by ar->data_lock */ 403 u32 changed; /* IEEE80211_RC_* */ 404 u32 bw; 405 u32 nss; 406 u32 smps; 407 enum hal_pn_type pn_type; 408 409 struct work_struct update_wk; 410 struct rate_info txrate; 411 struct rate_info last_txrate; 412 u64 rx_duration; 413 u64 tx_duration; 414 u8 rssi_comb; 415 struct ath12k_rx_peer_stats *rx_stats; 416 struct ath12k_wbm_tx_stats *wbm_tx_stats; 417 u32 bw_prev; 418 }; 419 420 #define ATH12K_MIN_5G_FREQ 4150 421 #define ATH12K_MIN_6G_FREQ 5945 422 #define ATH12K_MAX_6G_FREQ 7115 423 #define ATH12K_NUM_CHANS 100 424 #define ATH12K_MAX_5G_CHAN 173 425 426 enum ath12k_state { 427 ATH12K_STATE_OFF, 428 ATH12K_STATE_ON, 429 ATH12K_STATE_RESTARTING, 430 ATH12K_STATE_RESTARTED, 431 ATH12K_STATE_WEDGED, 432 /* Add other states as required */ 433 }; 434 435 /* Antenna noise floor */ 436 #define ATH12K_DEFAULT_NOISE_FLOOR -95 437 438 struct ath12k_fw_stats { 439 u32 pdev_id; 440 u32 stats_id; 441 struct list_head pdevs; 442 struct list_head vdevs; 443 struct list_head bcn; 444 }; 445 446 struct ath12k_per_peer_tx_stats { 447 u32 succ_bytes; 448 u32 retry_bytes; 449 u32 failed_bytes; 450 u32 duration; 451 u16 succ_pkts; 452 u16 retry_pkts; 453 u16 failed_pkts; 454 u16 ru_start; 455 u16 ru_tones; 456 u8 ba_fails; 457 u8 ppdu_type; 458 u32 mu_grpid; 459 u32 mu_pos; 460 bool is_ampdu; 461 }; 462 463 #define ATH12K_FLUSH_TIMEOUT (5 * HZ) 464 #define ATH12K_VDEV_DELETE_TIMEOUT_HZ (5 * HZ) 465 466 struct ath12k { 467 struct ath12k_base *ab; 468 struct ath12k_pdev *pdev; 469 struct ieee80211_hw *hw; 470 struct ieee80211_ops *ops; 471 struct ath12k_wmi_pdev *wmi; 472 struct ath12k_pdev_dp dp; 473 u8 mac_addr[ETH_ALEN]; 474 u32 ht_cap_info; 475 u32 vht_cap_info; 476 struct ath12k_he ar_he; 477 enum ath12k_state state; 478 bool supports_6ghz; 479 struct { 480 struct completion started; 481 struct completion completed; 482 struct completion on_channel; 483 struct delayed_work timeout; 484 enum ath12k_scan_state state; 485 bool is_roc; 486 int vdev_id; 487 int roc_freq; 488 bool roc_notify; 489 } scan; 490 491 struct { 492 struct ieee80211_supported_band sbands[NUM_NL80211_BANDS]; 493 struct ieee80211_sband_iftype_data 494 iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES]; 495 } mac; 496 497 unsigned long dev_flags; 498 unsigned int filter_flags; 499 unsigned long monitor_flags; 500 u32 min_tx_power; 501 u32 max_tx_power; 502 u32 txpower_limit_2g; 503 u32 txpower_limit_5g; 504 u32 txpower_scale; 505 u32 power_scale; 506 u32 chan_tx_pwr; 507 u32 num_stations; 508 u32 max_num_stations; 509 bool monitor_present; 510 /* To synchronize concurrent synchronous mac80211 callback operations, 511 * concurrent debugfs configuration and concurrent FW statistics events. 512 */ 513 struct mutex conf_mutex; 514 /* protects the radio specific data like debug stats, ppdu_stats_info stats, 515 * vdev_stop_status info, scan data, ath12k_sta info, ath12k_vif info, 516 * channel context data, survey info, test mode data. 517 */ 518 spinlock_t data_lock; 519 520 struct list_head arvifs; 521 /* should never be NULL; needed for regular htt rx */ 522 struct ieee80211_channel *rx_channel; 523 524 /* valid during scan; needed for mgmt rx during scan */ 525 struct ieee80211_channel *scan_channel; 526 527 u8 cfg_tx_chainmask; 528 u8 cfg_rx_chainmask; 529 u8 num_rx_chains; 530 u8 num_tx_chains; 531 /* pdev_idx starts from 0 whereas pdev->pdev_id starts with 1 */ 532 u8 pdev_idx; 533 u8 lmac_id; 534 535 struct completion peer_assoc_done; 536 struct completion peer_delete_done; 537 538 int install_key_status; 539 struct completion install_key_done; 540 541 int last_wmi_vdev_start_status; 542 struct completion vdev_setup_done; 543 struct completion vdev_delete_done; 544 545 int num_peers; 546 int max_num_peers; 547 u32 num_started_vdevs; 548 u32 num_created_vdevs; 549 unsigned long long allocated_vdev_map; 550 551 struct idr txmgmt_idr; 552 /* protects txmgmt_idr data */ 553 spinlock_t txmgmt_idr_lock; 554 atomic_t num_pending_mgmt_tx; 555 wait_queue_head_t txmgmt_empty_waitq; 556 557 /* cycle count is reported twice for each visited channel during scan. 558 * access protected by data_lock 559 */ 560 u32 survey_last_rx_clear_count; 561 u32 survey_last_cycle_count; 562 563 /* Channel info events are expected to come in pairs without and with 564 * COMPLETE flag set respectively for each channel visit during scan. 565 * 566 * However there are deviations from this rule. This flag is used to 567 * avoid reporting garbage data. 568 */ 569 bool ch_info_can_report_survey; 570 struct survey_info survey[ATH12K_NUM_CHANS]; 571 struct completion bss_survey_done; 572 573 struct work_struct regd_update_work; 574 575 struct work_struct wmi_mgmt_tx_work; 576 struct sk_buff_head wmi_mgmt_tx_queue; 577 578 struct ath12k_per_peer_tx_stats peer_tx_stats; 579 struct list_head ppdu_stats_info; 580 u32 ppdu_stat_list_depth; 581 582 struct ath12k_per_peer_tx_stats cached_stats; 583 u32 last_ppdu_id; 584 u32 cached_ppdu_id; 585 586 bool dfs_block_radar_events; 587 bool monitor_conf_enabled; 588 bool monitor_vdev_created; 589 bool monitor_started; 590 int monitor_vdev_id; 591 }; 592 593 struct ath12k_band_cap { 594 u32 phy_id; 595 u32 max_bw_supported; 596 u32 ht_cap_info; 597 u32 he_cap_info[2]; 598 u32 he_mcs; 599 u32 he_cap_phy_info[PSOC_HOST_MAX_PHY_SIZE]; 600 struct ath12k_wmi_ppe_threshold_arg he_ppet; 601 u16 he_6ghz_capa; 602 u32 eht_cap_mac_info[WMI_MAX_EHTCAP_MAC_SIZE]; 603 u32 eht_cap_phy_info[WMI_MAX_EHTCAP_PHY_SIZE]; 604 u32 eht_mcs_20_only; 605 u32 eht_mcs_80; 606 u32 eht_mcs_160; 607 u32 eht_mcs_320; 608 struct ath12k_wmi_ppe_threshold_arg eht_ppet; 609 u32 eht_cap_info_internal; 610 }; 611 612 struct ath12k_pdev_cap { 613 u32 supported_bands; 614 u32 ampdu_density; 615 u32 vht_cap; 616 u32 vht_mcs; 617 u32 he_mcs; 618 u32 tx_chain_mask; 619 u32 rx_chain_mask; 620 u32 tx_chain_mask_shift; 621 u32 rx_chain_mask_shift; 622 struct ath12k_band_cap band[NUM_NL80211_BANDS]; 623 }; 624 625 struct mlo_timestamp { 626 u32 info; 627 u32 sync_timestamp_lo_us; 628 u32 sync_timestamp_hi_us; 629 u32 mlo_offset_lo; 630 u32 mlo_offset_hi; 631 u32 mlo_offset_clks; 632 u32 mlo_comp_clks; 633 u32 mlo_comp_timer; 634 }; 635 636 struct ath12k_pdev { 637 struct ath12k *ar; 638 u32 pdev_id; 639 struct ath12k_pdev_cap cap; 640 u8 mac_addr[ETH_ALEN]; 641 struct mlo_timestamp timestamp; 642 }; 643 644 struct ath12k_fw_pdev { 645 u32 pdev_id; 646 u32 phy_id; 647 u32 supported_bands; 648 }; 649 650 struct ath12k_board_data { 651 const struct firmware *fw; 652 const void *data; 653 size_t len; 654 }; 655 656 struct ath12k_soc_dp_tx_err_stats { 657 /* TCL Ring Descriptor unavailable */ 658 u32 desc_na[DP_TCL_NUM_RING_MAX]; 659 /* Other failures during dp_tx due to mem allocation failure 660 * idr unavailable etc. 661 */ 662 atomic_t misc_fail; 663 }; 664 665 struct ath12k_soc_dp_stats { 666 u32 err_ring_pkts; 667 u32 invalid_rbm; 668 u32 rxdma_error[HAL_REO_ENTR_RING_RXDMA_ECODE_MAX]; 669 u32 reo_error[HAL_REO_DEST_RING_ERROR_CODE_MAX]; 670 u32 hal_reo_error[DP_REO_DST_RING_MAX]; 671 struct ath12k_soc_dp_tx_err_stats tx_err; 672 }; 673 674 /* Master structure to hold the hw data which may be used in core module */ 675 struct ath12k_base { 676 enum ath12k_hw_rev hw_rev; 677 struct platform_device *pdev; 678 struct device *dev; 679 struct ath12k_qmi qmi; 680 struct ath12k_wmi_base wmi_ab; 681 struct completion fw_ready; 682 int num_radios; 683 /* HW channel counters frequency value in hertz common to all MACs */ 684 u32 cc_freq_hz; 685 686 struct ath12k_htc htc; 687 688 struct ath12k_dp dp; 689 690 void __iomem *mem; 691 unsigned long mem_len; 692 693 struct { 694 enum ath12k_bus bus; 695 const struct ath12k_hif_ops *ops; 696 } hif; 697 698 struct ath12k_ce ce; 699 struct timer_list rx_replenish_retry; 700 struct ath12k_hal hal; 701 /* To synchronize core_start/core_stop */ 702 struct mutex core_lock; 703 /* Protects data like peers */ 704 spinlock_t base_lock; 705 706 /* Single pdev device (struct ath12k_hw_params::single_pdev_only): 707 * 708 * Firmware maintains data for all bands but advertises a single 709 * phy to the host which is stored as a single element in this 710 * array. 711 * 712 * Other devices: 713 * 714 * This array will contain as many elements as the number of 715 * radios. 716 */ 717 struct ath12k_pdev pdevs[MAX_RADIOS]; 718 719 /* struct ath12k_hw_params::single_pdev_only devices use this to 720 * store phy specific data 721 */ 722 struct ath12k_fw_pdev fw_pdev[MAX_RADIOS]; 723 u8 fw_pdev_count; 724 725 struct ath12k_pdev __rcu *pdevs_active[MAX_RADIOS]; 726 struct ath12k_wmi_hal_reg_capabilities_ext_arg hal_reg_cap[MAX_RADIOS]; 727 unsigned long long free_vdev_map; 728 unsigned long long free_vdev_stats_id_map; 729 struct list_head peers; 730 wait_queue_head_t peer_mapping_wq; 731 u8 mac_addr[ETH_ALEN]; 732 bool wmi_ready; 733 u32 wlan_init_status; 734 int irq_num[ATH12K_IRQ_NUM_MAX]; 735 struct ath12k_ext_irq_grp ext_irq_grp[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 736 struct napi_struct *napi; 737 struct ath12k_wmi_target_cap_arg target_caps; 738 u32 ext_service_bitmap[WMI_SERVICE_EXT_BM_SIZE]; 739 bool pdevs_macaddr_valid; 740 741 const struct ath12k_hw_params *hw_params; 742 743 const struct firmware *cal_file; 744 745 /* Below regd's are protected by ab->data_lock */ 746 /* This is the regd set for every radio 747 * by the firmware during initialization 748 */ 749 struct ieee80211_regdomain *default_regd[MAX_RADIOS]; 750 /* This regd is set during dynamic country setting 751 * This may or may not be used during the runtime 752 */ 753 struct ieee80211_regdomain *new_regd[MAX_RADIOS]; 754 755 /* Current DFS Regulatory */ 756 enum ath12k_dfs_region dfs_region; 757 struct ath12k_soc_dp_stats soc_stats; 758 759 unsigned long dev_flags; 760 struct completion driver_recovery; 761 struct workqueue_struct *workqueue; 762 struct work_struct restart_work; 763 struct workqueue_struct *workqueue_aux; 764 struct work_struct reset_work; 765 atomic_t reset_count; 766 atomic_t recovery_count; 767 atomic_t recovery_start_count; 768 bool is_reset; 769 struct completion reset_complete; 770 struct completion reconfigure_complete; 771 struct completion recovery_start; 772 /* continuous recovery fail count */ 773 atomic_t fail_cont_count; 774 unsigned long reset_fail_timeout; 775 struct { 776 /* protected by data_lock */ 777 u32 fw_crash_counter; 778 } stats; 779 u32 pktlog_defs_checksum; 780 781 struct ath12k_dbring_cap *db_caps; 782 u32 num_db_cap; 783 784 struct timer_list mon_reap_timer; 785 786 struct completion htc_suspend; 787 788 u64 fw_soc_drop_count; 789 bool static_window_map; 790 791 struct work_struct rfkill_work; 792 /* true means radio is on */ 793 bool rfkill_radio_on; 794 795 /* must be last */ 796 u8 drv_priv[] __aligned(sizeof(void *)); 797 }; 798 799 int ath12k_core_qmi_firmware_ready(struct ath12k_base *ab); 800 int ath12k_core_pre_init(struct ath12k_base *ab); 801 int ath12k_core_init(struct ath12k_base *ath12k); 802 void ath12k_core_deinit(struct ath12k_base *ath12k); 803 struct ath12k_base *ath12k_core_alloc(struct device *dev, size_t priv_size, 804 enum ath12k_bus bus); 805 void ath12k_core_free(struct ath12k_base *ath12k); 806 int ath12k_core_fetch_board_data_api_1(struct ath12k_base *ab, 807 struct ath12k_board_data *bd, 808 char *filename); 809 int ath12k_core_fetch_bdf(struct ath12k_base *ath12k, 810 struct ath12k_board_data *bd); 811 void ath12k_core_free_bdf(struct ath12k_base *ab, struct ath12k_board_data *bd); 812 int ath12k_core_check_dt(struct ath12k_base *ath12k); 813 int ath12k_core_check_smbios(struct ath12k_base *ab); 814 void ath12k_core_halt(struct ath12k *ar); 815 int ath12k_core_resume(struct ath12k_base *ab); 816 int ath12k_core_suspend(struct ath12k_base *ab); 817 818 const struct firmware *ath12k_core_firmware_request(struct ath12k_base *ab, 819 const char *filename); 820 821 static inline const char *ath12k_scan_state_str(enum ath12k_scan_state state) 822 { 823 switch (state) { 824 case ATH12K_SCAN_IDLE: 825 return "idle"; 826 case ATH12K_SCAN_STARTING: 827 return "starting"; 828 case ATH12K_SCAN_RUNNING: 829 return "running"; 830 case ATH12K_SCAN_ABORTING: 831 return "aborting"; 832 } 833 834 return "unknown"; 835 } 836 837 static inline struct ath12k_skb_cb *ATH12K_SKB_CB(struct sk_buff *skb) 838 { 839 BUILD_BUG_ON(sizeof(struct ath12k_skb_cb) > 840 IEEE80211_TX_INFO_DRIVER_DATA_SIZE); 841 return (struct ath12k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data; 842 } 843 844 static inline struct ath12k_skb_rxcb *ATH12K_SKB_RXCB(struct sk_buff *skb) 845 { 846 BUILD_BUG_ON(sizeof(struct ath12k_skb_rxcb) > sizeof(skb->cb)); 847 return (struct ath12k_skb_rxcb *)skb->cb; 848 } 849 850 static inline struct ath12k_vif *ath12k_vif_to_arvif(struct ieee80211_vif *vif) 851 { 852 return (struct ath12k_vif *)vif->drv_priv; 853 } 854 855 static inline struct ath12k_sta *ath12k_sta_to_arsta(struct ieee80211_sta *sta) 856 { 857 return (struct ath12k_sta *)sta->drv_priv; 858 } 859 860 static inline struct ath12k *ath12k_ab_to_ar(struct ath12k_base *ab, 861 int mac_id) 862 { 863 return ab->pdevs[ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id)].ar; 864 } 865 866 static inline void ath12k_core_create_firmware_path(struct ath12k_base *ab, 867 const char *filename, 868 void *buf, size_t buf_len) 869 { 870 snprintf(buf, buf_len, "%s/%s/%s", ATH12K_FW_DIR, 871 ab->hw_params->fw.dir, filename); 872 } 873 874 static inline const char *ath12k_bus_str(enum ath12k_bus bus) 875 { 876 switch (bus) { 877 case ATH12K_BUS_PCI: 878 return "pci"; 879 } 880 881 return "unknown"; 882 } 883 884 #endif /* _CORE_H_ */ 885