1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef ATH12K_CORE_H 8 #define ATH12K_CORE_H 9 10 #include <linux/types.h> 11 #include <linux/interrupt.h> 12 #include <linux/irq.h> 13 #include <linux/bitfield.h> 14 #include <linux/dmi.h> 15 #include <linux/ctype.h> 16 #include "qmi.h" 17 #include "htc.h" 18 #include "wmi.h" 19 #include "hal.h" 20 #include "dp.h" 21 #include "ce.h" 22 #include "mac.h" 23 #include "hw.h" 24 #include "hal_rx.h" 25 #include "reg.h" 26 #include "dbring.h" 27 28 #define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK) 29 30 #define ATH12K_TX_MGMT_NUM_PENDING_MAX 512 31 32 #define ATH12K_TX_MGMT_TARGET_MAX_SUPPORT_WMI 64 33 34 /* Pending management packets threshold for dropping probe responses */ 35 #define ATH12K_PRB_RSP_DROP_THRESHOLD ((ATH12K_TX_MGMT_TARGET_MAX_SUPPORT_WMI * 3) / 4) 36 37 /* SMBIOS type containing Board Data File Name Extension */ 38 #define ATH12K_SMBIOS_BDF_EXT_TYPE 0xF8 39 40 /* SMBIOS type structure length (excluding strings-set) */ 41 #define ATH12K_SMBIOS_BDF_EXT_LENGTH 0x9 42 43 /* The magic used by QCA spec */ 44 #define ATH12K_SMBIOS_BDF_EXT_MAGIC "BDF_" 45 46 #define ATH12K_INVALID_HW_MAC_ID 0xFF 47 #define ATH12K_RX_RATE_TABLE_NUM 320 48 #define ATH12K_RX_RATE_TABLE_11AX_NUM 576 49 50 #define ATH12K_MON_TIMER_INTERVAL 10 51 #define ATH12K_RESET_TIMEOUT_HZ (20 * HZ) 52 #define ATH12K_RESET_MAX_FAIL_COUNT_FIRST 3 53 #define ATH12K_RESET_MAX_FAIL_COUNT_FINAL 5 54 #define ATH12K_RESET_FAIL_TIMEOUT_HZ (20 * HZ) 55 #define ATH12K_RECONFIGURE_TIMEOUT_HZ (10 * HZ) 56 #define ATH12K_RECOVER_START_TIMEOUT_HZ (20 * HZ) 57 58 enum wme_ac { 59 WME_AC_BE, 60 WME_AC_BK, 61 WME_AC_VI, 62 WME_AC_VO, 63 WME_NUM_AC 64 }; 65 66 #define ATH12K_HT_MCS_MAX 7 67 #define ATH12K_VHT_MCS_MAX 9 68 #define ATH12K_HE_MCS_MAX 11 69 70 enum ath12k_crypt_mode { 71 /* Only use hardware crypto engine */ 72 ATH12K_CRYPT_MODE_HW, 73 /* Only use software crypto */ 74 ATH12K_CRYPT_MODE_SW, 75 }; 76 77 static inline enum wme_ac ath12k_tid_to_ac(u32 tid) 78 { 79 return (((tid == 0) || (tid == 3)) ? WME_AC_BE : 80 ((tid == 1) || (tid == 2)) ? WME_AC_BK : 81 ((tid == 4) || (tid == 5)) ? WME_AC_VI : 82 WME_AC_VO); 83 } 84 85 enum ath12k_skb_flags { 86 ATH12K_SKB_HW_80211_ENCAP = BIT(0), 87 ATH12K_SKB_CIPHER_SET = BIT(1), 88 }; 89 90 struct ath12k_skb_cb { 91 dma_addr_t paddr; 92 struct ath12k *ar; 93 struct ieee80211_vif *vif; 94 dma_addr_t paddr_ext_desc; 95 u32 cipher; 96 u8 flags; 97 }; 98 99 struct ath12k_skb_rxcb { 100 dma_addr_t paddr; 101 bool is_first_msdu; 102 bool is_last_msdu; 103 bool is_continuation; 104 bool is_mcbc; 105 bool is_eapol; 106 struct hal_rx_desc *rx_desc; 107 u8 err_rel_src; 108 u8 err_code; 109 u8 mac_id; 110 u8 unmapped; 111 u8 is_frag; 112 u8 tid; 113 u16 peer_id; 114 }; 115 116 enum ath12k_hw_rev { 117 ATH12K_HW_QCN9274_HW10, 118 ATH12K_HW_QCN9274_HW20, 119 ATH12K_HW_WCN7850_HW20 120 }; 121 122 enum ath12k_firmware_mode { 123 /* the default mode, standard 802.11 functionality */ 124 ATH12K_FIRMWARE_MODE_NORMAL, 125 126 /* factory tests etc */ 127 ATH12K_FIRMWARE_MODE_FTM, 128 }; 129 130 #define ATH12K_IRQ_NUM_MAX 57 131 #define ATH12K_EXT_IRQ_NUM_MAX 16 132 133 struct ath12k_ext_irq_grp { 134 struct ath12k_base *ab; 135 u32 irqs[ATH12K_EXT_IRQ_NUM_MAX]; 136 u32 num_irq; 137 u32 grp_id; 138 u64 timestamp; 139 struct napi_struct napi; 140 struct net_device napi_ndev; 141 }; 142 143 struct ath12k_smbios_bdf { 144 struct dmi_header hdr; 145 u32 padding; 146 u8 bdf_enabled; 147 u8 bdf_ext[]; 148 } __packed; 149 150 #define HEHANDLE_CAP_PHYINFO_SIZE 3 151 #define HECAP_PHYINFO_SIZE 9 152 #define HECAP_MACINFO_SIZE 5 153 #define HECAP_TXRX_MCS_NSS_SIZE 2 154 #define HECAP_PPET16_PPET8_MAX_SIZE 25 155 156 #define HE_PPET16_PPET8_SIZE 8 157 158 /* 802.11ax PPE (PPDU packet Extension) threshold */ 159 struct he_ppe_threshold { 160 u32 numss_m1; 161 u32 ru_mask; 162 u32 ppet16_ppet8_ru3_ru0[HE_PPET16_PPET8_SIZE]; 163 }; 164 165 struct ath12k_he { 166 u8 hecap_macinfo[HECAP_MACINFO_SIZE]; 167 u32 hecap_rxmcsnssmap; 168 u32 hecap_txmcsnssmap; 169 u32 hecap_phyinfo[HEHANDLE_CAP_PHYINFO_SIZE]; 170 struct he_ppe_threshold hecap_ppet; 171 u32 heop_param; 172 }; 173 174 #define MAX_RADIOS 3 175 176 enum { 177 WMI_HOST_TP_SCALE_MAX = 0, 178 WMI_HOST_TP_SCALE_50 = 1, 179 WMI_HOST_TP_SCALE_25 = 2, 180 WMI_HOST_TP_SCALE_12 = 3, 181 WMI_HOST_TP_SCALE_MIN = 4, 182 WMI_HOST_TP_SCALE_SIZE = 5, 183 }; 184 185 enum ath12k_scan_state { 186 ATH12K_SCAN_IDLE, 187 ATH12K_SCAN_STARTING, 188 ATH12K_SCAN_RUNNING, 189 ATH12K_SCAN_ABORTING, 190 }; 191 192 enum ath12k_dev_flags { 193 ATH12K_CAC_RUNNING, 194 ATH12K_FLAG_CRASH_FLUSH, 195 ATH12K_FLAG_RAW_MODE, 196 ATH12K_FLAG_HW_CRYPTO_DISABLED, 197 ATH12K_FLAG_RECOVERY, 198 ATH12K_FLAG_UNREGISTERING, 199 ATH12K_FLAG_REGISTERED, 200 ATH12K_FLAG_QMI_FAIL, 201 ATH12K_FLAG_HTC_SUSPEND_COMPLETE, 202 ATH12K_FLAG_CE_IRQ_ENABLED, 203 ATH12K_FLAG_EXT_IRQ_ENABLED, 204 }; 205 206 enum ath12k_monitor_flags { 207 ATH12K_FLAG_MONITOR_ENABLED, 208 }; 209 210 struct ath12k_vif { 211 u32 vdev_id; 212 enum wmi_vdev_type vdev_type; 213 enum wmi_vdev_subtype vdev_subtype; 214 u32 beacon_interval; 215 u32 dtim_period; 216 u16 ast_hash; 217 u16 ast_idx; 218 u16 tcl_metadata; 219 u8 hal_addr_search_flags; 220 u8 search_type; 221 222 struct ath12k *ar; 223 struct ieee80211_vif *vif; 224 225 int bank_id; 226 u8 vdev_id_check_en; 227 228 struct wmi_wmm_params_all_arg wmm_params; 229 struct list_head list; 230 union { 231 struct { 232 u32 uapsd; 233 } sta; 234 struct { 235 /* 127 stations; wmi limit */ 236 u8 tim_bitmap[16]; 237 u8 tim_len; 238 u32 ssid_len; 239 u8 ssid[IEEE80211_MAX_SSID_LEN]; 240 bool hidden_ssid; 241 /* P2P_IE with NoA attribute for P2P_GO case */ 242 u32 noa_len; 243 u8 *noa_data; 244 } ap; 245 } u; 246 247 bool is_started; 248 bool is_up; 249 u32 aid; 250 u8 bssid[ETH_ALEN]; 251 struct cfg80211_bitrate_mask bitrate_mask; 252 int num_legacy_stations; 253 int rtscts_prot_mode; 254 int txpower; 255 bool rsnie_present; 256 bool wpaie_present; 257 struct ieee80211_chanctx_conf chanctx; 258 u32 key_cipher; 259 u8 tx_encap_type; 260 u8 vdev_stats_id; 261 u32 punct_bitmap; 262 }; 263 264 struct ath12k_vif_iter { 265 u32 vdev_id; 266 struct ath12k_vif *arvif; 267 }; 268 269 #define HAL_AST_IDX_INVALID 0xFFFF 270 #define HAL_RX_MAX_MCS 12 271 #define HAL_RX_MAX_MCS_HT 31 272 #define HAL_RX_MAX_MCS_VHT 9 273 #define HAL_RX_MAX_MCS_HE 11 274 #define HAL_RX_MAX_NSS 8 275 #define HAL_RX_MAX_NUM_LEGACY_RATES 12 276 #define ATH12K_RX_RATE_TABLE_11AX_NUM 576 277 #define ATH12K_RX_RATE_TABLE_NUM 320 278 279 struct ath12k_rx_peer_rate_stats { 280 u64 ht_mcs_count[HAL_RX_MAX_MCS_HT + 1]; 281 u64 vht_mcs_count[HAL_RX_MAX_MCS_VHT + 1]; 282 u64 he_mcs_count[HAL_RX_MAX_MCS_HE + 1]; 283 u64 nss_count[HAL_RX_MAX_NSS]; 284 u64 bw_count[HAL_RX_BW_MAX]; 285 u64 gi_count[HAL_RX_GI_MAX]; 286 u64 legacy_count[HAL_RX_MAX_NUM_LEGACY_RATES]; 287 u64 rx_rate[ATH12K_RX_RATE_TABLE_11AX_NUM]; 288 }; 289 290 struct ath12k_rx_peer_stats { 291 u64 num_msdu; 292 u64 num_mpdu_fcs_ok; 293 u64 num_mpdu_fcs_err; 294 u64 tcp_msdu_count; 295 u64 udp_msdu_count; 296 u64 other_msdu_count; 297 u64 ampdu_msdu_count; 298 u64 non_ampdu_msdu_count; 299 u64 stbc_count; 300 u64 beamformed_count; 301 u64 mcs_count[HAL_RX_MAX_MCS + 1]; 302 u64 nss_count[HAL_RX_MAX_NSS]; 303 u64 bw_count[HAL_RX_BW_MAX]; 304 u64 gi_count[HAL_RX_GI_MAX]; 305 u64 coding_count[HAL_RX_SU_MU_CODING_MAX]; 306 u64 tid_count[IEEE80211_NUM_TIDS + 1]; 307 u64 pream_cnt[HAL_RX_PREAMBLE_MAX]; 308 u64 reception_type[HAL_RX_RECEPTION_TYPE_MAX]; 309 u64 rx_duration; 310 u64 dcm_count; 311 u64 ru_alloc_cnt[HAL_RX_RU_ALLOC_TYPE_MAX]; 312 struct ath12k_rx_peer_rate_stats pkt_stats; 313 struct ath12k_rx_peer_rate_stats byte_stats; 314 }; 315 316 #define ATH12K_HE_MCS_NUM 12 317 #define ATH12K_VHT_MCS_NUM 10 318 #define ATH12K_BW_NUM 5 319 #define ATH12K_NSS_NUM 4 320 #define ATH12K_LEGACY_NUM 12 321 #define ATH12K_GI_NUM 4 322 #define ATH12K_HT_MCS_NUM 32 323 324 enum ath12k_pkt_rx_err { 325 ATH12K_PKT_RX_ERR_FCS, 326 ATH12K_PKT_RX_ERR_TKIP, 327 ATH12K_PKT_RX_ERR_CRYPT, 328 ATH12K_PKT_RX_ERR_PEER_IDX_INVAL, 329 ATH12K_PKT_RX_ERR_MAX, 330 }; 331 332 enum ath12k_ampdu_subfrm_num { 333 ATH12K_AMPDU_SUBFRM_NUM_10, 334 ATH12K_AMPDU_SUBFRM_NUM_20, 335 ATH12K_AMPDU_SUBFRM_NUM_30, 336 ATH12K_AMPDU_SUBFRM_NUM_40, 337 ATH12K_AMPDU_SUBFRM_NUM_50, 338 ATH12K_AMPDU_SUBFRM_NUM_60, 339 ATH12K_AMPDU_SUBFRM_NUM_MORE, 340 ATH12K_AMPDU_SUBFRM_NUM_MAX, 341 }; 342 343 enum ath12k_amsdu_subfrm_num { 344 ATH12K_AMSDU_SUBFRM_NUM_1, 345 ATH12K_AMSDU_SUBFRM_NUM_2, 346 ATH12K_AMSDU_SUBFRM_NUM_3, 347 ATH12K_AMSDU_SUBFRM_NUM_4, 348 ATH12K_AMSDU_SUBFRM_NUM_MORE, 349 ATH12K_AMSDU_SUBFRM_NUM_MAX, 350 }; 351 352 enum ath12k_counter_type { 353 ATH12K_COUNTER_TYPE_BYTES, 354 ATH12K_COUNTER_TYPE_PKTS, 355 ATH12K_COUNTER_TYPE_MAX, 356 }; 357 358 enum ath12k_stats_type { 359 ATH12K_STATS_TYPE_SUCC, 360 ATH12K_STATS_TYPE_FAIL, 361 ATH12K_STATS_TYPE_RETRY, 362 ATH12K_STATS_TYPE_AMPDU, 363 ATH12K_STATS_TYPE_MAX, 364 }; 365 366 struct ath12k_htt_data_stats { 367 u64 legacy[ATH12K_COUNTER_TYPE_MAX][ATH12K_LEGACY_NUM]; 368 u64 ht[ATH12K_COUNTER_TYPE_MAX][ATH12K_HT_MCS_NUM]; 369 u64 vht[ATH12K_COUNTER_TYPE_MAX][ATH12K_VHT_MCS_NUM]; 370 u64 he[ATH12K_COUNTER_TYPE_MAX][ATH12K_HE_MCS_NUM]; 371 u64 bw[ATH12K_COUNTER_TYPE_MAX][ATH12K_BW_NUM]; 372 u64 nss[ATH12K_COUNTER_TYPE_MAX][ATH12K_NSS_NUM]; 373 u64 gi[ATH12K_COUNTER_TYPE_MAX][ATH12K_GI_NUM]; 374 u64 transmit_type[ATH12K_COUNTER_TYPE_MAX][HAL_RX_RECEPTION_TYPE_MAX]; 375 u64 ru_loc[ATH12K_COUNTER_TYPE_MAX][HAL_RX_RU_ALLOC_TYPE_MAX]; 376 }; 377 378 struct ath12k_htt_tx_stats { 379 struct ath12k_htt_data_stats stats[ATH12K_STATS_TYPE_MAX]; 380 u64 tx_duration; 381 u64 ba_fails; 382 u64 ack_fails; 383 u16 ru_start; 384 u16 ru_tones; 385 u32 mu_group[MAX_MU_GROUP_ID]; 386 }; 387 388 struct ath12k_per_ppdu_tx_stats { 389 u16 succ_pkts; 390 u16 failed_pkts; 391 u16 retry_pkts; 392 u32 succ_bytes; 393 u32 failed_bytes; 394 u32 retry_bytes; 395 }; 396 397 struct ath12k_wbm_tx_stats { 398 u64 wbm_tx_comp_stats[HAL_WBM_REL_HTT_TX_COMP_STATUS_MAX]; 399 }; 400 401 struct ath12k_sta { 402 struct ath12k_vif *arvif; 403 404 /* the following are protected by ar->data_lock */ 405 u32 changed; /* IEEE80211_RC_* */ 406 u32 bw; 407 u32 nss; 408 u32 smps; 409 enum hal_pn_type pn_type; 410 411 struct work_struct update_wk; 412 struct rate_info txrate; 413 struct rate_info last_txrate; 414 u64 rx_duration; 415 u64 tx_duration; 416 u8 rssi_comb; 417 struct ath12k_rx_peer_stats *rx_stats; 418 struct ath12k_wbm_tx_stats *wbm_tx_stats; 419 u32 bw_prev; 420 }; 421 422 #define ATH12K_MIN_5G_FREQ 4150 423 #define ATH12K_MIN_6G_FREQ 5945 424 #define ATH12K_MAX_6G_FREQ 7115 425 #define ATH12K_NUM_CHANS 100 426 #define ATH12K_MAX_5G_CHAN 173 427 428 enum ath12k_state { 429 ATH12K_STATE_OFF, 430 ATH12K_STATE_ON, 431 ATH12K_STATE_RESTARTING, 432 ATH12K_STATE_RESTARTED, 433 ATH12K_STATE_WEDGED, 434 /* Add other states as required */ 435 }; 436 437 /* Antenna noise floor */ 438 #define ATH12K_DEFAULT_NOISE_FLOOR -95 439 440 struct ath12k_fw_stats { 441 u32 pdev_id; 442 u32 stats_id; 443 struct list_head pdevs; 444 struct list_head vdevs; 445 struct list_head bcn; 446 }; 447 448 struct ath12k_per_peer_tx_stats { 449 u32 succ_bytes; 450 u32 retry_bytes; 451 u32 failed_bytes; 452 u32 duration; 453 u16 succ_pkts; 454 u16 retry_pkts; 455 u16 failed_pkts; 456 u16 ru_start; 457 u16 ru_tones; 458 u8 ba_fails; 459 u8 ppdu_type; 460 u32 mu_grpid; 461 u32 mu_pos; 462 bool is_ampdu; 463 }; 464 465 #define ATH12K_FLUSH_TIMEOUT (5 * HZ) 466 #define ATH12K_VDEV_DELETE_TIMEOUT_HZ (5 * HZ) 467 468 struct ath12k { 469 struct ath12k_base *ab; 470 struct ath12k_pdev *pdev; 471 struct ieee80211_hw *hw; 472 struct ath12k_wmi_pdev *wmi; 473 struct ath12k_pdev_dp dp; 474 u8 mac_addr[ETH_ALEN]; 475 u32 ht_cap_info; 476 u32 vht_cap_info; 477 struct ath12k_he ar_he; 478 enum ath12k_state state; 479 bool supports_6ghz; 480 struct { 481 struct completion started; 482 struct completion completed; 483 struct completion on_channel; 484 struct delayed_work timeout; 485 enum ath12k_scan_state state; 486 bool is_roc; 487 int vdev_id; 488 int roc_freq; 489 bool roc_notify; 490 } scan; 491 492 struct { 493 struct ieee80211_supported_band sbands[NUM_NL80211_BANDS]; 494 struct ieee80211_sband_iftype_data 495 iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES]; 496 } mac; 497 498 unsigned long dev_flags; 499 unsigned int filter_flags; 500 unsigned long monitor_flags; 501 u32 min_tx_power; 502 u32 max_tx_power; 503 u32 txpower_limit_2g; 504 u32 txpower_limit_5g; 505 u32 txpower_scale; 506 u32 power_scale; 507 u32 chan_tx_pwr; 508 u32 num_stations; 509 u32 max_num_stations; 510 bool monitor_present; 511 /* To synchronize concurrent synchronous mac80211 callback operations, 512 * concurrent debugfs configuration and concurrent FW statistics events. 513 */ 514 struct mutex conf_mutex; 515 /* protects the radio specific data like debug stats, ppdu_stats_info stats, 516 * vdev_stop_status info, scan data, ath12k_sta info, ath12k_vif info, 517 * channel context data, survey info, test mode data. 518 */ 519 spinlock_t data_lock; 520 521 struct list_head arvifs; 522 /* should never be NULL; needed for regular htt rx */ 523 struct ieee80211_channel *rx_channel; 524 525 /* valid during scan; needed for mgmt rx during scan */ 526 struct ieee80211_channel *scan_channel; 527 528 u8 cfg_tx_chainmask; 529 u8 cfg_rx_chainmask; 530 u8 num_rx_chains; 531 u8 num_tx_chains; 532 /* pdev_idx starts from 0 whereas pdev->pdev_id starts with 1 */ 533 u8 pdev_idx; 534 u8 lmac_id; 535 536 struct completion peer_assoc_done; 537 struct completion peer_delete_done; 538 539 int install_key_status; 540 struct completion install_key_done; 541 542 int last_wmi_vdev_start_status; 543 struct completion vdev_setup_done; 544 struct completion vdev_delete_done; 545 546 int num_peers; 547 int max_num_peers; 548 u32 num_started_vdevs; 549 u32 num_created_vdevs; 550 unsigned long long allocated_vdev_map; 551 552 struct idr txmgmt_idr; 553 /* protects txmgmt_idr data */ 554 spinlock_t txmgmt_idr_lock; 555 atomic_t num_pending_mgmt_tx; 556 wait_queue_head_t txmgmt_empty_waitq; 557 558 /* cycle count is reported twice for each visited channel during scan. 559 * access protected by data_lock 560 */ 561 u32 survey_last_rx_clear_count; 562 u32 survey_last_cycle_count; 563 564 /* Channel info events are expected to come in pairs without and with 565 * COMPLETE flag set respectively for each channel visit during scan. 566 * 567 * However there are deviations from this rule. This flag is used to 568 * avoid reporting garbage data. 569 */ 570 bool ch_info_can_report_survey; 571 struct survey_info survey[ATH12K_NUM_CHANS]; 572 struct completion bss_survey_done; 573 574 struct work_struct regd_update_work; 575 576 struct work_struct wmi_mgmt_tx_work; 577 struct sk_buff_head wmi_mgmt_tx_queue; 578 579 struct ath12k_per_peer_tx_stats peer_tx_stats; 580 struct list_head ppdu_stats_info; 581 u32 ppdu_stat_list_depth; 582 583 struct ath12k_per_peer_tx_stats cached_stats; 584 u32 last_ppdu_id; 585 u32 cached_ppdu_id; 586 587 bool dfs_block_radar_events; 588 bool monitor_conf_enabled; 589 bool monitor_vdev_created; 590 bool monitor_started; 591 int monitor_vdev_id; 592 }; 593 594 struct ath12k_band_cap { 595 u32 phy_id; 596 u32 max_bw_supported; 597 u32 ht_cap_info; 598 u32 he_cap_info[2]; 599 u32 he_mcs; 600 u32 he_cap_phy_info[PSOC_HOST_MAX_PHY_SIZE]; 601 struct ath12k_wmi_ppe_threshold_arg he_ppet; 602 u16 he_6ghz_capa; 603 u32 eht_cap_mac_info[WMI_MAX_EHTCAP_MAC_SIZE]; 604 u32 eht_cap_phy_info[WMI_MAX_EHTCAP_PHY_SIZE]; 605 u32 eht_mcs_20_only; 606 u32 eht_mcs_80; 607 u32 eht_mcs_160; 608 u32 eht_mcs_320; 609 struct ath12k_wmi_ppe_threshold_arg eht_ppet; 610 u32 eht_cap_info_internal; 611 }; 612 613 struct ath12k_pdev_cap { 614 u32 supported_bands; 615 u32 ampdu_density; 616 u32 vht_cap; 617 u32 vht_mcs; 618 u32 he_mcs; 619 u32 tx_chain_mask; 620 u32 rx_chain_mask; 621 u32 tx_chain_mask_shift; 622 u32 rx_chain_mask_shift; 623 struct ath12k_band_cap band[NUM_NL80211_BANDS]; 624 }; 625 626 struct mlo_timestamp { 627 u32 info; 628 u32 sync_timestamp_lo_us; 629 u32 sync_timestamp_hi_us; 630 u32 mlo_offset_lo; 631 u32 mlo_offset_hi; 632 u32 mlo_offset_clks; 633 u32 mlo_comp_clks; 634 u32 mlo_comp_timer; 635 }; 636 637 struct ath12k_pdev { 638 struct ath12k *ar; 639 u32 pdev_id; 640 struct ath12k_pdev_cap cap; 641 u8 mac_addr[ETH_ALEN]; 642 struct mlo_timestamp timestamp; 643 }; 644 645 struct ath12k_fw_pdev { 646 u32 pdev_id; 647 u32 phy_id; 648 u32 supported_bands; 649 }; 650 651 struct ath12k_board_data { 652 const struct firmware *fw; 653 const void *data; 654 size_t len; 655 }; 656 657 struct ath12k_soc_dp_tx_err_stats { 658 /* TCL Ring Descriptor unavailable */ 659 u32 desc_na[DP_TCL_NUM_RING_MAX]; 660 /* Other failures during dp_tx due to mem allocation failure 661 * idr unavailable etc. 662 */ 663 atomic_t misc_fail; 664 }; 665 666 struct ath12k_soc_dp_stats { 667 u32 err_ring_pkts; 668 u32 invalid_rbm; 669 u32 rxdma_error[HAL_REO_ENTR_RING_RXDMA_ECODE_MAX]; 670 u32 reo_error[HAL_REO_DEST_RING_ERROR_CODE_MAX]; 671 u32 hal_reo_error[DP_REO_DST_RING_MAX]; 672 struct ath12k_soc_dp_tx_err_stats tx_err; 673 }; 674 675 /* Master structure to hold the hw data which may be used in core module */ 676 struct ath12k_base { 677 enum ath12k_hw_rev hw_rev; 678 struct platform_device *pdev; 679 struct device *dev; 680 struct ath12k_qmi qmi; 681 struct ath12k_wmi_base wmi_ab; 682 struct completion fw_ready; 683 int num_radios; 684 /* HW channel counters frequency value in hertz common to all MACs */ 685 u32 cc_freq_hz; 686 687 struct ath12k_htc htc; 688 689 struct ath12k_dp dp; 690 691 void __iomem *mem; 692 unsigned long mem_len; 693 694 struct { 695 enum ath12k_bus bus; 696 const struct ath12k_hif_ops *ops; 697 } hif; 698 699 struct ath12k_ce ce; 700 struct timer_list rx_replenish_retry; 701 struct ath12k_hal hal; 702 /* To synchronize core_start/core_stop */ 703 struct mutex core_lock; 704 /* Protects data like peers */ 705 spinlock_t base_lock; 706 707 /* Single pdev device (struct ath12k_hw_params::single_pdev_only): 708 * 709 * Firmware maintains data for all bands but advertises a single 710 * phy to the host which is stored as a single element in this 711 * array. 712 * 713 * Other devices: 714 * 715 * This array will contain as many elements as the number of 716 * radios. 717 */ 718 struct ath12k_pdev pdevs[MAX_RADIOS]; 719 720 /* struct ath12k_hw_params::single_pdev_only devices use this to 721 * store phy specific data 722 */ 723 struct ath12k_fw_pdev fw_pdev[MAX_RADIOS]; 724 u8 fw_pdev_count; 725 726 struct ath12k_pdev __rcu *pdevs_active[MAX_RADIOS]; 727 struct ath12k_wmi_hal_reg_capabilities_ext_arg hal_reg_cap[MAX_RADIOS]; 728 unsigned long long free_vdev_map; 729 unsigned long long free_vdev_stats_id_map; 730 struct list_head peers; 731 wait_queue_head_t peer_mapping_wq; 732 u8 mac_addr[ETH_ALEN]; 733 bool wmi_ready; 734 u32 wlan_init_status; 735 int irq_num[ATH12K_IRQ_NUM_MAX]; 736 struct ath12k_ext_irq_grp ext_irq_grp[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 737 struct napi_struct *napi; 738 struct ath12k_wmi_target_cap_arg target_caps; 739 u32 ext_service_bitmap[WMI_SERVICE_EXT_BM_SIZE]; 740 bool pdevs_macaddr_valid; 741 742 const struct ath12k_hw_params *hw_params; 743 744 const struct firmware *cal_file; 745 746 /* Below regd's are protected by ab->data_lock */ 747 /* This is the regd set for every radio 748 * by the firmware during initialization 749 */ 750 struct ieee80211_regdomain *default_regd[MAX_RADIOS]; 751 /* This regd is set during dynamic country setting 752 * This may or may not be used during the runtime 753 */ 754 struct ieee80211_regdomain *new_regd[MAX_RADIOS]; 755 756 /* Current DFS Regulatory */ 757 enum ath12k_dfs_region dfs_region; 758 struct ath12k_soc_dp_stats soc_stats; 759 760 unsigned long dev_flags; 761 struct completion driver_recovery; 762 struct workqueue_struct *workqueue; 763 struct work_struct restart_work; 764 struct workqueue_struct *workqueue_aux; 765 struct work_struct reset_work; 766 atomic_t reset_count; 767 atomic_t recovery_count; 768 atomic_t recovery_start_count; 769 bool is_reset; 770 struct completion reset_complete; 771 struct completion reconfigure_complete; 772 struct completion recovery_start; 773 /* continuous recovery fail count */ 774 atomic_t fail_cont_count; 775 unsigned long reset_fail_timeout; 776 struct { 777 /* protected by data_lock */ 778 u32 fw_crash_counter; 779 } stats; 780 u32 pktlog_defs_checksum; 781 782 struct ath12k_dbring_cap *db_caps; 783 u32 num_db_cap; 784 785 struct timer_list mon_reap_timer; 786 787 struct completion htc_suspend; 788 789 u64 fw_soc_drop_count; 790 bool static_window_map; 791 792 struct work_struct rfkill_work; 793 /* true means radio is on */ 794 bool rfkill_radio_on; 795 796 /* must be last */ 797 u8 drv_priv[] __aligned(sizeof(void *)); 798 }; 799 800 int ath12k_core_qmi_firmware_ready(struct ath12k_base *ab); 801 int ath12k_core_pre_init(struct ath12k_base *ab); 802 int ath12k_core_init(struct ath12k_base *ath12k); 803 void ath12k_core_deinit(struct ath12k_base *ath12k); 804 struct ath12k_base *ath12k_core_alloc(struct device *dev, size_t priv_size, 805 enum ath12k_bus bus); 806 void ath12k_core_free(struct ath12k_base *ath12k); 807 int ath12k_core_fetch_board_data_api_1(struct ath12k_base *ab, 808 struct ath12k_board_data *bd, 809 char *filename); 810 int ath12k_core_fetch_bdf(struct ath12k_base *ath12k, 811 struct ath12k_board_data *bd); 812 void ath12k_core_free_bdf(struct ath12k_base *ab, struct ath12k_board_data *bd); 813 int ath12k_core_check_dt(struct ath12k_base *ath12k); 814 int ath12k_core_check_smbios(struct ath12k_base *ab); 815 void ath12k_core_halt(struct ath12k *ar); 816 int ath12k_core_resume(struct ath12k_base *ab); 817 int ath12k_core_suspend(struct ath12k_base *ab); 818 819 const struct firmware *ath12k_core_firmware_request(struct ath12k_base *ab, 820 const char *filename); 821 822 static inline const char *ath12k_scan_state_str(enum ath12k_scan_state state) 823 { 824 switch (state) { 825 case ATH12K_SCAN_IDLE: 826 return "idle"; 827 case ATH12K_SCAN_STARTING: 828 return "starting"; 829 case ATH12K_SCAN_RUNNING: 830 return "running"; 831 case ATH12K_SCAN_ABORTING: 832 return "aborting"; 833 } 834 835 return "unknown"; 836 } 837 838 static inline struct ath12k_skb_cb *ATH12K_SKB_CB(struct sk_buff *skb) 839 { 840 BUILD_BUG_ON(sizeof(struct ath12k_skb_cb) > 841 IEEE80211_TX_INFO_DRIVER_DATA_SIZE); 842 return (struct ath12k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data; 843 } 844 845 static inline struct ath12k_skb_rxcb *ATH12K_SKB_RXCB(struct sk_buff *skb) 846 { 847 BUILD_BUG_ON(sizeof(struct ath12k_skb_rxcb) > sizeof(skb->cb)); 848 return (struct ath12k_skb_rxcb *)skb->cb; 849 } 850 851 static inline struct ath12k_vif *ath12k_vif_to_arvif(struct ieee80211_vif *vif) 852 { 853 return (struct ath12k_vif *)vif->drv_priv; 854 } 855 856 static inline struct ath12k_sta *ath12k_sta_to_arsta(struct ieee80211_sta *sta) 857 { 858 return (struct ath12k_sta *)sta->drv_priv; 859 } 860 861 static inline struct ath12k *ath12k_ab_to_ar(struct ath12k_base *ab, 862 int mac_id) 863 { 864 return ab->pdevs[ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id)].ar; 865 } 866 867 static inline void ath12k_core_create_firmware_path(struct ath12k_base *ab, 868 const char *filename, 869 void *buf, size_t buf_len) 870 { 871 snprintf(buf, buf_len, "%s/%s/%s", ATH12K_FW_DIR, 872 ab->hw_params->fw.dir, filename); 873 } 874 875 static inline const char *ath12k_bus_str(enum ath12k_bus bus) 876 { 877 switch (bus) { 878 case ATH12K_BUS_PCI: 879 return "pci"; 880 } 881 882 return "unknown"; 883 } 884 885 #endif /* _CORE_H_ */ 886