1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef ATH12K_CORE_H 8 #define ATH12K_CORE_H 9 10 #include <linux/types.h> 11 #include <linux/interrupt.h> 12 #include <linux/irq.h> 13 #include <linux/bitfield.h> 14 #include <linux/dmi.h> 15 #include <linux/ctype.h> 16 #include <linux/firmware.h> 17 #include <linux/of_reserved_mem.h> 18 #include <linux/panic_notifier.h> 19 #include <linux/average.h> 20 #include <linux/of.h> 21 #include "qmi.h" 22 #include "htc.h" 23 #include "wmi.h" 24 #include "hal.h" 25 #include "dp.h" 26 #include "ce.h" 27 #include "mac.h" 28 #include "hw.h" 29 #include "hal_rx.h" 30 #include "reg.h" 31 #include "dbring.h" 32 #include "fw.h" 33 #include "acpi.h" 34 #include "wow.h" 35 #include "debugfs_htt_stats.h" 36 #include "coredump.h" 37 38 #define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK) 39 40 #define ATH12K_TX_MGMT_NUM_PENDING_MAX 512 41 42 #define ATH12K_TX_MGMT_TARGET_MAX_SUPPORT_WMI 64 43 44 /* Pending management packets threshold for dropping probe responses */ 45 #define ATH12K_PRB_RSP_DROP_THRESHOLD ((ATH12K_TX_MGMT_TARGET_MAX_SUPPORT_WMI * 3) / 4) 46 47 /* SMBIOS type containing Board Data File Name Extension */ 48 #define ATH12K_SMBIOS_BDF_EXT_TYPE 0xF8 49 50 /* SMBIOS type structure length (excluding strings-set) */ 51 #define ATH12K_SMBIOS_BDF_EXT_LENGTH 0x9 52 53 /* The magic used by QCA spec */ 54 #define ATH12K_SMBIOS_BDF_EXT_MAGIC "BDF_" 55 56 #define ATH12K_INVALID_HW_MAC_ID 0xFF 57 #define ATH12K_CONNECTION_LOSS_HZ (3 * HZ) 58 59 #define ATH12K_MON_TIMER_INTERVAL 10 60 #define ATH12K_RESET_TIMEOUT_HZ (20 * HZ) 61 #define ATH12K_RESET_MAX_FAIL_COUNT_FIRST 3 62 #define ATH12K_RESET_MAX_FAIL_COUNT_FINAL 5 63 #define ATH12K_RESET_FAIL_TIMEOUT_HZ (20 * HZ) 64 #define ATH12K_RECONFIGURE_TIMEOUT_HZ (10 * HZ) 65 #define ATH12K_RECOVER_START_TIMEOUT_HZ (20 * HZ) 66 67 #define ATH12K_MAX_DEVICES 3 68 #define ATH12K_GROUP_MAX_RADIO (ATH12K_MAX_DEVICES * MAX_RADIOS) 69 #define ATH12K_INVALID_GROUP_ID 0xFF 70 #define ATH12K_INVALID_DEVICE_ID 0xFF 71 72 #define ATH12K_MAX_MLO_PEERS 256 73 #define ATH12K_MLO_PEER_ID_INVALID 0xFFFF 74 75 enum ath12k_bdf_search { 76 ATH12K_BDF_SEARCH_DEFAULT, 77 ATH12K_BDF_SEARCH_BUS_AND_BOARD, 78 }; 79 80 enum wme_ac { 81 WME_AC_BE, 82 WME_AC_BK, 83 WME_AC_VI, 84 WME_AC_VO, 85 WME_NUM_AC 86 }; 87 88 #define ATH12K_HT_MCS_MAX 7 89 #define ATH12K_VHT_MCS_MAX 9 90 #define ATH12K_HE_MCS_MAX 11 91 #define ATH12K_EHT_MCS_MAX 15 92 93 enum ath12k_crypt_mode { 94 /* Only use hardware crypto engine */ 95 ATH12K_CRYPT_MODE_HW, 96 /* Only use software crypto */ 97 ATH12K_CRYPT_MODE_SW, 98 }; 99 100 static inline enum wme_ac ath12k_tid_to_ac(u32 tid) 101 { 102 return (((tid == 0) || (tid == 3)) ? WME_AC_BE : 103 ((tid == 1) || (tid == 2)) ? WME_AC_BK : 104 ((tid == 4) || (tid == 5)) ? WME_AC_VI : 105 WME_AC_VO); 106 } 107 108 static inline u64 ath12k_le32hilo_to_u64(__le32 hi, __le32 lo) 109 { 110 u64 hi64 = le32_to_cpu(hi); 111 u64 lo64 = le32_to_cpu(lo); 112 113 return (hi64 << 32) | lo64; 114 } 115 116 enum ath12k_skb_flags { 117 ATH12K_SKB_HW_80211_ENCAP = BIT(0), 118 ATH12K_SKB_CIPHER_SET = BIT(1), 119 }; 120 121 struct ath12k_skb_cb { 122 dma_addr_t paddr; 123 struct ath12k *ar; 124 struct ieee80211_vif *vif; 125 dma_addr_t paddr_ext_desc; 126 u32 cipher; 127 u8 flags; 128 u8 link_id; 129 }; 130 131 struct ath12k_skb_rxcb { 132 dma_addr_t paddr; 133 bool is_first_msdu; 134 bool is_last_msdu; 135 bool is_continuation; 136 bool is_mcbc; 137 bool is_eapol; 138 struct hal_rx_desc *rx_desc; 139 u8 err_rel_src; 140 u8 err_code; 141 u8 hw_link_id; 142 u8 unmapped; 143 u8 is_frag; 144 u8 tid; 145 u16 peer_id; 146 bool is_end_of_ppdu; 147 }; 148 149 enum ath12k_hw_rev { 150 ATH12K_HW_QCN9274_HW10, 151 ATH12K_HW_QCN9274_HW20, 152 ATH12K_HW_WCN7850_HW20, 153 ATH12K_HW_IPQ5332_HW10, 154 }; 155 156 enum ath12k_firmware_mode { 157 /* the default mode, standard 802.11 functionality */ 158 ATH12K_FIRMWARE_MODE_NORMAL, 159 160 /* factory tests etc */ 161 ATH12K_FIRMWARE_MODE_FTM, 162 }; 163 164 #define ATH12K_IRQ_NUM_MAX 57 165 #define ATH12K_EXT_IRQ_NUM_MAX 16 166 #define ATH12K_MAX_TCL_RING_NUM 3 167 168 struct ath12k_ext_irq_grp { 169 struct ath12k_base *ab; 170 u32 irqs[ATH12K_EXT_IRQ_NUM_MAX]; 171 u32 num_irq; 172 u32 grp_id; 173 u64 timestamp; 174 bool napi_enabled; 175 struct napi_struct napi; 176 struct net_device *napi_ndev; 177 }; 178 179 enum ath12k_smbios_cc_type { 180 /* disable country code setting from SMBIOS */ 181 ATH12K_SMBIOS_CC_DISABLE = 0, 182 183 /* set country code by ANSI country name, based on ISO3166-1 alpha2 */ 184 ATH12K_SMBIOS_CC_ISO = 1, 185 186 /* worldwide regdomain */ 187 ATH12K_SMBIOS_CC_WW = 2, 188 }; 189 190 struct ath12k_smbios_bdf { 191 struct dmi_header hdr; 192 u8 features_disabled; 193 194 /* enum ath12k_smbios_cc_type */ 195 u8 country_code_flag; 196 197 /* To set specific country, you need to set country code 198 * flag=ATH12K_SMBIOS_CC_ISO first, then if country is United 199 * States, then country code value = 0x5553 ("US",'U' = 0x55, 'S'= 200 * 0x53). To set country to INDONESIA, then country code value = 201 * 0x4944 ("IN", 'I'=0x49, 'D'=0x44). If country code flag = 202 * ATH12K_SMBIOS_CC_WW, then you can use worldwide regulatory 203 * setting. 204 */ 205 u16 cc_code; 206 207 u8 bdf_enabled; 208 u8 bdf_ext[]; 209 } __packed; 210 211 #define HEHANDLE_CAP_PHYINFO_SIZE 3 212 #define HECAP_PHYINFO_SIZE 9 213 #define HECAP_MACINFO_SIZE 5 214 #define HECAP_TXRX_MCS_NSS_SIZE 2 215 #define HECAP_PPET16_PPET8_MAX_SIZE 25 216 217 #define HE_PPET16_PPET8_SIZE 8 218 219 /* 802.11ax PPE (PPDU packet Extension) threshold */ 220 struct he_ppe_threshold { 221 u32 numss_m1; 222 u32 ru_mask; 223 u32 ppet16_ppet8_ru3_ru0[HE_PPET16_PPET8_SIZE]; 224 }; 225 226 struct ath12k_he { 227 u8 hecap_macinfo[HECAP_MACINFO_SIZE]; 228 u32 hecap_rxmcsnssmap; 229 u32 hecap_txmcsnssmap; 230 u32 hecap_phyinfo[HEHANDLE_CAP_PHYINFO_SIZE]; 231 struct he_ppe_threshold hecap_ppet; 232 u32 heop_param; 233 }; 234 235 enum { 236 WMI_HOST_TP_SCALE_MAX = 0, 237 WMI_HOST_TP_SCALE_50 = 1, 238 WMI_HOST_TP_SCALE_25 = 2, 239 WMI_HOST_TP_SCALE_12 = 3, 240 WMI_HOST_TP_SCALE_MIN = 4, 241 WMI_HOST_TP_SCALE_SIZE = 5, 242 }; 243 244 enum ath12k_scan_state { 245 ATH12K_SCAN_IDLE, 246 ATH12K_SCAN_STARTING, 247 ATH12K_SCAN_RUNNING, 248 ATH12K_SCAN_ABORTING, 249 }; 250 251 enum ath12k_11d_state { 252 ATH12K_11D_IDLE, 253 ATH12K_11D_PREPARING, 254 ATH12K_11D_RUNNING, 255 }; 256 257 enum ath12k_hw_group_flags { 258 ATH12K_GROUP_FLAG_REGISTERED, 259 ATH12K_GROUP_FLAG_UNREGISTER, 260 }; 261 262 enum ath12k_dev_flags { 263 ATH12K_FLAG_CAC_RUNNING, 264 ATH12K_FLAG_CRASH_FLUSH, 265 ATH12K_FLAG_RAW_MODE, 266 ATH12K_FLAG_HW_CRYPTO_DISABLED, 267 ATH12K_FLAG_RECOVERY, 268 ATH12K_FLAG_UNREGISTERING, 269 ATH12K_FLAG_REGISTERED, 270 ATH12K_FLAG_QMI_FAIL, 271 ATH12K_FLAG_HTC_SUSPEND_COMPLETE, 272 ATH12K_FLAG_CE_IRQ_ENABLED, 273 ATH12K_FLAG_EXT_IRQ_ENABLED, 274 ATH12K_FLAG_QMI_FW_READY_COMPLETE, 275 ATH12K_FLAG_FTM_SEGMENTED, 276 ATH12K_FLAG_FIXED_MEM_REGION, 277 }; 278 279 struct ath12k_tx_conf { 280 bool changed; 281 u16 ac; 282 struct ieee80211_tx_queue_params tx_queue_params; 283 }; 284 285 struct ath12k_key_conf { 286 enum set_key_cmd cmd; 287 struct list_head list; 288 struct ieee80211_sta *sta; 289 struct ieee80211_key_conf *key; 290 }; 291 292 struct ath12k_vif_cache { 293 struct ath12k_tx_conf tx_conf; 294 struct ath12k_key_conf key_conf; 295 u32 bss_conf_changed; 296 }; 297 298 struct ath12k_rekey_data { 299 u8 kck[NL80211_KCK_LEN]; 300 u8 kek[NL80211_KCK_LEN]; 301 u64 replay_ctr; 302 bool enable_offload; 303 }; 304 305 struct ath12k_link_vif { 306 u32 vdev_id; 307 u32 beacon_interval; 308 u32 dtim_period; 309 u16 ast_hash; 310 u16 ast_idx; 311 u16 tcl_metadata; 312 u8 hal_addr_search_flags; 313 u8 search_type; 314 315 struct ath12k *ar; 316 317 int bank_id; 318 u8 vdev_id_check_en; 319 320 struct wmi_wmm_params_all_arg wmm_params; 321 struct list_head list; 322 323 bool is_created; 324 bool is_started; 325 bool is_up; 326 u8 bssid[ETH_ALEN]; 327 struct cfg80211_bitrate_mask bitrate_mask; 328 struct delayed_work connection_loss_work; 329 int num_legacy_stations; 330 int rtscts_prot_mode; 331 int txpower; 332 bool rsnie_present; 333 bool wpaie_present; 334 u8 vdev_stats_id; 335 u32 punct_bitmap; 336 u8 link_id; 337 struct ath12k_vif *ahvif; 338 struct ath12k_rekey_data rekey_data; 339 struct ath12k_link_stats link_stats; 340 spinlock_t link_stats_lock; /* Protects updates to link_stats */ 341 342 u8 current_cntdown_counter; 343 344 /* only used in station mode */ 345 bool is_sta_assoc_link; 346 347 struct ath12k_reg_tpc_power_info reg_tpc_info; 348 349 bool group_key_valid; 350 struct wmi_vdev_install_key_arg group_key; 351 bool pairwise_key_done; 352 }; 353 354 struct ath12k_vif { 355 enum wmi_vdev_type vdev_type; 356 enum wmi_vdev_subtype vdev_subtype; 357 struct ieee80211_vif *vif; 358 struct ath12k_hw *ah; 359 360 union { 361 struct { 362 u32 uapsd; 363 } sta; 364 struct { 365 /* 127 stations; wmi limit */ 366 u8 tim_bitmap[16]; 367 u8 tim_len; 368 u32 ssid_len; 369 u8 ssid[IEEE80211_MAX_SSID_LEN]; 370 bool hidden_ssid; 371 /* P2P_IE with NoA attribute for P2P_GO case */ 372 u32 noa_len; 373 u8 *noa_data; 374 } ap; 375 } u; 376 377 u32 aid; 378 u32 key_cipher; 379 u8 tx_encap_type; 380 bool ps; 381 atomic_t mcbc_gsn; 382 383 struct ath12k_link_vif deflink; 384 struct ath12k_link_vif __rcu *link[ATH12K_NUM_MAX_LINKS]; 385 struct ath12k_vif_cache *cache[IEEE80211_MLD_MAX_NUM_LINKS]; 386 /* indicates bitmap of link vif created in FW */ 387 u32 links_map; 388 /* Must be last - ends in a flexible-array member. 389 * 390 * FIXME: Driver should not copy struct ieee80211_chanctx_conf, 391 * especially because it has a flexible array. Find a better way. 392 */ 393 struct ieee80211_chanctx_conf chanctx; 394 }; 395 396 struct ath12k_vif_iter { 397 u32 vdev_id; 398 struct ath12k *ar; 399 struct ath12k_link_vif *arvif; 400 }; 401 402 #define HAL_AST_IDX_INVALID 0xFFFF 403 #define HAL_RX_MAX_MCS 12 404 #define HAL_RX_MAX_MCS_HT 31 405 #define HAL_RX_MAX_MCS_VHT 9 406 #define HAL_RX_MAX_MCS_HE 11 407 #define HAL_RX_MAX_MCS_BE 15 408 #define HAL_RX_MAX_NSS 8 409 #define HAL_RX_MAX_NUM_LEGACY_RATES 12 410 411 #define ATH12K_SCAN_TIMEOUT_HZ (20 * HZ) 412 413 struct ath12k_rx_peer_rate_stats { 414 u64 ht_mcs_count[HAL_RX_MAX_MCS_HT + 1]; 415 u64 vht_mcs_count[HAL_RX_MAX_MCS_VHT + 1]; 416 u64 he_mcs_count[HAL_RX_MAX_MCS_HE + 1]; 417 u64 be_mcs_count[HAL_RX_MAX_MCS_BE + 1]; 418 u64 nss_count[HAL_RX_MAX_NSS]; 419 u64 bw_count[HAL_RX_BW_MAX]; 420 u64 gi_count[HAL_RX_GI_MAX]; 421 u64 legacy_count[HAL_RX_MAX_NUM_LEGACY_RATES]; 422 u64 rx_rate[HAL_RX_BW_MAX][HAL_RX_GI_MAX][HAL_RX_MAX_NSS][HAL_RX_MAX_MCS_HT + 1]; 423 }; 424 425 struct ath12k_rx_peer_stats { 426 u64 num_msdu; 427 u64 num_mpdu_fcs_ok; 428 u64 num_mpdu_fcs_err; 429 u64 tcp_msdu_count; 430 u64 udp_msdu_count; 431 u64 other_msdu_count; 432 u64 ampdu_msdu_count; 433 u64 non_ampdu_msdu_count; 434 u64 stbc_count; 435 u64 beamformed_count; 436 u64 coding_count[HAL_RX_SU_MU_CODING_MAX]; 437 u64 tid_count[IEEE80211_NUM_TIDS + 1]; 438 u64 pream_cnt[HAL_RX_PREAMBLE_MAX]; 439 u64 reception_type[HAL_RX_RECEPTION_TYPE_MAX]; 440 u64 rx_duration; 441 u64 dcm_count; 442 u64 ru_alloc_cnt[HAL_RX_RU_ALLOC_TYPE_MAX]; 443 struct ath12k_rx_peer_rate_stats pkt_stats; 444 struct ath12k_rx_peer_rate_stats byte_stats; 445 }; 446 447 #define ATH12K_HE_MCS_NUM 12 448 #define ATH12K_VHT_MCS_NUM 10 449 #define ATH12K_BW_NUM 5 450 #define ATH12K_NSS_NUM 4 451 #define ATH12K_LEGACY_NUM 12 452 #define ATH12K_GI_NUM 4 453 #define ATH12K_HT_MCS_NUM 32 454 455 enum ath12k_pkt_rx_err { 456 ATH12K_PKT_RX_ERR_FCS, 457 ATH12K_PKT_RX_ERR_TKIP, 458 ATH12K_PKT_RX_ERR_CRYPT, 459 ATH12K_PKT_RX_ERR_PEER_IDX_INVAL, 460 ATH12K_PKT_RX_ERR_MAX, 461 }; 462 463 enum ath12k_ampdu_subfrm_num { 464 ATH12K_AMPDU_SUBFRM_NUM_10, 465 ATH12K_AMPDU_SUBFRM_NUM_20, 466 ATH12K_AMPDU_SUBFRM_NUM_30, 467 ATH12K_AMPDU_SUBFRM_NUM_40, 468 ATH12K_AMPDU_SUBFRM_NUM_50, 469 ATH12K_AMPDU_SUBFRM_NUM_60, 470 ATH12K_AMPDU_SUBFRM_NUM_MORE, 471 ATH12K_AMPDU_SUBFRM_NUM_MAX, 472 }; 473 474 enum ath12k_amsdu_subfrm_num { 475 ATH12K_AMSDU_SUBFRM_NUM_1, 476 ATH12K_AMSDU_SUBFRM_NUM_2, 477 ATH12K_AMSDU_SUBFRM_NUM_3, 478 ATH12K_AMSDU_SUBFRM_NUM_4, 479 ATH12K_AMSDU_SUBFRM_NUM_MORE, 480 ATH12K_AMSDU_SUBFRM_NUM_MAX, 481 }; 482 483 enum ath12k_counter_type { 484 ATH12K_COUNTER_TYPE_BYTES, 485 ATH12K_COUNTER_TYPE_PKTS, 486 ATH12K_COUNTER_TYPE_MAX, 487 }; 488 489 enum ath12k_stats_type { 490 ATH12K_STATS_TYPE_SUCC, 491 ATH12K_STATS_TYPE_FAIL, 492 ATH12K_STATS_TYPE_RETRY, 493 ATH12K_STATS_TYPE_AMPDU, 494 ATH12K_STATS_TYPE_MAX, 495 }; 496 497 struct ath12k_htt_data_stats { 498 u64 legacy[ATH12K_COUNTER_TYPE_MAX][ATH12K_LEGACY_NUM]; 499 u64 ht[ATH12K_COUNTER_TYPE_MAX][ATH12K_HT_MCS_NUM]; 500 u64 vht[ATH12K_COUNTER_TYPE_MAX][ATH12K_VHT_MCS_NUM]; 501 u64 he[ATH12K_COUNTER_TYPE_MAX][ATH12K_HE_MCS_NUM]; 502 u64 bw[ATH12K_COUNTER_TYPE_MAX][ATH12K_BW_NUM]; 503 u64 nss[ATH12K_COUNTER_TYPE_MAX][ATH12K_NSS_NUM]; 504 u64 gi[ATH12K_COUNTER_TYPE_MAX][ATH12K_GI_NUM]; 505 u64 transmit_type[ATH12K_COUNTER_TYPE_MAX][HAL_RX_RECEPTION_TYPE_MAX]; 506 u64 ru_loc[ATH12K_COUNTER_TYPE_MAX][HAL_RX_RU_ALLOC_TYPE_MAX]; 507 }; 508 509 struct ath12k_htt_tx_stats { 510 struct ath12k_htt_data_stats stats[ATH12K_STATS_TYPE_MAX]; 511 u64 tx_duration; 512 u64 ba_fails; 513 u64 ack_fails; 514 u16 ru_start; 515 u16 ru_tones; 516 u32 mu_group[MAX_MU_GROUP_ID]; 517 }; 518 519 struct ath12k_per_ppdu_tx_stats { 520 u16 succ_pkts; 521 u16 failed_pkts; 522 u16 retry_pkts; 523 u32 succ_bytes; 524 u32 failed_bytes; 525 u32 retry_bytes; 526 }; 527 528 struct ath12k_wbm_tx_stats { 529 u64 wbm_tx_comp_stats[HAL_WBM_REL_HTT_TX_COMP_STATUS_MAX]; 530 }; 531 532 DECLARE_EWMA(avg_rssi, 10, 8) 533 534 struct ath12k_link_sta { 535 struct ath12k_link_vif *arvif; 536 struct ath12k_sta *ahsta; 537 538 /* link address similar to ieee80211_link_sta */ 539 u8 addr[ETH_ALEN]; 540 541 /* the following are protected by ar->data_lock */ 542 u32 changed; /* IEEE80211_RC_* */ 543 u32 bw; 544 u32 nss; 545 u32 smps; 546 547 struct wiphy_work update_wk; 548 struct rate_info txrate; 549 struct rate_info last_txrate; 550 u64 rx_duration; 551 u64 tx_duration; 552 u8 rssi_comb; 553 struct ewma_avg_rssi avg_rssi; 554 u8 link_id; 555 struct ath12k_rx_peer_stats *rx_stats; 556 struct ath12k_wbm_tx_stats *wbm_tx_stats; 557 u32 bw_prev; 558 u32 peer_nss; 559 s8 rssi_beacon; 560 561 /* For now the assoc link will be considered primary */ 562 bool is_assoc_link; 563 564 /* for firmware use only */ 565 u8 link_idx; 566 }; 567 568 struct ath12k_reoq_buf { 569 void *vaddr; 570 dma_addr_t paddr_aligned; 571 u32 size; 572 }; 573 574 struct ath12k_sta { 575 struct ath12k_vif *ahvif; 576 enum hal_pn_type pn_type; 577 struct ath12k_link_sta deflink; 578 struct ath12k_link_sta __rcu *link[IEEE80211_MLD_MAX_NUM_LINKS]; 579 /* indicates bitmap of link sta created in FW */ 580 u16 links_map; 581 u8 assoc_link_id; 582 u16 ml_peer_id; 583 u8 num_peer; 584 585 enum ieee80211_sta_state state; 586 587 struct ath12k_reoq_buf reoq_bufs[IEEE80211_NUM_TIDS + 1]; 588 }; 589 590 #define ATH12K_HALF_20MHZ_BW 10 591 #define ATH12K_2GHZ_MIN_CENTER 2412 592 #define ATH12K_2GHZ_MAX_CENTER 2484 593 #define ATH12K_5GHZ_MIN_CENTER 4900 594 #define ATH12K_5GHZ_MAX_CENTER 5920 595 #define ATH12K_6GHZ_MIN_CENTER 5935 596 #define ATH12K_6GHZ_MAX_CENTER 7115 597 #define ATH12K_MIN_2GHZ_FREQ (ATH12K_2GHZ_MIN_CENTER - ATH12K_HALF_20MHZ_BW - 1) 598 #define ATH12K_MAX_2GHZ_FREQ (ATH12K_2GHZ_MAX_CENTER + ATH12K_HALF_20MHZ_BW + 1) 599 #define ATH12K_MIN_5GHZ_FREQ (ATH12K_5GHZ_MIN_CENTER - ATH12K_HALF_20MHZ_BW) 600 #define ATH12K_MAX_5GHZ_FREQ (ATH12K_5GHZ_MAX_CENTER + ATH12K_HALF_20MHZ_BW) 601 #define ATH12K_MIN_6GHZ_FREQ (ATH12K_6GHZ_MIN_CENTER - ATH12K_HALF_20MHZ_BW) 602 #define ATH12K_MAX_6GHZ_FREQ (ATH12K_6GHZ_MAX_CENTER + ATH12K_HALF_20MHZ_BW) 603 #define ATH12K_NUM_CHANS 101 604 #define ATH12K_MAX_5GHZ_CHAN 173 605 606 static inline bool ath12k_is_2ghz_channel_freq(u32 freq) 607 { 608 return freq >= ATH12K_MIN_2GHZ_FREQ && 609 freq <= ATH12K_MAX_2GHZ_FREQ; 610 } 611 612 enum ath12k_hw_state { 613 ATH12K_HW_STATE_OFF, 614 ATH12K_HW_STATE_ON, 615 ATH12K_HW_STATE_RESTARTING, 616 ATH12K_HW_STATE_RESTARTED, 617 ATH12K_HW_STATE_WEDGED, 618 ATH12K_HW_STATE_TM, 619 /* Add other states as required */ 620 }; 621 622 /* Antenna noise floor */ 623 #define ATH12K_DEFAULT_NOISE_FLOOR -95 624 625 struct ath12k_ftm_event_obj { 626 u32 data_pos; 627 u32 expected_seq; 628 u8 *eventdata; 629 }; 630 631 struct ath12k_fw_stats { 632 u32 pdev_id; 633 u32 stats_id; 634 struct list_head pdevs; 635 struct list_head vdevs; 636 struct list_head bcn; 637 u32 num_vdev_recvd; 638 u32 num_bcn_recvd; 639 }; 640 641 struct ath12k_dbg_htt_stats { 642 enum ath12k_dbg_htt_ext_stats_type type; 643 u32 cfg_param[4]; 644 u8 reset; 645 struct debug_htt_stats_req *stats_req; 646 }; 647 648 struct ath12k_debug { 649 struct dentry *debugfs_pdev; 650 struct dentry *debugfs_pdev_symlink; 651 struct ath12k_dbg_htt_stats htt_stats; 652 enum wmi_halphy_ctrl_path_stats_id tpc_stats_type; 653 bool tpc_request; 654 struct completion tpc_complete; 655 struct wmi_tpc_stats_arg *tpc_stats; 656 u32 rx_filter; 657 bool extd_rx_stats; 658 }; 659 660 struct ath12k_per_peer_tx_stats { 661 u32 succ_bytes; 662 u32 retry_bytes; 663 u32 failed_bytes; 664 u32 duration; 665 u16 succ_pkts; 666 u16 retry_pkts; 667 u16 failed_pkts; 668 u16 ru_start; 669 u16 ru_tones; 670 u8 ba_fails; 671 u8 ppdu_type; 672 u32 mu_grpid; 673 u32 mu_pos; 674 bool is_ampdu; 675 }; 676 677 #define ATH12K_FLUSH_TIMEOUT (5 * HZ) 678 #define ATH12K_VDEV_DELETE_TIMEOUT_HZ (5 * HZ) 679 680 struct ath12k { 681 struct ath12k_base *ab; 682 struct ath12k_pdev *pdev; 683 struct ath12k_hw *ah; 684 struct ath12k_wmi_pdev *wmi; 685 struct ath12k_pdev_dp dp; 686 u8 mac_addr[ETH_ALEN]; 687 u32 ht_cap_info; 688 u32 vht_cap_info; 689 struct ath12k_he ar_he; 690 bool supports_6ghz; 691 struct { 692 struct completion started; 693 struct completion completed; 694 struct completion on_channel; 695 struct delayed_work timeout; 696 enum ath12k_scan_state state; 697 bool is_roc; 698 int roc_freq; 699 bool roc_notify; 700 struct wiphy_work vdev_clean_wk; 701 struct ath12k_link_vif *arvif; 702 } scan; 703 704 struct { 705 struct ieee80211_supported_band sbands[NUM_NL80211_BANDS]; 706 struct ieee80211_sband_iftype_data 707 iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES]; 708 } mac; 709 710 unsigned long dev_flags; 711 unsigned int filter_flags; 712 u32 min_tx_power; 713 u32 max_tx_power; 714 u32 txpower_limit_2g; 715 u32 txpower_limit_5g; 716 u32 txpower_scale; 717 u32 power_scale; 718 u32 chan_tx_pwr; 719 u32 num_stations; 720 u32 max_num_stations; 721 722 /* protects the radio specific data like debug stats, ppdu_stats_info stats, 723 * vdev_stop_status info, scan data, ath12k_sta info, ath12k_link_vif info, 724 * channel context data, survey info, test mode data, regd_channel_update_queue. 725 */ 726 spinlock_t data_lock; 727 728 struct list_head arvifs; 729 /* should never be NULL; needed for regular htt rx */ 730 struct ieee80211_channel *rx_channel; 731 732 /* valid during scan; needed for mgmt rx during scan */ 733 struct ieee80211_channel *scan_channel; 734 735 u8 cfg_tx_chainmask; 736 u8 cfg_rx_chainmask; 737 u8 num_rx_chains; 738 u8 num_tx_chains; 739 /* pdev_idx starts from 0 whereas pdev->pdev_id starts with 1 */ 740 u8 pdev_idx; 741 u8 lmac_id; 742 u8 hw_link_id; 743 744 struct completion peer_assoc_done; 745 struct completion peer_delete_done; 746 747 int install_key_status; 748 struct completion install_key_done; 749 750 int last_wmi_vdev_start_status; 751 struct completion vdev_setup_done; 752 struct completion vdev_delete_done; 753 754 int num_peers; 755 int max_num_peers; 756 u32 num_started_vdevs; 757 u32 num_created_vdevs; 758 unsigned long long allocated_vdev_map; 759 760 struct idr txmgmt_idr; 761 /* protects txmgmt_idr data */ 762 spinlock_t txmgmt_idr_lock; 763 atomic_t num_pending_mgmt_tx; 764 wait_queue_head_t txmgmt_empty_waitq; 765 766 /* cycle count is reported twice for each visited channel during scan. 767 * access protected by data_lock 768 */ 769 u32 survey_last_rx_clear_count; 770 u32 survey_last_cycle_count; 771 772 /* Channel info events are expected to come in pairs without and with 773 * COMPLETE flag set respectively for each channel visit during scan. 774 * 775 * However there are deviations from this rule. This flag is used to 776 * avoid reporting garbage data. 777 */ 778 bool ch_info_can_report_survey; 779 struct survey_info survey[ATH12K_NUM_CHANS]; 780 struct completion bss_survey_done; 781 782 struct work_struct regd_update_work; 783 struct work_struct regd_channel_update_work; 784 struct list_head regd_channel_update_queue; 785 786 struct wiphy_work wmi_mgmt_tx_work; 787 struct sk_buff_head wmi_mgmt_tx_queue; 788 789 struct ath12k_wow wow; 790 struct completion target_suspend; 791 bool target_suspend_ack; 792 struct ath12k_per_peer_tx_stats peer_tx_stats; 793 struct list_head ppdu_stats_info; 794 u32 ppdu_stat_list_depth; 795 796 struct ath12k_per_peer_tx_stats cached_stats; 797 u32 last_ppdu_id; 798 u32 cached_ppdu_id; 799 #ifdef CONFIG_ATH12K_DEBUGFS 800 struct ath12k_debug debug; 801 #endif 802 803 bool dfs_block_radar_events; 804 bool monitor_vdev_created; 805 bool monitor_started; 806 int monitor_vdev_id; 807 808 struct wiphy_radio_freq_range freq_range; 809 810 bool nlo_enabled; 811 812 /* Protected by wiphy::mtx lock. */ 813 u32 vdev_id_11d_scan; 814 struct completion completed_11d_scan; 815 enum ath12k_11d_state state_11d; 816 u8 alpha2[REG_ALPHA2_LEN]; 817 bool regdom_set_by_user; 818 struct completion regd_update_completed; 819 820 struct completion fw_stats_complete; 821 struct completion fw_stats_done; 822 823 struct completion mlo_setup_done; 824 u32 mlo_setup_status; 825 u8 ftm_msgref; 826 struct ath12k_fw_stats fw_stats; 827 unsigned long last_tx_power_update; 828 829 s8 max_allowed_tx_power; 830 }; 831 832 struct ath12k_hw { 833 struct ieee80211_hw *hw; 834 struct device *dev; 835 836 /* Protect the write operation of the hardware state ath12k_hw::state 837 * between hardware start<=>reconfigure<=>stop transitions. 838 */ 839 struct mutex hw_mutex; 840 enum ath12k_hw_state state; 841 bool regd_updated; 842 bool use_6ghz_regd; 843 844 u8 num_radio; 845 846 DECLARE_BITMAP(free_ml_peer_id_map, ATH12K_MAX_MLO_PEERS); 847 848 /* protected by wiphy_lock() */ 849 struct list_head ml_peers; 850 851 /* Keep last */ 852 struct ath12k radio[] __aligned(sizeof(void *)); 853 }; 854 855 struct ath12k_band_cap { 856 u32 phy_id; 857 u32 max_bw_supported; 858 u32 ht_cap_info; 859 u32 he_cap_info[2]; 860 u32 he_mcs; 861 u32 he_cap_phy_info[PSOC_HOST_MAX_PHY_SIZE]; 862 struct ath12k_wmi_ppe_threshold_arg he_ppet; 863 u16 he_6ghz_capa; 864 u32 eht_cap_mac_info[WMI_MAX_EHTCAP_MAC_SIZE]; 865 u32 eht_cap_phy_info[WMI_MAX_EHTCAP_PHY_SIZE]; 866 u32 eht_mcs_20_only; 867 u32 eht_mcs_80; 868 u32 eht_mcs_160; 869 u32 eht_mcs_320; 870 struct ath12k_wmi_ppe_threshold_arg eht_ppet; 871 u32 eht_cap_info_internal; 872 }; 873 874 struct ath12k_pdev_cap { 875 u32 supported_bands; 876 u32 ampdu_density; 877 u32 vht_cap; 878 u32 vht_mcs; 879 u32 he_mcs; 880 u32 tx_chain_mask; 881 u32 rx_chain_mask; 882 u32 tx_chain_mask_shift; 883 u32 rx_chain_mask_shift; 884 struct ath12k_band_cap band[NUM_NL80211_BANDS]; 885 u32 eml_cap; 886 u32 mld_cap; 887 }; 888 889 struct mlo_timestamp { 890 u32 info; 891 u32 sync_timestamp_lo_us; 892 u32 sync_timestamp_hi_us; 893 u32 mlo_offset_lo; 894 u32 mlo_offset_hi; 895 u32 mlo_offset_clks; 896 u32 mlo_comp_clks; 897 u32 mlo_comp_timer; 898 }; 899 900 struct ath12k_pdev { 901 struct ath12k *ar; 902 u32 pdev_id; 903 u32 hw_link_id; 904 struct ath12k_pdev_cap cap; 905 u8 mac_addr[ETH_ALEN]; 906 struct mlo_timestamp timestamp; 907 }; 908 909 struct ath12k_fw_pdev { 910 u32 pdev_id; 911 u32 phy_id; 912 u32 supported_bands; 913 }; 914 915 struct ath12k_board_data { 916 const struct firmware *fw; 917 const void *data; 918 size_t len; 919 }; 920 921 struct ath12k_device_dp_tx_err_stats { 922 /* TCL Ring Descriptor unavailable */ 923 u32 desc_na[DP_TCL_NUM_RING_MAX]; 924 /* Other failures during dp_tx due to mem allocation failure 925 * idr unavailable etc. 926 */ 927 atomic_t misc_fail; 928 }; 929 930 struct ath12k_device_dp_stats { 931 u32 err_ring_pkts; 932 u32 invalid_rbm; 933 u32 rxdma_error[HAL_REO_ENTR_RING_RXDMA_ECODE_MAX]; 934 u32 reo_error[HAL_REO_DEST_RING_ERROR_CODE_MAX]; 935 u32 hal_reo_error[DP_REO_DST_RING_MAX]; 936 struct ath12k_device_dp_tx_err_stats tx_err; 937 u32 reo_rx[DP_REO_DST_RING_MAX][ATH12K_MAX_DEVICES]; 938 u32 rx_wbm_rel_source[HAL_WBM_REL_SRC_MODULE_MAX][ATH12K_MAX_DEVICES]; 939 u32 tqm_rel_reason[MAX_TQM_RELEASE_REASON]; 940 u32 fw_tx_status[MAX_FW_TX_STATUS]; 941 u32 tx_wbm_rel_source[HAL_WBM_REL_SRC_MODULE_MAX]; 942 u32 tx_enqueued[DP_TCL_NUM_RING_MAX]; 943 u32 tx_completed[DP_TCL_NUM_RING_MAX]; 944 }; 945 946 struct ath12k_reg_freq { 947 u32 start_freq; 948 u32 end_freq; 949 }; 950 951 struct ath12k_mlo_memory { 952 struct target_mem_chunk chunk[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 953 int mlo_mem_size; 954 bool init_done; 955 }; 956 957 struct ath12k_hw_link { 958 u8 device_id; 959 u8 pdev_idx; 960 }; 961 962 /* Holds info on the group of devices that are registered as a single 963 * wiphy, protected with struct ath12k_hw_group::mutex. 964 */ 965 struct ath12k_hw_group { 966 struct list_head list; 967 u8 id; 968 u8 num_devices; 969 u8 num_probed; 970 u8 num_started; 971 unsigned long flags; 972 struct ath12k_base *ab[ATH12K_MAX_DEVICES]; 973 974 /* protects access to this struct */ 975 struct mutex mutex; 976 977 /* Holds information of wiphy (hw) registration. 978 * 979 * In Multi/Single Link Operation case, all pdevs are registered as 980 * a single wiphy. In other (legacy/Non-MLO) cases, each pdev is 981 * registered as separate wiphys. 982 */ 983 struct ath12k_hw *ah[ATH12K_GROUP_MAX_RADIO]; 984 u8 num_hw; 985 bool mlo_capable; 986 struct device_node *wsi_node[ATH12K_MAX_DEVICES]; 987 struct ath12k_mlo_memory mlo_mem; 988 struct ath12k_hw_link hw_links[ATH12K_GROUP_MAX_RADIO]; 989 bool hw_link_id_init_done; 990 }; 991 992 /* Holds WSI info specific to each device, excluding WSI group info */ 993 struct ath12k_wsi_info { 994 u32 index; 995 u32 hw_link_id_base; 996 }; 997 998 /* Master structure to hold the hw data which may be used in core module */ 999 struct ath12k_base { 1000 enum ath12k_hw_rev hw_rev; 1001 struct platform_device *pdev; 1002 struct device *dev; 1003 struct ath12k_qmi qmi; 1004 struct ath12k_wmi_base wmi_ab; 1005 struct completion fw_ready; 1006 u8 device_id; 1007 int num_radios; 1008 /* HW channel counters frequency value in hertz common to all MACs */ 1009 u32 cc_freq_hz; 1010 1011 struct ath12k_dump_file_data *dump_data; 1012 size_t ath12k_coredump_len; 1013 struct work_struct dump_work; 1014 1015 struct ath12k_htc htc; 1016 1017 struct ath12k_dp dp; 1018 1019 void __iomem *mem; 1020 unsigned long mem_len; 1021 1022 void __iomem *mem_ce; 1023 u32 ce_remap_base_addr; 1024 bool ce_remap; 1025 1026 struct { 1027 enum ath12k_bus bus; 1028 const struct ath12k_hif_ops *ops; 1029 } hif; 1030 1031 struct { 1032 struct completion wakeup_completed; 1033 u32 wmi_conf_rx_decap_mode; 1034 } wow; 1035 1036 struct ath12k_ce ce; 1037 struct timer_list rx_replenish_retry; 1038 struct ath12k_hal hal; 1039 /* To synchronize core_start/core_stop */ 1040 struct mutex core_lock; 1041 /* Protects data like peers */ 1042 spinlock_t base_lock; 1043 1044 /* Single pdev device (struct ath12k_hw_params::single_pdev_only): 1045 * 1046 * Firmware maintains data for all bands but advertises a single 1047 * phy to the host which is stored as a single element in this 1048 * array. 1049 * 1050 * Other devices: 1051 * 1052 * This array will contain as many elements as the number of 1053 * radios. 1054 */ 1055 struct ath12k_pdev pdevs[MAX_RADIOS]; 1056 1057 /* struct ath12k_hw_params::single_pdev_only devices use this to 1058 * store phy specific data 1059 */ 1060 struct ath12k_fw_pdev fw_pdev[MAX_RADIOS]; 1061 u8 fw_pdev_count; 1062 1063 struct ath12k_pdev __rcu *pdevs_active[MAX_RADIOS]; 1064 1065 struct ath12k_wmi_hal_reg_capabilities_ext_arg hal_reg_cap[MAX_RADIOS]; 1066 unsigned long long free_vdev_map; 1067 unsigned long long free_vdev_stats_id_map; 1068 struct list_head peers; 1069 wait_queue_head_t peer_mapping_wq; 1070 u8 mac_addr[ETH_ALEN]; 1071 bool wmi_ready; 1072 u32 wlan_init_status; 1073 int irq_num[ATH12K_IRQ_NUM_MAX]; 1074 struct ath12k_ext_irq_grp ext_irq_grp[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 1075 struct napi_struct *napi; 1076 struct ath12k_wmi_target_cap_arg target_caps; 1077 u32 ext_service_bitmap[WMI_SERVICE_EXT_BM_SIZE]; 1078 bool pdevs_macaddr_valid; 1079 1080 const struct ath12k_hw_params *hw_params; 1081 1082 const struct firmware *cal_file; 1083 1084 /* Below regd's are protected by ab->data_lock */ 1085 /* This is the regd set for every radio 1086 * by the firmware during initialization 1087 */ 1088 struct ieee80211_regdomain *default_regd[MAX_RADIOS]; 1089 /* This regd is set during dynamic country setting 1090 * This may or may not be used during the runtime 1091 */ 1092 struct ieee80211_regdomain *new_regd[MAX_RADIOS]; 1093 1094 struct ath12k_reg_info *reg_info[MAX_RADIOS]; 1095 1096 /* Current DFS Regulatory */ 1097 enum ath12k_dfs_region dfs_region; 1098 struct ath12k_device_dp_stats device_stats; 1099 #ifdef CONFIG_ATH12K_DEBUGFS 1100 struct dentry *debugfs_soc; 1101 #endif 1102 1103 unsigned long dev_flags; 1104 struct completion driver_recovery; 1105 struct workqueue_struct *workqueue; 1106 struct work_struct restart_work; 1107 struct workqueue_struct *workqueue_aux; 1108 struct work_struct reset_work; 1109 atomic_t reset_count; 1110 atomic_t recovery_count; 1111 bool is_reset; 1112 struct completion reset_complete; 1113 /* continuous recovery fail count */ 1114 atomic_t fail_cont_count; 1115 unsigned long reset_fail_timeout; 1116 struct work_struct update_11d_work; 1117 u8 new_alpha2[2]; 1118 struct { 1119 /* protected by data_lock */ 1120 u32 fw_crash_counter; 1121 } stats; 1122 u32 pktlog_defs_checksum; 1123 1124 struct ath12k_dbring_cap *db_caps; 1125 u32 num_db_cap; 1126 1127 struct completion htc_suspend; 1128 1129 u64 fw_soc_drop_count; 1130 bool static_window_map; 1131 1132 struct work_struct rfkill_work; 1133 /* true means radio is on */ 1134 bool rfkill_radio_on; 1135 1136 struct { 1137 enum ath12k_bdf_search bdf_search; 1138 u32 vendor; 1139 u32 device; 1140 u32 subsystem_vendor; 1141 u32 subsystem_device; 1142 } id; 1143 1144 struct { 1145 u32 api_version; 1146 1147 const struct firmware *fw; 1148 const u8 *amss_data; 1149 size_t amss_len; 1150 const u8 *amss_dualmac_data; 1151 size_t amss_dualmac_len; 1152 const u8 *m3_data; 1153 size_t m3_len; 1154 1155 DECLARE_BITMAP(fw_features, ATH12K_FW_FEATURE_COUNT); 1156 bool fw_features_valid; 1157 } fw; 1158 1159 const struct hal_rx_ops *hal_rx_ops; 1160 1161 struct completion restart_completed; 1162 1163 #ifdef CONFIG_ACPI 1164 1165 struct { 1166 bool started; 1167 u32 func_bit; 1168 bool acpi_tas_enable; 1169 bool acpi_bios_sar_enable; 1170 bool acpi_disable_11be; 1171 bool acpi_disable_rfkill; 1172 bool acpi_cca_enable; 1173 bool acpi_band_edge_enable; 1174 bool acpi_enable_bdf; 1175 u32 bit_flag; 1176 char bdf_string[ATH12K_ACPI_BDF_MAX_LEN]; 1177 u8 tas_cfg[ATH12K_ACPI_DSM_TAS_CFG_SIZE]; 1178 u8 tas_sar_power_table[ATH12K_ACPI_DSM_TAS_DATA_SIZE]; 1179 u8 bios_sar_data[ATH12K_ACPI_DSM_BIOS_SAR_DATA_SIZE]; 1180 u8 geo_offset_data[ATH12K_ACPI_DSM_GEO_OFFSET_DATA_SIZE]; 1181 u8 cca_data[ATH12K_ACPI_DSM_CCA_DATA_SIZE]; 1182 u8 band_edge_power[ATH12K_ACPI_DSM_BAND_EDGE_DATA_SIZE]; 1183 } acpi; 1184 1185 #endif /* CONFIG_ACPI */ 1186 1187 struct notifier_block panic_nb; 1188 1189 struct ath12k_hw_group *ag; 1190 struct ath12k_wsi_info wsi_info; 1191 enum ath12k_firmware_mode fw_mode; 1192 struct ath12k_ftm_event_obj ftm_event_obj; 1193 bool hw_group_ref; 1194 1195 /* Denote whether MLO is possible within the device */ 1196 bool single_chip_mlo_support; 1197 1198 struct ath12k_reg_freq reg_freq_2ghz; 1199 struct ath12k_reg_freq reg_freq_5ghz; 1200 struct ath12k_reg_freq reg_freq_6ghz; 1201 1202 /* must be last */ 1203 u8 drv_priv[] __aligned(sizeof(void *)); 1204 }; 1205 1206 struct ath12k_pdev_map { 1207 struct ath12k_base *ab; 1208 u8 pdev_idx; 1209 }; 1210 1211 struct ath12k_fw_stats_vdev { 1212 struct list_head list; 1213 1214 u32 vdev_id; 1215 u32 beacon_snr; 1216 u32 data_snr; 1217 u32 num_tx_frames[WLAN_MAX_AC]; 1218 u32 num_rx_frames; 1219 u32 num_tx_frames_retries[WLAN_MAX_AC]; 1220 u32 num_tx_frames_failures[WLAN_MAX_AC]; 1221 u32 num_rts_fail; 1222 u32 num_rts_success; 1223 u32 num_rx_err; 1224 u32 num_rx_discard; 1225 u32 num_tx_not_acked; 1226 u32 tx_rate_history[MAX_TX_RATE_VALUES]; 1227 u32 beacon_rssi_history[MAX_TX_RATE_VALUES]; 1228 }; 1229 1230 struct ath12k_fw_stats_bcn { 1231 struct list_head list; 1232 1233 u32 vdev_id; 1234 u32 tx_bcn_succ_cnt; 1235 u32 tx_bcn_outage_cnt; 1236 }; 1237 1238 struct ath12k_fw_stats_pdev { 1239 struct list_head list; 1240 1241 /* PDEV stats */ 1242 s32 ch_noise_floor; 1243 u32 tx_frame_count; 1244 u32 rx_frame_count; 1245 u32 rx_clear_count; 1246 u32 cycle_count; 1247 u32 phy_err_count; 1248 u32 chan_tx_power; 1249 u32 ack_rx_bad; 1250 u32 rts_bad; 1251 u32 rts_good; 1252 u32 fcs_bad; 1253 u32 no_beacons; 1254 u32 mib_int_count; 1255 1256 /* PDEV TX stats */ 1257 s32 comp_queued; 1258 s32 comp_delivered; 1259 s32 msdu_enqued; 1260 s32 mpdu_enqued; 1261 s32 wmm_drop; 1262 s32 local_enqued; 1263 s32 local_freed; 1264 s32 hw_queued; 1265 s32 hw_reaped; 1266 s32 underrun; 1267 s32 tx_abort; 1268 s32 mpdus_requed; 1269 u32 tx_ko; 1270 u32 data_rc; 1271 u32 self_triggers; 1272 u32 sw_retry_failure; 1273 u32 illgl_rate_phy_err; 1274 u32 pdev_cont_xretry; 1275 u32 pdev_tx_timeout; 1276 u32 pdev_resets; 1277 u32 stateless_tid_alloc_failure; 1278 u32 phy_underrun; 1279 u32 txop_ovf; 1280 1281 /* PDEV RX stats */ 1282 s32 mid_ppdu_route_change; 1283 s32 status_rcvd; 1284 s32 r0_frags; 1285 s32 r1_frags; 1286 s32 r2_frags; 1287 s32 r3_frags; 1288 s32 htt_msdus; 1289 s32 htt_mpdus; 1290 s32 loc_msdus; 1291 s32 loc_mpdus; 1292 s32 oversize_amsdu; 1293 s32 phy_errs; 1294 s32 phy_err_drop; 1295 s32 mpdu_errs; 1296 }; 1297 1298 int ath12k_core_qmi_firmware_ready(struct ath12k_base *ab); 1299 void ath12k_core_hw_group_cleanup(struct ath12k_hw_group *ag); 1300 int ath12k_core_pre_init(struct ath12k_base *ab); 1301 int ath12k_core_init(struct ath12k_base *ath12k); 1302 void ath12k_core_deinit(struct ath12k_base *ath12k); 1303 struct ath12k_base *ath12k_core_alloc(struct device *dev, size_t priv_size, 1304 enum ath12k_bus bus); 1305 void ath12k_core_free(struct ath12k_base *ath12k); 1306 int ath12k_core_fetch_board_data_api_1(struct ath12k_base *ab, 1307 struct ath12k_board_data *bd, 1308 char *filename); 1309 int ath12k_core_fetch_bdf(struct ath12k_base *ath12k, 1310 struct ath12k_board_data *bd); 1311 void ath12k_core_free_bdf(struct ath12k_base *ab, struct ath12k_board_data *bd); 1312 int ath12k_core_fetch_regdb(struct ath12k_base *ab, struct ath12k_board_data *bd); 1313 int ath12k_core_check_dt(struct ath12k_base *ath12k); 1314 int ath12k_core_check_smbios(struct ath12k_base *ab); 1315 void ath12k_core_halt(struct ath12k *ar); 1316 int ath12k_core_resume_early(struct ath12k_base *ab); 1317 int ath12k_core_resume(struct ath12k_base *ab); 1318 int ath12k_core_suspend(struct ath12k_base *ab); 1319 int ath12k_core_suspend_late(struct ath12k_base *ab); 1320 void ath12k_core_hw_group_unassign(struct ath12k_base *ab); 1321 u8 ath12k_get_num_partner_link(struct ath12k *ar); 1322 1323 const struct firmware *ath12k_core_firmware_request(struct ath12k_base *ab, 1324 const char *filename); 1325 u32 ath12k_core_get_max_station_per_radio(struct ath12k_base *ab); 1326 u32 ath12k_core_get_max_peers_per_radio(struct ath12k_base *ab); 1327 u32 ath12k_core_get_max_num_tids(struct ath12k_base *ab); 1328 1329 void ath12k_core_hw_group_set_mlo_capable(struct ath12k_hw_group *ag); 1330 void ath12k_fw_stats_init(struct ath12k *ar); 1331 void ath12k_fw_stats_bcn_free(struct list_head *head); 1332 void ath12k_fw_stats_free(struct ath12k_fw_stats *stats); 1333 void ath12k_fw_stats_reset(struct ath12k *ar); 1334 struct reserved_mem *ath12k_core_get_reserved_mem(struct ath12k_base *ab, 1335 int index); 1336 1337 static inline const char *ath12k_scan_state_str(enum ath12k_scan_state state) 1338 { 1339 switch (state) { 1340 case ATH12K_SCAN_IDLE: 1341 return "idle"; 1342 case ATH12K_SCAN_STARTING: 1343 return "starting"; 1344 case ATH12K_SCAN_RUNNING: 1345 return "running"; 1346 case ATH12K_SCAN_ABORTING: 1347 return "aborting"; 1348 } 1349 1350 return "unknown"; 1351 } 1352 1353 static inline struct ath12k_skb_cb *ATH12K_SKB_CB(struct sk_buff *skb) 1354 { 1355 BUILD_BUG_ON(sizeof(struct ath12k_skb_cb) > 1356 IEEE80211_TX_INFO_DRIVER_DATA_SIZE); 1357 return (struct ath12k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data; 1358 } 1359 1360 static inline struct ath12k_skb_rxcb *ATH12K_SKB_RXCB(struct sk_buff *skb) 1361 { 1362 BUILD_BUG_ON(sizeof(struct ath12k_skb_rxcb) > sizeof(skb->cb)); 1363 return (struct ath12k_skb_rxcb *)skb->cb; 1364 } 1365 1366 static inline struct ath12k_vif *ath12k_vif_to_ahvif(struct ieee80211_vif *vif) 1367 { 1368 return (struct ath12k_vif *)vif->drv_priv; 1369 } 1370 1371 static inline struct ath12k_sta *ath12k_sta_to_ahsta(struct ieee80211_sta *sta) 1372 { 1373 return (struct ath12k_sta *)sta->drv_priv; 1374 } 1375 1376 static inline struct ieee80211_sta *ath12k_ahsta_to_sta(struct ath12k_sta *ahsta) 1377 { 1378 return container_of((void *)ahsta, struct ieee80211_sta, drv_priv); 1379 } 1380 1381 static inline struct ieee80211_vif *ath12k_ahvif_to_vif(struct ath12k_vif *ahvif) 1382 { 1383 return container_of((void *)ahvif, struct ieee80211_vif, drv_priv); 1384 } 1385 1386 static inline struct ath12k *ath12k_ab_to_ar(struct ath12k_base *ab, 1387 int mac_id) 1388 { 1389 return ab->pdevs[ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id)].ar; 1390 } 1391 1392 static inline void ath12k_core_create_firmware_path(struct ath12k_base *ab, 1393 const char *filename, 1394 void *buf, size_t buf_len) 1395 { 1396 const char *fw_name = NULL; 1397 1398 of_property_read_string(ab->dev->of_node, "firmware-name", &fw_name); 1399 1400 if (fw_name && strncmp(filename, "board", 5)) 1401 snprintf(buf, buf_len, "%s/%s/%s/%s", ATH12K_FW_DIR, 1402 ab->hw_params->fw.dir, fw_name, filename); 1403 else 1404 snprintf(buf, buf_len, "%s/%s/%s", ATH12K_FW_DIR, 1405 ab->hw_params->fw.dir, filename); 1406 } 1407 1408 static inline const char *ath12k_bus_str(enum ath12k_bus bus) 1409 { 1410 switch (bus) { 1411 case ATH12K_BUS_PCI: 1412 return "pci"; 1413 case ATH12K_BUS_AHB: 1414 return "ahb"; 1415 } 1416 1417 return "unknown"; 1418 } 1419 1420 static inline struct ath12k_hw *ath12k_hw_to_ah(struct ieee80211_hw *hw) 1421 { 1422 return hw->priv; 1423 } 1424 1425 static inline struct ath12k *ath12k_ah_to_ar(struct ath12k_hw *ah, u8 hw_link_id) 1426 { 1427 if (WARN(hw_link_id >= ah->num_radio, 1428 "bad hw link id %d, so switch to default link\n", hw_link_id)) 1429 hw_link_id = 0; 1430 1431 return &ah->radio[hw_link_id]; 1432 } 1433 1434 static inline struct ath12k_hw *ath12k_ar_to_ah(struct ath12k *ar) 1435 { 1436 return ar->ah; 1437 } 1438 1439 static inline struct ieee80211_hw *ath12k_ar_to_hw(struct ath12k *ar) 1440 { 1441 return ar->ah->hw; 1442 } 1443 1444 #define for_each_ar(ah, ar, index) \ 1445 for ((index) = 0; ((index) < (ah)->num_radio && \ 1446 ((ar) = &(ah)->radio[(index)])); (index)++) 1447 1448 static inline struct ath12k_hw *ath12k_ag_to_ah(struct ath12k_hw_group *ag, int idx) 1449 { 1450 return ag->ah[idx]; 1451 } 1452 1453 static inline void ath12k_ag_set_ah(struct ath12k_hw_group *ag, int idx, 1454 struct ath12k_hw *ah) 1455 { 1456 ag->ah[idx] = ah; 1457 } 1458 1459 static inline struct ath12k_hw_group *ath12k_ab_to_ag(struct ath12k_base *ab) 1460 { 1461 return ab->ag; 1462 } 1463 1464 static inline struct ath12k_base *ath12k_ag_to_ab(struct ath12k_hw_group *ag, 1465 u8 device_id) 1466 { 1467 return ag->ab[device_id]; 1468 } 1469 1470 #endif /* _CORE_H_ */ 1471