1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef ATH12K_CORE_H 8 #define ATH12K_CORE_H 9 10 #include <linux/types.h> 11 #include <linux/interrupt.h> 12 #include <linux/irq.h> 13 #include <linux/bitfield.h> 14 #include <linux/dmi.h> 15 #include <linux/ctype.h> 16 #include <linux/firmware.h> 17 #include <linux/of_reserved_mem.h> 18 #include <linux/panic_notifier.h> 19 #include <linux/average.h> 20 #include "qmi.h" 21 #include "htc.h" 22 #include "wmi.h" 23 #include "hal.h" 24 #include "dp.h" 25 #include "ce.h" 26 #include "mac.h" 27 #include "hw.h" 28 #include "hal_rx.h" 29 #include "reg.h" 30 #include "dbring.h" 31 #include "fw.h" 32 #include "acpi.h" 33 #include "wow.h" 34 #include "debugfs_htt_stats.h" 35 #include "coredump.h" 36 37 #define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK) 38 39 #define ATH12K_TX_MGMT_NUM_PENDING_MAX 512 40 41 #define ATH12K_TX_MGMT_TARGET_MAX_SUPPORT_WMI 64 42 43 /* Pending management packets threshold for dropping probe responses */ 44 #define ATH12K_PRB_RSP_DROP_THRESHOLD ((ATH12K_TX_MGMT_TARGET_MAX_SUPPORT_WMI * 3) / 4) 45 46 /* SMBIOS type containing Board Data File Name Extension */ 47 #define ATH12K_SMBIOS_BDF_EXT_TYPE 0xF8 48 49 /* SMBIOS type structure length (excluding strings-set) */ 50 #define ATH12K_SMBIOS_BDF_EXT_LENGTH 0x9 51 52 /* The magic used by QCA spec */ 53 #define ATH12K_SMBIOS_BDF_EXT_MAGIC "BDF_" 54 55 #define ATH12K_INVALID_HW_MAC_ID 0xFF 56 #define ATH12K_CONNECTION_LOSS_HZ (3 * HZ) 57 58 #define ATH12K_MON_TIMER_INTERVAL 10 59 #define ATH12K_RESET_TIMEOUT_HZ (20 * HZ) 60 #define ATH12K_RESET_MAX_FAIL_COUNT_FIRST 3 61 #define ATH12K_RESET_MAX_FAIL_COUNT_FINAL 5 62 #define ATH12K_RESET_FAIL_TIMEOUT_HZ (20 * HZ) 63 #define ATH12K_RECONFIGURE_TIMEOUT_HZ (10 * HZ) 64 #define ATH12K_RECOVER_START_TIMEOUT_HZ (20 * HZ) 65 66 #define ATH12K_MAX_SOCS 3 67 #define ATH12K_GROUP_MAX_RADIO (ATH12K_MAX_SOCS * MAX_RADIOS) 68 #define ATH12K_INVALID_GROUP_ID 0xFF 69 #define ATH12K_INVALID_DEVICE_ID 0xFF 70 71 #define ATH12K_MAX_MLO_PEERS 256 72 #define ATH12K_MLO_PEER_ID_INVALID 0xFFFF 73 74 enum ath12k_bdf_search { 75 ATH12K_BDF_SEARCH_DEFAULT, 76 ATH12K_BDF_SEARCH_BUS_AND_BOARD, 77 }; 78 79 enum wme_ac { 80 WME_AC_BE, 81 WME_AC_BK, 82 WME_AC_VI, 83 WME_AC_VO, 84 WME_NUM_AC 85 }; 86 87 #define ATH12K_HT_MCS_MAX 7 88 #define ATH12K_VHT_MCS_MAX 9 89 #define ATH12K_HE_MCS_MAX 11 90 #define ATH12K_EHT_MCS_MAX 15 91 92 enum ath12k_crypt_mode { 93 /* Only use hardware crypto engine */ 94 ATH12K_CRYPT_MODE_HW, 95 /* Only use software crypto */ 96 ATH12K_CRYPT_MODE_SW, 97 }; 98 99 static inline enum wme_ac ath12k_tid_to_ac(u32 tid) 100 { 101 return (((tid == 0) || (tid == 3)) ? WME_AC_BE : 102 ((tid == 1) || (tid == 2)) ? WME_AC_BK : 103 ((tid == 4) || (tid == 5)) ? WME_AC_VI : 104 WME_AC_VO); 105 } 106 107 static inline u64 ath12k_le32hilo_to_u64(__le32 hi, __le32 lo) 108 { 109 u64 hi64 = le32_to_cpu(hi); 110 u64 lo64 = le32_to_cpu(lo); 111 112 return (hi64 << 32) | lo64; 113 } 114 115 enum ath12k_skb_flags { 116 ATH12K_SKB_HW_80211_ENCAP = BIT(0), 117 ATH12K_SKB_CIPHER_SET = BIT(1), 118 }; 119 120 struct ath12k_skb_cb { 121 dma_addr_t paddr; 122 struct ath12k *ar; 123 struct ieee80211_vif *vif; 124 dma_addr_t paddr_ext_desc; 125 u32 cipher; 126 u8 flags; 127 u8 link_id; 128 }; 129 130 struct ath12k_skb_rxcb { 131 dma_addr_t paddr; 132 bool is_first_msdu; 133 bool is_last_msdu; 134 bool is_continuation; 135 bool is_mcbc; 136 bool is_eapol; 137 struct hal_rx_desc *rx_desc; 138 u8 err_rel_src; 139 u8 err_code; 140 u8 hw_link_id; 141 u8 unmapped; 142 u8 is_frag; 143 u8 tid; 144 u16 peer_id; 145 bool is_end_of_ppdu; 146 }; 147 148 enum ath12k_hw_rev { 149 ATH12K_HW_QCN9274_HW10, 150 ATH12K_HW_QCN9274_HW20, 151 ATH12K_HW_WCN7850_HW20, 152 ATH12K_HW_IPQ5332_HW10, 153 }; 154 155 enum ath12k_firmware_mode { 156 /* the default mode, standard 802.11 functionality */ 157 ATH12K_FIRMWARE_MODE_NORMAL, 158 159 /* factory tests etc */ 160 ATH12K_FIRMWARE_MODE_FTM, 161 }; 162 163 #define ATH12K_IRQ_NUM_MAX 57 164 #define ATH12K_EXT_IRQ_NUM_MAX 16 165 #define ATH12K_MAX_TCL_RING_NUM 3 166 167 struct ath12k_ext_irq_grp { 168 struct ath12k_base *ab; 169 u32 irqs[ATH12K_EXT_IRQ_NUM_MAX]; 170 u32 num_irq; 171 u32 grp_id; 172 u64 timestamp; 173 bool napi_enabled; 174 struct napi_struct napi; 175 struct net_device *napi_ndev; 176 }; 177 178 struct ath12k_smbios_bdf { 179 struct dmi_header hdr; 180 u32 padding; 181 u8 bdf_enabled; 182 u8 bdf_ext[]; 183 } __packed; 184 185 #define HEHANDLE_CAP_PHYINFO_SIZE 3 186 #define HECAP_PHYINFO_SIZE 9 187 #define HECAP_MACINFO_SIZE 5 188 #define HECAP_TXRX_MCS_NSS_SIZE 2 189 #define HECAP_PPET16_PPET8_MAX_SIZE 25 190 191 #define HE_PPET16_PPET8_SIZE 8 192 193 /* 802.11ax PPE (PPDU packet Extension) threshold */ 194 struct he_ppe_threshold { 195 u32 numss_m1; 196 u32 ru_mask; 197 u32 ppet16_ppet8_ru3_ru0[HE_PPET16_PPET8_SIZE]; 198 }; 199 200 struct ath12k_he { 201 u8 hecap_macinfo[HECAP_MACINFO_SIZE]; 202 u32 hecap_rxmcsnssmap; 203 u32 hecap_txmcsnssmap; 204 u32 hecap_phyinfo[HEHANDLE_CAP_PHYINFO_SIZE]; 205 struct he_ppe_threshold hecap_ppet; 206 u32 heop_param; 207 }; 208 209 enum { 210 WMI_HOST_TP_SCALE_MAX = 0, 211 WMI_HOST_TP_SCALE_50 = 1, 212 WMI_HOST_TP_SCALE_25 = 2, 213 WMI_HOST_TP_SCALE_12 = 3, 214 WMI_HOST_TP_SCALE_MIN = 4, 215 WMI_HOST_TP_SCALE_SIZE = 5, 216 }; 217 218 enum ath12k_scan_state { 219 ATH12K_SCAN_IDLE, 220 ATH12K_SCAN_STARTING, 221 ATH12K_SCAN_RUNNING, 222 ATH12K_SCAN_ABORTING, 223 }; 224 225 enum ath12k_11d_state { 226 ATH12K_11D_IDLE, 227 ATH12K_11D_PREPARING, 228 ATH12K_11D_RUNNING, 229 }; 230 231 enum ath12k_hw_group_flags { 232 ATH12K_GROUP_FLAG_REGISTERED, 233 ATH12K_GROUP_FLAG_UNREGISTER, 234 }; 235 236 enum ath12k_dev_flags { 237 ATH12K_FLAG_CAC_RUNNING, 238 ATH12K_FLAG_CRASH_FLUSH, 239 ATH12K_FLAG_RAW_MODE, 240 ATH12K_FLAG_HW_CRYPTO_DISABLED, 241 ATH12K_FLAG_RECOVERY, 242 ATH12K_FLAG_UNREGISTERING, 243 ATH12K_FLAG_REGISTERED, 244 ATH12K_FLAG_QMI_FAIL, 245 ATH12K_FLAG_HTC_SUSPEND_COMPLETE, 246 ATH12K_FLAG_CE_IRQ_ENABLED, 247 ATH12K_FLAG_EXT_IRQ_ENABLED, 248 ATH12K_FLAG_QMI_FW_READY_COMPLETE, 249 ATH12K_FLAG_FTM_SEGMENTED, 250 ATH12K_FLAG_FIXED_MEM_REGION, 251 }; 252 253 struct ath12k_tx_conf { 254 bool changed; 255 u16 ac; 256 struct ieee80211_tx_queue_params tx_queue_params; 257 }; 258 259 struct ath12k_key_conf { 260 enum set_key_cmd cmd; 261 struct list_head list; 262 struct ieee80211_sta *sta; 263 struct ieee80211_key_conf *key; 264 }; 265 266 struct ath12k_vif_cache { 267 struct ath12k_tx_conf tx_conf; 268 struct ath12k_key_conf key_conf; 269 u32 bss_conf_changed; 270 }; 271 272 struct ath12k_rekey_data { 273 u8 kck[NL80211_KCK_LEN]; 274 u8 kek[NL80211_KCK_LEN]; 275 u64 replay_ctr; 276 bool enable_offload; 277 }; 278 279 struct ath12k_link_vif { 280 u32 vdev_id; 281 u32 beacon_interval; 282 u32 dtim_period; 283 u16 ast_hash; 284 u16 ast_idx; 285 u16 tcl_metadata; 286 u8 hal_addr_search_flags; 287 u8 search_type; 288 289 struct ath12k *ar; 290 291 int bank_id; 292 u8 vdev_id_check_en; 293 294 struct wmi_wmm_params_all_arg wmm_params; 295 struct list_head list; 296 297 bool is_created; 298 bool is_started; 299 bool is_up; 300 u8 bssid[ETH_ALEN]; 301 struct cfg80211_bitrate_mask bitrate_mask; 302 struct delayed_work connection_loss_work; 303 int num_legacy_stations; 304 int rtscts_prot_mode; 305 int txpower; 306 bool rsnie_present; 307 bool wpaie_present; 308 u8 vdev_stats_id; 309 u32 punct_bitmap; 310 u8 link_id; 311 struct ath12k_vif *ahvif; 312 struct ath12k_rekey_data rekey_data; 313 struct ath12k_link_stats link_stats; 314 spinlock_t link_stats_lock; /* Protects updates to link_stats */ 315 316 u8 current_cntdown_counter; 317 318 /* only used in station mode */ 319 bool is_sta_assoc_link; 320 }; 321 322 struct ath12k_vif { 323 enum wmi_vdev_type vdev_type; 324 enum wmi_vdev_subtype vdev_subtype; 325 struct ieee80211_vif *vif; 326 struct ath12k_hw *ah; 327 328 union { 329 struct { 330 u32 uapsd; 331 } sta; 332 struct { 333 /* 127 stations; wmi limit */ 334 u8 tim_bitmap[16]; 335 u8 tim_len; 336 u32 ssid_len; 337 u8 ssid[IEEE80211_MAX_SSID_LEN]; 338 bool hidden_ssid; 339 /* P2P_IE with NoA attribute for P2P_GO case */ 340 u32 noa_len; 341 u8 *noa_data; 342 } ap; 343 } u; 344 345 u32 aid; 346 u32 key_cipher; 347 u8 tx_encap_type; 348 bool ps; 349 atomic_t mcbc_gsn; 350 351 struct ath12k_link_vif deflink; 352 struct ath12k_link_vif __rcu *link[ATH12K_NUM_MAX_LINKS]; 353 struct ath12k_vif_cache *cache[IEEE80211_MLD_MAX_NUM_LINKS]; 354 /* indicates bitmap of link vif created in FW */ 355 u16 links_map; 356 u8 last_scan_link; 357 358 /* Must be last - ends in a flexible-array member. 359 * 360 * FIXME: Driver should not copy struct ieee80211_chanctx_conf, 361 * especially because it has a flexible array. Find a better way. 362 */ 363 struct ieee80211_chanctx_conf chanctx; 364 }; 365 366 struct ath12k_vif_iter { 367 u32 vdev_id; 368 struct ath12k *ar; 369 struct ath12k_link_vif *arvif; 370 }; 371 372 #define HAL_AST_IDX_INVALID 0xFFFF 373 #define HAL_RX_MAX_MCS 12 374 #define HAL_RX_MAX_MCS_HT 31 375 #define HAL_RX_MAX_MCS_VHT 9 376 #define HAL_RX_MAX_MCS_HE 11 377 #define HAL_RX_MAX_MCS_BE 15 378 #define HAL_RX_MAX_NSS 8 379 #define HAL_RX_MAX_NUM_LEGACY_RATES 12 380 381 #define ATH12K_SCAN_TIMEOUT_HZ (20 * HZ) 382 383 struct ath12k_rx_peer_rate_stats { 384 u64 ht_mcs_count[HAL_RX_MAX_MCS_HT + 1]; 385 u64 vht_mcs_count[HAL_RX_MAX_MCS_VHT + 1]; 386 u64 he_mcs_count[HAL_RX_MAX_MCS_HE + 1]; 387 u64 be_mcs_count[HAL_RX_MAX_MCS_BE + 1]; 388 u64 nss_count[HAL_RX_MAX_NSS]; 389 u64 bw_count[HAL_RX_BW_MAX]; 390 u64 gi_count[HAL_RX_GI_MAX]; 391 u64 legacy_count[HAL_RX_MAX_NUM_LEGACY_RATES]; 392 u64 rx_rate[HAL_RX_BW_MAX][HAL_RX_GI_MAX][HAL_RX_MAX_NSS][HAL_RX_MAX_MCS_HT + 1]; 393 }; 394 395 struct ath12k_rx_peer_stats { 396 u64 num_msdu; 397 u64 num_mpdu_fcs_ok; 398 u64 num_mpdu_fcs_err; 399 u64 tcp_msdu_count; 400 u64 udp_msdu_count; 401 u64 other_msdu_count; 402 u64 ampdu_msdu_count; 403 u64 non_ampdu_msdu_count; 404 u64 stbc_count; 405 u64 beamformed_count; 406 u64 coding_count[HAL_RX_SU_MU_CODING_MAX]; 407 u64 tid_count[IEEE80211_NUM_TIDS + 1]; 408 u64 pream_cnt[HAL_RX_PREAMBLE_MAX]; 409 u64 reception_type[HAL_RX_RECEPTION_TYPE_MAX]; 410 u64 rx_duration; 411 u64 dcm_count; 412 u64 ru_alloc_cnt[HAL_RX_RU_ALLOC_TYPE_MAX]; 413 struct ath12k_rx_peer_rate_stats pkt_stats; 414 struct ath12k_rx_peer_rate_stats byte_stats; 415 }; 416 417 #define ATH12K_HE_MCS_NUM 12 418 #define ATH12K_VHT_MCS_NUM 10 419 #define ATH12K_BW_NUM 5 420 #define ATH12K_NSS_NUM 4 421 #define ATH12K_LEGACY_NUM 12 422 #define ATH12K_GI_NUM 4 423 #define ATH12K_HT_MCS_NUM 32 424 425 enum ath12k_pkt_rx_err { 426 ATH12K_PKT_RX_ERR_FCS, 427 ATH12K_PKT_RX_ERR_TKIP, 428 ATH12K_PKT_RX_ERR_CRYPT, 429 ATH12K_PKT_RX_ERR_PEER_IDX_INVAL, 430 ATH12K_PKT_RX_ERR_MAX, 431 }; 432 433 enum ath12k_ampdu_subfrm_num { 434 ATH12K_AMPDU_SUBFRM_NUM_10, 435 ATH12K_AMPDU_SUBFRM_NUM_20, 436 ATH12K_AMPDU_SUBFRM_NUM_30, 437 ATH12K_AMPDU_SUBFRM_NUM_40, 438 ATH12K_AMPDU_SUBFRM_NUM_50, 439 ATH12K_AMPDU_SUBFRM_NUM_60, 440 ATH12K_AMPDU_SUBFRM_NUM_MORE, 441 ATH12K_AMPDU_SUBFRM_NUM_MAX, 442 }; 443 444 enum ath12k_amsdu_subfrm_num { 445 ATH12K_AMSDU_SUBFRM_NUM_1, 446 ATH12K_AMSDU_SUBFRM_NUM_2, 447 ATH12K_AMSDU_SUBFRM_NUM_3, 448 ATH12K_AMSDU_SUBFRM_NUM_4, 449 ATH12K_AMSDU_SUBFRM_NUM_MORE, 450 ATH12K_AMSDU_SUBFRM_NUM_MAX, 451 }; 452 453 enum ath12k_counter_type { 454 ATH12K_COUNTER_TYPE_BYTES, 455 ATH12K_COUNTER_TYPE_PKTS, 456 ATH12K_COUNTER_TYPE_MAX, 457 }; 458 459 enum ath12k_stats_type { 460 ATH12K_STATS_TYPE_SUCC, 461 ATH12K_STATS_TYPE_FAIL, 462 ATH12K_STATS_TYPE_RETRY, 463 ATH12K_STATS_TYPE_AMPDU, 464 ATH12K_STATS_TYPE_MAX, 465 }; 466 467 struct ath12k_htt_data_stats { 468 u64 legacy[ATH12K_COUNTER_TYPE_MAX][ATH12K_LEGACY_NUM]; 469 u64 ht[ATH12K_COUNTER_TYPE_MAX][ATH12K_HT_MCS_NUM]; 470 u64 vht[ATH12K_COUNTER_TYPE_MAX][ATH12K_VHT_MCS_NUM]; 471 u64 he[ATH12K_COUNTER_TYPE_MAX][ATH12K_HE_MCS_NUM]; 472 u64 bw[ATH12K_COUNTER_TYPE_MAX][ATH12K_BW_NUM]; 473 u64 nss[ATH12K_COUNTER_TYPE_MAX][ATH12K_NSS_NUM]; 474 u64 gi[ATH12K_COUNTER_TYPE_MAX][ATH12K_GI_NUM]; 475 u64 transmit_type[ATH12K_COUNTER_TYPE_MAX][HAL_RX_RECEPTION_TYPE_MAX]; 476 u64 ru_loc[ATH12K_COUNTER_TYPE_MAX][HAL_RX_RU_ALLOC_TYPE_MAX]; 477 }; 478 479 struct ath12k_htt_tx_stats { 480 struct ath12k_htt_data_stats stats[ATH12K_STATS_TYPE_MAX]; 481 u64 tx_duration; 482 u64 ba_fails; 483 u64 ack_fails; 484 u16 ru_start; 485 u16 ru_tones; 486 u32 mu_group[MAX_MU_GROUP_ID]; 487 }; 488 489 struct ath12k_per_ppdu_tx_stats { 490 u16 succ_pkts; 491 u16 failed_pkts; 492 u16 retry_pkts; 493 u32 succ_bytes; 494 u32 failed_bytes; 495 u32 retry_bytes; 496 }; 497 498 struct ath12k_wbm_tx_stats { 499 u64 wbm_tx_comp_stats[HAL_WBM_REL_HTT_TX_COMP_STATUS_MAX]; 500 }; 501 502 DECLARE_EWMA(avg_rssi, 10, 8) 503 504 struct ath12k_link_sta { 505 struct ath12k_link_vif *arvif; 506 struct ath12k_sta *ahsta; 507 508 /* link address similar to ieee80211_link_sta */ 509 u8 addr[ETH_ALEN]; 510 511 /* the following are protected by ar->data_lock */ 512 u32 changed; /* IEEE80211_RC_* */ 513 u32 bw; 514 u32 nss; 515 u32 smps; 516 517 struct wiphy_work update_wk; 518 struct rate_info txrate; 519 struct rate_info last_txrate; 520 u64 rx_duration; 521 u64 tx_duration; 522 u8 rssi_comb; 523 struct ewma_avg_rssi avg_rssi; 524 u8 link_id; 525 struct ath12k_rx_peer_stats *rx_stats; 526 struct ath12k_wbm_tx_stats *wbm_tx_stats; 527 u32 bw_prev; 528 u32 peer_nss; 529 s8 rssi_beacon; 530 531 /* For now the assoc link will be considered primary */ 532 bool is_assoc_link; 533 534 /* for firmware use only */ 535 u8 link_idx; 536 }; 537 538 struct ath12k_reoq_buf { 539 void *vaddr; 540 dma_addr_t paddr_aligned; 541 u32 size; 542 }; 543 544 struct ath12k_sta { 545 struct ath12k_vif *ahvif; 546 enum hal_pn_type pn_type; 547 struct ath12k_link_sta deflink; 548 struct ath12k_link_sta __rcu *link[IEEE80211_MLD_MAX_NUM_LINKS]; 549 /* indicates bitmap of link sta created in FW */ 550 u16 links_map; 551 u8 assoc_link_id; 552 u16 ml_peer_id; 553 u8 num_peer; 554 555 enum ieee80211_sta_state state; 556 557 struct ath12k_reoq_buf reoq_bufs[IEEE80211_NUM_TIDS + 1]; 558 }; 559 560 #define ATH12K_HALF_20MHZ_BW 10 561 #define ATH12K_2GHZ_MIN_CENTER 2412 562 #define ATH12K_2GHZ_MAX_CENTER 2484 563 #define ATH12K_5GHZ_MIN_CENTER 4900 564 #define ATH12K_5GHZ_MAX_CENTER 5920 565 #define ATH12K_6GHZ_MIN_CENTER 5935 566 #define ATH12K_6GHZ_MAX_CENTER 7115 567 #define ATH12K_MIN_2GHZ_FREQ (ATH12K_2GHZ_MIN_CENTER - ATH12K_HALF_20MHZ_BW - 1) 568 #define ATH12K_MAX_2GHZ_FREQ (ATH12K_2GHZ_MAX_CENTER + ATH12K_HALF_20MHZ_BW + 1) 569 #define ATH12K_MIN_5GHZ_FREQ (ATH12K_5GHZ_MIN_CENTER - ATH12K_HALF_20MHZ_BW) 570 #define ATH12K_MAX_5GHZ_FREQ (ATH12K_5GHZ_MAX_CENTER + ATH12K_HALF_20MHZ_BW) 571 #define ATH12K_MIN_6GHZ_FREQ (ATH12K_6GHZ_MIN_CENTER - ATH12K_HALF_20MHZ_BW) 572 #define ATH12K_MAX_6GHZ_FREQ (ATH12K_6GHZ_MAX_CENTER + ATH12K_HALF_20MHZ_BW) 573 #define ATH12K_NUM_CHANS 101 574 #define ATH12K_MAX_5GHZ_CHAN 173 575 576 enum ath12k_hw_state { 577 ATH12K_HW_STATE_OFF, 578 ATH12K_HW_STATE_ON, 579 ATH12K_HW_STATE_RESTARTING, 580 ATH12K_HW_STATE_RESTARTED, 581 ATH12K_HW_STATE_WEDGED, 582 ATH12K_HW_STATE_TM, 583 /* Add other states as required */ 584 }; 585 586 /* Antenna noise floor */ 587 #define ATH12K_DEFAULT_NOISE_FLOOR -95 588 589 struct ath12k_ftm_event_obj { 590 u32 data_pos; 591 u32 expected_seq; 592 u8 *eventdata; 593 }; 594 595 struct ath12k_fw_stats { 596 u32 pdev_id; 597 u32 stats_id; 598 struct list_head pdevs; 599 struct list_head vdevs; 600 struct list_head bcn; 601 bool fw_stats_done; 602 }; 603 604 struct ath12k_dbg_htt_stats { 605 enum ath12k_dbg_htt_ext_stats_type type; 606 u32 cfg_param[4]; 607 u8 reset; 608 struct debug_htt_stats_req *stats_req; 609 }; 610 611 struct ath12k_debug { 612 struct dentry *debugfs_pdev; 613 struct dentry *debugfs_pdev_symlink; 614 struct ath12k_dbg_htt_stats htt_stats; 615 enum wmi_halphy_ctrl_path_stats_id tpc_stats_type; 616 bool tpc_request; 617 struct completion tpc_complete; 618 struct wmi_tpc_stats_arg *tpc_stats; 619 u32 rx_filter; 620 bool extd_rx_stats; 621 }; 622 623 struct ath12k_per_peer_tx_stats { 624 u32 succ_bytes; 625 u32 retry_bytes; 626 u32 failed_bytes; 627 u32 duration; 628 u16 succ_pkts; 629 u16 retry_pkts; 630 u16 failed_pkts; 631 u16 ru_start; 632 u16 ru_tones; 633 u8 ba_fails; 634 u8 ppdu_type; 635 u32 mu_grpid; 636 u32 mu_pos; 637 bool is_ampdu; 638 }; 639 640 #define ATH12K_FLUSH_TIMEOUT (5 * HZ) 641 #define ATH12K_VDEV_DELETE_TIMEOUT_HZ (5 * HZ) 642 643 struct ath12k { 644 struct ath12k_base *ab; 645 struct ath12k_pdev *pdev; 646 struct ath12k_hw *ah; 647 struct ath12k_wmi_pdev *wmi; 648 struct ath12k_pdev_dp dp; 649 u8 mac_addr[ETH_ALEN]; 650 u32 ht_cap_info; 651 u32 vht_cap_info; 652 struct ath12k_he ar_he; 653 bool supports_6ghz; 654 struct { 655 struct completion started; 656 struct completion completed; 657 struct completion on_channel; 658 struct delayed_work timeout; 659 enum ath12k_scan_state state; 660 bool is_roc; 661 int roc_freq; 662 bool roc_notify; 663 struct wiphy_work vdev_clean_wk; 664 struct ath12k_link_vif *arvif; 665 } scan; 666 667 struct { 668 struct ieee80211_supported_band sbands[NUM_NL80211_BANDS]; 669 struct ieee80211_sband_iftype_data 670 iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES]; 671 } mac; 672 673 unsigned long dev_flags; 674 unsigned int filter_flags; 675 u32 min_tx_power; 676 u32 max_tx_power; 677 u32 txpower_limit_2g; 678 u32 txpower_limit_5g; 679 u32 txpower_scale; 680 u32 power_scale; 681 u32 chan_tx_pwr; 682 u32 num_stations; 683 u32 max_num_stations; 684 685 /* protects the radio specific data like debug stats, ppdu_stats_info stats, 686 * vdev_stop_status info, scan data, ath12k_sta info, ath12k_link_vif info, 687 * channel context data, survey info, test mode data. 688 */ 689 spinlock_t data_lock; 690 691 struct list_head arvifs; 692 /* should never be NULL; needed for regular htt rx */ 693 struct ieee80211_channel *rx_channel; 694 695 /* valid during scan; needed for mgmt rx during scan */ 696 struct ieee80211_channel *scan_channel; 697 698 u8 cfg_tx_chainmask; 699 u8 cfg_rx_chainmask; 700 u8 num_rx_chains; 701 u8 num_tx_chains; 702 /* pdev_idx starts from 0 whereas pdev->pdev_id starts with 1 */ 703 u8 pdev_idx; 704 u8 lmac_id; 705 u8 hw_link_id; 706 707 struct completion peer_assoc_done; 708 struct completion peer_delete_done; 709 710 int install_key_status; 711 struct completion install_key_done; 712 713 int last_wmi_vdev_start_status; 714 struct completion vdev_setup_done; 715 struct completion vdev_delete_done; 716 717 int num_peers; 718 int max_num_peers; 719 u32 num_started_vdevs; 720 u32 num_created_vdevs; 721 unsigned long long allocated_vdev_map; 722 723 struct idr txmgmt_idr; 724 /* protects txmgmt_idr data */ 725 spinlock_t txmgmt_idr_lock; 726 atomic_t num_pending_mgmt_tx; 727 wait_queue_head_t txmgmt_empty_waitq; 728 729 /* cycle count is reported twice for each visited channel during scan. 730 * access protected by data_lock 731 */ 732 u32 survey_last_rx_clear_count; 733 u32 survey_last_cycle_count; 734 735 /* Channel info events are expected to come in pairs without and with 736 * COMPLETE flag set respectively for each channel visit during scan. 737 * 738 * However there are deviations from this rule. This flag is used to 739 * avoid reporting garbage data. 740 */ 741 bool ch_info_can_report_survey; 742 struct survey_info survey[ATH12K_NUM_CHANS]; 743 struct completion bss_survey_done; 744 745 struct work_struct regd_update_work; 746 747 struct wiphy_work wmi_mgmt_tx_work; 748 struct sk_buff_head wmi_mgmt_tx_queue; 749 750 struct ath12k_wow wow; 751 struct completion target_suspend; 752 bool target_suspend_ack; 753 struct ath12k_per_peer_tx_stats peer_tx_stats; 754 struct list_head ppdu_stats_info; 755 u32 ppdu_stat_list_depth; 756 757 struct ath12k_per_peer_tx_stats cached_stats; 758 u32 last_ppdu_id; 759 u32 cached_ppdu_id; 760 #ifdef CONFIG_ATH12K_DEBUGFS 761 struct ath12k_debug debug; 762 #endif 763 764 bool dfs_block_radar_events; 765 bool monitor_vdev_created; 766 bool monitor_started; 767 int monitor_vdev_id; 768 769 struct wiphy_radio_freq_range freq_range; 770 771 bool nlo_enabled; 772 773 /* Protected by wiphy::mtx lock. */ 774 u32 vdev_id_11d_scan; 775 struct completion completed_11d_scan; 776 enum ath12k_11d_state state_11d; 777 u8 alpha2[REG_ALPHA2_LEN]; 778 bool regdom_set_by_user; 779 780 struct completion fw_stats_complete; 781 782 struct completion mlo_setup_done; 783 u32 mlo_setup_status; 784 u8 ftm_msgref; 785 struct ath12k_fw_stats fw_stats; 786 unsigned long last_tx_power_update; 787 }; 788 789 struct ath12k_hw { 790 struct ieee80211_hw *hw; 791 struct device *dev; 792 793 /* Protect the write operation of the hardware state ath12k_hw::state 794 * between hardware start<=>reconfigure<=>stop transitions. 795 */ 796 struct mutex hw_mutex; 797 enum ath12k_hw_state state; 798 bool regd_updated; 799 bool use_6ghz_regd; 800 801 u8 num_radio; 802 803 DECLARE_BITMAP(free_ml_peer_id_map, ATH12K_MAX_MLO_PEERS); 804 805 /* protected by wiphy_lock() */ 806 struct list_head ml_peers; 807 808 /* Keep last */ 809 struct ath12k radio[] __aligned(sizeof(void *)); 810 }; 811 812 struct ath12k_band_cap { 813 u32 phy_id; 814 u32 max_bw_supported; 815 u32 ht_cap_info; 816 u32 he_cap_info[2]; 817 u32 he_mcs; 818 u32 he_cap_phy_info[PSOC_HOST_MAX_PHY_SIZE]; 819 struct ath12k_wmi_ppe_threshold_arg he_ppet; 820 u16 he_6ghz_capa; 821 u32 eht_cap_mac_info[WMI_MAX_EHTCAP_MAC_SIZE]; 822 u32 eht_cap_phy_info[WMI_MAX_EHTCAP_PHY_SIZE]; 823 u32 eht_mcs_20_only; 824 u32 eht_mcs_80; 825 u32 eht_mcs_160; 826 u32 eht_mcs_320; 827 struct ath12k_wmi_ppe_threshold_arg eht_ppet; 828 u32 eht_cap_info_internal; 829 }; 830 831 struct ath12k_pdev_cap { 832 u32 supported_bands; 833 u32 ampdu_density; 834 u32 vht_cap; 835 u32 vht_mcs; 836 u32 he_mcs; 837 u32 tx_chain_mask; 838 u32 rx_chain_mask; 839 u32 tx_chain_mask_shift; 840 u32 rx_chain_mask_shift; 841 struct ath12k_band_cap band[NUM_NL80211_BANDS]; 842 u32 eml_cap; 843 u32 mld_cap; 844 }; 845 846 struct mlo_timestamp { 847 u32 info; 848 u32 sync_timestamp_lo_us; 849 u32 sync_timestamp_hi_us; 850 u32 mlo_offset_lo; 851 u32 mlo_offset_hi; 852 u32 mlo_offset_clks; 853 u32 mlo_comp_clks; 854 u32 mlo_comp_timer; 855 }; 856 857 struct ath12k_pdev { 858 struct ath12k *ar; 859 u32 pdev_id; 860 u32 hw_link_id; 861 struct ath12k_pdev_cap cap; 862 u8 mac_addr[ETH_ALEN]; 863 struct mlo_timestamp timestamp; 864 }; 865 866 struct ath12k_fw_pdev { 867 u32 pdev_id; 868 u32 phy_id; 869 u32 supported_bands; 870 }; 871 872 struct ath12k_board_data { 873 const struct firmware *fw; 874 const void *data; 875 size_t len; 876 }; 877 878 struct ath12k_soc_dp_tx_err_stats { 879 /* TCL Ring Descriptor unavailable */ 880 u32 desc_na[DP_TCL_NUM_RING_MAX]; 881 /* Other failures during dp_tx due to mem allocation failure 882 * idr unavailable etc. 883 */ 884 atomic_t misc_fail; 885 }; 886 887 struct ath12k_soc_dp_stats { 888 u32 err_ring_pkts; 889 u32 invalid_rbm; 890 u32 rxdma_error[HAL_REO_ENTR_RING_RXDMA_ECODE_MAX]; 891 u32 reo_error[HAL_REO_DEST_RING_ERROR_CODE_MAX]; 892 u32 hal_reo_error[DP_REO_DST_RING_MAX]; 893 struct ath12k_soc_dp_tx_err_stats tx_err; 894 }; 895 896 struct ath12k_reg_freq { 897 u32 start_freq; 898 u32 end_freq; 899 }; 900 901 struct ath12k_mlo_memory { 902 struct target_mem_chunk chunk[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 903 int mlo_mem_size; 904 bool init_done; 905 }; 906 907 struct ath12k_hw_link { 908 u8 device_id; 909 u8 pdev_idx; 910 }; 911 912 /* Holds info on the group of devices that are registered as a single 913 * wiphy, protected with struct ath12k_hw_group::mutex. 914 */ 915 struct ath12k_hw_group { 916 struct list_head list; 917 u8 id; 918 u8 num_devices; 919 u8 num_probed; 920 u8 num_started; 921 unsigned long flags; 922 struct ath12k_base *ab[ATH12K_MAX_SOCS]; 923 924 /* protects access to this struct */ 925 struct mutex mutex; 926 927 /* Holds information of wiphy (hw) registration. 928 * 929 * In Multi/Single Link Operation case, all pdevs are registered as 930 * a single wiphy. In other (legacy/Non-MLO) cases, each pdev is 931 * registered as separate wiphys. 932 */ 933 struct ath12k_hw *ah[ATH12K_GROUP_MAX_RADIO]; 934 u8 num_hw; 935 bool mlo_capable; 936 struct device_node *wsi_node[ATH12K_MAX_SOCS]; 937 struct ath12k_mlo_memory mlo_mem; 938 struct ath12k_hw_link hw_links[ATH12K_GROUP_MAX_RADIO]; 939 bool hw_link_id_init_done; 940 }; 941 942 /* Holds WSI info specific to each device, excluding WSI group info */ 943 struct ath12k_wsi_info { 944 u32 index; 945 u32 hw_link_id_base; 946 }; 947 948 /* Master structure to hold the hw data which may be used in core module */ 949 struct ath12k_base { 950 enum ath12k_hw_rev hw_rev; 951 struct platform_device *pdev; 952 struct device *dev; 953 struct ath12k_qmi qmi; 954 struct ath12k_wmi_base wmi_ab; 955 struct completion fw_ready; 956 u8 device_id; 957 int num_radios; 958 /* HW channel counters frequency value in hertz common to all MACs */ 959 u32 cc_freq_hz; 960 961 struct ath12k_dump_file_data *dump_data; 962 size_t ath12k_coredump_len; 963 struct work_struct dump_work; 964 965 struct ath12k_htc htc; 966 967 struct ath12k_dp dp; 968 969 void __iomem *mem; 970 unsigned long mem_len; 971 972 void __iomem *mem_ce; 973 u32 ce_remap_base_addr; 974 bool ce_remap; 975 976 struct { 977 enum ath12k_bus bus; 978 const struct ath12k_hif_ops *ops; 979 } hif; 980 981 struct { 982 struct completion wakeup_completed; 983 u32 wmi_conf_rx_decap_mode; 984 } wow; 985 986 struct ath12k_ce ce; 987 struct timer_list rx_replenish_retry; 988 struct ath12k_hal hal; 989 /* To synchronize core_start/core_stop */ 990 struct mutex core_lock; 991 /* Protects data like peers */ 992 spinlock_t base_lock; 993 994 /* Single pdev device (struct ath12k_hw_params::single_pdev_only): 995 * 996 * Firmware maintains data for all bands but advertises a single 997 * phy to the host which is stored as a single element in this 998 * array. 999 * 1000 * Other devices: 1001 * 1002 * This array will contain as many elements as the number of 1003 * radios. 1004 */ 1005 struct ath12k_pdev pdevs[MAX_RADIOS]; 1006 1007 /* struct ath12k_hw_params::single_pdev_only devices use this to 1008 * store phy specific data 1009 */ 1010 struct ath12k_fw_pdev fw_pdev[MAX_RADIOS]; 1011 u8 fw_pdev_count; 1012 1013 struct ath12k_pdev __rcu *pdevs_active[MAX_RADIOS]; 1014 1015 struct ath12k_wmi_hal_reg_capabilities_ext_arg hal_reg_cap[MAX_RADIOS]; 1016 unsigned long long free_vdev_map; 1017 unsigned long long free_vdev_stats_id_map; 1018 struct list_head peers; 1019 wait_queue_head_t peer_mapping_wq; 1020 u8 mac_addr[ETH_ALEN]; 1021 bool wmi_ready; 1022 u32 wlan_init_status; 1023 int irq_num[ATH12K_IRQ_NUM_MAX]; 1024 struct ath12k_ext_irq_grp ext_irq_grp[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 1025 struct napi_struct *napi; 1026 struct ath12k_wmi_target_cap_arg target_caps; 1027 u32 ext_service_bitmap[WMI_SERVICE_EXT_BM_SIZE]; 1028 bool pdevs_macaddr_valid; 1029 1030 const struct ath12k_hw_params *hw_params; 1031 1032 const struct firmware *cal_file; 1033 1034 /* Below regd's are protected by ab->data_lock */ 1035 /* This is the regd set for every radio 1036 * by the firmware during initialization 1037 */ 1038 struct ieee80211_regdomain *default_regd[MAX_RADIOS]; 1039 /* This regd is set during dynamic country setting 1040 * This may or may not be used during the runtime 1041 */ 1042 struct ieee80211_regdomain *new_regd[MAX_RADIOS]; 1043 1044 /* Current DFS Regulatory */ 1045 enum ath12k_dfs_region dfs_region; 1046 struct ath12k_soc_dp_stats soc_stats; 1047 #ifdef CONFIG_ATH12K_DEBUGFS 1048 struct dentry *debugfs_soc; 1049 #endif 1050 1051 unsigned long dev_flags; 1052 struct completion driver_recovery; 1053 struct workqueue_struct *workqueue; 1054 struct work_struct restart_work; 1055 struct workqueue_struct *workqueue_aux; 1056 struct work_struct reset_work; 1057 atomic_t reset_count; 1058 atomic_t recovery_count; 1059 bool is_reset; 1060 struct completion reset_complete; 1061 /* continuous recovery fail count */ 1062 atomic_t fail_cont_count; 1063 unsigned long reset_fail_timeout; 1064 struct work_struct update_11d_work; 1065 u8 new_alpha2[2]; 1066 struct { 1067 /* protected by data_lock */ 1068 u32 fw_crash_counter; 1069 } stats; 1070 u32 pktlog_defs_checksum; 1071 1072 struct ath12k_dbring_cap *db_caps; 1073 u32 num_db_cap; 1074 1075 struct timer_list mon_reap_timer; 1076 1077 struct completion htc_suspend; 1078 1079 u64 fw_soc_drop_count; 1080 bool static_window_map; 1081 1082 struct work_struct rfkill_work; 1083 /* true means radio is on */ 1084 bool rfkill_radio_on; 1085 1086 struct { 1087 enum ath12k_bdf_search bdf_search; 1088 u32 vendor; 1089 u32 device; 1090 u32 subsystem_vendor; 1091 u32 subsystem_device; 1092 } id; 1093 1094 struct { 1095 u32 api_version; 1096 1097 const struct firmware *fw; 1098 const u8 *amss_data; 1099 size_t amss_len; 1100 const u8 *amss_dualmac_data; 1101 size_t amss_dualmac_len; 1102 const u8 *m3_data; 1103 size_t m3_len; 1104 1105 DECLARE_BITMAP(fw_features, ATH12K_FW_FEATURE_COUNT); 1106 bool fw_features_valid; 1107 } fw; 1108 1109 const struct hal_rx_ops *hal_rx_ops; 1110 1111 struct completion restart_completed; 1112 1113 #ifdef CONFIG_ACPI 1114 1115 struct { 1116 bool started; 1117 u32 func_bit; 1118 bool acpi_tas_enable; 1119 bool acpi_bios_sar_enable; 1120 bool acpi_disable_11be; 1121 bool acpi_disable_rfkill; 1122 bool acpi_cca_enable; 1123 bool acpi_band_edge_enable; 1124 bool acpi_enable_bdf; 1125 u32 bit_flag; 1126 char bdf_string[ATH12K_ACPI_BDF_MAX_LEN]; 1127 u8 tas_cfg[ATH12K_ACPI_DSM_TAS_CFG_SIZE]; 1128 u8 tas_sar_power_table[ATH12K_ACPI_DSM_TAS_DATA_SIZE]; 1129 u8 bios_sar_data[ATH12K_ACPI_DSM_BIOS_SAR_DATA_SIZE]; 1130 u8 geo_offset_data[ATH12K_ACPI_DSM_GEO_OFFSET_DATA_SIZE]; 1131 u8 cca_data[ATH12K_ACPI_DSM_CCA_DATA_SIZE]; 1132 u8 band_edge_power[ATH12K_ACPI_DSM_BAND_EDGE_DATA_SIZE]; 1133 } acpi; 1134 1135 #endif /* CONFIG_ACPI */ 1136 1137 struct notifier_block panic_nb; 1138 1139 struct ath12k_hw_group *ag; 1140 struct ath12k_wsi_info wsi_info; 1141 enum ath12k_firmware_mode fw_mode; 1142 struct ath12k_ftm_event_obj ftm_event_obj; 1143 bool hw_group_ref; 1144 1145 /* Denote whether MLO is possible within the device */ 1146 bool single_chip_mlo_support; 1147 1148 struct ath12k_reg_freq reg_freq_2ghz; 1149 struct ath12k_reg_freq reg_freq_5ghz; 1150 struct ath12k_reg_freq reg_freq_6ghz; 1151 1152 /* must be last */ 1153 u8 drv_priv[] __aligned(sizeof(void *)); 1154 }; 1155 1156 struct ath12k_pdev_map { 1157 struct ath12k_base *ab; 1158 u8 pdev_idx; 1159 }; 1160 1161 struct ath12k_fw_stats_vdev { 1162 struct list_head list; 1163 1164 u32 vdev_id; 1165 u32 beacon_snr; 1166 u32 data_snr; 1167 u32 num_tx_frames[WLAN_MAX_AC]; 1168 u32 num_rx_frames; 1169 u32 num_tx_frames_retries[WLAN_MAX_AC]; 1170 u32 num_tx_frames_failures[WLAN_MAX_AC]; 1171 u32 num_rts_fail; 1172 u32 num_rts_success; 1173 u32 num_rx_err; 1174 u32 num_rx_discard; 1175 u32 num_tx_not_acked; 1176 u32 tx_rate_history[MAX_TX_RATE_VALUES]; 1177 u32 beacon_rssi_history[MAX_TX_RATE_VALUES]; 1178 }; 1179 1180 struct ath12k_fw_stats_bcn { 1181 struct list_head list; 1182 1183 u32 vdev_id; 1184 u32 tx_bcn_succ_cnt; 1185 u32 tx_bcn_outage_cnt; 1186 }; 1187 1188 struct ath12k_fw_stats_pdev { 1189 struct list_head list; 1190 1191 /* PDEV stats */ 1192 s32 ch_noise_floor; 1193 u32 tx_frame_count; 1194 u32 rx_frame_count; 1195 u32 rx_clear_count; 1196 u32 cycle_count; 1197 u32 phy_err_count; 1198 u32 chan_tx_power; 1199 u32 ack_rx_bad; 1200 u32 rts_bad; 1201 u32 rts_good; 1202 u32 fcs_bad; 1203 u32 no_beacons; 1204 u32 mib_int_count; 1205 1206 /* PDEV TX stats */ 1207 s32 comp_queued; 1208 s32 comp_delivered; 1209 s32 msdu_enqued; 1210 s32 mpdu_enqued; 1211 s32 wmm_drop; 1212 s32 local_enqued; 1213 s32 local_freed; 1214 s32 hw_queued; 1215 s32 hw_reaped; 1216 s32 underrun; 1217 s32 tx_abort; 1218 s32 mpdus_requed; 1219 u32 tx_ko; 1220 u32 data_rc; 1221 u32 self_triggers; 1222 u32 sw_retry_failure; 1223 u32 illgl_rate_phy_err; 1224 u32 pdev_cont_xretry; 1225 u32 pdev_tx_timeout; 1226 u32 pdev_resets; 1227 u32 stateless_tid_alloc_failure; 1228 u32 phy_underrun; 1229 u32 txop_ovf; 1230 1231 /* PDEV RX stats */ 1232 s32 mid_ppdu_route_change; 1233 s32 status_rcvd; 1234 s32 r0_frags; 1235 s32 r1_frags; 1236 s32 r2_frags; 1237 s32 r3_frags; 1238 s32 htt_msdus; 1239 s32 htt_mpdus; 1240 s32 loc_msdus; 1241 s32 loc_mpdus; 1242 s32 oversize_amsdu; 1243 s32 phy_errs; 1244 s32 phy_err_drop; 1245 s32 mpdu_errs; 1246 }; 1247 1248 int ath12k_core_qmi_firmware_ready(struct ath12k_base *ab); 1249 int ath12k_core_pre_init(struct ath12k_base *ab); 1250 int ath12k_core_init(struct ath12k_base *ath12k); 1251 void ath12k_core_deinit(struct ath12k_base *ath12k); 1252 struct ath12k_base *ath12k_core_alloc(struct device *dev, size_t priv_size, 1253 enum ath12k_bus bus); 1254 void ath12k_core_free(struct ath12k_base *ath12k); 1255 int ath12k_core_fetch_board_data_api_1(struct ath12k_base *ab, 1256 struct ath12k_board_data *bd, 1257 char *filename); 1258 int ath12k_core_fetch_bdf(struct ath12k_base *ath12k, 1259 struct ath12k_board_data *bd); 1260 void ath12k_core_free_bdf(struct ath12k_base *ab, struct ath12k_board_data *bd); 1261 int ath12k_core_fetch_regdb(struct ath12k_base *ab, struct ath12k_board_data *bd); 1262 int ath12k_core_check_dt(struct ath12k_base *ath12k); 1263 int ath12k_core_check_smbios(struct ath12k_base *ab); 1264 void ath12k_core_halt(struct ath12k *ar); 1265 int ath12k_core_resume_early(struct ath12k_base *ab); 1266 int ath12k_core_resume(struct ath12k_base *ab); 1267 int ath12k_core_suspend(struct ath12k_base *ab); 1268 int ath12k_core_suspend_late(struct ath12k_base *ab); 1269 void ath12k_core_hw_group_unassign(struct ath12k_base *ab); 1270 u8 ath12k_get_num_partner_link(struct ath12k *ar); 1271 1272 const struct firmware *ath12k_core_firmware_request(struct ath12k_base *ab, 1273 const char *filename); 1274 u32 ath12k_core_get_max_station_per_radio(struct ath12k_base *ab); 1275 u32 ath12k_core_get_max_peers_per_radio(struct ath12k_base *ab); 1276 u32 ath12k_core_get_max_num_tids(struct ath12k_base *ab); 1277 1278 void ath12k_core_hw_group_set_mlo_capable(struct ath12k_hw_group *ag); 1279 void ath12k_fw_stats_init(struct ath12k *ar); 1280 void ath12k_fw_stats_bcn_free(struct list_head *head); 1281 void ath12k_fw_stats_free(struct ath12k_fw_stats *stats); 1282 void ath12k_fw_stats_reset(struct ath12k *ar); 1283 struct reserved_mem *ath12k_core_get_reserved_mem(struct ath12k_base *ab, 1284 int index); 1285 1286 static inline const char *ath12k_scan_state_str(enum ath12k_scan_state state) 1287 { 1288 switch (state) { 1289 case ATH12K_SCAN_IDLE: 1290 return "idle"; 1291 case ATH12K_SCAN_STARTING: 1292 return "starting"; 1293 case ATH12K_SCAN_RUNNING: 1294 return "running"; 1295 case ATH12K_SCAN_ABORTING: 1296 return "aborting"; 1297 } 1298 1299 return "unknown"; 1300 } 1301 1302 static inline struct ath12k_skb_cb *ATH12K_SKB_CB(struct sk_buff *skb) 1303 { 1304 BUILD_BUG_ON(sizeof(struct ath12k_skb_cb) > 1305 IEEE80211_TX_INFO_DRIVER_DATA_SIZE); 1306 return (struct ath12k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data; 1307 } 1308 1309 static inline struct ath12k_skb_rxcb *ATH12K_SKB_RXCB(struct sk_buff *skb) 1310 { 1311 BUILD_BUG_ON(sizeof(struct ath12k_skb_rxcb) > sizeof(skb->cb)); 1312 return (struct ath12k_skb_rxcb *)skb->cb; 1313 } 1314 1315 static inline struct ath12k_vif *ath12k_vif_to_ahvif(struct ieee80211_vif *vif) 1316 { 1317 return (struct ath12k_vif *)vif->drv_priv; 1318 } 1319 1320 static inline struct ath12k_sta *ath12k_sta_to_ahsta(struct ieee80211_sta *sta) 1321 { 1322 return (struct ath12k_sta *)sta->drv_priv; 1323 } 1324 1325 static inline struct ieee80211_sta *ath12k_ahsta_to_sta(struct ath12k_sta *ahsta) 1326 { 1327 return container_of((void *)ahsta, struct ieee80211_sta, drv_priv); 1328 } 1329 1330 static inline struct ieee80211_vif *ath12k_ahvif_to_vif(struct ath12k_vif *ahvif) 1331 { 1332 return container_of((void *)ahvif, struct ieee80211_vif, drv_priv); 1333 } 1334 1335 static inline struct ath12k *ath12k_ab_to_ar(struct ath12k_base *ab, 1336 int mac_id) 1337 { 1338 return ab->pdevs[ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id)].ar; 1339 } 1340 1341 static inline void ath12k_core_create_firmware_path(struct ath12k_base *ab, 1342 const char *filename, 1343 void *buf, size_t buf_len) 1344 { 1345 snprintf(buf, buf_len, "%s/%s/%s", ATH12K_FW_DIR, 1346 ab->hw_params->fw.dir, filename); 1347 } 1348 1349 static inline const char *ath12k_bus_str(enum ath12k_bus bus) 1350 { 1351 switch (bus) { 1352 case ATH12K_BUS_PCI: 1353 return "pci"; 1354 case ATH12K_BUS_AHB: 1355 return "ahb"; 1356 } 1357 1358 return "unknown"; 1359 } 1360 1361 static inline struct ath12k_hw *ath12k_hw_to_ah(struct ieee80211_hw *hw) 1362 { 1363 return hw->priv; 1364 } 1365 1366 static inline struct ath12k *ath12k_ah_to_ar(struct ath12k_hw *ah, u8 hw_link_id) 1367 { 1368 if (WARN(hw_link_id >= ah->num_radio, 1369 "bad hw link id %d, so switch to default link\n", hw_link_id)) 1370 hw_link_id = 0; 1371 1372 return &ah->radio[hw_link_id]; 1373 } 1374 1375 static inline struct ath12k_hw *ath12k_ar_to_ah(struct ath12k *ar) 1376 { 1377 return ar->ah; 1378 } 1379 1380 static inline struct ieee80211_hw *ath12k_ar_to_hw(struct ath12k *ar) 1381 { 1382 return ar->ah->hw; 1383 } 1384 1385 #define for_each_ar(ah, ar, index) \ 1386 for ((index) = 0; ((index) < (ah)->num_radio && \ 1387 ((ar) = &(ah)->radio[(index)])); (index)++) 1388 1389 static inline struct ath12k_hw *ath12k_ag_to_ah(struct ath12k_hw_group *ag, int idx) 1390 { 1391 return ag->ah[idx]; 1392 } 1393 1394 static inline void ath12k_ag_set_ah(struct ath12k_hw_group *ag, int idx, 1395 struct ath12k_hw *ah) 1396 { 1397 ag->ah[idx] = ah; 1398 } 1399 1400 static inline struct ath12k_hw_group *ath12k_ab_to_ag(struct ath12k_base *ab) 1401 { 1402 return ab->ag; 1403 } 1404 1405 static inline struct ath12k_base *ath12k_ag_to_ab(struct ath12k_hw_group *ag, 1406 u8 device_id) 1407 { 1408 return ag->ab[device_id]; 1409 } 1410 1411 #endif /* _CORE_H_ */ 1412