1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef ATH12K_CORE_H 8 #define ATH12K_CORE_H 9 10 #include <linux/types.h> 11 #include <linux/interrupt.h> 12 #include <linux/irq.h> 13 #include <linux/bitfield.h> 14 #include <linux/dmi.h> 15 #include <linux/ctype.h> 16 #include <linux/firmware.h> 17 #include "qmi.h" 18 #include "htc.h" 19 #include "wmi.h" 20 #include "hal.h" 21 #include "dp.h" 22 #include "ce.h" 23 #include "mac.h" 24 #include "hw.h" 25 #include "hal_rx.h" 26 #include "reg.h" 27 #include "dbring.h" 28 #include "fw.h" 29 #include "acpi.h" 30 31 #define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK) 32 33 #define ATH12K_TX_MGMT_NUM_PENDING_MAX 512 34 35 #define ATH12K_TX_MGMT_TARGET_MAX_SUPPORT_WMI 64 36 37 /* Pending management packets threshold for dropping probe responses */ 38 #define ATH12K_PRB_RSP_DROP_THRESHOLD ((ATH12K_TX_MGMT_TARGET_MAX_SUPPORT_WMI * 3) / 4) 39 40 /* SMBIOS type containing Board Data File Name Extension */ 41 #define ATH12K_SMBIOS_BDF_EXT_TYPE 0xF8 42 43 /* SMBIOS type structure length (excluding strings-set) */ 44 #define ATH12K_SMBIOS_BDF_EXT_LENGTH 0x9 45 46 /* The magic used by QCA spec */ 47 #define ATH12K_SMBIOS_BDF_EXT_MAGIC "BDF_" 48 49 #define ATH12K_INVALID_HW_MAC_ID 0xFF 50 #define ATH12K_CONNECTION_LOSS_HZ (3 * HZ) 51 #define ATH12K_RX_RATE_TABLE_NUM 320 52 #define ATH12K_RX_RATE_TABLE_11AX_NUM 576 53 54 #define ATH12K_MON_TIMER_INTERVAL 10 55 #define ATH12K_RESET_TIMEOUT_HZ (20 * HZ) 56 #define ATH12K_RESET_MAX_FAIL_COUNT_FIRST 3 57 #define ATH12K_RESET_MAX_FAIL_COUNT_FINAL 5 58 #define ATH12K_RESET_FAIL_TIMEOUT_HZ (20 * HZ) 59 #define ATH12K_RECONFIGURE_TIMEOUT_HZ (10 * HZ) 60 #define ATH12K_RECOVER_START_TIMEOUT_HZ (20 * HZ) 61 62 enum ath12k_bdf_search { 63 ATH12K_BDF_SEARCH_DEFAULT, 64 ATH12K_BDF_SEARCH_BUS_AND_BOARD, 65 }; 66 67 enum wme_ac { 68 WME_AC_BE, 69 WME_AC_BK, 70 WME_AC_VI, 71 WME_AC_VO, 72 WME_NUM_AC 73 }; 74 75 #define ATH12K_HT_MCS_MAX 7 76 #define ATH12K_VHT_MCS_MAX 9 77 #define ATH12K_HE_MCS_MAX 11 78 79 enum ath12k_crypt_mode { 80 /* Only use hardware crypto engine */ 81 ATH12K_CRYPT_MODE_HW, 82 /* Only use software crypto */ 83 ATH12K_CRYPT_MODE_SW, 84 }; 85 86 static inline enum wme_ac ath12k_tid_to_ac(u32 tid) 87 { 88 return (((tid == 0) || (tid == 3)) ? WME_AC_BE : 89 ((tid == 1) || (tid == 2)) ? WME_AC_BK : 90 ((tid == 4) || (tid == 5)) ? WME_AC_VI : 91 WME_AC_VO); 92 } 93 94 enum ath12k_skb_flags { 95 ATH12K_SKB_HW_80211_ENCAP = BIT(0), 96 ATH12K_SKB_CIPHER_SET = BIT(1), 97 }; 98 99 struct ath12k_skb_cb { 100 dma_addr_t paddr; 101 struct ath12k *ar; 102 struct ieee80211_vif *vif; 103 dma_addr_t paddr_ext_desc; 104 u32 cipher; 105 u8 flags; 106 }; 107 108 struct ath12k_skb_rxcb { 109 dma_addr_t paddr; 110 bool is_first_msdu; 111 bool is_last_msdu; 112 bool is_continuation; 113 bool is_mcbc; 114 bool is_eapol; 115 struct hal_rx_desc *rx_desc; 116 u8 err_rel_src; 117 u8 err_code; 118 u8 mac_id; 119 u8 unmapped; 120 u8 is_frag; 121 u8 tid; 122 u16 peer_id; 123 }; 124 125 enum ath12k_hw_rev { 126 ATH12K_HW_QCN9274_HW10, 127 ATH12K_HW_QCN9274_HW20, 128 ATH12K_HW_WCN7850_HW20 129 }; 130 131 enum ath12k_firmware_mode { 132 /* the default mode, standard 802.11 functionality */ 133 ATH12K_FIRMWARE_MODE_NORMAL, 134 135 /* factory tests etc */ 136 ATH12K_FIRMWARE_MODE_FTM, 137 }; 138 139 #define ATH12K_IRQ_NUM_MAX 57 140 #define ATH12K_EXT_IRQ_NUM_MAX 16 141 142 struct ath12k_ext_irq_grp { 143 struct ath12k_base *ab; 144 u32 irqs[ATH12K_EXT_IRQ_NUM_MAX]; 145 u32 num_irq; 146 u32 grp_id; 147 u64 timestamp; 148 struct napi_struct napi; 149 struct net_device napi_ndev; 150 }; 151 152 struct ath12k_smbios_bdf { 153 struct dmi_header hdr; 154 u32 padding; 155 u8 bdf_enabled; 156 u8 bdf_ext[]; 157 } __packed; 158 159 #define HEHANDLE_CAP_PHYINFO_SIZE 3 160 #define HECAP_PHYINFO_SIZE 9 161 #define HECAP_MACINFO_SIZE 5 162 #define HECAP_TXRX_MCS_NSS_SIZE 2 163 #define HECAP_PPET16_PPET8_MAX_SIZE 25 164 165 #define HE_PPET16_PPET8_SIZE 8 166 167 /* 802.11ax PPE (PPDU packet Extension) threshold */ 168 struct he_ppe_threshold { 169 u32 numss_m1; 170 u32 ru_mask; 171 u32 ppet16_ppet8_ru3_ru0[HE_PPET16_PPET8_SIZE]; 172 }; 173 174 struct ath12k_he { 175 u8 hecap_macinfo[HECAP_MACINFO_SIZE]; 176 u32 hecap_rxmcsnssmap; 177 u32 hecap_txmcsnssmap; 178 u32 hecap_phyinfo[HEHANDLE_CAP_PHYINFO_SIZE]; 179 struct he_ppe_threshold hecap_ppet; 180 u32 heop_param; 181 }; 182 183 #define MAX_RADIOS 3 184 185 enum { 186 WMI_HOST_TP_SCALE_MAX = 0, 187 WMI_HOST_TP_SCALE_50 = 1, 188 WMI_HOST_TP_SCALE_25 = 2, 189 WMI_HOST_TP_SCALE_12 = 3, 190 WMI_HOST_TP_SCALE_MIN = 4, 191 WMI_HOST_TP_SCALE_SIZE = 5, 192 }; 193 194 enum ath12k_scan_state { 195 ATH12K_SCAN_IDLE, 196 ATH12K_SCAN_STARTING, 197 ATH12K_SCAN_RUNNING, 198 ATH12K_SCAN_ABORTING, 199 }; 200 201 enum ath12k_dev_flags { 202 ATH12K_CAC_RUNNING, 203 ATH12K_FLAG_CRASH_FLUSH, 204 ATH12K_FLAG_RAW_MODE, 205 ATH12K_FLAG_HW_CRYPTO_DISABLED, 206 ATH12K_FLAG_RECOVERY, 207 ATH12K_FLAG_UNREGISTERING, 208 ATH12K_FLAG_REGISTERED, 209 ATH12K_FLAG_QMI_FAIL, 210 ATH12K_FLAG_HTC_SUSPEND_COMPLETE, 211 ATH12K_FLAG_CE_IRQ_ENABLED, 212 ATH12K_FLAG_EXT_IRQ_ENABLED, 213 }; 214 215 enum ath12k_monitor_flags { 216 ATH12K_FLAG_MONITOR_ENABLED, 217 }; 218 219 struct ath12k_tx_conf { 220 bool changed; 221 u16 ac; 222 struct ieee80211_tx_queue_params tx_queue_params; 223 }; 224 225 struct ath12k_key_conf { 226 bool changed; 227 enum set_key_cmd cmd; 228 struct ieee80211_key_conf *key; 229 }; 230 231 struct ath12k_vif_cache { 232 struct ath12k_tx_conf tx_conf; 233 struct ath12k_key_conf key_conf; 234 u32 bss_conf_changed; 235 }; 236 237 struct ath12k_vif { 238 u32 vdev_id; 239 enum wmi_vdev_type vdev_type; 240 enum wmi_vdev_subtype vdev_subtype; 241 u32 beacon_interval; 242 u32 dtim_period; 243 u16 ast_hash; 244 u16 ast_idx; 245 u16 tcl_metadata; 246 u8 hal_addr_search_flags; 247 u8 search_type; 248 249 struct ath12k *ar; 250 struct ieee80211_vif *vif; 251 252 int bank_id; 253 u8 vdev_id_check_en; 254 255 struct wmi_wmm_params_all_arg wmm_params; 256 struct list_head list; 257 union { 258 struct { 259 u32 uapsd; 260 } sta; 261 struct { 262 /* 127 stations; wmi limit */ 263 u8 tim_bitmap[16]; 264 u8 tim_len; 265 u32 ssid_len; 266 u8 ssid[IEEE80211_MAX_SSID_LEN]; 267 bool hidden_ssid; 268 /* P2P_IE with NoA attribute for P2P_GO case */ 269 u32 noa_len; 270 u8 *noa_data; 271 } ap; 272 } u; 273 274 bool is_created; 275 bool is_started; 276 bool is_up; 277 u32 aid; 278 u8 bssid[ETH_ALEN]; 279 struct cfg80211_bitrate_mask bitrate_mask; 280 struct delayed_work connection_loss_work; 281 int num_legacy_stations; 282 int rtscts_prot_mode; 283 int txpower; 284 bool rsnie_present; 285 bool wpaie_present; 286 struct ieee80211_chanctx_conf chanctx; 287 u32 key_cipher; 288 u8 tx_encap_type; 289 u8 vdev_stats_id; 290 u32 punct_bitmap; 291 bool ps; 292 struct ath12k_vif_cache *cache; 293 }; 294 295 struct ath12k_vif_iter { 296 u32 vdev_id; 297 struct ath12k *ar; 298 struct ath12k_vif *arvif; 299 }; 300 301 #define HAL_AST_IDX_INVALID 0xFFFF 302 #define HAL_RX_MAX_MCS 12 303 #define HAL_RX_MAX_MCS_HT 31 304 #define HAL_RX_MAX_MCS_VHT 9 305 #define HAL_RX_MAX_MCS_HE 11 306 #define HAL_RX_MAX_NSS 8 307 #define HAL_RX_MAX_NUM_LEGACY_RATES 12 308 #define ATH12K_RX_RATE_TABLE_11AX_NUM 576 309 #define ATH12K_RX_RATE_TABLE_NUM 320 310 311 struct ath12k_rx_peer_rate_stats { 312 u64 ht_mcs_count[HAL_RX_MAX_MCS_HT + 1]; 313 u64 vht_mcs_count[HAL_RX_MAX_MCS_VHT + 1]; 314 u64 he_mcs_count[HAL_RX_MAX_MCS_HE + 1]; 315 u64 nss_count[HAL_RX_MAX_NSS]; 316 u64 bw_count[HAL_RX_BW_MAX]; 317 u64 gi_count[HAL_RX_GI_MAX]; 318 u64 legacy_count[HAL_RX_MAX_NUM_LEGACY_RATES]; 319 u64 rx_rate[ATH12K_RX_RATE_TABLE_11AX_NUM]; 320 }; 321 322 struct ath12k_rx_peer_stats { 323 u64 num_msdu; 324 u64 num_mpdu_fcs_ok; 325 u64 num_mpdu_fcs_err; 326 u64 tcp_msdu_count; 327 u64 udp_msdu_count; 328 u64 other_msdu_count; 329 u64 ampdu_msdu_count; 330 u64 non_ampdu_msdu_count; 331 u64 stbc_count; 332 u64 beamformed_count; 333 u64 mcs_count[HAL_RX_MAX_MCS + 1]; 334 u64 nss_count[HAL_RX_MAX_NSS]; 335 u64 bw_count[HAL_RX_BW_MAX]; 336 u64 gi_count[HAL_RX_GI_MAX]; 337 u64 coding_count[HAL_RX_SU_MU_CODING_MAX]; 338 u64 tid_count[IEEE80211_NUM_TIDS + 1]; 339 u64 pream_cnt[HAL_RX_PREAMBLE_MAX]; 340 u64 reception_type[HAL_RX_RECEPTION_TYPE_MAX]; 341 u64 rx_duration; 342 u64 dcm_count; 343 u64 ru_alloc_cnt[HAL_RX_RU_ALLOC_TYPE_MAX]; 344 struct ath12k_rx_peer_rate_stats pkt_stats; 345 struct ath12k_rx_peer_rate_stats byte_stats; 346 }; 347 348 #define ATH12K_HE_MCS_NUM 12 349 #define ATH12K_VHT_MCS_NUM 10 350 #define ATH12K_BW_NUM 5 351 #define ATH12K_NSS_NUM 4 352 #define ATH12K_LEGACY_NUM 12 353 #define ATH12K_GI_NUM 4 354 #define ATH12K_HT_MCS_NUM 32 355 356 enum ath12k_pkt_rx_err { 357 ATH12K_PKT_RX_ERR_FCS, 358 ATH12K_PKT_RX_ERR_TKIP, 359 ATH12K_PKT_RX_ERR_CRYPT, 360 ATH12K_PKT_RX_ERR_PEER_IDX_INVAL, 361 ATH12K_PKT_RX_ERR_MAX, 362 }; 363 364 enum ath12k_ampdu_subfrm_num { 365 ATH12K_AMPDU_SUBFRM_NUM_10, 366 ATH12K_AMPDU_SUBFRM_NUM_20, 367 ATH12K_AMPDU_SUBFRM_NUM_30, 368 ATH12K_AMPDU_SUBFRM_NUM_40, 369 ATH12K_AMPDU_SUBFRM_NUM_50, 370 ATH12K_AMPDU_SUBFRM_NUM_60, 371 ATH12K_AMPDU_SUBFRM_NUM_MORE, 372 ATH12K_AMPDU_SUBFRM_NUM_MAX, 373 }; 374 375 enum ath12k_amsdu_subfrm_num { 376 ATH12K_AMSDU_SUBFRM_NUM_1, 377 ATH12K_AMSDU_SUBFRM_NUM_2, 378 ATH12K_AMSDU_SUBFRM_NUM_3, 379 ATH12K_AMSDU_SUBFRM_NUM_4, 380 ATH12K_AMSDU_SUBFRM_NUM_MORE, 381 ATH12K_AMSDU_SUBFRM_NUM_MAX, 382 }; 383 384 enum ath12k_counter_type { 385 ATH12K_COUNTER_TYPE_BYTES, 386 ATH12K_COUNTER_TYPE_PKTS, 387 ATH12K_COUNTER_TYPE_MAX, 388 }; 389 390 enum ath12k_stats_type { 391 ATH12K_STATS_TYPE_SUCC, 392 ATH12K_STATS_TYPE_FAIL, 393 ATH12K_STATS_TYPE_RETRY, 394 ATH12K_STATS_TYPE_AMPDU, 395 ATH12K_STATS_TYPE_MAX, 396 }; 397 398 struct ath12k_htt_data_stats { 399 u64 legacy[ATH12K_COUNTER_TYPE_MAX][ATH12K_LEGACY_NUM]; 400 u64 ht[ATH12K_COUNTER_TYPE_MAX][ATH12K_HT_MCS_NUM]; 401 u64 vht[ATH12K_COUNTER_TYPE_MAX][ATH12K_VHT_MCS_NUM]; 402 u64 he[ATH12K_COUNTER_TYPE_MAX][ATH12K_HE_MCS_NUM]; 403 u64 bw[ATH12K_COUNTER_TYPE_MAX][ATH12K_BW_NUM]; 404 u64 nss[ATH12K_COUNTER_TYPE_MAX][ATH12K_NSS_NUM]; 405 u64 gi[ATH12K_COUNTER_TYPE_MAX][ATH12K_GI_NUM]; 406 u64 transmit_type[ATH12K_COUNTER_TYPE_MAX][HAL_RX_RECEPTION_TYPE_MAX]; 407 u64 ru_loc[ATH12K_COUNTER_TYPE_MAX][HAL_RX_RU_ALLOC_TYPE_MAX]; 408 }; 409 410 struct ath12k_htt_tx_stats { 411 struct ath12k_htt_data_stats stats[ATH12K_STATS_TYPE_MAX]; 412 u64 tx_duration; 413 u64 ba_fails; 414 u64 ack_fails; 415 u16 ru_start; 416 u16 ru_tones; 417 u32 mu_group[MAX_MU_GROUP_ID]; 418 }; 419 420 struct ath12k_per_ppdu_tx_stats { 421 u16 succ_pkts; 422 u16 failed_pkts; 423 u16 retry_pkts; 424 u32 succ_bytes; 425 u32 failed_bytes; 426 u32 retry_bytes; 427 }; 428 429 struct ath12k_wbm_tx_stats { 430 u64 wbm_tx_comp_stats[HAL_WBM_REL_HTT_TX_COMP_STATUS_MAX]; 431 }; 432 433 struct ath12k_sta { 434 struct ath12k_vif *arvif; 435 436 /* the following are protected by ar->data_lock */ 437 u32 changed; /* IEEE80211_RC_* */ 438 u32 bw; 439 u32 nss; 440 u32 smps; 441 enum hal_pn_type pn_type; 442 443 struct work_struct update_wk; 444 struct rate_info txrate; 445 struct rate_info last_txrate; 446 u64 rx_duration; 447 u64 tx_duration; 448 u8 rssi_comb; 449 struct ath12k_rx_peer_stats *rx_stats; 450 struct ath12k_wbm_tx_stats *wbm_tx_stats; 451 u32 bw_prev; 452 }; 453 454 #define ATH12K_MIN_5G_FREQ 4150 455 #define ATH12K_MIN_6G_FREQ 5925 456 #define ATH12K_MAX_6G_FREQ 7115 457 #define ATH12K_NUM_CHANS 100 458 #define ATH12K_MAX_5G_CHAN 173 459 460 enum ath12k_state { 461 ATH12K_STATE_OFF, 462 ATH12K_STATE_ON, 463 ATH12K_STATE_RESTARTING, 464 ATH12K_STATE_RESTARTED, 465 ATH12K_STATE_WEDGED, 466 /* Add other states as required */ 467 }; 468 469 /* Antenna noise floor */ 470 #define ATH12K_DEFAULT_NOISE_FLOOR -95 471 472 struct ath12k_fw_stats { 473 u32 pdev_id; 474 u32 stats_id; 475 struct list_head pdevs; 476 struct list_head vdevs; 477 struct list_head bcn; 478 }; 479 480 struct ath12k_debug { 481 struct dentry *debugfs_pdev; 482 }; 483 484 struct ath12k_per_peer_tx_stats { 485 u32 succ_bytes; 486 u32 retry_bytes; 487 u32 failed_bytes; 488 u32 duration; 489 u16 succ_pkts; 490 u16 retry_pkts; 491 u16 failed_pkts; 492 u16 ru_start; 493 u16 ru_tones; 494 u8 ba_fails; 495 u8 ppdu_type; 496 u32 mu_grpid; 497 u32 mu_pos; 498 bool is_ampdu; 499 }; 500 501 #define ATH12K_FLUSH_TIMEOUT (5 * HZ) 502 #define ATH12K_VDEV_DELETE_TIMEOUT_HZ (5 * HZ) 503 504 struct ath12k { 505 struct ath12k_base *ab; 506 struct ath12k_pdev *pdev; 507 struct ath12k_hw *ah; 508 struct ath12k_wmi_pdev *wmi; 509 struct ath12k_pdev_dp dp; 510 u8 mac_addr[ETH_ALEN]; 511 u32 ht_cap_info; 512 u32 vht_cap_info; 513 struct ath12k_he ar_he; 514 enum ath12k_state state; 515 bool supports_6ghz; 516 struct { 517 struct completion started; 518 struct completion completed; 519 struct completion on_channel; 520 struct delayed_work timeout; 521 enum ath12k_scan_state state; 522 bool is_roc; 523 int vdev_id; 524 int roc_freq; 525 bool roc_notify; 526 } scan; 527 528 struct { 529 struct ieee80211_supported_band sbands[NUM_NL80211_BANDS]; 530 struct ieee80211_sband_iftype_data 531 iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES]; 532 } mac; 533 534 unsigned long dev_flags; 535 unsigned int filter_flags; 536 unsigned long monitor_flags; 537 u32 min_tx_power; 538 u32 max_tx_power; 539 u32 txpower_limit_2g; 540 u32 txpower_limit_5g; 541 u32 txpower_scale; 542 u32 power_scale; 543 u32 chan_tx_pwr; 544 u32 num_stations; 545 u32 max_num_stations; 546 bool monitor_present; 547 /* To synchronize concurrent synchronous mac80211 callback operations, 548 * concurrent debugfs configuration and concurrent FW statistics events. 549 */ 550 struct mutex conf_mutex; 551 /* protects the radio specific data like debug stats, ppdu_stats_info stats, 552 * vdev_stop_status info, scan data, ath12k_sta info, ath12k_vif info, 553 * channel context data, survey info, test mode data. 554 */ 555 spinlock_t data_lock; 556 557 struct list_head arvifs; 558 /* should never be NULL; needed for regular htt rx */ 559 struct ieee80211_channel *rx_channel; 560 561 /* valid during scan; needed for mgmt rx during scan */ 562 struct ieee80211_channel *scan_channel; 563 564 u8 cfg_tx_chainmask; 565 u8 cfg_rx_chainmask; 566 u8 num_rx_chains; 567 u8 num_tx_chains; 568 /* pdev_idx starts from 0 whereas pdev->pdev_id starts with 1 */ 569 u8 pdev_idx; 570 u8 lmac_id; 571 u8 hw_link_id; 572 573 struct completion peer_assoc_done; 574 struct completion peer_delete_done; 575 576 int install_key_status; 577 struct completion install_key_done; 578 579 int last_wmi_vdev_start_status; 580 struct completion vdev_setup_done; 581 struct completion vdev_delete_done; 582 583 int num_peers; 584 int max_num_peers; 585 u32 num_started_vdevs; 586 u32 num_created_vdevs; 587 unsigned long long allocated_vdev_map; 588 589 struct idr txmgmt_idr; 590 /* protects txmgmt_idr data */ 591 spinlock_t txmgmt_idr_lock; 592 atomic_t num_pending_mgmt_tx; 593 wait_queue_head_t txmgmt_empty_waitq; 594 595 /* cycle count is reported twice for each visited channel during scan. 596 * access protected by data_lock 597 */ 598 u32 survey_last_rx_clear_count; 599 u32 survey_last_cycle_count; 600 601 /* Channel info events are expected to come in pairs without and with 602 * COMPLETE flag set respectively for each channel visit during scan. 603 * 604 * However there are deviations from this rule. This flag is used to 605 * avoid reporting garbage data. 606 */ 607 bool ch_info_can_report_survey; 608 struct survey_info survey[ATH12K_NUM_CHANS]; 609 struct completion bss_survey_done; 610 611 struct work_struct regd_update_work; 612 613 struct work_struct wmi_mgmt_tx_work; 614 struct sk_buff_head wmi_mgmt_tx_queue; 615 616 struct ath12k_per_peer_tx_stats peer_tx_stats; 617 struct list_head ppdu_stats_info; 618 u32 ppdu_stat_list_depth; 619 620 struct ath12k_per_peer_tx_stats cached_stats; 621 u32 last_ppdu_id; 622 u32 cached_ppdu_id; 623 #ifdef CONFIG_ATH12K_DEBUGFS 624 struct ath12k_debug debug; 625 #endif 626 627 bool dfs_block_radar_events; 628 bool monitor_conf_enabled; 629 bool monitor_vdev_created; 630 bool monitor_started; 631 int monitor_vdev_id; 632 633 u32 freq_low; 634 u32 freq_high; 635 }; 636 637 struct ath12k_hw { 638 struct ieee80211_hw *hw; 639 bool regd_updated; 640 bool use_6ghz_regd; 641 642 u8 num_radio; 643 struct ath12k radio[] __aligned(sizeof(void *)); 644 }; 645 646 struct ath12k_band_cap { 647 u32 phy_id; 648 u32 max_bw_supported; 649 u32 ht_cap_info; 650 u32 he_cap_info[2]; 651 u32 he_mcs; 652 u32 he_cap_phy_info[PSOC_HOST_MAX_PHY_SIZE]; 653 struct ath12k_wmi_ppe_threshold_arg he_ppet; 654 u16 he_6ghz_capa; 655 u32 eht_cap_mac_info[WMI_MAX_EHTCAP_MAC_SIZE]; 656 u32 eht_cap_phy_info[WMI_MAX_EHTCAP_PHY_SIZE]; 657 u32 eht_mcs_20_only; 658 u32 eht_mcs_80; 659 u32 eht_mcs_160; 660 u32 eht_mcs_320; 661 struct ath12k_wmi_ppe_threshold_arg eht_ppet; 662 u32 eht_cap_info_internal; 663 }; 664 665 struct ath12k_pdev_cap { 666 u32 supported_bands; 667 u32 ampdu_density; 668 u32 vht_cap; 669 u32 vht_mcs; 670 u32 he_mcs; 671 u32 tx_chain_mask; 672 u32 rx_chain_mask; 673 u32 tx_chain_mask_shift; 674 u32 rx_chain_mask_shift; 675 struct ath12k_band_cap band[NUM_NL80211_BANDS]; 676 }; 677 678 struct mlo_timestamp { 679 u32 info; 680 u32 sync_timestamp_lo_us; 681 u32 sync_timestamp_hi_us; 682 u32 mlo_offset_lo; 683 u32 mlo_offset_hi; 684 u32 mlo_offset_clks; 685 u32 mlo_comp_clks; 686 u32 mlo_comp_timer; 687 }; 688 689 struct ath12k_pdev { 690 struct ath12k *ar; 691 u32 pdev_id; 692 struct ath12k_pdev_cap cap; 693 u8 mac_addr[ETH_ALEN]; 694 struct mlo_timestamp timestamp; 695 }; 696 697 struct ath12k_fw_pdev { 698 u32 pdev_id; 699 u32 phy_id; 700 u32 supported_bands; 701 }; 702 703 struct ath12k_board_data { 704 const struct firmware *fw; 705 const void *data; 706 size_t len; 707 }; 708 709 struct ath12k_soc_dp_tx_err_stats { 710 /* TCL Ring Descriptor unavailable */ 711 u32 desc_na[DP_TCL_NUM_RING_MAX]; 712 /* Other failures during dp_tx due to mem allocation failure 713 * idr unavailable etc. 714 */ 715 atomic_t misc_fail; 716 }; 717 718 struct ath12k_soc_dp_stats { 719 u32 err_ring_pkts; 720 u32 invalid_rbm; 721 u32 rxdma_error[HAL_REO_ENTR_RING_RXDMA_ECODE_MAX]; 722 u32 reo_error[HAL_REO_DEST_RING_ERROR_CODE_MAX]; 723 u32 hal_reo_error[DP_REO_DST_RING_MAX]; 724 struct ath12k_soc_dp_tx_err_stats tx_err; 725 }; 726 727 /** 728 * enum ath12k_link_capable_flags - link capable flags 729 * 730 * Single/Multi link capability information 731 * 732 * @ATH12K_INTRA_DEVICE_MLO_SUPPORT: SLO/MLO form between the radio, where all 733 * the links (radios) present within a device. 734 * @ATH12K_INTER_DEVICE_MLO_SUPPORT: SLO/MLO form between the radio, where all 735 * the links (radios) present across the devices. 736 */ 737 enum ath12k_link_capable_flags { 738 ATH12K_INTRA_DEVICE_MLO_SUPPORT = BIT(0), 739 ATH12K_INTER_DEVICE_MLO_SUPPORT = BIT(1), 740 }; 741 742 /* Master structure to hold the hw data which may be used in core module */ 743 struct ath12k_base { 744 enum ath12k_hw_rev hw_rev; 745 struct platform_device *pdev; 746 struct device *dev; 747 struct ath12k_qmi qmi; 748 struct ath12k_wmi_base wmi_ab; 749 struct completion fw_ready; 750 int num_radios; 751 /* HW channel counters frequency value in hertz common to all MACs */ 752 u32 cc_freq_hz; 753 754 struct ath12k_htc htc; 755 756 struct ath12k_dp dp; 757 758 void __iomem *mem; 759 unsigned long mem_len; 760 761 struct { 762 enum ath12k_bus bus; 763 const struct ath12k_hif_ops *ops; 764 } hif; 765 766 struct ath12k_ce ce; 767 struct timer_list rx_replenish_retry; 768 struct ath12k_hal hal; 769 /* To synchronize core_start/core_stop */ 770 struct mutex core_lock; 771 /* Protects data like peers */ 772 spinlock_t base_lock; 773 774 /* Single pdev device (struct ath12k_hw_params::single_pdev_only): 775 * 776 * Firmware maintains data for all bands but advertises a single 777 * phy to the host which is stored as a single element in this 778 * array. 779 * 780 * Other devices: 781 * 782 * This array will contain as many elements as the number of 783 * radios. 784 */ 785 struct ath12k_pdev pdevs[MAX_RADIOS]; 786 787 /* struct ath12k_hw_params::single_pdev_only devices use this to 788 * store phy specific data 789 */ 790 struct ath12k_fw_pdev fw_pdev[MAX_RADIOS]; 791 u8 fw_pdev_count; 792 793 struct ath12k_pdev __rcu *pdevs_active[MAX_RADIOS]; 794 795 /* Holds information of wiphy (hw) registration. 796 * 797 * In Multi/Single Link Operation case, all pdevs are registered as 798 * a single wiphy. In other (legacy/Non-MLO) cases, each pdev is 799 * registered as separate wiphys. 800 */ 801 struct ath12k_hw *ah[MAX_RADIOS]; 802 u8 num_hw; 803 804 struct ath12k_wmi_hal_reg_capabilities_ext_arg hal_reg_cap[MAX_RADIOS]; 805 unsigned long long free_vdev_map; 806 unsigned long long free_vdev_stats_id_map; 807 struct list_head peers; 808 wait_queue_head_t peer_mapping_wq; 809 u8 mac_addr[ETH_ALEN]; 810 bool wmi_ready; 811 u32 wlan_init_status; 812 int irq_num[ATH12K_IRQ_NUM_MAX]; 813 struct ath12k_ext_irq_grp ext_irq_grp[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 814 struct napi_struct *napi; 815 struct ath12k_wmi_target_cap_arg target_caps; 816 u32 ext_service_bitmap[WMI_SERVICE_EXT_BM_SIZE]; 817 bool pdevs_macaddr_valid; 818 819 const struct ath12k_hw_params *hw_params; 820 821 const struct firmware *cal_file; 822 823 /* Below regd's are protected by ab->data_lock */ 824 /* This is the regd set for every radio 825 * by the firmware during initialization 826 */ 827 struct ieee80211_regdomain *default_regd[MAX_RADIOS]; 828 /* This regd is set during dynamic country setting 829 * This may or may not be used during the runtime 830 */ 831 struct ieee80211_regdomain *new_regd[MAX_RADIOS]; 832 833 /* Current DFS Regulatory */ 834 enum ath12k_dfs_region dfs_region; 835 struct ath12k_soc_dp_stats soc_stats; 836 #ifdef CONFIG_ATH12K_DEBUGFS 837 struct dentry *debugfs_soc; 838 #endif 839 840 unsigned long dev_flags; 841 struct completion driver_recovery; 842 struct workqueue_struct *workqueue; 843 struct work_struct restart_work; 844 struct workqueue_struct *workqueue_aux; 845 struct work_struct reset_work; 846 atomic_t reset_count; 847 atomic_t recovery_count; 848 atomic_t recovery_start_count; 849 bool is_reset; 850 struct completion reset_complete; 851 struct completion reconfigure_complete; 852 struct completion recovery_start; 853 /* continuous recovery fail count */ 854 atomic_t fail_cont_count; 855 unsigned long reset_fail_timeout; 856 struct { 857 /* protected by data_lock */ 858 u32 fw_crash_counter; 859 } stats; 860 u32 pktlog_defs_checksum; 861 862 struct ath12k_dbring_cap *db_caps; 863 u32 num_db_cap; 864 865 struct timer_list mon_reap_timer; 866 867 struct completion htc_suspend; 868 869 u64 fw_soc_drop_count; 870 bool static_window_map; 871 872 struct work_struct rfkill_work; 873 /* true means radio is on */ 874 bool rfkill_radio_on; 875 876 struct { 877 enum ath12k_bdf_search bdf_search; 878 u32 vendor; 879 u32 device; 880 u32 subsystem_vendor; 881 u32 subsystem_device; 882 } id; 883 884 struct { 885 u32 api_version; 886 887 const struct firmware *fw; 888 const u8 *amss_data; 889 size_t amss_len; 890 const u8 *amss_dualmac_data; 891 size_t amss_dualmac_len; 892 const u8 *m3_data; 893 size_t m3_len; 894 895 DECLARE_BITMAP(fw_features, ATH12K_FW_FEATURE_COUNT); 896 } fw; 897 898 const struct hal_rx_ops *hal_rx_ops; 899 900 /* mlo_capable_flags denotes the single/multi link operation 901 * capabilities of the Device. 902 * 903 * See enum ath12k_link_capable_flags 904 */ 905 u8 mlo_capable_flags; 906 907 struct completion restart_completed; 908 909 #ifdef CONFIG_ACPI 910 911 struct { 912 bool started; 913 u32 func_bit; 914 bool acpi_tas_enable; 915 bool acpi_bios_sar_enable; 916 u8 tas_cfg[ATH12K_ACPI_DSM_TAS_CFG_SIZE]; 917 u8 tas_sar_power_table[ATH12K_ACPI_DSM_TAS_DATA_SIZE]; 918 u8 bios_sar_data[ATH12K_ACPI_DSM_BIOS_SAR_DATA_SIZE]; 919 u8 geo_offset_data[ATH12K_ACPI_DSM_GEO_OFFSET_DATA_SIZE]; 920 u8 cca_data[ATH12K_ACPI_DSM_CCA_DATA_SIZE]; 921 u8 band_edge_power[ATH12K_ACPI_DSM_BAND_EDGE_DATA_SIZE]; 922 } acpi; 923 924 #endif /* CONFIG_ACPI */ 925 926 /* must be last */ 927 u8 drv_priv[] __aligned(sizeof(void *)); 928 }; 929 930 struct ath12k_pdev_map { 931 struct ath12k_base *ab; 932 u8 pdev_idx; 933 }; 934 935 int ath12k_core_qmi_firmware_ready(struct ath12k_base *ab); 936 int ath12k_core_pre_init(struct ath12k_base *ab); 937 int ath12k_core_init(struct ath12k_base *ath12k); 938 void ath12k_core_deinit(struct ath12k_base *ath12k); 939 struct ath12k_base *ath12k_core_alloc(struct device *dev, size_t priv_size, 940 enum ath12k_bus bus); 941 void ath12k_core_free(struct ath12k_base *ath12k); 942 int ath12k_core_fetch_board_data_api_1(struct ath12k_base *ab, 943 struct ath12k_board_data *bd, 944 char *filename); 945 int ath12k_core_fetch_bdf(struct ath12k_base *ath12k, 946 struct ath12k_board_data *bd); 947 void ath12k_core_free_bdf(struct ath12k_base *ab, struct ath12k_board_data *bd); 948 int ath12k_core_fetch_regdb(struct ath12k_base *ab, struct ath12k_board_data *bd); 949 int ath12k_core_check_dt(struct ath12k_base *ath12k); 950 int ath12k_core_check_smbios(struct ath12k_base *ab); 951 void ath12k_core_halt(struct ath12k *ar); 952 int ath12k_core_resume_early(struct ath12k_base *ab); 953 int ath12k_core_resume(struct ath12k_base *ab); 954 int ath12k_core_suspend(struct ath12k_base *ab); 955 int ath12k_core_suspend_late(struct ath12k_base *ab); 956 957 const struct firmware *ath12k_core_firmware_request(struct ath12k_base *ab, 958 const char *filename); 959 u32 ath12k_core_get_max_station_per_radio(struct ath12k_base *ab); 960 u32 ath12k_core_get_max_peers_per_radio(struct ath12k_base *ab); 961 u32 ath12k_core_get_max_num_tids(struct ath12k_base *ab); 962 963 static inline const char *ath12k_scan_state_str(enum ath12k_scan_state state) 964 { 965 switch (state) { 966 case ATH12K_SCAN_IDLE: 967 return "idle"; 968 case ATH12K_SCAN_STARTING: 969 return "starting"; 970 case ATH12K_SCAN_RUNNING: 971 return "running"; 972 case ATH12K_SCAN_ABORTING: 973 return "aborting"; 974 } 975 976 return "unknown"; 977 } 978 979 static inline struct ath12k_skb_cb *ATH12K_SKB_CB(struct sk_buff *skb) 980 { 981 BUILD_BUG_ON(sizeof(struct ath12k_skb_cb) > 982 IEEE80211_TX_INFO_DRIVER_DATA_SIZE); 983 return (struct ath12k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data; 984 } 985 986 static inline struct ath12k_skb_rxcb *ATH12K_SKB_RXCB(struct sk_buff *skb) 987 { 988 BUILD_BUG_ON(sizeof(struct ath12k_skb_rxcb) > sizeof(skb->cb)); 989 return (struct ath12k_skb_rxcb *)skb->cb; 990 } 991 992 static inline struct ath12k_vif *ath12k_vif_to_arvif(struct ieee80211_vif *vif) 993 { 994 return (struct ath12k_vif *)vif->drv_priv; 995 } 996 997 static inline struct ath12k_sta *ath12k_sta_to_arsta(struct ieee80211_sta *sta) 998 { 999 return (struct ath12k_sta *)sta->drv_priv; 1000 } 1001 1002 static inline struct ath12k *ath12k_ab_to_ar(struct ath12k_base *ab, 1003 int mac_id) 1004 { 1005 return ab->pdevs[ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id)].ar; 1006 } 1007 1008 static inline void ath12k_core_create_firmware_path(struct ath12k_base *ab, 1009 const char *filename, 1010 void *buf, size_t buf_len) 1011 { 1012 snprintf(buf, buf_len, "%s/%s/%s", ATH12K_FW_DIR, 1013 ab->hw_params->fw.dir, filename); 1014 } 1015 1016 static inline const char *ath12k_bus_str(enum ath12k_bus bus) 1017 { 1018 switch (bus) { 1019 case ATH12K_BUS_PCI: 1020 return "pci"; 1021 } 1022 1023 return "unknown"; 1024 } 1025 1026 static inline struct ath12k_hw *ath12k_hw_to_ah(struct ieee80211_hw *hw) 1027 { 1028 return hw->priv; 1029 } 1030 1031 static inline struct ath12k *ath12k_ah_to_ar(struct ath12k_hw *ah, u8 hw_link_id) 1032 { 1033 if (WARN(hw_link_id >= ah->num_radio, 1034 "bad hw link id %d, so switch to default link\n", hw_link_id)) 1035 hw_link_id = 0; 1036 1037 return &ah->radio[hw_link_id]; 1038 } 1039 1040 static inline struct ieee80211_hw *ath12k_ar_to_hw(struct ath12k *ar) 1041 { 1042 return ar->ah->hw; 1043 } 1044 1045 #define for_each_ar(ah, ar, index) \ 1046 for ((index) = 0; ((index) < (ah)->num_radio && \ 1047 ((ar) = &(ah)->radio[(index)])); (index)++) 1048 #endif /* _CORE_H_ */ 1049