1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 5 */ 6 7 #ifndef ATH12K_CE_H 8 #define ATH12K_CE_H 9 10 #define CE_COUNT_MAX 16 11 12 /* Byte swap data words */ 13 #define CE_ATTR_BYTE_SWAP_DATA 2 14 15 /* no interrupt on copy completion */ 16 #define CE_ATTR_DIS_INTR 8 17 18 /* Host software's Copy Engine configuration. */ 19 #define CE_ATTR_FLAGS 0 20 21 /* Threshold to poll for tx completion in case of Interrupt disabled CE's */ 22 #define ATH12K_CE_USAGE_THRESHOLD 32 23 24 /* Directions for interconnect pipe configuration. 25 * These definitions may be used during configuration and are shared 26 * between Host and Target. 27 * 28 * Pipe Directions are relative to the Host, so PIPEDIR_IN means 29 * "coming IN over air through Target to Host" as with a WiFi Rx operation. 30 * Conversely, PIPEDIR_OUT means "going OUT from Host through Target over air" 31 * as with a WiFi Tx operation. This is somewhat awkward for the "middle-man" 32 * Target since things that are "PIPEDIR_OUT" are coming IN to the Target 33 * over the interconnect. 34 */ 35 #define PIPEDIR_NONE 0 36 #define PIPEDIR_IN 1 /* Target-->Host, WiFi Rx direction */ 37 #define PIPEDIR_OUT 2 /* Host->Target, WiFi Tx direction */ 38 #define PIPEDIR_INOUT 3 /* bidirectional */ 39 #define PIPEDIR_INOUT_H2H 4 /* bidirectional, host to host */ 40 41 /* IPQ5332 CE address/mask */ 42 #define CE_HOST_IPQ5332_IE_ADDRESS 0x75804C 43 #define CE_HOST_IPQ5332_IE_2_ADDRESS 0x758050 44 #define CE_HOST_IPQ5332_IE_3_ADDRESS CE_HOST_IPQ5332_IE_ADDRESS 45 46 /* IPQ5424 CE address/mask */ 47 #define CE_HOST_IPQ5424_IE_ADDRESS 0x21804C 48 #define CE_HOST_IPQ5424_IE_2_ADDRESS 0x218050 49 #define CE_HOST_IPQ5424_IE_3_ADDRESS CE_HOST_IPQ5424_IE_ADDRESS 50 51 #define CE_HOST_IE_3_SHIFT 0xC 52 53 #define CE_RING_IDX_INCR(nentries_mask, idx) (((idx) + 1) & (nentries_mask)) 54 55 #define ATH12K_CE_RX_POST_RETRY_JIFFIES 50 56 57 struct ath12k_base; 58 59 /* Establish a mapping between a service/direction and a pipe. 60 * Configuration information for a Copy Engine pipe and services. 61 * Passed from Host to Target through QMI message and must be in 62 * little endian format. 63 */ 64 struct service_to_pipe { 65 __le32 service_id; 66 __le32 pipedir; 67 __le32 pipenum; 68 }; 69 70 /* Configuration information for a Copy Engine pipe. 71 * Passed from Host to Target through QMI message during startup (one per CE). 72 * 73 * NOTE: Structure is shared between Host software and Target firmware! 74 */ 75 struct ce_pipe_config { 76 __le32 pipenum; 77 __le32 pipedir; 78 __le32 nentries; 79 __le32 nbytes_max; 80 __le32 flags; 81 __le32 reserved; 82 }; 83 84 struct ce_ie_addr { 85 u32 ie1_reg_addr; 86 u32 ie2_reg_addr; 87 u32 ie3_reg_addr; 88 }; 89 90 struct ce_remap { 91 u32 base; 92 u32 size; 93 u32 cmem_offset; 94 }; 95 96 struct ce_attr { 97 /* CE_ATTR_* values */ 98 unsigned int flags; 99 100 /* #entries in source ring - Must be a power of 2 */ 101 unsigned int src_nentries; 102 103 /* Max source send size for this CE. 104 * This is also the minimum size of a destination buffer. 105 */ 106 unsigned int src_sz_max; 107 108 /* #entries in destination ring - Must be a power of 2 */ 109 unsigned int dest_nentries; 110 111 void (*recv_cb)(struct ath12k_base *ab, struct sk_buff *skb); 112 }; 113 114 #define CE_DESC_RING_ALIGN 8 115 116 struct ath12k_ce_ring { 117 /* Number of entries in this ring; must be power of 2 */ 118 unsigned int nentries; 119 unsigned int nentries_mask; 120 121 /* For dest ring, this is the next index to be processed 122 * by software after it was/is received into. 123 * 124 * For src ring, this is the last descriptor that was sent 125 * and completion processed by software. 126 * 127 * Regardless of src or dest ring, this is an invariant 128 * (modulo ring size): 129 * write index >= read index >= sw_index 130 */ 131 unsigned int sw_index; 132 /* cached copy */ 133 unsigned int write_index; 134 135 /* Start of DMA-coherent area reserved for descriptors */ 136 /* Host address space */ 137 void *base_addr_owner_space_unaligned; 138 /* CE address space */ 139 dma_addr_t base_addr_ce_space_unaligned; 140 141 /* Actual start of descriptors. 142 * Aligned to descriptor-size boundary. 143 * Points into reserved DMA-coherent area, above. 144 */ 145 /* Host address space */ 146 void *base_addr_owner_space; 147 148 /* CE address space */ 149 dma_addr_t base_addr_ce_space; 150 151 /* HAL ring id */ 152 u32 hal_ring_id; 153 154 /* keep last */ 155 struct sk_buff *skb[]; 156 }; 157 158 struct ath12k_ce_pipe { 159 struct ath12k_base *ab; 160 u16 pipe_num; 161 unsigned int attr_flags; 162 unsigned int buf_sz; 163 unsigned int rx_buf_needed; 164 165 void (*send_cb)(struct ath12k_ce_pipe *pipe); 166 void (*recv_cb)(struct ath12k_base *ab, struct sk_buff *skb); 167 168 struct work_struct intr_wq; 169 struct ath12k_ce_ring *src_ring; 170 struct ath12k_ce_ring *dest_ring; 171 struct ath12k_ce_ring *status_ring; 172 u64 timestamp; 173 }; 174 175 struct ath12k_ce { 176 struct ath12k_ce_pipe ce_pipe[CE_COUNT_MAX]; 177 /* Protects rings of all ce pipes */ 178 spinlock_t ce_lock; 179 struct ath12k_hp_update_timer hp_timer[CE_COUNT_MAX]; 180 }; 181 182 void ath12k_ce_cleanup_pipes(struct ath12k_base *ab); 183 void ath12k_ce_rx_replenish_retry(struct timer_list *t); 184 void ath12k_ce_per_engine_service(struct ath12k_base *ab, u16 ce_id); 185 int ath12k_ce_send(struct ath12k_base *ab, struct sk_buff *skb, u8 pipe_id, 186 u16 transfer_id); 187 void ath12k_ce_rx_post_buf(struct ath12k_base *ab); 188 int ath12k_ce_init_pipes(struct ath12k_base *ab); 189 int ath12k_ce_alloc_pipes(struct ath12k_base *ab); 190 void ath12k_ce_free_pipes(struct ath12k_base *ab); 191 int ath12k_ce_get_attr_flags(struct ath12k_base *ab, int ce_id); 192 void ath12k_ce_poll_send_completed(struct ath12k_base *ab, u8 pipe_id); 193 void ath12k_ce_get_shadow_config(struct ath12k_base *ab, 194 u32 **shadow_cfg, u32 *shadow_cfg_len); 195 #endif 196