1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2022, 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include "dp_rx.h" 8 #include "debug.h" 9 #include "hif.h" 10 11 const struct ce_attr ath12k_host_ce_config_qcn9274[] = { 12 /* CE0: host->target HTC control and raw streams */ 13 { 14 .flags = CE_ATTR_FLAGS, 15 .src_nentries = 16, 16 .src_sz_max = 2048, 17 .dest_nentries = 0, 18 }, 19 20 /* CE1: target->host HTT + HTC control */ 21 { 22 .flags = CE_ATTR_FLAGS, 23 .src_nentries = 0, 24 .src_sz_max = 2048, 25 .dest_nentries = 512, 26 .recv_cb = ath12k_htc_rx_completion_handler, 27 }, 28 29 /* CE2: target->host WMI */ 30 { 31 .flags = CE_ATTR_FLAGS, 32 .src_nentries = 0, 33 .src_sz_max = 2048, 34 .dest_nentries = 128, 35 .recv_cb = ath12k_htc_rx_completion_handler, 36 }, 37 38 /* CE3: host->target WMI (mac0) */ 39 { 40 .flags = CE_ATTR_FLAGS, 41 .src_nentries = 32, 42 .src_sz_max = 2048, 43 .dest_nentries = 0, 44 }, 45 46 /* CE4: host->target HTT */ 47 { 48 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, 49 .src_nentries = 2048, 50 .src_sz_max = 256, 51 .dest_nentries = 0, 52 }, 53 54 /* CE5: target->host pktlog */ 55 { 56 .flags = CE_ATTR_FLAGS, 57 .src_nentries = 0, 58 .src_sz_max = 2048, 59 .dest_nentries = 512, 60 .recv_cb = ath12k_dp_htt_htc_t2h_msg_handler, 61 }, 62 63 /* CE6: target autonomous hif_memcpy */ 64 { 65 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, 66 .src_nentries = 0, 67 .src_sz_max = 0, 68 .dest_nentries = 0, 69 }, 70 71 /* CE7: host->target WMI (mac1) */ 72 { 73 .flags = CE_ATTR_FLAGS, 74 .src_nentries = 32, 75 .src_sz_max = 2048, 76 .dest_nentries = 0, 77 }, 78 79 /* CE8: target autonomous hif_memcpy */ 80 { 81 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, 82 .src_nentries = 0, 83 .src_sz_max = 0, 84 .dest_nentries = 0, 85 }, 86 87 /* CE9: MHI */ 88 { 89 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, 90 .src_nentries = 0, 91 .src_sz_max = 0, 92 .dest_nentries = 0, 93 }, 94 95 /* CE10: MHI */ 96 { 97 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, 98 .src_nentries = 0, 99 .src_sz_max = 0, 100 .dest_nentries = 0, 101 }, 102 103 /* CE11: MHI */ 104 { 105 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, 106 .src_nentries = 0, 107 .src_sz_max = 0, 108 .dest_nentries = 0, 109 }, 110 111 /* CE12: CV Prefetch */ 112 { 113 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, 114 .src_nentries = 0, 115 .src_sz_max = 0, 116 .dest_nentries = 0, 117 }, 118 119 /* CE13: CV Prefetch */ 120 { 121 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, 122 .src_nentries = 0, 123 .src_sz_max = 0, 124 .dest_nentries = 0, 125 }, 126 127 /* CE14: target->host dbg log */ 128 { 129 .flags = CE_ATTR_FLAGS, 130 .src_nentries = 0, 131 .src_sz_max = 2048, 132 .dest_nentries = 512, 133 .recv_cb = ath12k_htc_rx_completion_handler, 134 }, 135 136 /* CE15: reserved for future use */ 137 { 138 .flags = (CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 139 .src_nentries = 0, 140 .src_sz_max = 0, 141 .dest_nentries = 0, 142 }, 143 }; 144 145 const struct ce_attr ath12k_host_ce_config_wcn7850[] = { 146 /* CE0: host->target HTC control and raw streams */ 147 { 148 .flags = CE_ATTR_FLAGS, 149 .src_nentries = 16, 150 .src_sz_max = 2048, 151 .dest_nentries = 0, 152 }, 153 154 /* CE1: target->host HTT + HTC control */ 155 { 156 .flags = CE_ATTR_FLAGS, 157 .src_nentries = 0, 158 .src_sz_max = 2048, 159 .dest_nentries = 512, 160 .recv_cb = ath12k_htc_rx_completion_handler, 161 }, 162 163 /* CE2: target->host WMI */ 164 { 165 .flags = CE_ATTR_FLAGS, 166 .src_nentries = 0, 167 .src_sz_max = 2048, 168 .dest_nentries = 64, 169 .recv_cb = ath12k_htc_rx_completion_handler, 170 }, 171 172 /* CE3: host->target WMI (mac0) */ 173 { 174 .flags = CE_ATTR_FLAGS, 175 .src_nentries = 32, 176 .src_sz_max = 2048, 177 .dest_nentries = 0, 178 }, 179 180 /* CE4: host->target HTT */ 181 { 182 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, 183 .src_nentries = 2048, 184 .src_sz_max = 256, 185 .dest_nentries = 0, 186 }, 187 188 /* CE5: target->host pktlog */ 189 { 190 .flags = CE_ATTR_FLAGS, 191 .src_nentries = 0, 192 .src_sz_max = 0, 193 .dest_nentries = 0, 194 }, 195 196 /* CE6: target autonomous hif_memcpy */ 197 { 198 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, 199 .src_nentries = 0, 200 .src_sz_max = 0, 201 .dest_nentries = 0, 202 }, 203 204 /* CE7: host->target WMI (mac1) */ 205 { 206 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, 207 .src_nentries = 0, 208 .src_sz_max = 2048, 209 .dest_nentries = 0, 210 }, 211 212 /* CE8: target autonomous hif_memcpy */ 213 { 214 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, 215 .src_nentries = 0, 216 .src_sz_max = 0, 217 .dest_nentries = 0, 218 }, 219 220 }; 221 222 const struct ce_attr ath12k_host_ce_config_ipq5332[] = { 223 /* CE0: host->target HTC control and raw streams */ 224 { 225 .flags = CE_ATTR_FLAGS, 226 .src_nentries = 16, 227 .src_sz_max = 2048, 228 .dest_nentries = 0, 229 }, 230 /* CE1: target->host HTT + HTC control */ 231 { 232 .flags = CE_ATTR_FLAGS, 233 .src_nentries = 0, 234 .src_sz_max = 2048, 235 .dest_nentries = 512, 236 .recv_cb = ath12k_htc_rx_completion_handler, 237 }, 238 /* CE2: target->host WMI */ 239 { 240 .flags = CE_ATTR_FLAGS, 241 .src_nentries = 0, 242 .src_sz_max = 2048, 243 .dest_nentries = 128, 244 .recv_cb = ath12k_htc_rx_completion_handler, 245 }, 246 /* CE3: host->target WMI */ 247 { 248 .flags = CE_ATTR_FLAGS, 249 .src_nentries = 32, 250 .src_sz_max = 2048, 251 .dest_nentries = 0, 252 }, 253 /* CE4: host->target HTT */ 254 { 255 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, 256 .src_nentries = 2048, 257 .src_sz_max = 256, 258 .dest_nentries = 0, 259 }, 260 /* CE5: target -> host PKTLOG */ 261 { 262 .flags = CE_ATTR_FLAGS, 263 .src_nentries = 0, 264 .src_sz_max = 2048, 265 .dest_nentries = 512, 266 .recv_cb = ath12k_dp_htt_htc_t2h_msg_handler, 267 }, 268 /* CE6: Target autonomous HIF_memcpy */ 269 { 270 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, 271 .src_nentries = 0, 272 .src_sz_max = 0, 273 .dest_nentries = 0, 274 }, 275 /* CE7: CV Prefetch */ 276 { 277 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, 278 .src_nentries = 0, 279 .src_sz_max = 0, 280 .dest_nentries = 0, 281 }, 282 /* CE8: Target HIF memcpy (Generic HIF memcypy) */ 283 { 284 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, 285 .src_nentries = 0, 286 .src_sz_max = 0, 287 .dest_nentries = 0, 288 }, 289 /* CE9: WMI logging/CFR/Spectral/Radar */ 290 { 291 .flags = CE_ATTR_FLAGS, 292 .src_nentries = 0, 293 .src_sz_max = 2048, 294 .dest_nentries = 128, 295 }, 296 /* CE10: Unused */ 297 { 298 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, 299 .src_nentries = 0, 300 .src_sz_max = 0, 301 .dest_nentries = 0, 302 }, 303 /* CE11: Unused */ 304 { 305 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, 306 .src_nentries = 0, 307 .src_sz_max = 0, 308 .dest_nentries = 0, 309 }, 310 }; 311 312 static int ath12k_ce_rx_buf_enqueue_pipe(struct ath12k_ce_pipe *pipe, 313 struct sk_buff *skb, dma_addr_t paddr) 314 { 315 struct ath12k_base *ab = pipe->ab; 316 struct ath12k_ce_ring *ring = pipe->dest_ring; 317 struct hal_srng *srng; 318 unsigned int write_index; 319 unsigned int nentries_mask = ring->nentries_mask; 320 struct hal_ce_srng_dest_desc *desc; 321 int ret; 322 323 lockdep_assert_held(&ab->ce.ce_lock); 324 325 write_index = ring->write_index; 326 327 srng = &ab->hal.srng_list[ring->hal_ring_id]; 328 329 spin_lock_bh(&srng->lock); 330 331 ath12k_hal_srng_access_begin(ab, srng); 332 333 if (unlikely(ath12k_hal_srng_src_num_free(ab, srng, false) < 1)) { 334 ret = -ENOSPC; 335 goto exit; 336 } 337 338 desc = ath12k_hal_srng_src_get_next_entry(ab, srng); 339 if (!desc) { 340 ret = -ENOSPC; 341 goto exit; 342 } 343 344 ath12k_hal_ce_dst_set_desc(desc, paddr); 345 346 ring->skb[write_index] = skb; 347 write_index = CE_RING_IDX_INCR(nentries_mask, write_index); 348 ring->write_index = write_index; 349 350 pipe->rx_buf_needed--; 351 352 ret = 0; 353 exit: 354 ath12k_hal_srng_access_end(ab, srng); 355 356 spin_unlock_bh(&srng->lock); 357 358 return ret; 359 } 360 361 static int ath12k_ce_rx_post_pipe(struct ath12k_ce_pipe *pipe) 362 { 363 struct ath12k_base *ab = pipe->ab; 364 struct sk_buff *skb; 365 dma_addr_t paddr; 366 int ret = 0; 367 368 if (!(pipe->dest_ring || pipe->status_ring)) 369 return 0; 370 371 spin_lock_bh(&ab->ce.ce_lock); 372 while (pipe->rx_buf_needed) { 373 skb = dev_alloc_skb(pipe->buf_sz); 374 if (!skb) { 375 ret = -ENOMEM; 376 goto exit; 377 } 378 379 WARN_ON_ONCE(!IS_ALIGNED((unsigned long)skb->data, 4)); 380 381 paddr = dma_map_single(ab->dev, skb->data, 382 skb->len + skb_tailroom(skb), 383 DMA_FROM_DEVICE); 384 if (unlikely(dma_mapping_error(ab->dev, paddr))) { 385 ath12k_warn(ab, "failed to dma map ce rx buf\n"); 386 dev_kfree_skb_any(skb); 387 ret = -EIO; 388 goto exit; 389 } 390 391 ATH12K_SKB_RXCB(skb)->paddr = paddr; 392 393 ret = ath12k_ce_rx_buf_enqueue_pipe(pipe, skb, paddr); 394 if (ret) { 395 ath12k_warn(ab, "failed to enqueue rx buf: %d\n", ret); 396 dma_unmap_single(ab->dev, paddr, 397 skb->len + skb_tailroom(skb), 398 DMA_FROM_DEVICE); 399 dev_kfree_skb_any(skb); 400 goto exit; 401 } 402 } 403 404 exit: 405 spin_unlock_bh(&ab->ce.ce_lock); 406 return ret; 407 } 408 409 static int ath12k_ce_completed_recv_next(struct ath12k_ce_pipe *pipe, 410 struct sk_buff **skb, int *nbytes) 411 { 412 struct ath12k_base *ab = pipe->ab; 413 struct hal_ce_srng_dst_status_desc *desc; 414 struct hal_srng *srng; 415 unsigned int sw_index; 416 unsigned int nentries_mask; 417 int ret = 0; 418 419 spin_lock_bh(&ab->ce.ce_lock); 420 421 sw_index = pipe->dest_ring->sw_index; 422 nentries_mask = pipe->dest_ring->nentries_mask; 423 424 srng = &ab->hal.srng_list[pipe->status_ring->hal_ring_id]; 425 426 spin_lock_bh(&srng->lock); 427 428 ath12k_hal_srng_access_begin(ab, srng); 429 430 desc = ath12k_hal_srng_dst_get_next_entry(ab, srng); 431 if (!desc) { 432 ret = -EIO; 433 goto err; 434 } 435 436 *nbytes = ath12k_hal_ce_dst_status_get_length(desc); 437 if (*nbytes == 0) { 438 ret = -EIO; 439 goto err; 440 } 441 442 *skb = pipe->dest_ring->skb[sw_index]; 443 pipe->dest_ring->skb[sw_index] = NULL; 444 445 sw_index = CE_RING_IDX_INCR(nentries_mask, sw_index); 446 pipe->dest_ring->sw_index = sw_index; 447 448 pipe->rx_buf_needed++; 449 err: 450 ath12k_hal_srng_access_end(ab, srng); 451 452 spin_unlock_bh(&srng->lock); 453 454 spin_unlock_bh(&ab->ce.ce_lock); 455 456 return ret; 457 } 458 459 static void ath12k_ce_recv_process_cb(struct ath12k_ce_pipe *pipe) 460 { 461 struct ath12k_base *ab = pipe->ab; 462 struct sk_buff *skb; 463 struct sk_buff_head list; 464 unsigned int nbytes, max_nbytes; 465 int ret; 466 467 __skb_queue_head_init(&list); 468 while (ath12k_ce_completed_recv_next(pipe, &skb, &nbytes) == 0) { 469 max_nbytes = skb->len + skb_tailroom(skb); 470 dma_unmap_single(ab->dev, ATH12K_SKB_RXCB(skb)->paddr, 471 max_nbytes, DMA_FROM_DEVICE); 472 473 if (unlikely(max_nbytes < nbytes)) { 474 ath12k_warn(ab, "rxed more than expected (nbytes %d, max %d)", 475 nbytes, max_nbytes); 476 dev_kfree_skb_any(skb); 477 continue; 478 } 479 480 skb_put(skb, nbytes); 481 __skb_queue_tail(&list, skb); 482 } 483 484 while ((skb = __skb_dequeue(&list))) { 485 ath12k_dbg(ab, ATH12K_DBG_AHB, "rx ce pipe %d len %d\n", 486 pipe->pipe_num, skb->len); 487 pipe->recv_cb(ab, skb); 488 } 489 490 ret = ath12k_ce_rx_post_pipe(pipe); 491 if (ret && ret != -ENOSPC) { 492 ath12k_warn(ab, "failed to post rx buf to pipe: %d err: %d\n", 493 pipe->pipe_num, ret); 494 mod_timer(&ab->rx_replenish_retry, 495 jiffies + ATH12K_CE_RX_POST_RETRY_JIFFIES); 496 } 497 } 498 499 static struct sk_buff *ath12k_ce_completed_send_next(struct ath12k_ce_pipe *pipe) 500 { 501 struct ath12k_base *ab = pipe->ab; 502 struct hal_ce_srng_src_desc *desc; 503 struct hal_srng *srng; 504 unsigned int sw_index; 505 unsigned int nentries_mask; 506 struct sk_buff *skb; 507 508 spin_lock_bh(&ab->ce.ce_lock); 509 510 sw_index = pipe->src_ring->sw_index; 511 nentries_mask = pipe->src_ring->nentries_mask; 512 513 srng = &ab->hal.srng_list[pipe->src_ring->hal_ring_id]; 514 515 spin_lock_bh(&srng->lock); 516 517 ath12k_hal_srng_access_begin(ab, srng); 518 519 desc = ath12k_hal_srng_src_reap_next(ab, srng); 520 if (!desc) { 521 skb = ERR_PTR(-EIO); 522 goto err_unlock; 523 } 524 525 skb = pipe->src_ring->skb[sw_index]; 526 527 pipe->src_ring->skb[sw_index] = NULL; 528 529 sw_index = CE_RING_IDX_INCR(nentries_mask, sw_index); 530 pipe->src_ring->sw_index = sw_index; 531 532 err_unlock: 533 spin_unlock_bh(&srng->lock); 534 535 spin_unlock_bh(&ab->ce.ce_lock); 536 537 return skb; 538 } 539 540 static void ath12k_ce_send_done_cb(struct ath12k_ce_pipe *pipe) 541 { 542 struct ath12k_base *ab = pipe->ab; 543 struct sk_buff *skb; 544 545 while (!IS_ERR(skb = ath12k_ce_completed_send_next(pipe))) { 546 if (!skb) 547 continue; 548 549 dma_unmap_single(ab->dev, ATH12K_SKB_CB(skb)->paddr, skb->len, 550 DMA_TO_DEVICE); 551 dev_kfree_skb_any(skb); 552 } 553 } 554 555 static void ath12k_ce_srng_msi_ring_params_setup(struct ath12k_base *ab, u32 ce_id, 556 struct hal_srng_params *ring_params) 557 { 558 u32 msi_data_start; 559 u32 msi_data_count, msi_data_idx; 560 u32 msi_irq_start; 561 u32 addr_lo; 562 u32 addr_hi; 563 int ret; 564 565 ret = ath12k_hif_get_user_msi_vector(ab, "CE", 566 &msi_data_count, &msi_data_start, 567 &msi_irq_start); 568 569 if (ret) 570 return; 571 572 ath12k_hif_get_msi_address(ab, &addr_lo, &addr_hi); 573 ath12k_hif_get_ce_msi_idx(ab, ce_id, &msi_data_idx); 574 575 ring_params->msi_addr = addr_lo; 576 ring_params->msi_addr |= (dma_addr_t)(((uint64_t)addr_hi) << 32); 577 ring_params->msi_data = (msi_data_idx % msi_data_count) + msi_data_start; 578 ring_params->flags |= HAL_SRNG_FLAGS_MSI_INTR; 579 } 580 581 static int ath12k_ce_init_ring(struct ath12k_base *ab, 582 struct ath12k_ce_ring *ce_ring, 583 int ce_id, enum hal_ring_type type) 584 { 585 struct hal_srng_params params = { 0 }; 586 int ret; 587 588 params.ring_base_paddr = ce_ring->base_addr_ce_space; 589 params.ring_base_vaddr = ce_ring->base_addr_owner_space; 590 params.num_entries = ce_ring->nentries; 591 592 if (!(CE_ATTR_DIS_INTR & ab->hw_params->host_ce_config[ce_id].flags)) 593 ath12k_ce_srng_msi_ring_params_setup(ab, ce_id, ¶ms); 594 595 switch (type) { 596 case HAL_CE_SRC: 597 if (!(CE_ATTR_DIS_INTR & ab->hw_params->host_ce_config[ce_id].flags)) 598 params.intr_batch_cntr_thres_entries = 1; 599 break; 600 case HAL_CE_DST: 601 params.max_buffer_len = ab->hw_params->host_ce_config[ce_id].src_sz_max; 602 if (!(ab->hw_params->host_ce_config[ce_id].flags & CE_ATTR_DIS_INTR)) { 603 params.intr_timer_thres_us = 1024; 604 params.flags |= HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN; 605 params.low_threshold = ce_ring->nentries - 3; 606 } 607 break; 608 case HAL_CE_DST_STATUS: 609 if (!(ab->hw_params->host_ce_config[ce_id].flags & CE_ATTR_DIS_INTR)) { 610 params.intr_batch_cntr_thres_entries = 1; 611 params.intr_timer_thres_us = 0x1000; 612 } 613 break; 614 default: 615 ath12k_warn(ab, "Invalid CE ring type %d\n", type); 616 return -EINVAL; 617 } 618 619 /* TODO: Init other params needed by HAL to init the ring */ 620 621 ret = ath12k_hal_srng_setup(ab, type, ce_id, 0, ¶ms); 622 if (ret < 0) { 623 ath12k_warn(ab, "failed to setup srng: %d ring_id %d\n", 624 ret, ce_id); 625 return ret; 626 } 627 628 ce_ring->hal_ring_id = ret; 629 630 return 0; 631 } 632 633 static struct ath12k_ce_ring * 634 ath12k_ce_alloc_ring(struct ath12k_base *ab, int nentries, int desc_sz) 635 { 636 struct ath12k_ce_ring *ce_ring; 637 dma_addr_t base_addr; 638 639 ce_ring = kzalloc(struct_size(ce_ring, skb, nentries), GFP_KERNEL); 640 if (!ce_ring) 641 return ERR_PTR(-ENOMEM); 642 643 ce_ring->nentries = nentries; 644 ce_ring->nentries_mask = nentries - 1; 645 646 /* Legacy platforms that do not support cache 647 * coherent DMA are unsupported 648 */ 649 ce_ring->base_addr_owner_space_unaligned = 650 dma_alloc_coherent(ab->dev, 651 nentries * desc_sz + CE_DESC_RING_ALIGN, 652 &base_addr, GFP_KERNEL); 653 if (!ce_ring->base_addr_owner_space_unaligned) { 654 kfree(ce_ring); 655 return ERR_PTR(-ENOMEM); 656 } 657 658 ce_ring->base_addr_ce_space_unaligned = base_addr; 659 660 ce_ring->base_addr_owner_space = 661 PTR_ALIGN(ce_ring->base_addr_owner_space_unaligned, 662 CE_DESC_RING_ALIGN); 663 664 ce_ring->base_addr_ce_space = ALIGN(ce_ring->base_addr_ce_space_unaligned, 665 CE_DESC_RING_ALIGN); 666 667 return ce_ring; 668 } 669 670 static int ath12k_ce_alloc_pipe(struct ath12k_base *ab, int ce_id) 671 { 672 struct ath12k_ce_pipe *pipe = &ab->ce.ce_pipe[ce_id]; 673 const struct ce_attr *attr = &ab->hw_params->host_ce_config[ce_id]; 674 struct ath12k_ce_ring *ring; 675 int nentries; 676 int desc_sz; 677 678 pipe->attr_flags = attr->flags; 679 680 if (attr->src_nentries) { 681 pipe->send_cb = ath12k_ce_send_done_cb; 682 nentries = roundup_pow_of_two(attr->src_nentries); 683 desc_sz = ath12k_hal_ce_get_desc_size(HAL_CE_DESC_SRC); 684 ring = ath12k_ce_alloc_ring(ab, nentries, desc_sz); 685 if (IS_ERR(ring)) 686 return PTR_ERR(ring); 687 pipe->src_ring = ring; 688 } 689 690 if (attr->dest_nentries) { 691 pipe->recv_cb = attr->recv_cb; 692 nentries = roundup_pow_of_two(attr->dest_nentries); 693 desc_sz = ath12k_hal_ce_get_desc_size(HAL_CE_DESC_DST); 694 ring = ath12k_ce_alloc_ring(ab, nentries, desc_sz); 695 if (IS_ERR(ring)) 696 return PTR_ERR(ring); 697 pipe->dest_ring = ring; 698 699 desc_sz = ath12k_hal_ce_get_desc_size(HAL_CE_DESC_DST_STATUS); 700 ring = ath12k_ce_alloc_ring(ab, nentries, desc_sz); 701 if (IS_ERR(ring)) 702 return PTR_ERR(ring); 703 pipe->status_ring = ring; 704 } 705 706 return 0; 707 } 708 709 void ath12k_ce_per_engine_service(struct ath12k_base *ab, u16 ce_id) 710 { 711 struct ath12k_ce_pipe *pipe = &ab->ce.ce_pipe[ce_id]; 712 713 if (pipe->send_cb) 714 pipe->send_cb(pipe); 715 716 if (pipe->recv_cb) 717 ath12k_ce_recv_process_cb(pipe); 718 } 719 720 void ath12k_ce_poll_send_completed(struct ath12k_base *ab, u8 pipe_id) 721 { 722 struct ath12k_ce_pipe *pipe = &ab->ce.ce_pipe[pipe_id]; 723 724 if ((pipe->attr_flags & CE_ATTR_DIS_INTR) && pipe->send_cb) 725 pipe->send_cb(pipe); 726 } 727 728 int ath12k_ce_send(struct ath12k_base *ab, struct sk_buff *skb, u8 pipe_id, 729 u16 transfer_id) 730 { 731 struct ath12k_ce_pipe *pipe = &ab->ce.ce_pipe[pipe_id]; 732 struct hal_ce_srng_src_desc *desc; 733 struct hal_srng *srng; 734 unsigned int write_index, sw_index; 735 unsigned int nentries_mask; 736 int ret = 0; 737 u8 byte_swap_data = 0; 738 int num_used; 739 740 /* Check if some entries could be regained by handling tx completion if 741 * the CE has interrupts disabled and the used entries is more than the 742 * defined usage threshold. 743 */ 744 if (pipe->attr_flags & CE_ATTR_DIS_INTR) { 745 spin_lock_bh(&ab->ce.ce_lock); 746 write_index = pipe->src_ring->write_index; 747 748 sw_index = pipe->src_ring->sw_index; 749 750 if (write_index >= sw_index) 751 num_used = write_index - sw_index; 752 else 753 num_used = pipe->src_ring->nentries - sw_index + 754 write_index; 755 756 spin_unlock_bh(&ab->ce.ce_lock); 757 758 if (num_used > ATH12K_CE_USAGE_THRESHOLD) 759 ath12k_ce_poll_send_completed(ab, pipe->pipe_num); 760 } 761 762 if (test_bit(ATH12K_FLAG_CRASH_FLUSH, &ab->dev_flags)) 763 return -ESHUTDOWN; 764 765 spin_lock_bh(&ab->ce.ce_lock); 766 767 write_index = pipe->src_ring->write_index; 768 nentries_mask = pipe->src_ring->nentries_mask; 769 770 srng = &ab->hal.srng_list[pipe->src_ring->hal_ring_id]; 771 772 spin_lock_bh(&srng->lock); 773 774 ath12k_hal_srng_access_begin(ab, srng); 775 776 if (unlikely(ath12k_hal_srng_src_num_free(ab, srng, false) < 1)) { 777 ath12k_hal_srng_access_end(ab, srng); 778 ret = -ENOBUFS; 779 goto unlock; 780 } 781 782 desc = ath12k_hal_srng_src_get_next_reaped(ab, srng); 783 if (!desc) { 784 ath12k_hal_srng_access_end(ab, srng); 785 ret = -ENOBUFS; 786 goto unlock; 787 } 788 789 if (pipe->attr_flags & CE_ATTR_BYTE_SWAP_DATA) 790 byte_swap_data = 1; 791 792 ath12k_hal_ce_src_set_desc(desc, ATH12K_SKB_CB(skb)->paddr, 793 skb->len, transfer_id, byte_swap_data); 794 795 pipe->src_ring->skb[write_index] = skb; 796 pipe->src_ring->write_index = CE_RING_IDX_INCR(nentries_mask, 797 write_index); 798 799 ath12k_hal_srng_access_end(ab, srng); 800 801 unlock: 802 spin_unlock_bh(&srng->lock); 803 804 spin_unlock_bh(&ab->ce.ce_lock); 805 806 return ret; 807 } 808 809 static void ath12k_ce_rx_pipe_cleanup(struct ath12k_ce_pipe *pipe) 810 { 811 struct ath12k_base *ab = pipe->ab; 812 struct ath12k_ce_ring *ring = pipe->dest_ring; 813 struct sk_buff *skb; 814 int i; 815 816 if (!(ring && pipe->buf_sz)) 817 return; 818 819 for (i = 0; i < ring->nentries; i++) { 820 skb = ring->skb[i]; 821 if (!skb) 822 continue; 823 824 ring->skb[i] = NULL; 825 dma_unmap_single(ab->dev, ATH12K_SKB_RXCB(skb)->paddr, 826 skb->len + skb_tailroom(skb), DMA_FROM_DEVICE); 827 dev_kfree_skb_any(skb); 828 } 829 } 830 831 void ath12k_ce_cleanup_pipes(struct ath12k_base *ab) 832 { 833 struct ath12k_ce_pipe *pipe; 834 int pipe_num; 835 836 for (pipe_num = 0; pipe_num < ab->hw_params->ce_count; pipe_num++) { 837 pipe = &ab->ce.ce_pipe[pipe_num]; 838 ath12k_ce_rx_pipe_cleanup(pipe); 839 840 /* Cleanup any src CE's which have interrupts disabled */ 841 ath12k_ce_poll_send_completed(ab, pipe_num); 842 843 /* NOTE: Should we also clean up tx buffer in all pipes? */ 844 } 845 } 846 847 void ath12k_ce_rx_post_buf(struct ath12k_base *ab) 848 { 849 struct ath12k_ce_pipe *pipe; 850 int i; 851 int ret; 852 853 for (i = 0; i < ab->hw_params->ce_count; i++) { 854 pipe = &ab->ce.ce_pipe[i]; 855 ret = ath12k_ce_rx_post_pipe(pipe); 856 if (ret) { 857 if (ret == -ENOSPC) 858 continue; 859 860 ath12k_warn(ab, "failed to post rx buf to pipe: %d err: %d\n", 861 i, ret); 862 mod_timer(&ab->rx_replenish_retry, 863 jiffies + ATH12K_CE_RX_POST_RETRY_JIFFIES); 864 865 return; 866 } 867 } 868 } 869 870 void ath12k_ce_rx_replenish_retry(struct timer_list *t) 871 { 872 struct ath12k_base *ab = from_timer(ab, t, rx_replenish_retry); 873 874 ath12k_ce_rx_post_buf(ab); 875 } 876 877 static void ath12k_ce_shadow_config(struct ath12k_base *ab) 878 { 879 int i; 880 881 for (i = 0; i < ab->hw_params->ce_count; i++) { 882 if (ab->hw_params->host_ce_config[i].src_nentries) 883 ath12k_hal_srng_update_shadow_config(ab, HAL_CE_SRC, i); 884 885 if (ab->hw_params->host_ce_config[i].dest_nentries) { 886 ath12k_hal_srng_update_shadow_config(ab, HAL_CE_DST, i); 887 ath12k_hal_srng_update_shadow_config(ab, HAL_CE_DST_STATUS, i); 888 } 889 } 890 } 891 892 void ath12k_ce_get_shadow_config(struct ath12k_base *ab, 893 u32 **shadow_cfg, u32 *shadow_cfg_len) 894 { 895 if (!ab->hw_params->supports_shadow_regs) 896 return; 897 898 ath12k_hal_srng_get_shadow_config(ab, shadow_cfg, shadow_cfg_len); 899 900 /* shadow is already configured */ 901 if (*shadow_cfg_len) 902 return; 903 904 /* shadow isn't configured yet, configure now. 905 * non-CE srngs are configured firstly, then 906 * all CE srngs. 907 */ 908 ath12k_hal_srng_shadow_config(ab); 909 ath12k_ce_shadow_config(ab); 910 911 /* get the shadow configuration */ 912 ath12k_hal_srng_get_shadow_config(ab, shadow_cfg, shadow_cfg_len); 913 } 914 915 int ath12k_ce_init_pipes(struct ath12k_base *ab) 916 { 917 struct ath12k_ce_pipe *pipe; 918 int i; 919 int ret; 920 921 ath12k_ce_get_shadow_config(ab, &ab->qmi.ce_cfg.shadow_reg_v3, 922 &ab->qmi.ce_cfg.shadow_reg_v3_len); 923 924 for (i = 0; i < ab->hw_params->ce_count; i++) { 925 pipe = &ab->ce.ce_pipe[i]; 926 927 if (pipe->src_ring) { 928 ret = ath12k_ce_init_ring(ab, pipe->src_ring, i, 929 HAL_CE_SRC); 930 if (ret) { 931 ath12k_warn(ab, "failed to init src ring: %d\n", 932 ret); 933 /* Should we clear any partial init */ 934 return ret; 935 } 936 937 pipe->src_ring->write_index = 0; 938 pipe->src_ring->sw_index = 0; 939 } 940 941 if (pipe->dest_ring) { 942 ret = ath12k_ce_init_ring(ab, pipe->dest_ring, i, 943 HAL_CE_DST); 944 if (ret) { 945 ath12k_warn(ab, "failed to init dest ring: %d\n", 946 ret); 947 /* Should we clear any partial init */ 948 return ret; 949 } 950 951 pipe->rx_buf_needed = pipe->dest_ring->nentries ? 952 pipe->dest_ring->nentries - 2 : 0; 953 954 pipe->dest_ring->write_index = 0; 955 pipe->dest_ring->sw_index = 0; 956 } 957 958 if (pipe->status_ring) { 959 ret = ath12k_ce_init_ring(ab, pipe->status_ring, i, 960 HAL_CE_DST_STATUS); 961 if (ret) { 962 ath12k_warn(ab, "failed to init dest status ing: %d\n", 963 ret); 964 /* Should we clear any partial init */ 965 return ret; 966 } 967 968 pipe->status_ring->write_index = 0; 969 pipe->status_ring->sw_index = 0; 970 } 971 } 972 973 return 0; 974 } 975 976 void ath12k_ce_free_pipes(struct ath12k_base *ab) 977 { 978 struct ath12k_ce_pipe *pipe; 979 int desc_sz; 980 int i; 981 982 for (i = 0; i < ab->hw_params->ce_count; i++) { 983 pipe = &ab->ce.ce_pipe[i]; 984 985 if (pipe->src_ring) { 986 desc_sz = ath12k_hal_ce_get_desc_size(HAL_CE_DESC_SRC); 987 dma_free_coherent(ab->dev, 988 pipe->src_ring->nentries * desc_sz + 989 CE_DESC_RING_ALIGN, 990 pipe->src_ring->base_addr_owner_space, 991 pipe->src_ring->base_addr_ce_space); 992 kfree(pipe->src_ring); 993 pipe->src_ring = NULL; 994 } 995 996 if (pipe->dest_ring) { 997 desc_sz = ath12k_hal_ce_get_desc_size(HAL_CE_DESC_DST); 998 dma_free_coherent(ab->dev, 999 pipe->dest_ring->nentries * desc_sz + 1000 CE_DESC_RING_ALIGN, 1001 pipe->dest_ring->base_addr_owner_space, 1002 pipe->dest_ring->base_addr_ce_space); 1003 kfree(pipe->dest_ring); 1004 pipe->dest_ring = NULL; 1005 } 1006 1007 if (pipe->status_ring) { 1008 desc_sz = 1009 ath12k_hal_ce_get_desc_size(HAL_CE_DESC_DST_STATUS); 1010 dma_free_coherent(ab->dev, 1011 pipe->status_ring->nentries * desc_sz + 1012 CE_DESC_RING_ALIGN, 1013 pipe->status_ring->base_addr_owner_space, 1014 pipe->status_ring->base_addr_ce_space); 1015 kfree(pipe->status_ring); 1016 pipe->status_ring = NULL; 1017 } 1018 } 1019 } 1020 1021 int ath12k_ce_alloc_pipes(struct ath12k_base *ab) 1022 { 1023 struct ath12k_ce_pipe *pipe; 1024 int i; 1025 int ret; 1026 const struct ce_attr *attr; 1027 1028 spin_lock_init(&ab->ce.ce_lock); 1029 1030 for (i = 0; i < ab->hw_params->ce_count; i++) { 1031 attr = &ab->hw_params->host_ce_config[i]; 1032 pipe = &ab->ce.ce_pipe[i]; 1033 pipe->pipe_num = i; 1034 pipe->ab = ab; 1035 pipe->buf_sz = attr->src_sz_max; 1036 1037 ret = ath12k_ce_alloc_pipe(ab, i); 1038 if (ret) { 1039 /* Free any partial successful allocation */ 1040 ath12k_ce_free_pipes(ab); 1041 return ret; 1042 } 1043 } 1044 1045 return 0; 1046 } 1047 1048 int ath12k_ce_get_attr_flags(struct ath12k_base *ab, int ce_id) 1049 { 1050 if (ce_id >= ab->hw_params->ce_count) 1051 return -EINVAL; 1052 1053 return ab->hw_params->host_ce_config[ce_id].flags; 1054 } 1055