1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef ATH11K_QMI_H 8 #define ATH11K_QMI_H 9 10 #include <linux/mutex.h> 11 #include <linux/soc/qcom/qmi.h> 12 13 #define ATH11K_HOST_VERSION_STRING "WIN" 14 #define ATH11K_QMI_WLANFW_TIMEOUT_MS 10000 15 #define ATH11K_QMI_MAX_BDF_FILE_NAME_SIZE 64 16 #define ATH11K_QMI_CALDB_ADDRESS 0x4BA00000 17 #define ATH11K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 128 18 #define ATH11K_QMI_WLFW_SERVICE_ID_V01 0x45 19 #define ATH11K_QMI_WLFW_SERVICE_VERS_V01 0x01 20 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01 0x02 21 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390 0x01 22 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074 0x02 23 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9074 0x07 24 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_WCN6750 0x03 25 #define ATH11K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 32 26 #define ATH11K_QMI_RESP_LEN_MAX 8192 27 #define ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01 52 28 #define ATH11K_QMI_CALDB_SIZE 0x480000 29 #define ATH11K_QMI_BDF_EXT_STR_LENGTH 0x20 30 #define ATH11K_QMI_FW_MEM_REQ_SEGMENT_CNT 3 31 32 #define QMI_WLFW_REQUEST_MEM_IND_V01 0x0035 33 #define QMI_WLFW_FW_MEM_READY_IND_V01 0x0037 34 #define QMI_WLFW_COLD_BOOT_CAL_DONE_IND_V01 0x0021 35 #define QMI_WLFW_FW_READY_IND_V01 0x0038 36 37 #define QMI_WLANFW_MAX_DATA_SIZE_V01 6144 38 #define ATH11K_FIRMWARE_MODE_OFF 4 39 #define ATH11K_COLD_BOOT_FW_RESET_DELAY (40 * HZ) 40 41 #define ATH11K_QMI_DEVICE_BAR_SIZE 0x200000 42 43 struct ath11k_base; 44 45 enum ath11k_qmi_file_type { 46 ATH11K_QMI_FILE_TYPE_BDF_GOLDEN, 47 ATH11K_QMI_FILE_TYPE_CALDATA = 2, 48 ATH11K_QMI_FILE_TYPE_EEPROM, 49 ATH11K_QMI_MAX_FILE_TYPE, 50 }; 51 52 enum ath11k_qmi_bdf_type { 53 ATH11K_QMI_BDF_TYPE_BIN = 0, 54 ATH11K_QMI_BDF_TYPE_ELF = 1, 55 ATH11K_QMI_BDF_TYPE_REGDB = 4, 56 }; 57 58 enum ath11k_qmi_event_type { 59 ATH11K_QMI_EVENT_SERVER_ARRIVE, 60 ATH11K_QMI_EVENT_SERVER_EXIT, 61 ATH11K_QMI_EVENT_REQUEST_MEM, 62 ATH11K_QMI_EVENT_FW_MEM_READY, 63 ATH11K_QMI_EVENT_FW_READY, 64 ATH11K_QMI_EVENT_COLD_BOOT_CAL_START, 65 ATH11K_QMI_EVENT_COLD_BOOT_CAL_DONE, 66 ATH11K_QMI_EVENT_REGISTER_DRIVER, 67 ATH11K_QMI_EVENT_UNREGISTER_DRIVER, 68 ATH11K_QMI_EVENT_RECOVERY, 69 ATH11K_QMI_EVENT_FORCE_FW_ASSERT, 70 ATH11K_QMI_EVENT_POWER_UP, 71 ATH11K_QMI_EVENT_POWER_DOWN, 72 ATH11K_QMI_EVENT_MAX, 73 }; 74 75 struct ath11k_qmi_driver_event { 76 struct list_head list; 77 enum ath11k_qmi_event_type type; 78 void *data; 79 }; 80 81 struct ath11k_qmi_ce_cfg { 82 const struct ce_pipe_config *tgt_ce; 83 int tgt_ce_len; 84 const struct service_to_pipe *svc_to_ce_map; 85 int svc_to_ce_map_len; 86 const u8 *shadow_reg; 87 int shadow_reg_len; 88 u32 *shadow_reg_v2; 89 int shadow_reg_v2_len; 90 }; 91 92 struct ath11k_qmi_event_msg { 93 struct list_head list; 94 enum ath11k_qmi_event_type type; 95 }; 96 97 struct target_mem_chunk { 98 u32 size; 99 u32 type; 100 dma_addr_t paddr; 101 u32 *vaddr; 102 void __iomem *iaddr; 103 }; 104 105 struct target_info { 106 u32 chip_id; 107 u32 chip_family; 108 u32 board_id; 109 u32 soc_id; 110 u32 fw_version; 111 u32 eeprom_caldata; 112 char fw_build_timestamp[ATH11K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1]; 113 char fw_build_id[ATH11K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1]; 114 char bdf_ext[ATH11K_QMI_BDF_EXT_STR_LENGTH]; 115 }; 116 117 struct m3_mem_region { 118 u32 size; 119 dma_addr_t paddr; 120 void *vaddr; 121 }; 122 123 struct ath11k_qmi { 124 struct ath11k_base *ab; 125 struct qmi_handle handle; 126 struct sockaddr_qrtr sq; 127 struct work_struct event_work; 128 struct workqueue_struct *event_wq; 129 struct list_head event_list; 130 spinlock_t event_lock; /* spinlock for qmi event list */ 131 struct ath11k_qmi_ce_cfg ce_cfg; 132 struct target_mem_chunk target_mem[ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 133 u32 mem_seg_count; 134 u32 target_mem_mode; 135 bool target_mem_delayed; 136 u8 cal_done; 137 struct target_info target; 138 struct m3_mem_region m3_mem; 139 unsigned int service_ins_id; 140 wait_queue_head_t cold_boot_waitq; 141 }; 142 143 #define QMI_WLANFW_HOST_CAP_REQ_MSG_V01_MAX_LEN 261 144 #define QMI_WLANFW_HOST_CAP_REQ_V01 0x0034 145 #define QMI_WLANFW_HOST_CAP_RESP_MSG_V01_MAX_LEN 7 146 #define QMI_WLFW_HOST_CAP_RESP_V01 0x0034 147 #define QMI_WLFW_MAX_NUM_GPIO_V01 32 148 #define QMI_IPQ8074_FW_MEM_MODE 0xFF 149 #define HOST_DDR_REGION_TYPE 0x1 150 #define BDF_MEM_REGION_TYPE 0x2 151 #define M3_DUMP_REGION_TYPE 0x3 152 #define CALDB_MEM_REGION_TYPE 0x4 153 154 struct qmi_wlanfw_host_cap_req_msg_v01 { 155 u8 num_clients_valid; 156 u32 num_clients; 157 u8 wake_msi_valid; 158 u32 wake_msi; 159 u8 gpios_valid; 160 u32 gpios_len; 161 u32 gpios[QMI_WLFW_MAX_NUM_GPIO_V01]; 162 u8 nm_modem_valid; 163 u8 nm_modem; 164 u8 bdf_support_valid; 165 u8 bdf_support; 166 u8 bdf_cache_support_valid; 167 u8 bdf_cache_support; 168 u8 m3_support_valid; 169 u8 m3_support; 170 u8 m3_cache_support_valid; 171 u8 m3_cache_support; 172 u8 cal_filesys_support_valid; 173 u8 cal_filesys_support; 174 u8 cal_cache_support_valid; 175 u8 cal_cache_support; 176 u8 cal_done_valid; 177 u8 cal_done; 178 u8 mem_bucket_valid; 179 u32 mem_bucket; 180 u8 mem_cfg_mode_valid; 181 u8 mem_cfg_mode; 182 }; 183 184 struct qmi_wlanfw_host_cap_resp_msg_v01 { 185 struct qmi_response_type_v01 resp; 186 }; 187 188 #define QMI_WLANFW_IND_REGISTER_REQ_MSG_V01_MAX_LEN 54 189 #define QMI_WLANFW_IND_REGISTER_REQ_V01 0x0020 190 #define QMI_WLANFW_IND_REGISTER_RESP_MSG_V01_MAX_LEN 18 191 #define QMI_WLANFW_IND_REGISTER_RESP_V01 0x0020 192 #define QMI_WLANFW_CLIENT_ID 0x4b4e454c 193 194 struct qmi_wlanfw_ind_register_req_msg_v01 { 195 u8 fw_ready_enable_valid; 196 u8 fw_ready_enable; 197 u8 initiate_cal_download_enable_valid; 198 u8 initiate_cal_download_enable; 199 u8 initiate_cal_update_enable_valid; 200 u8 initiate_cal_update_enable; 201 u8 msa_ready_enable_valid; 202 u8 msa_ready_enable; 203 u8 pin_connect_result_enable_valid; 204 u8 pin_connect_result_enable; 205 u8 client_id_valid; 206 u32 client_id; 207 u8 request_mem_enable_valid; 208 u8 request_mem_enable; 209 u8 fw_mem_ready_enable_valid; 210 u8 fw_mem_ready_enable; 211 u8 fw_init_done_enable_valid; 212 u8 fw_init_done_enable; 213 u8 rejuvenate_enable_valid; 214 u32 rejuvenate_enable; 215 u8 xo_cal_enable_valid; 216 u8 xo_cal_enable; 217 u8 cal_done_enable_valid; 218 u8 cal_done_enable; 219 }; 220 221 struct qmi_wlanfw_ind_register_resp_msg_v01 { 222 struct qmi_response_type_v01 resp; 223 u8 fw_status_valid; 224 u64 fw_status; 225 }; 226 227 #define QMI_WLANFW_REQUEST_MEM_IND_MSG_V01_MAX_LEN 1824 228 #define QMI_WLANFW_RESPOND_MEM_REQ_MSG_V01_MAX_LEN 888 229 #define QMI_WLANFW_RESPOND_MEM_RESP_MSG_V01_MAX_LEN 7 230 #define QMI_WLANFW_REQUEST_MEM_IND_V01 0x0035 231 #define QMI_WLANFW_RESPOND_MEM_REQ_V01 0x0036 232 #define QMI_WLANFW_RESPOND_MEM_RESP_V01 0x0036 233 #define QMI_WLANFW_MAX_NUM_MEM_CFG_V01 2 234 235 struct qmi_wlanfw_mem_cfg_s_v01 { 236 u64 offset; 237 u32 size; 238 u8 secure_flag; 239 }; 240 241 enum qmi_wlanfw_mem_type_enum_v01 { 242 WLANFW_MEM_TYPE_ENUM_MIN_VAL_V01 = INT_MIN, 243 QMI_WLANFW_MEM_TYPE_MSA_V01 = 0, 244 QMI_WLANFW_MEM_TYPE_DDR_V01 = 1, 245 QMI_WLANFW_MEM_BDF_V01 = 2, 246 QMI_WLANFW_MEM_M3_V01 = 3, 247 QMI_WLANFW_MEM_CAL_V01 = 4, 248 QMI_WLANFW_MEM_DPD_V01 = 5, 249 WLANFW_MEM_TYPE_ENUM_MAX_VAL_V01 = INT_MAX, 250 }; 251 252 struct qmi_wlanfw_mem_seg_s_v01 { 253 u32 size; 254 enum qmi_wlanfw_mem_type_enum_v01 type; 255 u32 mem_cfg_len; 256 struct qmi_wlanfw_mem_cfg_s_v01 mem_cfg[QMI_WLANFW_MAX_NUM_MEM_CFG_V01]; 257 }; 258 259 struct qmi_wlanfw_request_mem_ind_msg_v01 { 260 u32 mem_seg_len; 261 struct qmi_wlanfw_mem_seg_s_v01 mem_seg[ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 262 }; 263 264 struct qmi_wlanfw_mem_seg_resp_s_v01 { 265 u64 addr; 266 u32 size; 267 enum qmi_wlanfw_mem_type_enum_v01 type; 268 u8 restore; 269 }; 270 271 struct qmi_wlanfw_respond_mem_req_msg_v01 { 272 u32 mem_seg_len; 273 struct qmi_wlanfw_mem_seg_resp_s_v01 mem_seg[ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 274 }; 275 276 struct qmi_wlanfw_respond_mem_resp_msg_v01 { 277 struct qmi_response_type_v01 resp; 278 }; 279 280 struct qmi_wlanfw_fw_mem_ready_ind_msg_v01 { 281 char placeholder; 282 }; 283 284 struct qmi_wlanfw_fw_ready_ind_msg_v01 { 285 char placeholder; 286 }; 287 288 struct qmi_wlanfw_fw_cold_cal_done_ind_msg_v01 { 289 char placeholder; 290 }; 291 292 #define QMI_WLANFW_CAP_REQ_MSG_V01_MAX_LEN 0 293 #define QMI_WLANFW_CAP_RESP_MSG_V01_MAX_LEN 235 294 #define QMI_WLANFW_CAP_REQ_V01 0x0024 295 #define QMI_WLANFW_CAP_RESP_V01 0x0024 296 #define QMI_WLANFW_DEVICE_INFO_REQ_V01 0x004C 297 #define QMI_WLANFW_DEVICE_INFO_REQ_MSG_V01_MAX_LEN 0 298 299 enum qmi_wlanfw_pipedir_enum_v01 { 300 QMI_WLFW_PIPEDIR_NONE_V01 = 0, 301 QMI_WLFW_PIPEDIR_IN_V01 = 1, 302 QMI_WLFW_PIPEDIR_OUT_V01 = 2, 303 QMI_WLFW_PIPEDIR_INOUT_V01 = 3, 304 }; 305 306 struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01 { 307 __le32 pipe_num; 308 __le32 pipe_dir; 309 __le32 nentries; 310 __le32 nbytes_max; 311 __le32 flags; 312 }; 313 314 struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01 { 315 __le32 service_id; 316 __le32 pipe_dir; 317 __le32 pipe_num; 318 }; 319 320 struct qmi_wlanfw_shadow_reg_cfg_s_v01 { 321 u16 id; 322 u16 offset; 323 }; 324 325 struct qmi_wlanfw_shadow_reg_v2_cfg_s_v01 { 326 u32 addr; 327 }; 328 329 struct qmi_wlanfw_memory_region_info_s_v01 { 330 u64 region_addr; 331 u32 size; 332 u8 secure_flag; 333 }; 334 335 struct qmi_wlanfw_rf_chip_info_s_v01 { 336 u32 chip_id; 337 u32 chip_family; 338 }; 339 340 struct qmi_wlanfw_rf_board_info_s_v01 { 341 u32 board_id; 342 }; 343 344 struct qmi_wlanfw_soc_info_s_v01 { 345 u32 soc_id; 346 }; 347 348 struct qmi_wlanfw_fw_version_info_s_v01 { 349 u32 fw_version; 350 char fw_build_timestamp[ATH11K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1]; 351 }; 352 353 enum qmi_wlanfw_cal_temp_id_enum_v01 { 354 QMI_WLANFW_CAL_TEMP_IDX_0_V01 = 0, 355 QMI_WLANFW_CAL_TEMP_IDX_1_V01 = 1, 356 QMI_WLANFW_CAL_TEMP_IDX_2_V01 = 2, 357 QMI_WLANFW_CAL_TEMP_IDX_3_V01 = 3, 358 QMI_WLANFW_CAL_TEMP_IDX_4_V01 = 4, 359 QMI_WLANFW_CAL_TEMP_ID_MAX_V01 = 0xFF, 360 }; 361 362 struct qmi_wlanfw_cap_resp_msg_v01 { 363 struct qmi_response_type_v01 resp; 364 u8 chip_info_valid; 365 struct qmi_wlanfw_rf_chip_info_s_v01 chip_info; 366 u8 board_info_valid; 367 struct qmi_wlanfw_rf_board_info_s_v01 board_info; 368 u8 soc_info_valid; 369 struct qmi_wlanfw_soc_info_s_v01 soc_info; 370 u8 fw_version_info_valid; 371 struct qmi_wlanfw_fw_version_info_s_v01 fw_version_info; 372 u8 fw_build_id_valid; 373 char fw_build_id[ATH11K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1]; 374 u8 num_macs_valid; 375 u8 num_macs; 376 u8 voltage_mv_valid; 377 u32 voltage_mv; 378 u8 time_freq_hz_valid; 379 u32 time_freq_hz; 380 u8 otp_version_valid; 381 u32 otp_version; 382 u8 eeprom_read_timeout_valid; 383 u32 eeprom_read_timeout; 384 }; 385 386 struct qmi_wlanfw_cap_req_msg_v01 { 387 char placeholder; 388 }; 389 390 struct qmi_wlanfw_device_info_req_msg_v01 { 391 char placeholder; 392 }; 393 394 struct qmi_wlanfw_device_info_resp_msg_v01 { 395 struct qmi_response_type_v01 resp; 396 u64 bar_addr; 397 u32 bar_size; 398 u8 bar_addr_valid; 399 u8 bar_size_valid; 400 }; 401 402 #define QMI_WLANFW_BDF_DOWNLOAD_REQ_MSG_V01_MAX_LEN 6182 403 #define QMI_WLANFW_BDF_DOWNLOAD_RESP_MSG_V01_MAX_LEN 7 404 #define QMI_WLANFW_BDF_DOWNLOAD_RESP_V01 0x0025 405 #define QMI_WLANFW_BDF_DOWNLOAD_REQ_V01 0x0025 406 /* TODO: Need to check with MCL and FW team that data can be pointer and 407 * can be last element in structure 408 */ 409 struct qmi_wlanfw_bdf_download_req_msg_v01 { 410 u8 valid; 411 u8 file_id_valid; 412 enum qmi_wlanfw_cal_temp_id_enum_v01 file_id; 413 u8 total_size_valid; 414 u32 total_size; 415 u8 seg_id_valid; 416 u32 seg_id; 417 u8 data_valid; 418 u32 data_len; 419 u8 data[QMI_WLANFW_MAX_DATA_SIZE_V01]; 420 u8 end_valid; 421 u8 end; 422 u8 bdf_type_valid; 423 u8 bdf_type; 424 425 }; 426 427 struct qmi_wlanfw_bdf_download_resp_msg_v01 { 428 struct qmi_response_type_v01 resp; 429 }; 430 431 #define QMI_WLANFW_M3_INFO_REQ_MSG_V01_MAX_MSG_LEN 18 432 #define QMI_WLANFW_M3_INFO_RESP_MSG_V01_MAX_MSG_LEN 7 433 #define QMI_WLANFW_M3_INFO_RESP_V01 0x003C 434 #define QMI_WLANFW_M3_INFO_REQ_V01 0x003C 435 436 struct qmi_wlanfw_m3_info_req_msg_v01 { 437 u64 addr; 438 u32 size; 439 }; 440 441 struct qmi_wlanfw_m3_info_resp_msg_v01 { 442 struct qmi_response_type_v01 resp; 443 }; 444 445 #define QMI_WLANFW_WLAN_MODE_REQ_MSG_V01_MAX_LEN 11 446 #define QMI_WLANFW_WLAN_MODE_RESP_MSG_V01_MAX_LEN 7 447 #define QMI_WLANFW_WLAN_CFG_REQ_MSG_V01_MAX_LEN 803 448 #define QMI_WLANFW_WLAN_CFG_RESP_MSG_V01_MAX_LEN 7 449 #define QMI_WLANFW_WLAN_INI_REQ_MSG_V01_MAX_LEN 4 450 #define QMI_WLANFW_WLAN_MODE_REQ_V01 0x0022 451 #define QMI_WLANFW_WLAN_MODE_RESP_V01 0x0022 452 #define QMI_WLANFW_WLAN_CFG_REQ_V01 0x0023 453 #define QMI_WLANFW_WLAN_CFG_RESP_V01 0x0023 454 #define QMI_WLANFW_WLAN_INI_REQ_V01 0x002F 455 #define QMI_WLANFW_MAX_STR_LEN_V01 16 456 #define QMI_WLANFW_MAX_NUM_CE_V01 12 457 #define QMI_WLANFW_MAX_NUM_SVC_V01 24 458 #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V01 24 459 #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V2_V01 36 460 461 struct qmi_wlanfw_wlan_mode_req_msg_v01 { 462 u32 mode; 463 u8 hw_debug_valid; 464 u8 hw_debug; 465 }; 466 467 struct qmi_wlanfw_wlan_mode_resp_msg_v01 { 468 struct qmi_response_type_v01 resp; 469 }; 470 471 struct qmi_wlanfw_wlan_cfg_req_msg_v01 { 472 u8 host_version_valid; 473 char host_version[QMI_WLANFW_MAX_STR_LEN_V01 + 1]; 474 u8 tgt_cfg_valid; 475 u32 tgt_cfg_len; 476 struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01 477 tgt_cfg[QMI_WLANFW_MAX_NUM_CE_V01]; 478 u8 svc_cfg_valid; 479 u32 svc_cfg_len; 480 struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01 481 svc_cfg[QMI_WLANFW_MAX_NUM_SVC_V01]; 482 u8 shadow_reg_valid; 483 u32 shadow_reg_len; 484 struct qmi_wlanfw_shadow_reg_cfg_s_v01 485 shadow_reg[QMI_WLANFW_MAX_NUM_SHADOW_REG_V01]; 486 u8 shadow_reg_v2_valid; 487 u32 shadow_reg_v2_len; 488 struct qmi_wlanfw_shadow_reg_v2_cfg_s_v01 489 shadow_reg_v2[QMI_WLANFW_MAX_NUM_SHADOW_REG_V2_V01]; 490 }; 491 492 struct qmi_wlanfw_wlan_cfg_resp_msg_v01 { 493 struct qmi_response_type_v01 resp; 494 }; 495 496 struct qmi_wlanfw_wlan_ini_req_msg_v01 { 497 /* Must be set to true if enablefwlog is being passed */ 498 u8 enablefwlog_valid; 499 u8 enablefwlog; 500 }; 501 502 struct qmi_wlanfw_wlan_ini_resp_msg_v01 { 503 struct qmi_response_type_v01 resp; 504 }; 505 506 int ath11k_qmi_firmware_start(struct ath11k_base *ab, 507 u32 mode); 508 void ath11k_qmi_firmware_stop(struct ath11k_base *ab); 509 void ath11k_qmi_event_work(struct work_struct *work); 510 void ath11k_qmi_msg_recv_work(struct work_struct *work); 511 void ath11k_qmi_deinit_service(struct ath11k_base *ab); 512 int ath11k_qmi_init_service(struct ath11k_base *ab); 513 void ath11k_qmi_free_resource(struct ath11k_base *ab); 514 515 #endif 516