1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef ATH11K_QMI_H 7 #define ATH11K_QMI_H 8 9 #include <linux/mutex.h> 10 #include <linux/soc/qcom/qmi.h> 11 12 #define ATH11K_HOST_VERSION_STRING "WIN" 13 #define ATH11K_QMI_WLANFW_TIMEOUT_MS 10000 14 #define ATH11K_QMI_MAX_BDF_FILE_NAME_SIZE 64 15 #define ATH11K_QMI_CALDB_ADDRESS 0x4BA00000 16 #define ATH11K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 128 17 #define ATH11K_QMI_WLFW_SERVICE_ID_V01 0x45 18 #define ATH11K_QMI_WLFW_SERVICE_VERS_V01 0x01 19 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01 0x02 20 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390 0x01 21 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074 0x02 22 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9074 0x07 23 #define ATH11K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 32 24 #define ATH11K_QMI_RESP_LEN_MAX 8192 25 #define ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01 52 26 #define ATH11K_QMI_CALDB_SIZE 0x480000 27 #define ATH11K_QMI_BDF_EXT_STR_LENGTH 0x20 28 #define ATH11K_QMI_FW_MEM_REQ_SEGMENT_CNT 3 29 30 #define QMI_WLFW_REQUEST_MEM_IND_V01 0x0035 31 #define QMI_WLFW_FW_MEM_READY_IND_V01 0x0037 32 #define QMI_WLFW_COLD_BOOT_CAL_DONE_IND_V01 0x0021 33 #define QMI_WLFW_FW_READY_IND_V01 0x0038 34 35 #define QMI_WLANFW_MAX_DATA_SIZE_V01 6144 36 #define ATH11K_FIRMWARE_MODE_OFF 4 37 #define ATH11K_COLD_BOOT_FW_RESET_DELAY (40 * HZ) 38 39 struct ath11k_base; 40 41 enum ath11k_qmi_file_type { 42 ATH11K_QMI_FILE_TYPE_BDF_GOLDEN, 43 ATH11K_QMI_FILE_TYPE_CALDATA = 2, 44 ATH11K_QMI_FILE_TYPE_EEPROM, 45 ATH11K_QMI_MAX_FILE_TYPE, 46 }; 47 48 enum ath11k_qmi_bdf_type { 49 ATH11K_QMI_BDF_TYPE_BIN = 0, 50 ATH11K_QMI_BDF_TYPE_ELF = 1, 51 ATH11K_QMI_BDF_TYPE_REGDB = 4, 52 }; 53 54 enum ath11k_qmi_event_type { 55 ATH11K_QMI_EVENT_SERVER_ARRIVE, 56 ATH11K_QMI_EVENT_SERVER_EXIT, 57 ATH11K_QMI_EVENT_REQUEST_MEM, 58 ATH11K_QMI_EVENT_FW_MEM_READY, 59 ATH11K_QMI_EVENT_FW_READY, 60 ATH11K_QMI_EVENT_COLD_BOOT_CAL_START, 61 ATH11K_QMI_EVENT_COLD_BOOT_CAL_DONE, 62 ATH11K_QMI_EVENT_REGISTER_DRIVER, 63 ATH11K_QMI_EVENT_UNREGISTER_DRIVER, 64 ATH11K_QMI_EVENT_RECOVERY, 65 ATH11K_QMI_EVENT_FORCE_FW_ASSERT, 66 ATH11K_QMI_EVENT_POWER_UP, 67 ATH11K_QMI_EVENT_POWER_DOWN, 68 ATH11K_QMI_EVENT_MAX, 69 }; 70 71 struct ath11k_qmi_driver_event { 72 struct list_head list; 73 enum ath11k_qmi_event_type type; 74 void *data; 75 }; 76 77 struct ath11k_qmi_ce_cfg { 78 const struct ce_pipe_config *tgt_ce; 79 int tgt_ce_len; 80 const struct service_to_pipe *svc_to_ce_map; 81 int svc_to_ce_map_len; 82 const u8 *shadow_reg; 83 int shadow_reg_len; 84 u32 *shadow_reg_v2; 85 int shadow_reg_v2_len; 86 }; 87 88 struct ath11k_qmi_event_msg { 89 struct list_head list; 90 enum ath11k_qmi_event_type type; 91 }; 92 93 struct target_mem_chunk { 94 u32 size; 95 u32 type; 96 dma_addr_t paddr; 97 u32 *vaddr; 98 void __iomem *iaddr; 99 }; 100 101 struct target_info { 102 u32 chip_id; 103 u32 chip_family; 104 u32 board_id; 105 u32 soc_id; 106 u32 fw_version; 107 u32 eeprom_caldata; 108 char fw_build_timestamp[ATH11K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1]; 109 char fw_build_id[ATH11K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1]; 110 char bdf_ext[ATH11K_QMI_BDF_EXT_STR_LENGTH]; 111 }; 112 113 struct m3_mem_region { 114 u32 size; 115 dma_addr_t paddr; 116 void *vaddr; 117 }; 118 119 struct ath11k_qmi { 120 struct ath11k_base *ab; 121 struct qmi_handle handle; 122 struct sockaddr_qrtr sq; 123 struct work_struct event_work; 124 struct workqueue_struct *event_wq; 125 struct list_head event_list; 126 spinlock_t event_lock; /* spinlock for qmi event list */ 127 struct ath11k_qmi_ce_cfg ce_cfg; 128 struct target_mem_chunk target_mem[ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 129 u32 mem_seg_count; 130 u32 target_mem_mode; 131 bool target_mem_delayed; 132 u8 cal_done; 133 struct target_info target; 134 struct m3_mem_region m3_mem; 135 unsigned int service_ins_id; 136 wait_queue_head_t cold_boot_waitq; 137 }; 138 139 #define QMI_WLANFW_HOST_CAP_REQ_MSG_V01_MAX_LEN 261 140 #define QMI_WLANFW_HOST_CAP_REQ_V01 0x0034 141 #define QMI_WLANFW_HOST_CAP_RESP_MSG_V01_MAX_LEN 7 142 #define QMI_WLFW_HOST_CAP_RESP_V01 0x0034 143 #define QMI_WLFW_MAX_NUM_GPIO_V01 32 144 #define QMI_IPQ8074_FW_MEM_MODE 0xFF 145 #define HOST_DDR_REGION_TYPE 0x1 146 #define BDF_MEM_REGION_TYPE 0x2 147 #define M3_DUMP_REGION_TYPE 0x3 148 #define CALDB_MEM_REGION_TYPE 0x4 149 150 struct qmi_wlanfw_host_cap_req_msg_v01 { 151 u8 num_clients_valid; 152 u32 num_clients; 153 u8 wake_msi_valid; 154 u32 wake_msi; 155 u8 gpios_valid; 156 u32 gpios_len; 157 u32 gpios[QMI_WLFW_MAX_NUM_GPIO_V01]; 158 u8 nm_modem_valid; 159 u8 nm_modem; 160 u8 bdf_support_valid; 161 u8 bdf_support; 162 u8 bdf_cache_support_valid; 163 u8 bdf_cache_support; 164 u8 m3_support_valid; 165 u8 m3_support; 166 u8 m3_cache_support_valid; 167 u8 m3_cache_support; 168 u8 cal_filesys_support_valid; 169 u8 cal_filesys_support; 170 u8 cal_cache_support_valid; 171 u8 cal_cache_support; 172 u8 cal_done_valid; 173 u8 cal_done; 174 u8 mem_bucket_valid; 175 u32 mem_bucket; 176 u8 mem_cfg_mode_valid; 177 u8 mem_cfg_mode; 178 }; 179 180 struct qmi_wlanfw_host_cap_resp_msg_v01 { 181 struct qmi_response_type_v01 resp; 182 }; 183 184 #define QMI_WLANFW_IND_REGISTER_REQ_MSG_V01_MAX_LEN 54 185 #define QMI_WLANFW_IND_REGISTER_REQ_V01 0x0020 186 #define QMI_WLANFW_IND_REGISTER_RESP_MSG_V01_MAX_LEN 18 187 #define QMI_WLANFW_IND_REGISTER_RESP_V01 0x0020 188 #define QMI_WLANFW_CLIENT_ID 0x4b4e454c 189 190 struct qmi_wlanfw_ind_register_req_msg_v01 { 191 u8 fw_ready_enable_valid; 192 u8 fw_ready_enable; 193 u8 initiate_cal_download_enable_valid; 194 u8 initiate_cal_download_enable; 195 u8 initiate_cal_update_enable_valid; 196 u8 initiate_cal_update_enable; 197 u8 msa_ready_enable_valid; 198 u8 msa_ready_enable; 199 u8 pin_connect_result_enable_valid; 200 u8 pin_connect_result_enable; 201 u8 client_id_valid; 202 u32 client_id; 203 u8 request_mem_enable_valid; 204 u8 request_mem_enable; 205 u8 fw_mem_ready_enable_valid; 206 u8 fw_mem_ready_enable; 207 u8 fw_init_done_enable_valid; 208 u8 fw_init_done_enable; 209 u8 rejuvenate_enable_valid; 210 u32 rejuvenate_enable; 211 u8 xo_cal_enable_valid; 212 u8 xo_cal_enable; 213 u8 cal_done_enable_valid; 214 u8 cal_done_enable; 215 }; 216 217 struct qmi_wlanfw_ind_register_resp_msg_v01 { 218 struct qmi_response_type_v01 resp; 219 u8 fw_status_valid; 220 u64 fw_status; 221 }; 222 223 #define QMI_WLANFW_REQUEST_MEM_IND_MSG_V01_MAX_LEN 1824 224 #define QMI_WLANFW_RESPOND_MEM_REQ_MSG_V01_MAX_LEN 888 225 #define QMI_WLANFW_RESPOND_MEM_RESP_MSG_V01_MAX_LEN 7 226 #define QMI_WLANFW_REQUEST_MEM_IND_V01 0x0035 227 #define QMI_WLANFW_RESPOND_MEM_REQ_V01 0x0036 228 #define QMI_WLANFW_RESPOND_MEM_RESP_V01 0x0036 229 #define QMI_WLANFW_MAX_NUM_MEM_CFG_V01 2 230 231 struct qmi_wlanfw_mem_cfg_s_v01 { 232 u64 offset; 233 u32 size; 234 u8 secure_flag; 235 }; 236 237 enum qmi_wlanfw_mem_type_enum_v01 { 238 WLANFW_MEM_TYPE_ENUM_MIN_VAL_V01 = INT_MIN, 239 QMI_WLANFW_MEM_TYPE_MSA_V01 = 0, 240 QMI_WLANFW_MEM_TYPE_DDR_V01 = 1, 241 QMI_WLANFW_MEM_BDF_V01 = 2, 242 QMI_WLANFW_MEM_M3_V01 = 3, 243 QMI_WLANFW_MEM_CAL_V01 = 4, 244 QMI_WLANFW_MEM_DPD_V01 = 5, 245 WLANFW_MEM_TYPE_ENUM_MAX_VAL_V01 = INT_MAX, 246 }; 247 248 struct qmi_wlanfw_mem_seg_s_v01 { 249 u32 size; 250 enum qmi_wlanfw_mem_type_enum_v01 type; 251 u32 mem_cfg_len; 252 struct qmi_wlanfw_mem_cfg_s_v01 mem_cfg[QMI_WLANFW_MAX_NUM_MEM_CFG_V01]; 253 }; 254 255 struct qmi_wlanfw_request_mem_ind_msg_v01 { 256 u32 mem_seg_len; 257 struct qmi_wlanfw_mem_seg_s_v01 mem_seg[ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 258 }; 259 260 struct qmi_wlanfw_mem_seg_resp_s_v01 { 261 u64 addr; 262 u32 size; 263 enum qmi_wlanfw_mem_type_enum_v01 type; 264 u8 restore; 265 }; 266 267 struct qmi_wlanfw_respond_mem_req_msg_v01 { 268 u32 mem_seg_len; 269 struct qmi_wlanfw_mem_seg_resp_s_v01 mem_seg[ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 270 }; 271 272 struct qmi_wlanfw_respond_mem_resp_msg_v01 { 273 struct qmi_response_type_v01 resp; 274 }; 275 276 struct qmi_wlanfw_fw_mem_ready_ind_msg_v01 { 277 char placeholder; 278 }; 279 280 struct qmi_wlanfw_fw_ready_ind_msg_v01 { 281 char placeholder; 282 }; 283 284 struct qmi_wlanfw_fw_cold_cal_done_ind_msg_v01 { 285 char placeholder; 286 }; 287 288 #define QMI_WLANFW_CAP_REQ_MSG_V01_MAX_LEN 0 289 #define QMI_WLANFW_CAP_RESP_MSG_V01_MAX_LEN 235 290 #define QMI_WLANFW_CAP_REQ_V01 0x0024 291 #define QMI_WLANFW_CAP_RESP_V01 0x0024 292 293 enum qmi_wlanfw_pipedir_enum_v01 { 294 QMI_WLFW_PIPEDIR_NONE_V01 = 0, 295 QMI_WLFW_PIPEDIR_IN_V01 = 1, 296 QMI_WLFW_PIPEDIR_OUT_V01 = 2, 297 QMI_WLFW_PIPEDIR_INOUT_V01 = 3, 298 }; 299 300 struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01 { 301 __le32 pipe_num; 302 __le32 pipe_dir; 303 __le32 nentries; 304 __le32 nbytes_max; 305 __le32 flags; 306 }; 307 308 struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01 { 309 __le32 service_id; 310 __le32 pipe_dir; 311 __le32 pipe_num; 312 }; 313 314 struct qmi_wlanfw_shadow_reg_cfg_s_v01 { 315 u16 id; 316 u16 offset; 317 }; 318 319 struct qmi_wlanfw_shadow_reg_v2_cfg_s_v01 { 320 u32 addr; 321 }; 322 323 struct qmi_wlanfw_memory_region_info_s_v01 { 324 u64 region_addr; 325 u32 size; 326 u8 secure_flag; 327 }; 328 329 struct qmi_wlanfw_rf_chip_info_s_v01 { 330 u32 chip_id; 331 u32 chip_family; 332 }; 333 334 struct qmi_wlanfw_rf_board_info_s_v01 { 335 u32 board_id; 336 }; 337 338 struct qmi_wlanfw_soc_info_s_v01 { 339 u32 soc_id; 340 }; 341 342 struct qmi_wlanfw_fw_version_info_s_v01 { 343 u32 fw_version; 344 char fw_build_timestamp[ATH11K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1]; 345 }; 346 347 enum qmi_wlanfw_cal_temp_id_enum_v01 { 348 QMI_WLANFW_CAL_TEMP_IDX_0_V01 = 0, 349 QMI_WLANFW_CAL_TEMP_IDX_1_V01 = 1, 350 QMI_WLANFW_CAL_TEMP_IDX_2_V01 = 2, 351 QMI_WLANFW_CAL_TEMP_IDX_3_V01 = 3, 352 QMI_WLANFW_CAL_TEMP_IDX_4_V01 = 4, 353 QMI_WLANFW_CAL_TEMP_ID_MAX_V01 = 0xFF, 354 }; 355 356 struct qmi_wlanfw_cap_resp_msg_v01 { 357 struct qmi_response_type_v01 resp; 358 u8 chip_info_valid; 359 struct qmi_wlanfw_rf_chip_info_s_v01 chip_info; 360 u8 board_info_valid; 361 struct qmi_wlanfw_rf_board_info_s_v01 board_info; 362 u8 soc_info_valid; 363 struct qmi_wlanfw_soc_info_s_v01 soc_info; 364 u8 fw_version_info_valid; 365 struct qmi_wlanfw_fw_version_info_s_v01 fw_version_info; 366 u8 fw_build_id_valid; 367 char fw_build_id[ATH11K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1]; 368 u8 num_macs_valid; 369 u8 num_macs; 370 u8 voltage_mv_valid; 371 u32 voltage_mv; 372 u8 time_freq_hz_valid; 373 u32 time_freq_hz; 374 u8 otp_version_valid; 375 u32 otp_version; 376 u8 eeprom_read_timeout_valid; 377 u32 eeprom_read_timeout; 378 }; 379 380 struct qmi_wlanfw_cap_req_msg_v01 { 381 char placeholder; 382 }; 383 384 #define QMI_WLANFW_BDF_DOWNLOAD_REQ_MSG_V01_MAX_LEN 6182 385 #define QMI_WLANFW_BDF_DOWNLOAD_RESP_MSG_V01_MAX_LEN 7 386 #define QMI_WLANFW_BDF_DOWNLOAD_RESP_V01 0x0025 387 #define QMI_WLANFW_BDF_DOWNLOAD_REQ_V01 0x0025 388 /* TODO: Need to check with MCL and FW team that data can be pointer and 389 * can be last element in structure 390 */ 391 struct qmi_wlanfw_bdf_download_req_msg_v01 { 392 u8 valid; 393 u8 file_id_valid; 394 enum qmi_wlanfw_cal_temp_id_enum_v01 file_id; 395 u8 total_size_valid; 396 u32 total_size; 397 u8 seg_id_valid; 398 u32 seg_id; 399 u8 data_valid; 400 u32 data_len; 401 u8 data[QMI_WLANFW_MAX_DATA_SIZE_V01]; 402 u8 end_valid; 403 u8 end; 404 u8 bdf_type_valid; 405 u8 bdf_type; 406 407 }; 408 409 struct qmi_wlanfw_bdf_download_resp_msg_v01 { 410 struct qmi_response_type_v01 resp; 411 }; 412 413 #define QMI_WLANFW_M3_INFO_REQ_MSG_V01_MAX_MSG_LEN 18 414 #define QMI_WLANFW_M3_INFO_RESP_MSG_V01_MAX_MSG_LEN 7 415 #define QMI_WLANFW_M3_INFO_RESP_V01 0x003C 416 #define QMI_WLANFW_M3_INFO_REQ_V01 0x003C 417 418 struct qmi_wlanfw_m3_info_req_msg_v01 { 419 u64 addr; 420 u32 size; 421 }; 422 423 struct qmi_wlanfw_m3_info_resp_msg_v01 { 424 struct qmi_response_type_v01 resp; 425 }; 426 427 #define QMI_WLANFW_WLAN_MODE_REQ_MSG_V01_MAX_LEN 11 428 #define QMI_WLANFW_WLAN_MODE_RESP_MSG_V01_MAX_LEN 7 429 #define QMI_WLANFW_WLAN_CFG_REQ_MSG_V01_MAX_LEN 803 430 #define QMI_WLANFW_WLAN_CFG_RESP_MSG_V01_MAX_LEN 7 431 #define QMI_WLANFW_WLAN_INI_REQ_MSG_V01_MAX_LEN 4 432 #define QMI_WLANFW_WLAN_MODE_REQ_V01 0x0022 433 #define QMI_WLANFW_WLAN_MODE_RESP_V01 0x0022 434 #define QMI_WLANFW_WLAN_CFG_REQ_V01 0x0023 435 #define QMI_WLANFW_WLAN_CFG_RESP_V01 0x0023 436 #define QMI_WLANFW_WLAN_INI_REQ_V01 0x002F 437 #define QMI_WLANFW_MAX_STR_LEN_V01 16 438 #define QMI_WLANFW_MAX_NUM_CE_V01 12 439 #define QMI_WLANFW_MAX_NUM_SVC_V01 24 440 #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V01 24 441 #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V2_V01 36 442 443 struct qmi_wlanfw_wlan_mode_req_msg_v01 { 444 u32 mode; 445 u8 hw_debug_valid; 446 u8 hw_debug; 447 }; 448 449 struct qmi_wlanfw_wlan_mode_resp_msg_v01 { 450 struct qmi_response_type_v01 resp; 451 }; 452 453 struct qmi_wlanfw_wlan_cfg_req_msg_v01 { 454 u8 host_version_valid; 455 char host_version[QMI_WLANFW_MAX_STR_LEN_V01 + 1]; 456 u8 tgt_cfg_valid; 457 u32 tgt_cfg_len; 458 struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01 459 tgt_cfg[QMI_WLANFW_MAX_NUM_CE_V01]; 460 u8 svc_cfg_valid; 461 u32 svc_cfg_len; 462 struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01 463 svc_cfg[QMI_WLANFW_MAX_NUM_SVC_V01]; 464 u8 shadow_reg_valid; 465 u32 shadow_reg_len; 466 struct qmi_wlanfw_shadow_reg_cfg_s_v01 467 shadow_reg[QMI_WLANFW_MAX_NUM_SHADOW_REG_V01]; 468 u8 shadow_reg_v2_valid; 469 u32 shadow_reg_v2_len; 470 struct qmi_wlanfw_shadow_reg_v2_cfg_s_v01 471 shadow_reg_v2[QMI_WLANFW_MAX_NUM_SHADOW_REG_V2_V01]; 472 }; 473 474 struct qmi_wlanfw_wlan_cfg_resp_msg_v01 { 475 struct qmi_response_type_v01 resp; 476 }; 477 478 struct qmi_wlanfw_wlan_ini_req_msg_v01 { 479 /* Must be set to true if enablefwlog is being passed */ 480 u8 enablefwlog_valid; 481 u8 enablefwlog; 482 }; 483 484 struct qmi_wlanfw_wlan_ini_resp_msg_v01 { 485 struct qmi_response_type_v01 resp; 486 }; 487 488 int ath11k_qmi_firmware_start(struct ath11k_base *ab, 489 u32 mode); 490 void ath11k_qmi_firmware_stop(struct ath11k_base *ab); 491 void ath11k_qmi_event_work(struct work_struct *work); 492 void ath11k_qmi_msg_recv_work(struct work_struct *work); 493 void ath11k_qmi_deinit_service(struct ath11k_base *ab); 494 int ath11k_qmi_init_service(struct ath11k_base *ab); 495 496 #endif 497