1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include <linux/module.h> 8 #include <linux/msi.h> 9 #include <linux/pci.h> 10 #include <linux/of.h> 11 12 #include "pci.h" 13 #include "core.h" 14 #include "hif.h" 15 #include "mhi.h" 16 #include "debug.h" 17 #include "pcic.h" 18 #include "qmi.h" 19 20 #define ATH11K_PCI_BAR_NUM 0 21 #define ATH11K_PCI_DMA_MASK 36 22 #define ATH11K_PCI_COHERENT_DMA_MASK 32 23 24 #define TCSR_SOC_HW_VERSION 0x0224 25 #define TCSR_SOC_HW_VERSION_MAJOR_MASK GENMASK(11, 8) 26 #define TCSR_SOC_HW_VERSION_MINOR_MASK GENMASK(7, 0) 27 28 #define QCA6390_DEVICE_ID 0x1101 29 #define QCN9074_DEVICE_ID 0x1104 30 #define WCN6855_DEVICE_ID 0x1103 31 32 static const struct pci_device_id ath11k_pci_id_table[] = { 33 { PCI_VDEVICE(QCOM, QCA6390_DEVICE_ID) }, 34 { PCI_VDEVICE(QCOM, WCN6855_DEVICE_ID) }, 35 { PCI_VDEVICE(QCOM, QCN9074_DEVICE_ID) }, 36 {0} 37 }; 38 39 MODULE_DEVICE_TABLE(pci, ath11k_pci_id_table); 40 41 static int ath11k_pci_bus_wake_up(struct ath11k_base *ab) 42 { 43 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 44 45 return mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev); 46 } 47 48 static void ath11k_pci_bus_release(struct ath11k_base *ab) 49 { 50 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 51 52 mhi_device_put(ab_pci->mhi_ctrl->mhi_dev); 53 } 54 55 static u32 ath11k_pci_get_window_start(struct ath11k_base *ab, u32 offset) 56 { 57 if (!ab->hw_params.static_window_map) 58 return ATH11K_PCI_WINDOW_START; 59 60 if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < ATH11K_PCI_WINDOW_RANGE_MASK) 61 /* if offset lies within DP register range, use 3rd window */ 62 return 3 * ATH11K_PCI_WINDOW_START; 63 else if ((offset ^ HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab)) < 64 ATH11K_PCI_WINDOW_RANGE_MASK) 65 /* if offset lies within CE register range, use 2nd window */ 66 return 2 * ATH11K_PCI_WINDOW_START; 67 else 68 return ATH11K_PCI_WINDOW_START; 69 } 70 71 static inline void ath11k_pci_select_window(struct ath11k_pci *ab_pci, u32 offset) 72 { 73 struct ath11k_base *ab = ab_pci->ab; 74 75 u32 window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, offset); 76 77 lockdep_assert_held(&ab_pci->window_lock); 78 79 if (window != ab_pci->register_window) { 80 iowrite32(ATH11K_PCI_WINDOW_ENABLE_BIT | window, 81 ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS); 82 ioread32(ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS); 83 ab_pci->register_window = window; 84 } 85 } 86 87 static void 88 ath11k_pci_window_write32(struct ath11k_base *ab, u32 offset, u32 value) 89 { 90 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 91 u32 window_start; 92 93 window_start = ath11k_pci_get_window_start(ab, offset); 94 95 if (window_start == ATH11K_PCI_WINDOW_START) { 96 spin_lock_bh(&ab_pci->window_lock); 97 ath11k_pci_select_window(ab_pci, offset); 98 iowrite32(value, ab->mem + window_start + 99 (offset & ATH11K_PCI_WINDOW_RANGE_MASK)); 100 spin_unlock_bh(&ab_pci->window_lock); 101 } else { 102 iowrite32(value, ab->mem + window_start + 103 (offset & ATH11K_PCI_WINDOW_RANGE_MASK)); 104 } 105 } 106 107 static u32 ath11k_pci_window_read32(struct ath11k_base *ab, u32 offset) 108 { 109 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 110 u32 window_start, val; 111 112 window_start = ath11k_pci_get_window_start(ab, offset); 113 114 if (window_start == ATH11K_PCI_WINDOW_START) { 115 spin_lock_bh(&ab_pci->window_lock); 116 ath11k_pci_select_window(ab_pci, offset); 117 val = ioread32(ab->mem + window_start + 118 (offset & ATH11K_PCI_WINDOW_RANGE_MASK)); 119 spin_unlock_bh(&ab_pci->window_lock); 120 } else { 121 val = ioread32(ab->mem + window_start + 122 (offset & ATH11K_PCI_WINDOW_RANGE_MASK)); 123 } 124 125 return val; 126 } 127 128 int ath11k_pci_get_msi_irq(struct ath11k_base *ab, unsigned int vector) 129 { 130 struct pci_dev *pci_dev = to_pci_dev(ab->dev); 131 132 return pci_irq_vector(pci_dev, vector); 133 } 134 135 static const struct ath11k_pci_ops ath11k_pci_ops_qca6390 = { 136 .wakeup = ath11k_pci_bus_wake_up, 137 .release = ath11k_pci_bus_release, 138 .get_msi_irq = ath11k_pci_get_msi_irq, 139 .window_write32 = ath11k_pci_window_write32, 140 .window_read32 = ath11k_pci_window_read32, 141 }; 142 143 static const struct ath11k_pci_ops ath11k_pci_ops_qcn9074 = { 144 .wakeup = NULL, 145 .release = NULL, 146 .get_msi_irq = ath11k_pci_get_msi_irq, 147 .window_write32 = ath11k_pci_window_write32, 148 .window_read32 = ath11k_pci_window_read32, 149 }; 150 151 static const struct ath11k_msi_config msi_config_one_msi = { 152 .total_vectors = 1, 153 .total_users = 4, 154 .users = (struct ath11k_msi_user[]) { 155 { .name = "MHI", .num_vectors = 3, .base_vector = 0 }, 156 { .name = "CE", .num_vectors = 1, .base_vector = 0 }, 157 { .name = "WAKE", .num_vectors = 1, .base_vector = 0 }, 158 { .name = "DP", .num_vectors = 1, .base_vector = 0 }, 159 }, 160 }; 161 162 static inline void ath11k_pci_select_static_window(struct ath11k_pci *ab_pci) 163 { 164 u32 umac_window; 165 u32 ce_window; 166 u32 window; 167 168 umac_window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, HAL_SEQ_WCSS_UMAC_OFFSET); 169 ce_window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, HAL_CE_WFSS_CE_REG_BASE); 170 window = (umac_window << 12) | (ce_window << 6); 171 172 iowrite32(ATH11K_PCI_WINDOW_ENABLE_BIT | window, 173 ab_pci->ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS); 174 } 175 176 static void ath11k_pci_soc_global_reset(struct ath11k_base *ab) 177 { 178 u32 val, delay; 179 180 val = ath11k_pcic_read32(ab, PCIE_SOC_GLOBAL_RESET); 181 182 val |= PCIE_SOC_GLOBAL_RESET_V; 183 184 ath11k_pcic_write32(ab, PCIE_SOC_GLOBAL_RESET, val); 185 186 /* TODO: exact time to sleep is uncertain */ 187 delay = 10; 188 mdelay(delay); 189 190 /* Need to toggle V bit back otherwise stuck in reset status */ 191 val &= ~PCIE_SOC_GLOBAL_RESET_V; 192 193 ath11k_pcic_write32(ab, PCIE_SOC_GLOBAL_RESET, val); 194 195 mdelay(delay); 196 197 val = ath11k_pcic_read32(ab, PCIE_SOC_GLOBAL_RESET); 198 if (val == 0xffffffff) 199 ath11k_warn(ab, "link down error during global reset\n"); 200 } 201 202 static void ath11k_pci_clear_dbg_registers(struct ath11k_base *ab) 203 { 204 u32 val; 205 206 /* read cookie */ 207 val = ath11k_pcic_read32(ab, PCIE_Q6_COOKIE_ADDR); 208 ath11k_dbg(ab, ATH11K_DBG_PCI, "pcie_q6_cookie_addr 0x%x\n", val); 209 210 val = ath11k_pcic_read32(ab, WLAON_WARM_SW_ENTRY); 211 ath11k_dbg(ab, ATH11K_DBG_PCI, "wlaon_warm_sw_entry 0x%x\n", val); 212 213 /* TODO: exact time to sleep is uncertain */ 214 mdelay(10); 215 216 /* write 0 to WLAON_WARM_SW_ENTRY to prevent Q6 from 217 * continuing warm path and entering dead loop. 218 */ 219 ath11k_pcic_write32(ab, WLAON_WARM_SW_ENTRY, 0); 220 mdelay(10); 221 222 val = ath11k_pcic_read32(ab, WLAON_WARM_SW_ENTRY); 223 ath11k_dbg(ab, ATH11K_DBG_PCI, "wlaon_warm_sw_entry 0x%x\n", val); 224 225 /* A read clear register. clear the register to prevent 226 * Q6 from entering wrong code path. 227 */ 228 val = ath11k_pcic_read32(ab, WLAON_SOC_RESET_CAUSE_REG); 229 ath11k_dbg(ab, ATH11K_DBG_PCI, "soc reset cause %d\n", val); 230 } 231 232 static int ath11k_pci_set_link_reg(struct ath11k_base *ab, 233 u32 offset, u32 value, u32 mask) 234 { 235 u32 v; 236 int i; 237 238 v = ath11k_pcic_read32(ab, offset); 239 if ((v & mask) == value) 240 return 0; 241 242 for (i = 0; i < 10; i++) { 243 ath11k_pcic_write32(ab, offset, (v & ~mask) | value); 244 245 v = ath11k_pcic_read32(ab, offset); 246 if ((v & mask) == value) 247 return 0; 248 249 mdelay(2); 250 } 251 252 ath11k_warn(ab, "failed to set pcie link register 0x%08x: 0x%08x != 0x%08x\n", 253 offset, v & mask, value); 254 255 return -ETIMEDOUT; 256 } 257 258 static int ath11k_pci_fix_l1ss(struct ath11k_base *ab) 259 { 260 int ret; 261 262 ret = ath11k_pci_set_link_reg(ab, 263 PCIE_QSERDES_COM_SYSCLK_EN_SEL_REG(ab), 264 PCIE_QSERDES_COM_SYSCLK_EN_SEL_VAL, 265 PCIE_QSERDES_COM_SYSCLK_EN_SEL_MSK); 266 if (ret) { 267 ath11k_warn(ab, "failed to set sysclk: %d\n", ret); 268 return ret; 269 } 270 271 ret = ath11k_pci_set_link_reg(ab, 272 PCIE_PCS_OSC_DTCT_CONFIG1_REG(ab), 273 PCIE_PCS_OSC_DTCT_CONFIG1_VAL, 274 PCIE_PCS_OSC_DTCT_CONFIG_MSK); 275 if (ret) { 276 ath11k_warn(ab, "failed to set dtct config1 error: %d\n", ret); 277 return ret; 278 } 279 280 ret = ath11k_pci_set_link_reg(ab, 281 PCIE_PCS_OSC_DTCT_CONFIG2_REG(ab), 282 PCIE_PCS_OSC_DTCT_CONFIG2_VAL, 283 PCIE_PCS_OSC_DTCT_CONFIG_MSK); 284 if (ret) { 285 ath11k_warn(ab, "failed to set dtct config2: %d\n", ret); 286 return ret; 287 } 288 289 ret = ath11k_pci_set_link_reg(ab, 290 PCIE_PCS_OSC_DTCT_CONFIG4_REG(ab), 291 PCIE_PCS_OSC_DTCT_CONFIG4_VAL, 292 PCIE_PCS_OSC_DTCT_CONFIG_MSK); 293 if (ret) { 294 ath11k_warn(ab, "failed to set dtct config4: %d\n", ret); 295 return ret; 296 } 297 298 return 0; 299 } 300 301 static void ath11k_pci_enable_ltssm(struct ath11k_base *ab) 302 { 303 u32 val; 304 int i; 305 306 val = ath11k_pcic_read32(ab, PCIE_PCIE_PARF_LTSSM); 307 308 /* PCIE link seems very unstable after the Hot Reset*/ 309 for (i = 0; val != PARM_LTSSM_VALUE && i < 5; i++) { 310 if (val == 0xffffffff) 311 mdelay(5); 312 313 ath11k_pcic_write32(ab, PCIE_PCIE_PARF_LTSSM, PARM_LTSSM_VALUE); 314 val = ath11k_pcic_read32(ab, PCIE_PCIE_PARF_LTSSM); 315 } 316 317 ath11k_dbg(ab, ATH11K_DBG_PCI, "ltssm 0x%x\n", val); 318 319 val = ath11k_pcic_read32(ab, GCC_GCC_PCIE_HOT_RST); 320 val |= GCC_GCC_PCIE_HOT_RST_VAL; 321 ath11k_pcic_write32(ab, GCC_GCC_PCIE_HOT_RST, val); 322 val = ath11k_pcic_read32(ab, GCC_GCC_PCIE_HOT_RST); 323 324 ath11k_dbg(ab, ATH11K_DBG_PCI, "pcie_hot_rst 0x%x\n", val); 325 326 mdelay(5); 327 } 328 329 static void ath11k_pci_clear_all_intrs(struct ath11k_base *ab) 330 { 331 /* This is a WAR for PCIE Hotreset. 332 * When target receive Hotreset, but will set the interrupt. 333 * So when download SBL again, SBL will open Interrupt and 334 * receive it, and crash immediately. 335 */ 336 ath11k_pcic_write32(ab, PCIE_PCIE_INT_ALL_CLEAR, PCIE_INT_CLEAR_ALL); 337 } 338 339 static void ath11k_pci_set_wlaon_pwr_ctrl(struct ath11k_base *ab) 340 { 341 u32 val; 342 343 val = ath11k_pcic_read32(ab, WLAON_QFPROM_PWR_CTRL_REG); 344 val &= ~QFPROM_PWR_CTRL_VDD4BLOW_MASK; 345 ath11k_pcic_write32(ab, WLAON_QFPROM_PWR_CTRL_REG, val); 346 } 347 348 static void ath11k_pci_force_wake(struct ath11k_base *ab) 349 { 350 ath11k_pcic_write32(ab, PCIE_SOC_WAKE_PCIE_LOCAL_REG, 1); 351 mdelay(5); 352 } 353 354 static void ath11k_pci_sw_reset(struct ath11k_base *ab, bool power_on) 355 { 356 mdelay(100); 357 358 if (power_on) { 359 ath11k_pci_enable_ltssm(ab); 360 ath11k_pci_clear_all_intrs(ab); 361 ath11k_pci_set_wlaon_pwr_ctrl(ab); 362 if (ab->hw_params.fix_l1ss) 363 ath11k_pci_fix_l1ss(ab); 364 } 365 366 ath11k_mhi_clear_vector(ab); 367 ath11k_pci_clear_dbg_registers(ab); 368 ath11k_pci_soc_global_reset(ab); 369 ath11k_mhi_set_mhictrl_reset(ab); 370 } 371 372 static void ath11k_pci_init_qmi_ce_config(struct ath11k_base *ab) 373 { 374 struct ath11k_qmi_ce_cfg *cfg = &ab->qmi.ce_cfg; 375 376 cfg->tgt_ce = ab->hw_params.target_ce_config; 377 cfg->tgt_ce_len = ab->hw_params.target_ce_count; 378 379 cfg->svc_to_ce_map = ab->hw_params.svc_to_ce_map; 380 cfg->svc_to_ce_map_len = ab->hw_params.svc_to_ce_map_len; 381 ab->qmi.service_ins_id = ab->hw_params.qmi_service_ins_id; 382 383 ath11k_ce_get_shadow_config(ab, &cfg->shadow_reg_v2, 384 &cfg->shadow_reg_v2_len); 385 } 386 387 static void ath11k_pci_msi_config(struct ath11k_pci *ab_pci, bool enable) 388 { 389 struct pci_dev *dev = ab_pci->pdev; 390 u16 control; 391 392 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); 393 394 if (enable) 395 control |= PCI_MSI_FLAGS_ENABLE; 396 else 397 control &= ~PCI_MSI_FLAGS_ENABLE; 398 399 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); 400 } 401 402 static void ath11k_pci_msi_enable(struct ath11k_pci *ab_pci) 403 { 404 ath11k_pci_msi_config(ab_pci, true); 405 } 406 407 static void ath11k_pci_msi_disable(struct ath11k_pci *ab_pci) 408 { 409 ath11k_pci_msi_config(ab_pci, false); 410 } 411 412 static int ath11k_pci_alloc_msi(struct ath11k_pci *ab_pci) 413 { 414 struct ath11k_base *ab = ab_pci->ab; 415 const struct ath11k_msi_config *msi_config = ab->pci.msi.config; 416 struct pci_dev *pci_dev = ab_pci->pdev; 417 struct msi_desc *msi_desc; 418 int num_vectors; 419 int ret; 420 421 num_vectors = pci_alloc_irq_vectors(pci_dev, 422 msi_config->total_vectors, 423 msi_config->total_vectors, 424 PCI_IRQ_MSI); 425 if (num_vectors == msi_config->total_vectors) { 426 set_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags); 427 } else { 428 num_vectors = pci_alloc_irq_vectors(ab_pci->pdev, 429 1, 430 1, 431 PCI_IRQ_MSI); 432 if (num_vectors < 0) { 433 ret = -EINVAL; 434 goto reset_msi_config; 435 } 436 clear_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags); 437 ab->pci.msi.config = &msi_config_one_msi; 438 ath11k_dbg(ab, ATH11K_DBG_PCI, "request one msi vector\n"); 439 } 440 ath11k_info(ab, "MSI vectors: %d\n", num_vectors); 441 442 ath11k_pci_msi_disable(ab_pci); 443 444 msi_desc = irq_get_msi_desc(ab_pci->pdev->irq); 445 if (!msi_desc) { 446 ath11k_err(ab, "msi_desc is NULL!\n"); 447 ret = -EINVAL; 448 goto free_msi_vector; 449 } 450 451 ab->pci.msi.ep_base_data = msi_desc->msg.data; 452 453 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_LO, 454 &ab->pci.msi.addr_lo); 455 456 if (msi_desc->pci.msi_attrib.is_64) { 457 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_HI, 458 &ab->pci.msi.addr_hi); 459 } else { 460 ab->pci.msi.addr_hi = 0; 461 } 462 463 ath11k_dbg(ab, ATH11K_DBG_PCI, "msi base data is %d\n", ab->pci.msi.ep_base_data); 464 465 return 0; 466 467 free_msi_vector: 468 pci_free_irq_vectors(ab_pci->pdev); 469 470 reset_msi_config: 471 return ret; 472 } 473 474 static void ath11k_pci_free_msi(struct ath11k_pci *ab_pci) 475 { 476 pci_free_irq_vectors(ab_pci->pdev); 477 } 478 479 static int ath11k_pci_config_msi_data(struct ath11k_pci *ab_pci) 480 { 481 struct msi_desc *msi_desc; 482 483 msi_desc = irq_get_msi_desc(ab_pci->pdev->irq); 484 if (!msi_desc) { 485 ath11k_err(ab_pci->ab, "msi_desc is NULL!\n"); 486 pci_free_irq_vectors(ab_pci->pdev); 487 return -EINVAL; 488 } 489 490 ab_pci->ab->pci.msi.ep_base_data = msi_desc->msg.data; 491 492 ath11k_dbg(ab_pci->ab, ATH11K_DBG_PCI, "after request_irq msi_ep_base_data %d\n", 493 ab_pci->ab->pci.msi.ep_base_data); 494 495 return 0; 496 } 497 498 static int ath11k_pci_claim(struct ath11k_pci *ab_pci, struct pci_dev *pdev) 499 { 500 struct ath11k_base *ab = ab_pci->ab; 501 u16 device_id; 502 int ret = 0; 503 504 pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id); 505 if (device_id != ab_pci->dev_id) { 506 ath11k_err(ab, "pci device id mismatch: 0x%x 0x%x\n", 507 device_id, ab_pci->dev_id); 508 ret = -EIO; 509 goto out; 510 } 511 512 ret = pci_assign_resource(pdev, ATH11K_PCI_BAR_NUM); 513 if (ret) { 514 ath11k_err(ab, "failed to assign pci resource: %d\n", ret); 515 goto out; 516 } 517 518 ret = pci_enable_device(pdev); 519 if (ret) { 520 ath11k_err(ab, "failed to enable pci device: %d\n", ret); 521 goto out; 522 } 523 524 ret = pci_request_region(pdev, ATH11K_PCI_BAR_NUM, "ath11k_pci"); 525 if (ret) { 526 ath11k_err(ab, "failed to request pci region: %d\n", ret); 527 goto disable_device; 528 } 529 530 ret = dma_set_mask(&pdev->dev, 531 DMA_BIT_MASK(ATH11K_PCI_DMA_MASK)); 532 if (ret) { 533 ath11k_err(ab, "failed to set pci dma mask to %d: %d\n", 534 ATH11K_PCI_DMA_MASK, ret); 535 goto release_region; 536 } 537 538 ab_pci->dma_mask = DMA_BIT_MASK(ATH11K_PCI_DMA_MASK); 539 540 ret = dma_set_coherent_mask(&pdev->dev, 541 DMA_BIT_MASK(ATH11K_PCI_COHERENT_DMA_MASK)); 542 if (ret) { 543 ath11k_err(ab, "failed to set pci coherent dma mask to %d: %d\n", 544 ATH11K_PCI_COHERENT_DMA_MASK, ret); 545 goto release_region; 546 } 547 548 pci_set_master(pdev); 549 550 ab->mem_len = pci_resource_len(pdev, ATH11K_PCI_BAR_NUM); 551 ab->mem = pci_iomap(pdev, ATH11K_PCI_BAR_NUM, 0); 552 if (!ab->mem) { 553 ath11k_err(ab, "failed to map pci bar %d\n", ATH11K_PCI_BAR_NUM); 554 ret = -EIO; 555 goto release_region; 556 } 557 558 ab->mem_ce = ab->mem; 559 560 ath11k_dbg(ab, ATH11K_DBG_BOOT, "pci_mem 0x%p\n", ab->mem); 561 return 0; 562 563 release_region: 564 pci_release_region(pdev, ATH11K_PCI_BAR_NUM); 565 disable_device: 566 pci_disable_device(pdev); 567 out: 568 return ret; 569 } 570 571 static void ath11k_pci_free_region(struct ath11k_pci *ab_pci) 572 { 573 struct ath11k_base *ab = ab_pci->ab; 574 struct pci_dev *pci_dev = ab_pci->pdev; 575 576 pci_iounmap(pci_dev, ab->mem); 577 ab->mem = NULL; 578 pci_release_region(pci_dev, ATH11K_PCI_BAR_NUM); 579 if (pci_is_enabled(pci_dev)) 580 pci_disable_device(pci_dev); 581 } 582 583 static void ath11k_pci_aspm_disable(struct ath11k_pci *ab_pci) 584 { 585 struct ath11k_base *ab = ab_pci->ab; 586 587 pcie_capability_read_word(ab_pci->pdev, PCI_EXP_LNKCTL, 588 &ab_pci->link_ctl); 589 590 ath11k_dbg(ab, ATH11K_DBG_PCI, "link_ctl 0x%04x L0s %d L1 %d\n", 591 ab_pci->link_ctl, 592 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L0S), 593 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L1)); 594 595 /* disable L0s and L1 */ 596 pcie_capability_clear_word(ab_pci->pdev, PCI_EXP_LNKCTL, 597 PCI_EXP_LNKCTL_ASPMC); 598 599 set_bit(ATH11K_PCI_ASPM_RESTORE, &ab_pci->flags); 600 } 601 602 static void ath11k_pci_aspm_restore(struct ath11k_pci *ab_pci) 603 { 604 if (test_and_clear_bit(ATH11K_PCI_ASPM_RESTORE, &ab_pci->flags)) 605 pcie_capability_clear_and_set_word(ab_pci->pdev, PCI_EXP_LNKCTL, 606 PCI_EXP_LNKCTL_ASPMC, 607 ab_pci->link_ctl & 608 PCI_EXP_LNKCTL_ASPMC); 609 } 610 611 static int ath11k_pci_power_up(struct ath11k_base *ab) 612 { 613 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 614 int ret; 615 616 ab_pci->register_window = 0; 617 clear_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags); 618 ath11k_pci_sw_reset(ab_pci->ab, true); 619 620 /* Disable ASPM during firmware download due to problems switching 621 * to AMSS state. 622 */ 623 ath11k_pci_aspm_disable(ab_pci); 624 625 ath11k_pci_msi_enable(ab_pci); 626 627 ret = ath11k_mhi_start(ab_pci); 628 if (ret) { 629 ath11k_err(ab, "failed to start mhi: %d\n", ret); 630 return ret; 631 } 632 633 if (ab->hw_params.static_window_map) 634 ath11k_pci_select_static_window(ab_pci); 635 636 return 0; 637 } 638 639 static void ath11k_pci_power_down(struct ath11k_base *ab) 640 { 641 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 642 643 /* restore aspm in case firmware bootup fails */ 644 ath11k_pci_aspm_restore(ab_pci); 645 646 ath11k_pci_force_wake(ab_pci->ab); 647 648 ath11k_pci_msi_disable(ab_pci); 649 650 ath11k_mhi_stop(ab_pci); 651 clear_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags); 652 ath11k_pci_sw_reset(ab_pci->ab, false); 653 } 654 655 static int ath11k_pci_hif_suspend(struct ath11k_base *ab) 656 { 657 struct ath11k_pci *ar_pci = ath11k_pci_priv(ab); 658 659 return ath11k_mhi_suspend(ar_pci); 660 } 661 662 static int ath11k_pci_hif_resume(struct ath11k_base *ab) 663 { 664 struct ath11k_pci *ar_pci = ath11k_pci_priv(ab); 665 666 return ath11k_mhi_resume(ar_pci); 667 } 668 669 static void ath11k_pci_hif_ce_irq_enable(struct ath11k_base *ab) 670 { 671 ath11k_pcic_ce_irqs_enable(ab); 672 } 673 674 static void ath11k_pci_hif_ce_irq_disable(struct ath11k_base *ab) 675 { 676 ath11k_pcic_ce_irq_disable_sync(ab); 677 } 678 679 static int ath11k_pci_start(struct ath11k_base *ab) 680 { 681 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 682 683 /* TODO: for now don't restore ASPM in case of single MSI 684 * vector as MHI register reading in M2 causes system hang. 685 */ 686 if (test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags)) 687 ath11k_pci_aspm_restore(ab_pci); 688 else 689 ath11k_info(ab, "leaving PCI ASPM disabled to avoid MHI M2 problems\n"); 690 691 ath11k_pcic_start(ab); 692 693 return 0; 694 } 695 696 static const struct ath11k_hif_ops ath11k_pci_hif_ops = { 697 .start = ath11k_pci_start, 698 .stop = ath11k_pcic_stop, 699 .read32 = ath11k_pcic_read32, 700 .write32 = ath11k_pcic_write32, 701 .read = ath11k_pcic_read, 702 .power_down = ath11k_pci_power_down, 703 .power_up = ath11k_pci_power_up, 704 .suspend = ath11k_pci_hif_suspend, 705 .resume = ath11k_pci_hif_resume, 706 .irq_enable = ath11k_pcic_ext_irq_enable, 707 .irq_disable = ath11k_pcic_ext_irq_disable, 708 .get_msi_address = ath11k_pcic_get_msi_address, 709 .get_user_msi_vector = ath11k_pcic_get_user_msi_assignment, 710 .map_service_to_pipe = ath11k_pcic_map_service_to_pipe, 711 .ce_irq_enable = ath11k_pci_hif_ce_irq_enable, 712 .ce_irq_disable = ath11k_pci_hif_ce_irq_disable, 713 .get_ce_msi_idx = ath11k_pcic_get_ce_msi_idx, 714 }; 715 716 static void ath11k_pci_read_hw_version(struct ath11k_base *ab, u32 *major, u32 *minor) 717 { 718 u32 soc_hw_version; 719 720 soc_hw_version = ath11k_pcic_read32(ab, TCSR_SOC_HW_VERSION); 721 *major = FIELD_GET(TCSR_SOC_HW_VERSION_MAJOR_MASK, 722 soc_hw_version); 723 *minor = FIELD_GET(TCSR_SOC_HW_VERSION_MINOR_MASK, 724 soc_hw_version); 725 726 ath11k_dbg(ab, ATH11K_DBG_PCI, "tcsr_soc_hw_version major %d minor %d\n", 727 *major, *minor); 728 } 729 730 static int ath11k_pci_set_irq_affinity_hint(struct ath11k_pci *ab_pci, 731 const struct cpumask *m) 732 { 733 if (test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab_pci->ab->dev_flags)) 734 return 0; 735 736 return irq_set_affinity_hint(ab_pci->pdev->irq, m); 737 } 738 739 static int ath11k_pci_probe(struct pci_dev *pdev, 740 const struct pci_device_id *pci_dev) 741 { 742 struct ath11k_base *ab; 743 struct ath11k_pci *ab_pci; 744 u32 soc_hw_version_major, soc_hw_version_minor, addr; 745 const struct ath11k_pci_ops *pci_ops; 746 int ret; 747 748 ab = ath11k_core_alloc(&pdev->dev, sizeof(*ab_pci), ATH11K_BUS_PCI); 749 750 if (!ab) { 751 dev_err(&pdev->dev, "failed to allocate ath11k base\n"); 752 return -ENOMEM; 753 } 754 755 ab->dev = &pdev->dev; 756 pci_set_drvdata(pdev, ab); 757 ab_pci = ath11k_pci_priv(ab); 758 ab_pci->dev_id = pci_dev->device; 759 ab_pci->ab = ab; 760 ab_pci->pdev = pdev; 761 ab->hif.ops = &ath11k_pci_hif_ops; 762 ab->fw_mode = ATH11K_FIRMWARE_MODE_NORMAL; 763 pci_set_drvdata(pdev, ab); 764 spin_lock_init(&ab_pci->window_lock); 765 766 /* Set fixed_mem_region to true for platforms support reserved memory 767 * from DT. If memory is reserved from DT for FW, ath11k driver need not 768 * allocate memory. 769 */ 770 ret = of_property_read_u32(ab->dev->of_node, "memory-region", &addr); 771 if (!ret) 772 set_bit(ATH11K_FLAG_FIXED_MEM_RGN, &ab->dev_flags); 773 774 ret = ath11k_pci_claim(ab_pci, pdev); 775 if (ret) { 776 ath11k_err(ab, "failed to claim device: %d\n", ret); 777 goto err_free_core; 778 } 779 780 ath11k_dbg(ab, ATH11K_DBG_BOOT, "pci probe %04x:%04x %04x:%04x\n", 781 pdev->vendor, pdev->device, 782 pdev->subsystem_vendor, pdev->subsystem_device); 783 784 ab->id.vendor = pdev->vendor; 785 ab->id.device = pdev->device; 786 ab->id.subsystem_vendor = pdev->subsystem_vendor; 787 ab->id.subsystem_device = pdev->subsystem_device; 788 789 switch (pci_dev->device) { 790 case QCA6390_DEVICE_ID: 791 ath11k_pci_read_hw_version(ab, &soc_hw_version_major, 792 &soc_hw_version_minor); 793 switch (soc_hw_version_major) { 794 case 2: 795 ab->hw_rev = ATH11K_HW_QCA6390_HW20; 796 break; 797 default: 798 dev_err(&pdev->dev, "Unsupported QCA6390 SOC hardware version: %d %d\n", 799 soc_hw_version_major, soc_hw_version_minor); 800 ret = -EOPNOTSUPP; 801 goto err_pci_free_region; 802 } 803 804 pci_ops = &ath11k_pci_ops_qca6390; 805 break; 806 case QCN9074_DEVICE_ID: 807 pci_ops = &ath11k_pci_ops_qcn9074; 808 ab->hw_rev = ATH11K_HW_QCN9074_HW10; 809 break; 810 case WCN6855_DEVICE_ID: 811 ab->id.bdf_search = ATH11K_BDF_SEARCH_BUS_AND_BOARD; 812 ath11k_pci_read_hw_version(ab, &soc_hw_version_major, 813 &soc_hw_version_minor); 814 switch (soc_hw_version_major) { 815 case 2: 816 switch (soc_hw_version_minor) { 817 case 0x00: 818 case 0x01: 819 ab->hw_rev = ATH11K_HW_WCN6855_HW20; 820 break; 821 case 0x10: 822 case 0x11: 823 ab->hw_rev = ATH11K_HW_WCN6855_HW21; 824 break; 825 default: 826 goto unsupported_wcn6855_soc; 827 } 828 break; 829 default: 830 unsupported_wcn6855_soc: 831 dev_err(&pdev->dev, "Unsupported WCN6855 SOC hardware version: %d %d\n", 832 soc_hw_version_major, soc_hw_version_minor); 833 ret = -EOPNOTSUPP; 834 goto err_pci_free_region; 835 } 836 837 pci_ops = &ath11k_pci_ops_qca6390; 838 break; 839 default: 840 dev_err(&pdev->dev, "Unknown PCI device found: 0x%x\n", 841 pci_dev->device); 842 ret = -EOPNOTSUPP; 843 goto err_pci_free_region; 844 } 845 846 ret = ath11k_pcic_register_pci_ops(ab, pci_ops); 847 if (ret) { 848 ath11k_err(ab, "failed to register PCI ops: %d\n", ret); 849 goto err_pci_free_region; 850 } 851 852 ret = ath11k_pcic_init_msi_config(ab); 853 if (ret) { 854 ath11k_err(ab, "failed to init msi config: %d\n", ret); 855 goto err_pci_free_region; 856 } 857 858 ret = ath11k_pci_alloc_msi(ab_pci); 859 if (ret) { 860 ath11k_err(ab, "failed to enable msi: %d\n", ret); 861 goto err_pci_free_region; 862 } 863 864 ret = ath11k_core_pre_init(ab); 865 if (ret) 866 goto err_pci_disable_msi; 867 868 ret = ath11k_pci_set_irq_affinity_hint(ab_pci, cpumask_of(0)); 869 if (ret) { 870 ath11k_err(ab, "failed to set irq affinity %d\n", ret); 871 goto err_pci_disable_msi; 872 } 873 874 ret = ath11k_mhi_register(ab_pci); 875 if (ret) { 876 ath11k_err(ab, "failed to register mhi: %d\n", ret); 877 goto err_irq_affinity_cleanup; 878 } 879 880 ret = ath11k_hal_srng_init(ab); 881 if (ret) 882 goto err_mhi_unregister; 883 884 ret = ath11k_ce_alloc_pipes(ab); 885 if (ret) { 886 ath11k_err(ab, "failed to allocate ce pipes: %d\n", ret); 887 goto err_hal_srng_deinit; 888 } 889 890 ath11k_pci_init_qmi_ce_config(ab); 891 892 ret = ath11k_pcic_config_irq(ab); 893 if (ret) { 894 ath11k_err(ab, "failed to config irq: %d\n", ret); 895 goto err_ce_free; 896 } 897 898 /* kernel may allocate a dummy vector before request_irq and 899 * then allocate a real vector when request_irq is called. 900 * So get msi_data here again to avoid spurious interrupt 901 * as msi_data will configured to srngs. 902 */ 903 ret = ath11k_pci_config_msi_data(ab_pci); 904 if (ret) { 905 ath11k_err(ab, "failed to config msi_data: %d\n", ret); 906 goto err_free_irq; 907 } 908 909 ret = ath11k_core_init(ab); 910 if (ret) { 911 ath11k_err(ab, "failed to init core: %d\n", ret); 912 goto err_free_irq; 913 } 914 ath11k_qmi_fwreset_from_cold_boot(ab); 915 return 0; 916 917 err_free_irq: 918 ath11k_pcic_free_irq(ab); 919 920 err_ce_free: 921 ath11k_ce_free_pipes(ab); 922 923 err_hal_srng_deinit: 924 ath11k_hal_srng_deinit(ab); 925 926 err_mhi_unregister: 927 ath11k_mhi_unregister(ab_pci); 928 929 err_irq_affinity_cleanup: 930 ath11k_pci_set_irq_affinity_hint(ab_pci, NULL); 931 932 err_pci_disable_msi: 933 ath11k_pci_free_msi(ab_pci); 934 935 err_pci_free_region: 936 ath11k_pci_free_region(ab_pci); 937 938 err_free_core: 939 ath11k_core_free(ab); 940 941 return ret; 942 } 943 944 static void ath11k_pci_remove(struct pci_dev *pdev) 945 { 946 struct ath11k_base *ab = pci_get_drvdata(pdev); 947 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 948 949 ath11k_pci_set_irq_affinity_hint(ab_pci, NULL); 950 951 if (test_bit(ATH11K_FLAG_QMI_FAIL, &ab->dev_flags)) { 952 ath11k_pci_power_down(ab); 953 ath11k_debugfs_soc_destroy(ab); 954 ath11k_qmi_deinit_service(ab); 955 goto qmi_fail; 956 } 957 958 set_bit(ATH11K_FLAG_UNREGISTERING, &ab->dev_flags); 959 960 ath11k_core_deinit(ab); 961 962 qmi_fail: 963 ath11k_mhi_unregister(ab_pci); 964 965 ath11k_pcic_free_irq(ab); 966 ath11k_pci_free_msi(ab_pci); 967 ath11k_pci_free_region(ab_pci); 968 969 ath11k_hal_srng_deinit(ab); 970 ath11k_ce_free_pipes(ab); 971 ath11k_core_free(ab); 972 } 973 974 static void ath11k_pci_shutdown(struct pci_dev *pdev) 975 { 976 struct ath11k_base *ab = pci_get_drvdata(pdev); 977 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 978 979 ath11k_pci_set_irq_affinity_hint(ab_pci, NULL); 980 ath11k_pci_power_down(ab); 981 } 982 983 static __maybe_unused int ath11k_pci_pm_suspend(struct device *dev) 984 { 985 struct ath11k_base *ab = dev_get_drvdata(dev); 986 int ret; 987 988 if (test_bit(ATH11K_FLAG_QMI_FAIL, &ab->dev_flags)) { 989 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot skipping pci suspend as qmi is not initialised\n"); 990 return 0; 991 } 992 993 ret = ath11k_core_suspend(ab); 994 if (ret) 995 ath11k_warn(ab, "failed to suspend core: %d\n", ret); 996 997 return 0; 998 } 999 1000 static __maybe_unused int ath11k_pci_pm_resume(struct device *dev) 1001 { 1002 struct ath11k_base *ab = dev_get_drvdata(dev); 1003 int ret; 1004 1005 if (test_bit(ATH11K_FLAG_QMI_FAIL, &ab->dev_flags)) { 1006 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot skipping pci resume as qmi is not initialised\n"); 1007 return 0; 1008 } 1009 1010 ret = ath11k_core_resume(ab); 1011 if (ret) 1012 ath11k_warn(ab, "failed to resume core: %d\n", ret); 1013 1014 return ret; 1015 } 1016 1017 static SIMPLE_DEV_PM_OPS(ath11k_pci_pm_ops, 1018 ath11k_pci_pm_suspend, 1019 ath11k_pci_pm_resume); 1020 1021 static struct pci_driver ath11k_pci_driver = { 1022 .name = "ath11k_pci", 1023 .id_table = ath11k_pci_id_table, 1024 .probe = ath11k_pci_probe, 1025 .remove = ath11k_pci_remove, 1026 .shutdown = ath11k_pci_shutdown, 1027 #ifdef CONFIG_PM 1028 .driver.pm = &ath11k_pci_pm_ops, 1029 #endif 1030 }; 1031 1032 static int ath11k_pci_init(void) 1033 { 1034 int ret; 1035 1036 ret = pci_register_driver(&ath11k_pci_driver); 1037 if (ret) 1038 pr_err("failed to register ath11k pci driver: %d\n", 1039 ret); 1040 1041 return ret; 1042 } 1043 module_init(ath11k_pci_init); 1044 1045 static void ath11k_pci_exit(void) 1046 { 1047 pci_unregister_driver(&ath11k_pci_driver); 1048 } 1049 1050 module_exit(ath11k_pci_exit); 1051 1052 MODULE_DESCRIPTION("Driver support for Qualcomm Technologies PCIe 802.11ax WLAN devices"); 1053 MODULE_LICENSE("Dual BSD/GPL"); 1054 1055 /* firmware files */ 1056 MODULE_FIRMWARE(ATH11K_FW_DIR "/QCA6390/hw2.0/*"); 1057 MODULE_FIRMWARE(ATH11K_FW_DIR "/QCN9074/hw1.0/*"); 1058 MODULE_FIRMWARE(ATH11K_FW_DIR "/WCN6855/hw2.0/*"); 1059 MODULE_FIRMWARE(ATH11K_FW_DIR "/WCN6855/hw2.1/*"); 1060