1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* Copyright (c) 2020 The Linux Foundation. All rights reserved. */ 3 4 #include <linux/msi.h> 5 #include <linux/pci.h> 6 #include <linux/of.h> 7 #include <linux/of_address.h> 8 #include <linux/ioport.h> 9 10 #include "core.h" 11 #include "debug.h" 12 #include "mhi.h" 13 #include "pci.h" 14 15 #define MHI_TIMEOUT_DEFAULT_MS 90000 16 17 static struct mhi_channel_config ath11k_mhi_channels_qca6390[] = { 18 { 19 .num = 0, 20 .name = "LOOPBACK", 21 .num_elements = 32, 22 .event_ring = 0, 23 .dir = DMA_TO_DEVICE, 24 .ee_mask = 0x4, 25 .pollcfg = 0, 26 .doorbell = MHI_DB_BRST_DISABLE, 27 .lpm_notify = false, 28 .offload_channel = false, 29 .doorbell_mode_switch = false, 30 .auto_queue = false, 31 }, 32 { 33 .num = 1, 34 .name = "LOOPBACK", 35 .num_elements = 32, 36 .event_ring = 0, 37 .dir = DMA_FROM_DEVICE, 38 .ee_mask = 0x4, 39 .pollcfg = 0, 40 .doorbell = MHI_DB_BRST_DISABLE, 41 .lpm_notify = false, 42 .offload_channel = false, 43 .doorbell_mode_switch = false, 44 .auto_queue = false, 45 }, 46 { 47 .num = 20, 48 .name = "IPCR", 49 .num_elements = 64, 50 .event_ring = 1, 51 .dir = DMA_TO_DEVICE, 52 .ee_mask = 0x4, 53 .pollcfg = 0, 54 .doorbell = MHI_DB_BRST_DISABLE, 55 .lpm_notify = false, 56 .offload_channel = false, 57 .doorbell_mode_switch = false, 58 .auto_queue = false, 59 }, 60 { 61 .num = 21, 62 .name = "IPCR", 63 .num_elements = 64, 64 .event_ring = 1, 65 .dir = DMA_FROM_DEVICE, 66 .ee_mask = 0x4, 67 .pollcfg = 0, 68 .doorbell = MHI_DB_BRST_DISABLE, 69 .lpm_notify = false, 70 .offload_channel = false, 71 .doorbell_mode_switch = false, 72 .auto_queue = true, 73 }, 74 }; 75 76 static struct mhi_event_config ath11k_mhi_events_qca6390[] = { 77 { 78 .num_elements = 32, 79 .irq_moderation_ms = 0, 80 .irq = 1, 81 .mode = MHI_DB_BRST_DISABLE, 82 .data_type = MHI_ER_CTRL, 83 .hardware_event = false, 84 .client_managed = false, 85 .offload_channel = false, 86 }, 87 { 88 .num_elements = 256, 89 .irq_moderation_ms = 1, 90 .irq = 2, 91 .mode = MHI_DB_BRST_DISABLE, 92 .priority = 1, 93 .hardware_event = false, 94 .client_managed = false, 95 .offload_channel = false, 96 }, 97 }; 98 99 static struct mhi_controller_config ath11k_mhi_config_qca6390 = { 100 .max_channels = 128, 101 .timeout_ms = 2000, 102 .use_bounce_buf = false, 103 .buf_len = 0, 104 .num_channels = ARRAY_SIZE(ath11k_mhi_channels_qca6390), 105 .ch_cfg = ath11k_mhi_channels_qca6390, 106 .num_events = ARRAY_SIZE(ath11k_mhi_events_qca6390), 107 .event_cfg = ath11k_mhi_events_qca6390, 108 }; 109 110 static struct mhi_channel_config ath11k_mhi_channels_qcn9074[] = { 111 { 112 .num = 0, 113 .name = "LOOPBACK", 114 .num_elements = 32, 115 .event_ring = 1, 116 .dir = DMA_TO_DEVICE, 117 .ee_mask = 0x14, 118 .pollcfg = 0, 119 .doorbell = MHI_DB_BRST_DISABLE, 120 .lpm_notify = false, 121 .offload_channel = false, 122 .doorbell_mode_switch = false, 123 .auto_queue = false, 124 }, 125 { 126 .num = 1, 127 .name = "LOOPBACK", 128 .num_elements = 32, 129 .event_ring = 1, 130 .dir = DMA_FROM_DEVICE, 131 .ee_mask = 0x14, 132 .pollcfg = 0, 133 .doorbell = MHI_DB_BRST_DISABLE, 134 .lpm_notify = false, 135 .offload_channel = false, 136 .doorbell_mode_switch = false, 137 .auto_queue = false, 138 }, 139 { 140 .num = 20, 141 .name = "IPCR", 142 .num_elements = 32, 143 .event_ring = 1, 144 .dir = DMA_TO_DEVICE, 145 .ee_mask = 0x14, 146 .pollcfg = 0, 147 .doorbell = MHI_DB_BRST_DISABLE, 148 .lpm_notify = false, 149 .offload_channel = false, 150 .doorbell_mode_switch = false, 151 .auto_queue = false, 152 }, 153 { 154 .num = 21, 155 .name = "IPCR", 156 .num_elements = 32, 157 .event_ring = 1, 158 .dir = DMA_FROM_DEVICE, 159 .ee_mask = 0x14, 160 .pollcfg = 0, 161 .doorbell = MHI_DB_BRST_DISABLE, 162 .lpm_notify = false, 163 .offload_channel = false, 164 .doorbell_mode_switch = false, 165 .auto_queue = true, 166 }, 167 }; 168 169 static struct mhi_event_config ath11k_mhi_events_qcn9074[] = { 170 { 171 .num_elements = 32, 172 .irq_moderation_ms = 0, 173 .irq = 1, 174 .data_type = MHI_ER_CTRL, 175 .mode = MHI_DB_BRST_DISABLE, 176 .hardware_event = false, 177 .client_managed = false, 178 .offload_channel = false, 179 }, 180 { 181 .num_elements = 256, 182 .irq_moderation_ms = 1, 183 .irq = 2, 184 .mode = MHI_DB_BRST_DISABLE, 185 .priority = 1, 186 .hardware_event = false, 187 .client_managed = false, 188 .offload_channel = false, 189 }, 190 }; 191 192 static struct mhi_controller_config ath11k_mhi_config_qcn9074 = { 193 .max_channels = 30, 194 .timeout_ms = 10000, 195 .use_bounce_buf = false, 196 .buf_len = 0, 197 .num_channels = ARRAY_SIZE(ath11k_mhi_channels_qcn9074), 198 .ch_cfg = ath11k_mhi_channels_qcn9074, 199 .num_events = ARRAY_SIZE(ath11k_mhi_events_qcn9074), 200 .event_cfg = ath11k_mhi_events_qcn9074, 201 }; 202 203 void ath11k_mhi_set_mhictrl_reset(struct ath11k_base *ab) 204 { 205 u32 val; 206 207 val = ath11k_pci_read32(ab, MHISTATUS); 208 209 ath11k_dbg(ab, ATH11K_DBG_PCI, "MHISTATUS 0x%x\n", val); 210 211 /* Observed on QCA6390 that after SOC_GLOBAL_RESET, MHISTATUS 212 * has SYSERR bit set and thus need to set MHICTRL_RESET 213 * to clear SYSERR. 214 */ 215 ath11k_pci_write32(ab, MHICTRL, MHICTRL_RESET_MASK); 216 217 mdelay(10); 218 } 219 220 static void ath11k_mhi_reset_txvecdb(struct ath11k_base *ab) 221 { 222 ath11k_pci_write32(ab, PCIE_TXVECDB, 0); 223 } 224 225 static void ath11k_mhi_reset_txvecstatus(struct ath11k_base *ab) 226 { 227 ath11k_pci_write32(ab, PCIE_TXVECSTATUS, 0); 228 } 229 230 static void ath11k_mhi_reset_rxvecdb(struct ath11k_base *ab) 231 { 232 ath11k_pci_write32(ab, PCIE_RXVECDB, 0); 233 } 234 235 static void ath11k_mhi_reset_rxvecstatus(struct ath11k_base *ab) 236 { 237 ath11k_pci_write32(ab, PCIE_RXVECSTATUS, 0); 238 } 239 240 void ath11k_mhi_clear_vector(struct ath11k_base *ab) 241 { 242 ath11k_mhi_reset_txvecdb(ab); 243 ath11k_mhi_reset_txvecstatus(ab); 244 ath11k_mhi_reset_rxvecdb(ab); 245 ath11k_mhi_reset_rxvecstatus(ab); 246 } 247 248 static int ath11k_mhi_get_msi(struct ath11k_pci *ab_pci) 249 { 250 struct ath11k_base *ab = ab_pci->ab; 251 u32 user_base_data, base_vector; 252 int ret, num_vectors, i; 253 int *irq; 254 unsigned int msi_data; 255 256 ret = ath11k_pci_get_user_msi_assignment(ab_pci, 257 "MHI", &num_vectors, 258 &user_base_data, &base_vector); 259 if (ret) 260 return ret; 261 262 ath11k_dbg(ab, ATH11K_DBG_PCI, "Number of assigned MSI for MHI is %d, base vector is %d\n", 263 num_vectors, base_vector); 264 265 irq = kcalloc(num_vectors, sizeof(int), GFP_KERNEL); 266 if (!irq) 267 return -ENOMEM; 268 269 for (i = 0; i < num_vectors; i++) { 270 msi_data = base_vector; 271 272 if (test_bit(ATH11K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags)) 273 msi_data += i; 274 275 irq[i] = ath11k_pci_get_msi_irq(ab->dev, 276 msi_data); 277 } 278 279 ab_pci->mhi_ctrl->irq = irq; 280 ab_pci->mhi_ctrl->nr_irqs = num_vectors; 281 282 return 0; 283 } 284 285 static int ath11k_mhi_op_runtime_get(struct mhi_controller *mhi_cntrl) 286 { 287 return 0; 288 } 289 290 static void ath11k_mhi_op_runtime_put(struct mhi_controller *mhi_cntrl) 291 { 292 } 293 294 static void ath11k_mhi_op_status_cb(struct mhi_controller *mhi_cntrl, 295 enum mhi_callback cb) 296 { 297 struct ath11k_base *ab = dev_get_drvdata(mhi_cntrl->cntrl_dev); 298 299 switch (cb) { 300 case MHI_CB_SYS_ERROR: 301 ath11k_warn(ab, "firmware crashed: MHI_CB_SYS_ERROR\n"); 302 break; 303 default: 304 break; 305 } 306 } 307 308 static int ath11k_mhi_op_read_reg(struct mhi_controller *mhi_cntrl, 309 void __iomem *addr, 310 u32 *out) 311 { 312 *out = readl(addr); 313 314 return 0; 315 } 316 317 static void ath11k_mhi_op_write_reg(struct mhi_controller *mhi_cntrl, 318 void __iomem *addr, 319 u32 val) 320 { 321 writel(val, addr); 322 } 323 324 static int ath11k_mhi_read_addr_from_dt(struct mhi_controller *mhi_ctrl) 325 { 326 struct device_node *np; 327 struct resource res; 328 int ret; 329 330 np = of_find_node_by_type(NULL, "memory"); 331 if (!np) 332 return -ENOENT; 333 334 ret = of_address_to_resource(np, 0, &res); 335 of_node_put(np); 336 if (ret) 337 return ret; 338 339 mhi_ctrl->iova_start = res.start + 0x1000000; 340 mhi_ctrl->iova_stop = res.end; 341 342 return 0; 343 } 344 345 int ath11k_mhi_register(struct ath11k_pci *ab_pci) 346 { 347 struct ath11k_base *ab = ab_pci->ab; 348 struct mhi_controller *mhi_ctrl; 349 struct mhi_controller_config *ath11k_mhi_config; 350 int ret; 351 352 mhi_ctrl = mhi_alloc_controller(); 353 if (!mhi_ctrl) 354 return -ENOMEM; 355 356 ath11k_core_create_firmware_path(ab, ATH11K_AMSS_FILE, 357 ab_pci->amss_path, 358 sizeof(ab_pci->amss_path)); 359 360 ab_pci->mhi_ctrl = mhi_ctrl; 361 mhi_ctrl->cntrl_dev = ab->dev; 362 mhi_ctrl->fw_image = ab_pci->amss_path; 363 mhi_ctrl->regs = ab->mem; 364 mhi_ctrl->reg_len = ab->mem_len; 365 366 ret = ath11k_mhi_get_msi(ab_pci); 367 if (ret) { 368 ath11k_err(ab, "failed to get msi for mhi\n"); 369 mhi_free_controller(mhi_ctrl); 370 return ret; 371 } 372 373 if (!test_bit(ATH11K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags)) 374 mhi_ctrl->irq_flags = IRQF_SHARED | IRQF_NOBALANCING; 375 376 if (test_bit(ATH11K_FLAG_FIXED_MEM_RGN, &ab->dev_flags)) { 377 ret = ath11k_mhi_read_addr_from_dt(mhi_ctrl); 378 if (ret < 0) 379 return ret; 380 } else { 381 mhi_ctrl->iova_start = 0; 382 mhi_ctrl->iova_stop = 0xFFFFFFFF; 383 } 384 385 mhi_ctrl->sbl_size = SZ_512K; 386 mhi_ctrl->seg_len = SZ_512K; 387 mhi_ctrl->fbc_download = true; 388 mhi_ctrl->runtime_get = ath11k_mhi_op_runtime_get; 389 mhi_ctrl->runtime_put = ath11k_mhi_op_runtime_put; 390 mhi_ctrl->status_cb = ath11k_mhi_op_status_cb; 391 mhi_ctrl->read_reg = ath11k_mhi_op_read_reg; 392 mhi_ctrl->write_reg = ath11k_mhi_op_write_reg; 393 394 switch (ab->hw_rev) { 395 case ATH11K_HW_QCN9074_HW10: 396 ath11k_mhi_config = &ath11k_mhi_config_qcn9074; 397 break; 398 case ATH11K_HW_QCA6390_HW20: 399 case ATH11K_HW_WCN6855_HW20: 400 case ATH11K_HW_WCN6855_HW21: 401 ath11k_mhi_config = &ath11k_mhi_config_qca6390; 402 break; 403 default: 404 ath11k_err(ab, "failed assign mhi_config for unknown hw rev %d\n", 405 ab->hw_rev); 406 mhi_free_controller(mhi_ctrl); 407 return -EINVAL; 408 } 409 410 ret = mhi_register_controller(mhi_ctrl, ath11k_mhi_config); 411 if (ret) { 412 ath11k_err(ab, "failed to register to mhi bus, err = %d\n", ret); 413 mhi_free_controller(mhi_ctrl); 414 return ret; 415 } 416 417 return 0; 418 } 419 420 void ath11k_mhi_unregister(struct ath11k_pci *ab_pci) 421 { 422 struct mhi_controller *mhi_ctrl = ab_pci->mhi_ctrl; 423 424 mhi_unregister_controller(mhi_ctrl); 425 kfree(mhi_ctrl->irq); 426 mhi_free_controller(mhi_ctrl); 427 } 428 429 static char *ath11k_mhi_state_to_str(enum ath11k_mhi_state mhi_state) 430 { 431 switch (mhi_state) { 432 case ATH11K_MHI_INIT: 433 return "INIT"; 434 case ATH11K_MHI_DEINIT: 435 return "DEINIT"; 436 case ATH11K_MHI_POWER_ON: 437 return "POWER_ON"; 438 case ATH11K_MHI_POWER_OFF: 439 return "POWER_OFF"; 440 case ATH11K_MHI_FORCE_POWER_OFF: 441 return "FORCE_POWER_OFF"; 442 case ATH11K_MHI_SUSPEND: 443 return "SUSPEND"; 444 case ATH11K_MHI_RESUME: 445 return "RESUME"; 446 case ATH11K_MHI_TRIGGER_RDDM: 447 return "TRIGGER_RDDM"; 448 case ATH11K_MHI_RDDM_DONE: 449 return "RDDM_DONE"; 450 default: 451 return "UNKNOWN"; 452 } 453 }; 454 455 static void ath11k_mhi_set_state_bit(struct ath11k_pci *ab_pci, 456 enum ath11k_mhi_state mhi_state) 457 { 458 struct ath11k_base *ab = ab_pci->ab; 459 460 switch (mhi_state) { 461 case ATH11K_MHI_INIT: 462 set_bit(ATH11K_MHI_INIT, &ab_pci->mhi_state); 463 break; 464 case ATH11K_MHI_DEINIT: 465 clear_bit(ATH11K_MHI_INIT, &ab_pci->mhi_state); 466 break; 467 case ATH11K_MHI_POWER_ON: 468 set_bit(ATH11K_MHI_POWER_ON, &ab_pci->mhi_state); 469 break; 470 case ATH11K_MHI_POWER_OFF: 471 case ATH11K_MHI_FORCE_POWER_OFF: 472 clear_bit(ATH11K_MHI_POWER_ON, &ab_pci->mhi_state); 473 clear_bit(ATH11K_MHI_TRIGGER_RDDM, &ab_pci->mhi_state); 474 clear_bit(ATH11K_MHI_RDDM_DONE, &ab_pci->mhi_state); 475 break; 476 case ATH11K_MHI_SUSPEND: 477 set_bit(ATH11K_MHI_SUSPEND, &ab_pci->mhi_state); 478 break; 479 case ATH11K_MHI_RESUME: 480 clear_bit(ATH11K_MHI_SUSPEND, &ab_pci->mhi_state); 481 break; 482 case ATH11K_MHI_TRIGGER_RDDM: 483 set_bit(ATH11K_MHI_TRIGGER_RDDM, &ab_pci->mhi_state); 484 break; 485 case ATH11K_MHI_RDDM_DONE: 486 set_bit(ATH11K_MHI_RDDM_DONE, &ab_pci->mhi_state); 487 break; 488 default: 489 ath11k_err(ab, "unhandled mhi state (%d)\n", mhi_state); 490 } 491 } 492 493 static int ath11k_mhi_check_state_bit(struct ath11k_pci *ab_pci, 494 enum ath11k_mhi_state mhi_state) 495 { 496 struct ath11k_base *ab = ab_pci->ab; 497 498 switch (mhi_state) { 499 case ATH11K_MHI_INIT: 500 if (!test_bit(ATH11K_MHI_INIT, &ab_pci->mhi_state)) 501 return 0; 502 break; 503 case ATH11K_MHI_DEINIT: 504 case ATH11K_MHI_POWER_ON: 505 if (test_bit(ATH11K_MHI_INIT, &ab_pci->mhi_state) && 506 !test_bit(ATH11K_MHI_POWER_ON, &ab_pci->mhi_state)) 507 return 0; 508 break; 509 case ATH11K_MHI_FORCE_POWER_OFF: 510 if (test_bit(ATH11K_MHI_POWER_ON, &ab_pci->mhi_state)) 511 return 0; 512 break; 513 case ATH11K_MHI_POWER_OFF: 514 case ATH11K_MHI_SUSPEND: 515 if (test_bit(ATH11K_MHI_POWER_ON, &ab_pci->mhi_state) && 516 !test_bit(ATH11K_MHI_SUSPEND, &ab_pci->mhi_state)) 517 return 0; 518 break; 519 case ATH11K_MHI_RESUME: 520 if (test_bit(ATH11K_MHI_SUSPEND, &ab_pci->mhi_state)) 521 return 0; 522 break; 523 case ATH11K_MHI_TRIGGER_RDDM: 524 if (test_bit(ATH11K_MHI_POWER_ON, &ab_pci->mhi_state) && 525 !test_bit(ATH11K_MHI_TRIGGER_RDDM, &ab_pci->mhi_state)) 526 return 0; 527 break; 528 case ATH11K_MHI_RDDM_DONE: 529 return 0; 530 default: 531 ath11k_err(ab, "unhandled mhi state: %s(%d)\n", 532 ath11k_mhi_state_to_str(mhi_state), mhi_state); 533 } 534 535 ath11k_err(ab, "failed to set mhi state %s(%d) in current mhi state (0x%lx)\n", 536 ath11k_mhi_state_to_str(mhi_state), mhi_state, 537 ab_pci->mhi_state); 538 539 return -EINVAL; 540 } 541 542 static int ath11k_mhi_set_state(struct ath11k_pci *ab_pci, 543 enum ath11k_mhi_state mhi_state) 544 { 545 struct ath11k_base *ab = ab_pci->ab; 546 int ret; 547 548 ret = ath11k_mhi_check_state_bit(ab_pci, mhi_state); 549 if (ret) 550 goto out; 551 552 ath11k_dbg(ab, ATH11K_DBG_PCI, "setting mhi state: %s(%d)\n", 553 ath11k_mhi_state_to_str(mhi_state), mhi_state); 554 555 switch (mhi_state) { 556 case ATH11K_MHI_INIT: 557 ret = mhi_prepare_for_power_up(ab_pci->mhi_ctrl); 558 break; 559 case ATH11K_MHI_DEINIT: 560 mhi_unprepare_after_power_down(ab_pci->mhi_ctrl); 561 ret = 0; 562 break; 563 case ATH11K_MHI_POWER_ON: 564 ret = mhi_async_power_up(ab_pci->mhi_ctrl); 565 break; 566 case ATH11K_MHI_POWER_OFF: 567 mhi_power_down(ab_pci->mhi_ctrl, true); 568 ret = 0; 569 break; 570 case ATH11K_MHI_FORCE_POWER_OFF: 571 mhi_power_down(ab_pci->mhi_ctrl, false); 572 ret = 0; 573 break; 574 case ATH11K_MHI_SUSPEND: 575 ret = mhi_pm_suspend(ab_pci->mhi_ctrl); 576 break; 577 case ATH11K_MHI_RESUME: 578 /* Do force MHI resume as some devices like QCA6390, WCN6855 579 * are not in M3 state but they are functional. So just ignore 580 * the MHI state while resuming. 581 */ 582 ret = mhi_pm_resume_force(ab_pci->mhi_ctrl); 583 break; 584 case ATH11K_MHI_TRIGGER_RDDM: 585 ret = mhi_force_rddm_mode(ab_pci->mhi_ctrl); 586 break; 587 case ATH11K_MHI_RDDM_DONE: 588 break; 589 default: 590 ath11k_err(ab, "unhandled MHI state (%d)\n", mhi_state); 591 ret = -EINVAL; 592 } 593 594 if (ret) 595 goto out; 596 597 ath11k_mhi_set_state_bit(ab_pci, mhi_state); 598 599 return 0; 600 601 out: 602 ath11k_err(ab, "failed to set mhi state: %s(%d)\n", 603 ath11k_mhi_state_to_str(mhi_state), mhi_state); 604 return ret; 605 } 606 607 int ath11k_mhi_start(struct ath11k_pci *ab_pci) 608 { 609 int ret; 610 611 ab_pci->mhi_ctrl->timeout_ms = MHI_TIMEOUT_DEFAULT_MS; 612 613 ret = ath11k_mhi_set_state(ab_pci, ATH11K_MHI_INIT); 614 if (ret) 615 goto out; 616 617 ret = ath11k_mhi_set_state(ab_pci, ATH11K_MHI_POWER_ON); 618 if (ret) 619 goto out; 620 621 return 0; 622 623 out: 624 return ret; 625 } 626 627 void ath11k_mhi_stop(struct ath11k_pci *ab_pci) 628 { 629 ath11k_mhi_set_state(ab_pci, ATH11K_MHI_POWER_OFF); 630 ath11k_mhi_set_state(ab_pci, ATH11K_MHI_DEINIT); 631 } 632 633 void ath11k_mhi_suspend(struct ath11k_pci *ab_pci) 634 { 635 ath11k_mhi_set_state(ab_pci, ATH11K_MHI_SUSPEND); 636 } 637 638 void ath11k_mhi_resume(struct ath11k_pci *ab_pci) 639 { 640 ath11k_mhi_set_state(ab_pci, ATH11K_MHI_RESUME); 641 } 642