1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef ATH11K_HW_H 7 #define ATH11K_HW_H 8 9 #include "wmi.h" 10 11 /* Target configuration defines */ 12 13 /* Num VDEVS per radio */ 14 #define TARGET_NUM_VDEVS (16 + 1) 15 16 #define TARGET_NUM_PEERS_PDEV (512 + TARGET_NUM_VDEVS) 17 18 /* Num of peers for Single Radio mode */ 19 #define TARGET_NUM_PEERS_SINGLE (TARGET_NUM_PEERS_PDEV) 20 21 /* Num of peers for DBS */ 22 #define TARGET_NUM_PEERS_DBS (2 * TARGET_NUM_PEERS_PDEV) 23 24 /* Num of peers for DBS_SBS */ 25 #define TARGET_NUM_PEERS_DBS_SBS (3 * TARGET_NUM_PEERS_PDEV) 26 27 /* Max num of stations (per radio) */ 28 #define TARGET_NUM_STATIONS 512 29 30 #define TARGET_NUM_PEERS(x) TARGET_NUM_PEERS_##x 31 #define TARGET_NUM_PEER_KEYS 2 32 #define TARGET_NUM_TIDS(x) (2 * TARGET_NUM_PEERS(x) + \ 33 4 * TARGET_NUM_VDEVS + 8) 34 35 #define TARGET_AST_SKID_LIMIT 16 36 #define TARGET_NUM_OFFLD_PEERS 4 37 #define TARGET_NUM_OFFLD_REORDER_BUFFS 4 38 39 #define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(4)) 40 #define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(4)) 41 #define TARGET_RX_TIMEOUT_LO_PRI 100 42 #define TARGET_RX_TIMEOUT_HI_PRI 40 43 44 #define TARGET_DECAP_MODE_RAW 0 45 #define TARGET_DECAP_MODE_NATIVE_WIFI 1 46 #define TARGET_DECAP_MODE_ETH 2 47 48 #define TARGET_SCAN_MAX_PENDING_REQS 4 49 #define TARGET_BMISS_OFFLOAD_MAX_VDEV 3 50 #define TARGET_ROAM_OFFLOAD_MAX_VDEV 3 51 #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8 52 #define TARGET_GTK_OFFLOAD_MAX_VDEV 3 53 #define TARGET_NUM_MCAST_GROUPS 12 54 #define TARGET_NUM_MCAST_TABLE_ELEMS 64 55 #define TARGET_MCAST2UCAST_MODE 2 56 #define TARGET_TX_DBG_LOG_SIZE 1024 57 #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1 58 #define TARGET_VOW_CONFIG 0 59 #define TARGET_NUM_MSDU_DESC (2500) 60 #define TARGET_MAX_FRAG_ENTRIES 6 61 #define TARGET_MAX_BCN_OFFLD 16 62 #define TARGET_NUM_WDS_ENTRIES 32 63 #define TARGET_DMA_BURST_SIZE 1 64 #define TARGET_RX_BATCHMODE 1 65 66 #define ATH11K_HW_MAX_QUEUES 4 67 #define ATH11K_QUEUE_LEN 4096 68 69 #define ATH11k_HW_RATECODE_CCK_SHORT_PREAM_MASK 0x4 70 71 #define ATH11K_FW_DIR "ath11k" 72 73 #define ATH11K_BOARD_MAGIC "QCA-ATH11K-BOARD" 74 #define ATH11K_BOARD_API2_FILE "board-2.bin" 75 #define ATH11K_DEFAULT_BOARD_FILE "board.bin" 76 #define ATH11K_DEFAULT_CAL_FILE "caldata.bin" 77 #define ATH11K_AMSS_FILE "amss.bin" 78 #define ATH11K_M3_FILE "m3.bin" 79 80 enum ath11k_hw_rate_cck { 81 ATH11K_HW_RATE_CCK_LP_11M = 0, 82 ATH11K_HW_RATE_CCK_LP_5_5M, 83 ATH11K_HW_RATE_CCK_LP_2M, 84 ATH11K_HW_RATE_CCK_LP_1M, 85 ATH11K_HW_RATE_CCK_SP_11M, 86 ATH11K_HW_RATE_CCK_SP_5_5M, 87 ATH11K_HW_RATE_CCK_SP_2M, 88 }; 89 90 enum ath11k_hw_rate_ofdm { 91 ATH11K_HW_RATE_OFDM_48M = 0, 92 ATH11K_HW_RATE_OFDM_24M, 93 ATH11K_HW_RATE_OFDM_12M, 94 ATH11K_HW_RATE_OFDM_6M, 95 ATH11K_HW_RATE_OFDM_54M, 96 ATH11K_HW_RATE_OFDM_36M, 97 ATH11K_HW_RATE_OFDM_18M, 98 ATH11K_HW_RATE_OFDM_9M, 99 }; 100 101 enum ath11k_bus { 102 ATH11K_BUS_AHB, 103 ATH11K_BUS_PCI, 104 }; 105 106 #define ATH11K_EXT_IRQ_GRP_NUM_MAX 11 107 108 struct hal_rx_desc; 109 struct hal_tcl_data_cmd; 110 111 struct ath11k_hw_ring_mask { 112 u8 tx[ATH11K_EXT_IRQ_GRP_NUM_MAX]; 113 u8 rx_mon_status[ATH11K_EXT_IRQ_GRP_NUM_MAX]; 114 u8 rx[ATH11K_EXT_IRQ_GRP_NUM_MAX]; 115 u8 rx_err[ATH11K_EXT_IRQ_GRP_NUM_MAX]; 116 u8 rx_wbm_rel[ATH11K_EXT_IRQ_GRP_NUM_MAX]; 117 u8 reo_status[ATH11K_EXT_IRQ_GRP_NUM_MAX]; 118 u8 rxdma2host[ATH11K_EXT_IRQ_GRP_NUM_MAX]; 119 u8 host2rxdma[ATH11K_EXT_IRQ_GRP_NUM_MAX]; 120 }; 121 122 struct ath11k_hw_params { 123 const char *name; 124 u16 hw_rev; 125 u8 max_radios; 126 u32 bdf_addr; 127 128 struct { 129 const char *dir; 130 size_t board_size; 131 size_t cal_size; 132 } fw; 133 134 const struct ath11k_hw_ops *hw_ops; 135 const struct ath11k_hw_ring_mask *ring_mask; 136 137 bool internal_sleep_clock; 138 139 const struct ath11k_hw_regs *regs; 140 u32 qmi_service_ins_id; 141 const struct ce_attr *host_ce_config; 142 u32 ce_count; 143 const struct ce_pipe_config *target_ce_config; 144 u32 target_ce_count; 145 const struct service_to_pipe *svc_to_ce_map; 146 u32 svc_to_ce_map_len; 147 148 bool single_pdev_only; 149 150 bool rxdma1_enable; 151 int num_rxmda_per_pdev; 152 bool rx_mac_buf_ring; 153 bool vdev_start_delay; 154 bool htt_peer_map_v2; 155 bool tcl_0_only; 156 u8 spectral_fft_sz; 157 158 u16 interface_modes; 159 bool supports_monitor; 160 bool supports_shadow_regs; 161 bool idle_ps; 162 bool cold_boot_calib; 163 bool supports_suspend; 164 u32 hal_desc_sz; 165 bool fix_l1ss; 166 }; 167 168 struct ath11k_hw_ops { 169 u8 (*get_hw_mac_from_pdev_id)(int pdev_id); 170 void (*wmi_init_config)(struct ath11k_base *ab, 171 struct target_resource_config *config); 172 int (*mac_id_to_pdev_id)(struct ath11k_hw_params *hw, int mac_id); 173 int (*mac_id_to_srng_id)(struct ath11k_hw_params *hw, int mac_id); 174 void (*tx_mesh_enable)(struct ath11k_base *ab, 175 struct hal_tcl_data_cmd *tcl_cmd); 176 bool (*rx_desc_get_first_msdu)(struct hal_rx_desc *desc); 177 bool (*rx_desc_get_last_msdu)(struct hal_rx_desc *desc); 178 u8 (*rx_desc_get_l3_pad_bytes)(struct hal_rx_desc *desc); 179 u8 *(*rx_desc_get_hdr_status)(struct hal_rx_desc *desc); 180 bool (*rx_desc_encrypt_valid)(struct hal_rx_desc *desc); 181 u32 (*rx_desc_get_encrypt_type)(struct hal_rx_desc *desc); 182 u8 (*rx_desc_get_decap_type)(struct hal_rx_desc *desc); 183 u8 (*rx_desc_get_mesh_ctl)(struct hal_rx_desc *desc); 184 bool (*rx_desc_get_mpdu_seq_ctl_vld)(struct hal_rx_desc *desc); 185 bool (*rx_desc_get_mpdu_fc_valid)(struct hal_rx_desc *desc); 186 u16 (*rx_desc_get_mpdu_start_seq_no)(struct hal_rx_desc *desc); 187 u16 (*rx_desc_get_msdu_len)(struct hal_rx_desc *desc); 188 u8 (*rx_desc_get_msdu_sgi)(struct hal_rx_desc *desc); 189 u8 (*rx_desc_get_msdu_rate_mcs)(struct hal_rx_desc *desc); 190 u8 (*rx_desc_get_msdu_rx_bw)(struct hal_rx_desc *desc); 191 u32 (*rx_desc_get_msdu_freq)(struct hal_rx_desc *desc); 192 u8 (*rx_desc_get_msdu_pkt_type)(struct hal_rx_desc *desc); 193 u8 (*rx_desc_get_msdu_nss)(struct hal_rx_desc *desc); 194 u8 (*rx_desc_get_mpdu_tid)(struct hal_rx_desc *desc); 195 u16 (*rx_desc_get_mpdu_peer_id)(struct hal_rx_desc *desc); 196 void (*rx_desc_copy_attn_end_tlv)(struct hal_rx_desc *fdesc, 197 struct hal_rx_desc *ldesc); 198 u32 (*rx_desc_get_mpdu_start_tag)(struct hal_rx_desc *desc); 199 u32 (*rx_desc_get_mpdu_ppdu_id)(struct hal_rx_desc *desc); 200 void (*rx_desc_set_msdu_len)(struct hal_rx_desc *desc, u16 len); 201 struct rx_attention *(*rx_desc_get_attention)(struct hal_rx_desc *desc); 202 u8 *(*rx_desc_get_msdu_payload)(struct hal_rx_desc *desc); 203 void (*reo_setup)(struct ath11k_base *ab); 204 u16 (*mpdu_info_get_peerid)(u8 *tlv_data); 205 }; 206 207 extern const struct ath11k_hw_ops ipq8074_ops; 208 extern const struct ath11k_hw_ops ipq6018_ops; 209 extern const struct ath11k_hw_ops qca6390_ops; 210 extern const struct ath11k_hw_ops qcn9074_ops; 211 extern const struct ath11k_hw_ops wcn6855_ops; 212 213 extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_ipq8074; 214 extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qca6390; 215 extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qcn9074; 216 217 static inline 218 int ath11k_hw_get_mac_from_pdev_id(struct ath11k_hw_params *hw, 219 int pdev_idx) 220 { 221 if (hw->hw_ops->get_hw_mac_from_pdev_id) 222 return hw->hw_ops->get_hw_mac_from_pdev_id(pdev_idx); 223 224 return 0; 225 } 226 227 static inline int ath11k_hw_mac_id_to_pdev_id(struct ath11k_hw_params *hw, 228 int mac_id) 229 { 230 if (hw->hw_ops->mac_id_to_pdev_id) 231 return hw->hw_ops->mac_id_to_pdev_id(hw, mac_id); 232 233 return 0; 234 } 235 236 static inline int ath11k_hw_mac_id_to_srng_id(struct ath11k_hw_params *hw, 237 int mac_id) 238 { 239 if (hw->hw_ops->mac_id_to_srng_id) 240 return hw->hw_ops->mac_id_to_srng_id(hw, mac_id); 241 242 return 0; 243 } 244 245 struct ath11k_fw_ie { 246 __le32 id; 247 __le32 len; 248 u8 data[]; 249 }; 250 251 enum ath11k_bd_ie_board_type { 252 ATH11K_BD_IE_BOARD_NAME = 0, 253 ATH11K_BD_IE_BOARD_DATA = 1, 254 }; 255 256 enum ath11k_bd_ie_type { 257 /* contains sub IEs of enum ath11k_bd_ie_board_type */ 258 ATH11K_BD_IE_BOARD = 0, 259 ATH11K_BD_IE_BOARD_EXT = 1, 260 }; 261 262 struct ath11k_hw_regs { 263 u32 hal_tcl1_ring_base_lsb; 264 u32 hal_tcl1_ring_base_msb; 265 u32 hal_tcl1_ring_id; 266 u32 hal_tcl1_ring_misc; 267 u32 hal_tcl1_ring_tp_addr_lsb; 268 u32 hal_tcl1_ring_tp_addr_msb; 269 u32 hal_tcl1_ring_consumer_int_setup_ix0; 270 u32 hal_tcl1_ring_consumer_int_setup_ix1; 271 u32 hal_tcl1_ring_msi1_base_lsb; 272 u32 hal_tcl1_ring_msi1_base_msb; 273 u32 hal_tcl1_ring_msi1_data; 274 u32 hal_tcl2_ring_base_lsb; 275 u32 hal_tcl_ring_base_lsb; 276 277 u32 hal_tcl_status_ring_base_lsb; 278 279 u32 hal_reo1_ring_base_lsb; 280 u32 hal_reo1_ring_base_msb; 281 u32 hal_reo1_ring_id; 282 u32 hal_reo1_ring_misc; 283 u32 hal_reo1_ring_hp_addr_lsb; 284 u32 hal_reo1_ring_hp_addr_msb; 285 u32 hal_reo1_ring_producer_int_setup; 286 u32 hal_reo1_ring_msi1_base_lsb; 287 u32 hal_reo1_ring_msi1_base_msb; 288 u32 hal_reo1_ring_msi1_data; 289 u32 hal_reo2_ring_base_lsb; 290 u32 hal_reo1_aging_thresh_ix_0; 291 u32 hal_reo1_aging_thresh_ix_1; 292 u32 hal_reo1_aging_thresh_ix_2; 293 u32 hal_reo1_aging_thresh_ix_3; 294 295 u32 hal_reo1_ring_hp; 296 u32 hal_reo1_ring_tp; 297 u32 hal_reo2_ring_hp; 298 299 u32 hal_reo_tcl_ring_base_lsb; 300 u32 hal_reo_tcl_ring_hp; 301 302 u32 hal_reo_status_ring_base_lsb; 303 u32 hal_reo_status_hp; 304 305 u32 hal_seq_wcss_umac_ce0_src_reg; 306 u32 hal_seq_wcss_umac_ce0_dst_reg; 307 u32 hal_seq_wcss_umac_ce1_src_reg; 308 u32 hal_seq_wcss_umac_ce1_dst_reg; 309 310 u32 hal_wbm_idle_link_ring_base_lsb; 311 u32 hal_wbm_idle_link_ring_misc; 312 313 u32 hal_wbm_release_ring_base_lsb; 314 315 u32 hal_wbm0_release_ring_base_lsb; 316 u32 hal_wbm1_release_ring_base_lsb; 317 318 u32 pcie_qserdes_sysclk_en_sel; 319 u32 pcie_pcs_osc_dtct_config_base; 320 }; 321 322 extern const struct ath11k_hw_regs ipq8074_regs; 323 extern const struct ath11k_hw_regs qca6390_regs; 324 extern const struct ath11k_hw_regs qcn9074_regs; 325 extern const struct ath11k_hw_regs wcn6855_regs; 326 327 #endif 328