1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2020 The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/types.h> 7 #include <linux/bitops.h> 8 #include <linux/bitfield.h> 9 10 #include "hw.h" 11 #include "core.h" 12 #include "ce.h" 13 #include "hif.h" 14 15 /* Map from pdev index to hw mac index */ 16 static u8 ath11k_hw_ipq8074_mac_from_pdev_id(int pdev_idx) 17 { 18 switch (pdev_idx) { 19 case 0: 20 return 0; 21 case 1: 22 return 2; 23 case 2: 24 return 1; 25 default: 26 return ATH11K_INVALID_HW_MAC_ID; 27 } 28 } 29 30 static u8 ath11k_hw_ipq6018_mac_from_pdev_id(int pdev_idx) 31 { 32 return pdev_idx; 33 } 34 35 static void ath11k_hw_ipq8074_tx_mesh_enable(struct ath11k_base *ab, 36 struct hal_tcl_data_cmd *tcl_cmd) 37 { 38 tcl_cmd->info2 |= FIELD_PREP(HAL_IPQ8074_TCL_DATA_CMD_INFO2_MESH_ENABLE, 39 true); 40 } 41 42 static void ath11k_hw_qcn9074_tx_mesh_enable(struct ath11k_base *ab, 43 struct hal_tcl_data_cmd *tcl_cmd) 44 { 45 tcl_cmd->info3 |= FIELD_PREP(HAL_QCN9074_TCL_DATA_CMD_INFO3_MESH_ENABLE, 46 true); 47 } 48 49 static void ath11k_hw_wcn6855_tx_mesh_enable(struct ath11k_base *ab, 50 struct hal_tcl_data_cmd *tcl_cmd) 51 { 52 tcl_cmd->info3 |= FIELD_PREP(HAL_QCN9074_TCL_DATA_CMD_INFO3_MESH_ENABLE, 53 true); 54 } 55 56 static void ath11k_init_wmi_config_qca6390(struct ath11k_base *ab, 57 struct target_resource_config *config) 58 { 59 config->num_vdevs = 4; 60 config->num_peers = 16; 61 config->num_tids = 32; 62 63 config->num_offload_peers = 3; 64 config->num_offload_reorder_buffs = 3; 65 config->num_peer_keys = TARGET_NUM_PEER_KEYS; 66 config->ast_skid_limit = TARGET_AST_SKID_LIMIT; 67 config->tx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 68 config->rx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 69 config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI; 70 config->rx_timeout_pri[1] = TARGET_RX_TIMEOUT_LO_PRI; 71 config->rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI; 72 config->rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI; 73 config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI; 74 config->scan_max_pending_req = TARGET_SCAN_MAX_PENDING_REQS; 75 config->bmiss_offload_max_vdev = TARGET_BMISS_OFFLOAD_MAX_VDEV; 76 config->roam_offload_max_vdev = TARGET_ROAM_OFFLOAD_MAX_VDEV; 77 config->roam_offload_max_ap_profiles = TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES; 78 config->num_mcast_groups = 0; 79 config->num_mcast_table_elems = 0; 80 config->mcast2ucast_mode = 0; 81 config->tx_dbg_log_size = TARGET_TX_DBG_LOG_SIZE; 82 config->num_wds_entries = 0; 83 config->dma_burst_size = 0; 84 config->rx_skip_defrag_timeout_dup_detection_check = 0; 85 config->vow_config = TARGET_VOW_CONFIG; 86 config->gtk_offload_max_vdev = 2; 87 config->num_msdu_desc = 0x400; 88 config->beacon_tx_offload_max_vdev = 2; 89 config->rx_batchmode = TARGET_RX_BATCHMODE; 90 91 config->peer_map_unmap_v2_support = 0; 92 config->use_pdev_id = 1; 93 config->max_frag_entries = 0xa; 94 config->num_tdls_vdevs = 0x1; 95 config->num_tdls_conn_table_entries = 8; 96 config->beacon_tx_offload_max_vdev = 0x2; 97 config->num_multicast_filter_entries = 0x20; 98 config->num_wow_filters = 0x16; 99 config->num_keep_alive_pattern = 0; 100 config->flag1 |= WMI_RSRC_CFG_FLAG1_BSS_CHANNEL_INFO_64; 101 } 102 103 static void ath11k_hw_ipq8074_reo_setup(struct ath11k_base *ab) 104 { 105 u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG; 106 u32 val; 107 /* Each hash entry uses three bits to map to a particular ring. */ 108 u32 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 | 109 HAL_HASH_ROUTING_RING_SW2 << 3 | 110 HAL_HASH_ROUTING_RING_SW3 << 6 | 111 HAL_HASH_ROUTING_RING_SW4 << 9 | 112 HAL_HASH_ROUTING_RING_SW1 << 12 | 113 HAL_HASH_ROUTING_RING_SW2 << 15 | 114 HAL_HASH_ROUTING_RING_SW3 << 18 | 115 HAL_HASH_ROUTING_RING_SW4 << 21; 116 117 val = ath11k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE); 118 119 val &= ~HAL_REO1_GEN_ENABLE_FRAG_DST_RING; 120 val |= FIELD_PREP(HAL_REO1_GEN_ENABLE_FRAG_DST_RING, 121 HAL_SRNG_RING_ID_REO2SW1) | 122 FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE, 1) | 123 FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE, 1); 124 ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val); 125 126 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab), 127 HAL_DEFAULT_REO_TIMEOUT_USEC); 128 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab), 129 HAL_DEFAULT_REO_TIMEOUT_USEC); 130 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab), 131 HAL_DEFAULT_REO_TIMEOUT_USEC); 132 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab), 133 HAL_DEFAULT_REO_TIMEOUT_USEC); 134 135 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_0, 136 FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP, 137 ring_hash_map)); 138 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_1, 139 FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP, 140 ring_hash_map)); 141 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2, 142 FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP, 143 ring_hash_map)); 144 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3, 145 FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP, 146 ring_hash_map)); 147 } 148 149 static void ath11k_init_wmi_config_ipq8074(struct ath11k_base *ab, 150 struct target_resource_config *config) 151 { 152 config->num_vdevs = ab->num_radios * TARGET_NUM_VDEVS; 153 154 if (ab->num_radios == 2) { 155 config->num_peers = TARGET_NUM_PEERS(DBS); 156 config->num_tids = TARGET_NUM_TIDS(DBS); 157 } else if (ab->num_radios == 3) { 158 config->num_peers = TARGET_NUM_PEERS(DBS_SBS); 159 config->num_tids = TARGET_NUM_TIDS(DBS_SBS); 160 } else { 161 /* Control should not reach here */ 162 config->num_peers = TARGET_NUM_PEERS(SINGLE); 163 config->num_tids = TARGET_NUM_TIDS(SINGLE); 164 } 165 config->num_offload_peers = TARGET_NUM_OFFLD_PEERS; 166 config->num_offload_reorder_buffs = TARGET_NUM_OFFLD_REORDER_BUFFS; 167 config->num_peer_keys = TARGET_NUM_PEER_KEYS; 168 config->ast_skid_limit = TARGET_AST_SKID_LIMIT; 169 config->tx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 170 config->rx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 171 config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI; 172 config->rx_timeout_pri[1] = TARGET_RX_TIMEOUT_LO_PRI; 173 config->rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI; 174 config->rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI; 175 176 if (test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags)) 177 config->rx_decap_mode = TARGET_DECAP_MODE_RAW; 178 else 179 config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI; 180 181 config->scan_max_pending_req = TARGET_SCAN_MAX_PENDING_REQS; 182 config->bmiss_offload_max_vdev = TARGET_BMISS_OFFLOAD_MAX_VDEV; 183 config->roam_offload_max_vdev = TARGET_ROAM_OFFLOAD_MAX_VDEV; 184 config->roam_offload_max_ap_profiles = TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES; 185 config->num_mcast_groups = TARGET_NUM_MCAST_GROUPS; 186 config->num_mcast_table_elems = TARGET_NUM_MCAST_TABLE_ELEMS; 187 config->mcast2ucast_mode = TARGET_MCAST2UCAST_MODE; 188 config->tx_dbg_log_size = TARGET_TX_DBG_LOG_SIZE; 189 config->num_wds_entries = TARGET_NUM_WDS_ENTRIES; 190 config->dma_burst_size = TARGET_DMA_BURST_SIZE; 191 config->rx_skip_defrag_timeout_dup_detection_check = 192 TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK; 193 config->vow_config = TARGET_VOW_CONFIG; 194 config->gtk_offload_max_vdev = TARGET_GTK_OFFLOAD_MAX_VDEV; 195 config->num_msdu_desc = TARGET_NUM_MSDU_DESC; 196 config->beacon_tx_offload_max_vdev = ab->num_radios * TARGET_MAX_BCN_OFFLD; 197 config->rx_batchmode = TARGET_RX_BATCHMODE; 198 config->peer_map_unmap_v2_support = 1; 199 config->twt_ap_pdev_count = ab->num_radios; 200 config->twt_ap_sta_count = 1000; 201 config->flag1 |= WMI_RSRC_CFG_FLAG1_BSS_CHANNEL_INFO_64; 202 } 203 204 static int ath11k_hw_mac_id_to_pdev_id_ipq8074(struct ath11k_hw_params *hw, 205 int mac_id) 206 { 207 return mac_id; 208 } 209 210 static int ath11k_hw_mac_id_to_srng_id_ipq8074(struct ath11k_hw_params *hw, 211 int mac_id) 212 { 213 return 0; 214 } 215 216 static int ath11k_hw_mac_id_to_pdev_id_qca6390(struct ath11k_hw_params *hw, 217 int mac_id) 218 { 219 return 0; 220 } 221 222 static int ath11k_hw_mac_id_to_srng_id_qca6390(struct ath11k_hw_params *hw, 223 int mac_id) 224 { 225 return mac_id; 226 } 227 228 static bool ath11k_hw_ipq8074_rx_desc_get_first_msdu(struct hal_rx_desc *desc) 229 { 230 return !!FIELD_GET(RX_MSDU_END_INFO2_FIRST_MSDU, 231 __le32_to_cpu(desc->u.ipq8074.msdu_end.info2)); 232 } 233 234 static bool ath11k_hw_ipq8074_rx_desc_get_last_msdu(struct hal_rx_desc *desc) 235 { 236 return !!FIELD_GET(RX_MSDU_END_INFO2_LAST_MSDU, 237 __le32_to_cpu(desc->u.ipq8074.msdu_end.info2)); 238 } 239 240 static u8 ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes(struct hal_rx_desc *desc) 241 { 242 return FIELD_GET(RX_MSDU_END_INFO2_L3_HDR_PADDING, 243 __le32_to_cpu(desc->u.ipq8074.msdu_end.info2)); 244 } 245 246 static u8 *ath11k_hw_ipq8074_rx_desc_get_hdr_status(struct hal_rx_desc *desc) 247 { 248 return desc->u.ipq8074.hdr_status; 249 } 250 251 static bool ath11k_hw_ipq8074_rx_desc_encrypt_valid(struct hal_rx_desc *desc) 252 { 253 return __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1) & 254 RX_MPDU_START_INFO1_ENCRYPT_INFO_VALID; 255 } 256 257 static u32 ath11k_hw_ipq8074_rx_desc_get_encrypt_type(struct hal_rx_desc *desc) 258 { 259 return FIELD_GET(RX_MPDU_START_INFO2_ENC_TYPE, 260 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info2)); 261 } 262 263 static u8 ath11k_hw_ipq8074_rx_desc_get_decap_type(struct hal_rx_desc *desc) 264 { 265 return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT, 266 __le32_to_cpu(desc->u.ipq8074.msdu_start.info2)); 267 } 268 269 static u8 ath11k_hw_ipq8074_rx_desc_get_mesh_ctl(struct hal_rx_desc *desc) 270 { 271 return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT, 272 __le32_to_cpu(desc->u.ipq8074.msdu_start.info2)); 273 } 274 275 static bool ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc *desc) 276 { 277 return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_CTRL_VALID, 278 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1)); 279 } 280 281 static bool ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc *desc) 282 { 283 return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_FCTRL_VALID, 284 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1)); 285 } 286 287 static u16 ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc *desc) 288 { 289 return FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_NUM, 290 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1)); 291 } 292 293 static u16 ath11k_hw_ipq8074_rx_desc_get_msdu_len(struct hal_rx_desc *desc) 294 { 295 return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH, 296 __le32_to_cpu(desc->u.ipq8074.msdu_start.info1)); 297 } 298 299 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_sgi(struct hal_rx_desc *desc) 300 { 301 return FIELD_GET(RX_MSDU_START_INFO3_SGI, 302 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 303 } 304 305 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc *desc) 306 { 307 return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS, 308 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 309 } 310 311 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw(struct hal_rx_desc *desc) 312 { 313 return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW, 314 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 315 } 316 317 static u32 ath11k_hw_ipq8074_rx_desc_get_msdu_freq(struct hal_rx_desc *desc) 318 { 319 return __le32_to_cpu(desc->u.ipq8074.msdu_start.phy_meta_data); 320 } 321 322 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type(struct hal_rx_desc *desc) 323 { 324 return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE, 325 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 326 } 327 328 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_nss(struct hal_rx_desc *desc) 329 { 330 return FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP, 331 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 332 } 333 334 static u8 ath11k_hw_ipq8074_rx_desc_get_mpdu_tid(struct hal_rx_desc *desc) 335 { 336 return FIELD_GET(RX_MPDU_START_INFO2_TID, 337 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info2)); 338 } 339 340 static u16 ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc) 341 { 342 return __le16_to_cpu(desc->u.ipq8074.mpdu_start.sw_peer_id); 343 } 344 345 static void ath11k_hw_ipq8074_rx_desc_copy_attn_end(struct hal_rx_desc *fdesc, 346 struct hal_rx_desc *ldesc) 347 { 348 memcpy((u8 *)&fdesc->u.ipq8074.msdu_end, (u8 *)&ldesc->u.ipq8074.msdu_end, 349 sizeof(struct rx_msdu_end_ipq8074)); 350 memcpy((u8 *)&fdesc->u.ipq8074.attention, (u8 *)&ldesc->u.ipq8074.attention, 351 sizeof(struct rx_attention)); 352 memcpy((u8 *)&fdesc->u.ipq8074.mpdu_end, (u8 *)&ldesc->u.ipq8074.mpdu_end, 353 sizeof(struct rx_mpdu_end)); 354 } 355 356 static u32 ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag(struct hal_rx_desc *desc) 357 { 358 return FIELD_GET(HAL_TLV_HDR_TAG, 359 __le32_to_cpu(desc->u.ipq8074.mpdu_start_tag)); 360 } 361 362 static u32 ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc *desc) 363 { 364 return __le16_to_cpu(desc->u.ipq8074.mpdu_start.phy_ppdu_id); 365 } 366 367 static void ath11k_hw_ipq8074_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len) 368 { 369 u32 info = __le32_to_cpu(desc->u.ipq8074.msdu_start.info1); 370 371 info &= ~RX_MSDU_START_INFO1_MSDU_LENGTH; 372 info |= FIELD_PREP(RX_MSDU_START_INFO1_MSDU_LENGTH, len); 373 374 desc->u.ipq8074.msdu_start.info1 = __cpu_to_le32(info); 375 } 376 377 static bool ath11k_hw_ipq8074_rx_desc_mac_addr2_valid(struct hal_rx_desc *desc) 378 { 379 return __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1) & 380 RX_MPDU_START_INFO1_MAC_ADDR2_VALID; 381 } 382 383 static u8 *ath11k_hw_ipq8074_rx_desc_mpdu_start_addr2(struct hal_rx_desc *desc) 384 { 385 return desc->u.ipq8074.mpdu_start.addr2; 386 } 387 388 static 389 struct rx_attention *ath11k_hw_ipq8074_rx_desc_get_attention(struct hal_rx_desc *desc) 390 { 391 return &desc->u.ipq8074.attention; 392 } 393 394 static u8 *ath11k_hw_ipq8074_rx_desc_get_msdu_payload(struct hal_rx_desc *desc) 395 { 396 return &desc->u.ipq8074.msdu_payload[0]; 397 } 398 399 static bool ath11k_hw_qcn9074_rx_desc_get_first_msdu(struct hal_rx_desc *desc) 400 { 401 return !!FIELD_GET(RX_MSDU_END_INFO4_FIRST_MSDU, 402 __le16_to_cpu(desc->u.qcn9074.msdu_end.info4)); 403 } 404 405 static bool ath11k_hw_qcn9074_rx_desc_get_last_msdu(struct hal_rx_desc *desc) 406 { 407 return !!FIELD_GET(RX_MSDU_END_INFO4_LAST_MSDU, 408 __le16_to_cpu(desc->u.qcn9074.msdu_end.info4)); 409 } 410 411 static u8 ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes(struct hal_rx_desc *desc) 412 { 413 return FIELD_GET(RX_MSDU_END_INFO4_L3_HDR_PADDING, 414 __le16_to_cpu(desc->u.qcn9074.msdu_end.info4)); 415 } 416 417 static u8 *ath11k_hw_qcn9074_rx_desc_get_hdr_status(struct hal_rx_desc *desc) 418 { 419 return desc->u.qcn9074.hdr_status; 420 } 421 422 static bool ath11k_hw_qcn9074_rx_desc_encrypt_valid(struct hal_rx_desc *desc) 423 { 424 return __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11) & 425 RX_MPDU_START_INFO11_ENCRYPT_INFO_VALID; 426 } 427 428 static u32 ath11k_hw_qcn9074_rx_desc_get_encrypt_type(struct hal_rx_desc *desc) 429 { 430 return FIELD_GET(RX_MPDU_START_INFO9_ENC_TYPE, 431 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info9)); 432 } 433 434 static u8 ath11k_hw_qcn9074_rx_desc_get_decap_type(struct hal_rx_desc *desc) 435 { 436 return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT, 437 __le32_to_cpu(desc->u.qcn9074.msdu_start.info2)); 438 } 439 440 static u8 ath11k_hw_qcn9074_rx_desc_get_mesh_ctl(struct hal_rx_desc *desc) 441 { 442 return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT, 443 __le32_to_cpu(desc->u.qcn9074.msdu_start.info2)); 444 } 445 446 static bool ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc *desc) 447 { 448 return !!FIELD_GET(RX_MPDU_START_INFO11_MPDU_SEQ_CTRL_VALID, 449 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11)); 450 } 451 452 static bool ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc *desc) 453 { 454 return !!FIELD_GET(RX_MPDU_START_INFO11_MPDU_FCTRL_VALID, 455 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11)); 456 } 457 458 static u16 ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc *desc) 459 { 460 return FIELD_GET(RX_MPDU_START_INFO11_MPDU_SEQ_NUM, 461 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11)); 462 } 463 464 static u16 ath11k_hw_qcn9074_rx_desc_get_msdu_len(struct hal_rx_desc *desc) 465 { 466 return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH, 467 __le32_to_cpu(desc->u.qcn9074.msdu_start.info1)); 468 } 469 470 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_sgi(struct hal_rx_desc *desc) 471 { 472 return FIELD_GET(RX_MSDU_START_INFO3_SGI, 473 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 474 } 475 476 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc *desc) 477 { 478 return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS, 479 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 480 } 481 482 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw(struct hal_rx_desc *desc) 483 { 484 return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW, 485 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 486 } 487 488 static u32 ath11k_hw_qcn9074_rx_desc_get_msdu_freq(struct hal_rx_desc *desc) 489 { 490 return __le32_to_cpu(desc->u.qcn9074.msdu_start.phy_meta_data); 491 } 492 493 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type(struct hal_rx_desc *desc) 494 { 495 return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE, 496 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 497 } 498 499 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_nss(struct hal_rx_desc *desc) 500 { 501 return FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP, 502 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 503 } 504 505 static u8 ath11k_hw_qcn9074_rx_desc_get_mpdu_tid(struct hal_rx_desc *desc) 506 { 507 return FIELD_GET(RX_MPDU_START_INFO9_TID, 508 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info9)); 509 } 510 511 static u16 ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc) 512 { 513 return __le16_to_cpu(desc->u.qcn9074.mpdu_start.sw_peer_id); 514 } 515 516 static void ath11k_hw_qcn9074_rx_desc_copy_attn_end(struct hal_rx_desc *fdesc, 517 struct hal_rx_desc *ldesc) 518 { 519 memcpy((u8 *)&fdesc->u.qcn9074.msdu_end, (u8 *)&ldesc->u.qcn9074.msdu_end, 520 sizeof(struct rx_msdu_end_qcn9074)); 521 memcpy((u8 *)&fdesc->u.qcn9074.attention, (u8 *)&ldesc->u.qcn9074.attention, 522 sizeof(struct rx_attention)); 523 memcpy((u8 *)&fdesc->u.qcn9074.mpdu_end, (u8 *)&ldesc->u.qcn9074.mpdu_end, 524 sizeof(struct rx_mpdu_end)); 525 } 526 527 static u32 ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag(struct hal_rx_desc *desc) 528 { 529 return FIELD_GET(HAL_TLV_HDR_TAG, 530 __le32_to_cpu(desc->u.qcn9074.mpdu_start_tag)); 531 } 532 533 static u32 ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc *desc) 534 { 535 return __le16_to_cpu(desc->u.qcn9074.mpdu_start.phy_ppdu_id); 536 } 537 538 static void ath11k_hw_qcn9074_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len) 539 { 540 u32 info = __le32_to_cpu(desc->u.qcn9074.msdu_start.info1); 541 542 info &= ~RX_MSDU_START_INFO1_MSDU_LENGTH; 543 info |= FIELD_PREP(RX_MSDU_START_INFO1_MSDU_LENGTH, len); 544 545 desc->u.qcn9074.msdu_start.info1 = __cpu_to_le32(info); 546 } 547 548 static 549 struct rx_attention *ath11k_hw_qcn9074_rx_desc_get_attention(struct hal_rx_desc *desc) 550 { 551 return &desc->u.qcn9074.attention; 552 } 553 554 static u8 *ath11k_hw_qcn9074_rx_desc_get_msdu_payload(struct hal_rx_desc *desc) 555 { 556 return &desc->u.qcn9074.msdu_payload[0]; 557 } 558 559 static bool ath11k_hw_ipq9074_rx_desc_mac_addr2_valid(struct hal_rx_desc *desc) 560 { 561 return __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11) & 562 RX_MPDU_START_INFO11_MAC_ADDR2_VALID; 563 } 564 565 static u8 *ath11k_hw_ipq9074_rx_desc_mpdu_start_addr2(struct hal_rx_desc *desc) 566 { 567 return desc->u.qcn9074.mpdu_start.addr2; 568 } 569 570 static bool ath11k_hw_wcn6855_rx_desc_get_first_msdu(struct hal_rx_desc *desc) 571 { 572 return !!FIELD_GET(RX_MSDU_END_INFO2_FIRST_MSDU_WCN6855, 573 __le32_to_cpu(desc->u.wcn6855.msdu_end.info2)); 574 } 575 576 static bool ath11k_hw_wcn6855_rx_desc_get_last_msdu(struct hal_rx_desc *desc) 577 { 578 return !!FIELD_GET(RX_MSDU_END_INFO2_LAST_MSDU_WCN6855, 579 __le32_to_cpu(desc->u.wcn6855.msdu_end.info2)); 580 } 581 582 static u8 ath11k_hw_wcn6855_rx_desc_get_l3_pad_bytes(struct hal_rx_desc *desc) 583 { 584 return FIELD_GET(RX_MSDU_END_INFO2_L3_HDR_PADDING, 585 __le32_to_cpu(desc->u.wcn6855.msdu_end.info2)); 586 } 587 588 static u8 *ath11k_hw_wcn6855_rx_desc_get_hdr_status(struct hal_rx_desc *desc) 589 { 590 return desc->u.wcn6855.hdr_status; 591 } 592 593 static bool ath11k_hw_wcn6855_rx_desc_encrypt_valid(struct hal_rx_desc *desc) 594 { 595 return __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1) & 596 RX_MPDU_START_INFO1_ENCRYPT_INFO_VALID; 597 } 598 599 static u32 ath11k_hw_wcn6855_rx_desc_get_encrypt_type(struct hal_rx_desc *desc) 600 { 601 return FIELD_GET(RX_MPDU_START_INFO2_ENC_TYPE, 602 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info2)); 603 } 604 605 static u8 ath11k_hw_wcn6855_rx_desc_get_decap_type(struct hal_rx_desc *desc) 606 { 607 return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT, 608 __le32_to_cpu(desc->u.wcn6855.msdu_start.info2)); 609 } 610 611 static u8 ath11k_hw_wcn6855_rx_desc_get_mesh_ctl(struct hal_rx_desc *desc) 612 { 613 return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT, 614 __le32_to_cpu(desc->u.wcn6855.msdu_start.info2)); 615 } 616 617 static bool ath11k_hw_wcn6855_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc *desc) 618 { 619 return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_CTRL_VALID, 620 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1)); 621 } 622 623 static bool ath11k_hw_wcn6855_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc *desc) 624 { 625 return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_FCTRL_VALID, 626 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1)); 627 } 628 629 static u16 ath11k_hw_wcn6855_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc *desc) 630 { 631 return FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_NUM, 632 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1)); 633 } 634 635 static u16 ath11k_hw_wcn6855_rx_desc_get_msdu_len(struct hal_rx_desc *desc) 636 { 637 return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH, 638 __le32_to_cpu(desc->u.wcn6855.msdu_start.info1)); 639 } 640 641 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_sgi(struct hal_rx_desc *desc) 642 { 643 return FIELD_GET(RX_MSDU_START_INFO3_SGI, 644 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3)); 645 } 646 647 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc *desc) 648 { 649 return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS, 650 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3)); 651 } 652 653 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_rx_bw(struct hal_rx_desc *desc) 654 { 655 return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW, 656 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3)); 657 } 658 659 static u32 ath11k_hw_wcn6855_rx_desc_get_msdu_freq(struct hal_rx_desc *desc) 660 { 661 return __le32_to_cpu(desc->u.wcn6855.msdu_start.phy_meta_data); 662 } 663 664 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_pkt_type(struct hal_rx_desc *desc) 665 { 666 return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE, 667 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3)); 668 } 669 670 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_nss(struct hal_rx_desc *desc) 671 { 672 return FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP, 673 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3)); 674 } 675 676 static u8 ath11k_hw_wcn6855_rx_desc_get_mpdu_tid(struct hal_rx_desc *desc) 677 { 678 return FIELD_GET(RX_MPDU_START_INFO2_TID_WCN6855, 679 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info2)); 680 } 681 682 static u16 ath11k_hw_wcn6855_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc) 683 { 684 return __le16_to_cpu(desc->u.wcn6855.mpdu_start.sw_peer_id); 685 } 686 687 static void ath11k_hw_wcn6855_rx_desc_copy_attn_end(struct hal_rx_desc *fdesc, 688 struct hal_rx_desc *ldesc) 689 { 690 memcpy((u8 *)&fdesc->u.wcn6855.msdu_end, (u8 *)&ldesc->u.wcn6855.msdu_end, 691 sizeof(struct rx_msdu_end_wcn6855)); 692 memcpy((u8 *)&fdesc->u.wcn6855.attention, (u8 *)&ldesc->u.wcn6855.attention, 693 sizeof(struct rx_attention)); 694 memcpy((u8 *)&fdesc->u.wcn6855.mpdu_end, (u8 *)&ldesc->u.wcn6855.mpdu_end, 695 sizeof(struct rx_mpdu_end)); 696 } 697 698 static u32 ath11k_hw_wcn6855_rx_desc_get_mpdu_start_tag(struct hal_rx_desc *desc) 699 { 700 return FIELD_GET(HAL_TLV_HDR_TAG, 701 __le32_to_cpu(desc->u.wcn6855.mpdu_start_tag)); 702 } 703 704 static u32 ath11k_hw_wcn6855_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc *desc) 705 { 706 return __le16_to_cpu(desc->u.wcn6855.mpdu_start.phy_ppdu_id); 707 } 708 709 static void ath11k_hw_wcn6855_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len) 710 { 711 u32 info = __le32_to_cpu(desc->u.wcn6855.msdu_start.info1); 712 713 info &= ~RX_MSDU_START_INFO1_MSDU_LENGTH; 714 info |= FIELD_PREP(RX_MSDU_START_INFO1_MSDU_LENGTH, len); 715 716 desc->u.wcn6855.msdu_start.info1 = __cpu_to_le32(info); 717 } 718 719 static 720 struct rx_attention *ath11k_hw_wcn6855_rx_desc_get_attention(struct hal_rx_desc *desc) 721 { 722 return &desc->u.wcn6855.attention; 723 } 724 725 static u8 *ath11k_hw_wcn6855_rx_desc_get_msdu_payload(struct hal_rx_desc *desc) 726 { 727 return &desc->u.wcn6855.msdu_payload[0]; 728 } 729 730 static bool ath11k_hw_wcn6855_rx_desc_mac_addr2_valid(struct hal_rx_desc *desc) 731 { 732 return __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1) & 733 RX_MPDU_START_INFO1_MAC_ADDR2_VALID; 734 } 735 736 static u8 *ath11k_hw_wcn6855_rx_desc_mpdu_start_addr2(struct hal_rx_desc *desc) 737 { 738 return desc->u.wcn6855.mpdu_start.addr2; 739 } 740 741 static void ath11k_hw_wcn6855_reo_setup(struct ath11k_base *ab) 742 { 743 u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG; 744 u32 val; 745 /* Each hash entry uses four bits to map to a particular ring. */ 746 u32 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 | 747 HAL_HASH_ROUTING_RING_SW2 << 4 | 748 HAL_HASH_ROUTING_RING_SW3 << 8 | 749 HAL_HASH_ROUTING_RING_SW4 << 12 | 750 HAL_HASH_ROUTING_RING_SW1 << 16 | 751 HAL_HASH_ROUTING_RING_SW2 << 20 | 752 HAL_HASH_ROUTING_RING_SW3 << 24 | 753 HAL_HASH_ROUTING_RING_SW4 << 28; 754 755 val = ath11k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE); 756 val |= FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE, 1) | 757 FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE, 1); 758 ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val); 759 760 val = ath11k_hif_read32(ab, reo_base + HAL_REO1_MISC_CTL); 761 val &= ~HAL_REO1_MISC_CTL_FRAGMENT_DST_RING; 762 val |= FIELD_PREP(HAL_REO1_MISC_CTL_FRAGMENT_DST_RING, HAL_SRNG_RING_ID_REO2SW1); 763 ath11k_hif_write32(ab, reo_base + HAL_REO1_MISC_CTL, val); 764 765 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab), 766 HAL_DEFAULT_REO_TIMEOUT_USEC); 767 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab), 768 HAL_DEFAULT_REO_TIMEOUT_USEC); 769 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab), 770 HAL_DEFAULT_REO_TIMEOUT_USEC); 771 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab), 772 HAL_DEFAULT_REO_TIMEOUT_USEC); 773 774 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2, 775 ring_hash_map); 776 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3, 777 ring_hash_map); 778 } 779 780 static u16 ath11k_hw_ipq8074_mpdu_info_get_peerid(u8 *tlv_data) 781 { 782 u16 peer_id = 0; 783 struct hal_rx_mpdu_info *mpdu_info = 784 (struct hal_rx_mpdu_info *)tlv_data; 785 786 peer_id = FIELD_GET(HAL_RX_MPDU_INFO_INFO0_PEERID, 787 __le32_to_cpu(mpdu_info->info0)); 788 789 return peer_id; 790 } 791 792 static u16 ath11k_hw_wcn6855_mpdu_info_get_peerid(u8 *tlv_data) 793 { 794 u16 peer_id = 0; 795 struct hal_rx_mpdu_info_wcn6855 *mpdu_info = 796 (struct hal_rx_mpdu_info_wcn6855 *)tlv_data; 797 798 peer_id = FIELD_GET(HAL_RX_MPDU_INFO_INFO0_PEERID_WCN6855, 799 __le32_to_cpu(mpdu_info->info0)); 800 return peer_id; 801 } 802 803 const struct ath11k_hw_ops ipq8074_ops = { 804 .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id, 805 .wmi_init_config = ath11k_init_wmi_config_ipq8074, 806 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074, 807 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074, 808 .tx_mesh_enable = ath11k_hw_ipq8074_tx_mesh_enable, 809 .rx_desc_get_first_msdu = ath11k_hw_ipq8074_rx_desc_get_first_msdu, 810 .rx_desc_get_last_msdu = ath11k_hw_ipq8074_rx_desc_get_last_msdu, 811 .rx_desc_get_l3_pad_bytes = ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes, 812 .rx_desc_get_hdr_status = ath11k_hw_ipq8074_rx_desc_get_hdr_status, 813 .rx_desc_encrypt_valid = ath11k_hw_ipq8074_rx_desc_encrypt_valid, 814 .rx_desc_get_encrypt_type = ath11k_hw_ipq8074_rx_desc_get_encrypt_type, 815 .rx_desc_get_decap_type = ath11k_hw_ipq8074_rx_desc_get_decap_type, 816 .rx_desc_get_mesh_ctl = ath11k_hw_ipq8074_rx_desc_get_mesh_ctl, 817 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld, 818 .rx_desc_get_mpdu_fc_valid = ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid, 819 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no, 820 .rx_desc_get_msdu_len = ath11k_hw_ipq8074_rx_desc_get_msdu_len, 821 .rx_desc_get_msdu_sgi = ath11k_hw_ipq8074_rx_desc_get_msdu_sgi, 822 .rx_desc_get_msdu_rate_mcs = ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs, 823 .rx_desc_get_msdu_rx_bw = ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw, 824 .rx_desc_get_msdu_freq = ath11k_hw_ipq8074_rx_desc_get_msdu_freq, 825 .rx_desc_get_msdu_pkt_type = ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type, 826 .rx_desc_get_msdu_nss = ath11k_hw_ipq8074_rx_desc_get_msdu_nss, 827 .rx_desc_get_mpdu_tid = ath11k_hw_ipq8074_rx_desc_get_mpdu_tid, 828 .rx_desc_get_mpdu_peer_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id, 829 .rx_desc_copy_attn_end_tlv = ath11k_hw_ipq8074_rx_desc_copy_attn_end, 830 .rx_desc_get_mpdu_start_tag = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag, 831 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id, 832 .rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len, 833 .rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention, 834 .rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload, 835 .reo_setup = ath11k_hw_ipq8074_reo_setup, 836 .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, 837 .rx_desc_mac_addr2_valid = ath11k_hw_ipq8074_rx_desc_mac_addr2_valid, 838 .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq8074_rx_desc_mpdu_start_addr2, 839 }; 840 841 const struct ath11k_hw_ops ipq6018_ops = { 842 .get_hw_mac_from_pdev_id = ath11k_hw_ipq6018_mac_from_pdev_id, 843 .wmi_init_config = ath11k_init_wmi_config_ipq8074, 844 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074, 845 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074, 846 .tx_mesh_enable = ath11k_hw_ipq8074_tx_mesh_enable, 847 .rx_desc_get_first_msdu = ath11k_hw_ipq8074_rx_desc_get_first_msdu, 848 .rx_desc_get_last_msdu = ath11k_hw_ipq8074_rx_desc_get_last_msdu, 849 .rx_desc_get_l3_pad_bytes = ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes, 850 .rx_desc_get_hdr_status = ath11k_hw_ipq8074_rx_desc_get_hdr_status, 851 .rx_desc_encrypt_valid = ath11k_hw_ipq8074_rx_desc_encrypt_valid, 852 .rx_desc_get_encrypt_type = ath11k_hw_ipq8074_rx_desc_get_encrypt_type, 853 .rx_desc_get_decap_type = ath11k_hw_ipq8074_rx_desc_get_decap_type, 854 .rx_desc_get_mesh_ctl = ath11k_hw_ipq8074_rx_desc_get_mesh_ctl, 855 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld, 856 .rx_desc_get_mpdu_fc_valid = ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid, 857 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no, 858 .rx_desc_get_msdu_len = ath11k_hw_ipq8074_rx_desc_get_msdu_len, 859 .rx_desc_get_msdu_sgi = ath11k_hw_ipq8074_rx_desc_get_msdu_sgi, 860 .rx_desc_get_msdu_rate_mcs = ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs, 861 .rx_desc_get_msdu_rx_bw = ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw, 862 .rx_desc_get_msdu_freq = ath11k_hw_ipq8074_rx_desc_get_msdu_freq, 863 .rx_desc_get_msdu_pkt_type = ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type, 864 .rx_desc_get_msdu_nss = ath11k_hw_ipq8074_rx_desc_get_msdu_nss, 865 .rx_desc_get_mpdu_tid = ath11k_hw_ipq8074_rx_desc_get_mpdu_tid, 866 .rx_desc_get_mpdu_peer_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id, 867 .rx_desc_copy_attn_end_tlv = ath11k_hw_ipq8074_rx_desc_copy_attn_end, 868 .rx_desc_get_mpdu_start_tag = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag, 869 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id, 870 .rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len, 871 .rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention, 872 .rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload, 873 .reo_setup = ath11k_hw_ipq8074_reo_setup, 874 .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, 875 .rx_desc_mac_addr2_valid = ath11k_hw_ipq8074_rx_desc_mac_addr2_valid, 876 .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq8074_rx_desc_mpdu_start_addr2, 877 }; 878 879 const struct ath11k_hw_ops qca6390_ops = { 880 .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id, 881 .wmi_init_config = ath11k_init_wmi_config_qca6390, 882 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390, 883 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390, 884 .tx_mesh_enable = ath11k_hw_ipq8074_tx_mesh_enable, 885 .rx_desc_get_first_msdu = ath11k_hw_ipq8074_rx_desc_get_first_msdu, 886 .rx_desc_get_last_msdu = ath11k_hw_ipq8074_rx_desc_get_last_msdu, 887 .rx_desc_get_l3_pad_bytes = ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes, 888 .rx_desc_get_hdr_status = ath11k_hw_ipq8074_rx_desc_get_hdr_status, 889 .rx_desc_encrypt_valid = ath11k_hw_ipq8074_rx_desc_encrypt_valid, 890 .rx_desc_get_encrypt_type = ath11k_hw_ipq8074_rx_desc_get_encrypt_type, 891 .rx_desc_get_decap_type = ath11k_hw_ipq8074_rx_desc_get_decap_type, 892 .rx_desc_get_mesh_ctl = ath11k_hw_ipq8074_rx_desc_get_mesh_ctl, 893 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld, 894 .rx_desc_get_mpdu_fc_valid = ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid, 895 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no, 896 .rx_desc_get_msdu_len = ath11k_hw_ipq8074_rx_desc_get_msdu_len, 897 .rx_desc_get_msdu_sgi = ath11k_hw_ipq8074_rx_desc_get_msdu_sgi, 898 .rx_desc_get_msdu_rate_mcs = ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs, 899 .rx_desc_get_msdu_rx_bw = ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw, 900 .rx_desc_get_msdu_freq = ath11k_hw_ipq8074_rx_desc_get_msdu_freq, 901 .rx_desc_get_msdu_pkt_type = ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type, 902 .rx_desc_get_msdu_nss = ath11k_hw_ipq8074_rx_desc_get_msdu_nss, 903 .rx_desc_get_mpdu_tid = ath11k_hw_ipq8074_rx_desc_get_mpdu_tid, 904 .rx_desc_get_mpdu_peer_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id, 905 .rx_desc_copy_attn_end_tlv = ath11k_hw_ipq8074_rx_desc_copy_attn_end, 906 .rx_desc_get_mpdu_start_tag = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag, 907 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id, 908 .rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len, 909 .rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention, 910 .rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload, 911 .reo_setup = ath11k_hw_ipq8074_reo_setup, 912 .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, 913 .rx_desc_mac_addr2_valid = ath11k_hw_ipq8074_rx_desc_mac_addr2_valid, 914 .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq8074_rx_desc_mpdu_start_addr2, 915 }; 916 917 const struct ath11k_hw_ops qcn9074_ops = { 918 .get_hw_mac_from_pdev_id = ath11k_hw_ipq6018_mac_from_pdev_id, 919 .wmi_init_config = ath11k_init_wmi_config_ipq8074, 920 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074, 921 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074, 922 .tx_mesh_enable = ath11k_hw_qcn9074_tx_mesh_enable, 923 .rx_desc_get_first_msdu = ath11k_hw_qcn9074_rx_desc_get_first_msdu, 924 .rx_desc_get_last_msdu = ath11k_hw_qcn9074_rx_desc_get_last_msdu, 925 .rx_desc_get_l3_pad_bytes = ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes, 926 .rx_desc_get_hdr_status = ath11k_hw_qcn9074_rx_desc_get_hdr_status, 927 .rx_desc_encrypt_valid = ath11k_hw_qcn9074_rx_desc_encrypt_valid, 928 .rx_desc_get_encrypt_type = ath11k_hw_qcn9074_rx_desc_get_encrypt_type, 929 .rx_desc_get_decap_type = ath11k_hw_qcn9074_rx_desc_get_decap_type, 930 .rx_desc_get_mesh_ctl = ath11k_hw_qcn9074_rx_desc_get_mesh_ctl, 931 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld, 932 .rx_desc_get_mpdu_fc_valid = ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid, 933 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no, 934 .rx_desc_get_msdu_len = ath11k_hw_qcn9074_rx_desc_get_msdu_len, 935 .rx_desc_get_msdu_sgi = ath11k_hw_qcn9074_rx_desc_get_msdu_sgi, 936 .rx_desc_get_msdu_rate_mcs = ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs, 937 .rx_desc_get_msdu_rx_bw = ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw, 938 .rx_desc_get_msdu_freq = ath11k_hw_qcn9074_rx_desc_get_msdu_freq, 939 .rx_desc_get_msdu_pkt_type = ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type, 940 .rx_desc_get_msdu_nss = ath11k_hw_qcn9074_rx_desc_get_msdu_nss, 941 .rx_desc_get_mpdu_tid = ath11k_hw_qcn9074_rx_desc_get_mpdu_tid, 942 .rx_desc_get_mpdu_peer_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id, 943 .rx_desc_copy_attn_end_tlv = ath11k_hw_qcn9074_rx_desc_copy_attn_end, 944 .rx_desc_get_mpdu_start_tag = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag, 945 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id, 946 .rx_desc_set_msdu_len = ath11k_hw_qcn9074_rx_desc_set_msdu_len, 947 .rx_desc_get_attention = ath11k_hw_qcn9074_rx_desc_get_attention, 948 .rx_desc_get_msdu_payload = ath11k_hw_qcn9074_rx_desc_get_msdu_payload, 949 .reo_setup = ath11k_hw_ipq8074_reo_setup, 950 .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, 951 .rx_desc_mac_addr2_valid = ath11k_hw_ipq9074_rx_desc_mac_addr2_valid, 952 .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq9074_rx_desc_mpdu_start_addr2, 953 }; 954 955 const struct ath11k_hw_ops wcn6855_ops = { 956 .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id, 957 .wmi_init_config = ath11k_init_wmi_config_qca6390, 958 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390, 959 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390, 960 .tx_mesh_enable = ath11k_hw_wcn6855_tx_mesh_enable, 961 .rx_desc_get_first_msdu = ath11k_hw_wcn6855_rx_desc_get_first_msdu, 962 .rx_desc_get_last_msdu = ath11k_hw_wcn6855_rx_desc_get_last_msdu, 963 .rx_desc_get_l3_pad_bytes = ath11k_hw_wcn6855_rx_desc_get_l3_pad_bytes, 964 .rx_desc_get_hdr_status = ath11k_hw_wcn6855_rx_desc_get_hdr_status, 965 .rx_desc_encrypt_valid = ath11k_hw_wcn6855_rx_desc_encrypt_valid, 966 .rx_desc_get_encrypt_type = ath11k_hw_wcn6855_rx_desc_get_encrypt_type, 967 .rx_desc_get_decap_type = ath11k_hw_wcn6855_rx_desc_get_decap_type, 968 .rx_desc_get_mesh_ctl = ath11k_hw_wcn6855_rx_desc_get_mesh_ctl, 969 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_wcn6855_rx_desc_get_mpdu_seq_ctl_vld, 970 .rx_desc_get_mpdu_fc_valid = ath11k_hw_wcn6855_rx_desc_get_mpdu_fc_valid, 971 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_wcn6855_rx_desc_get_mpdu_start_seq_no, 972 .rx_desc_get_msdu_len = ath11k_hw_wcn6855_rx_desc_get_msdu_len, 973 .rx_desc_get_msdu_sgi = ath11k_hw_wcn6855_rx_desc_get_msdu_sgi, 974 .rx_desc_get_msdu_rate_mcs = ath11k_hw_wcn6855_rx_desc_get_msdu_rate_mcs, 975 .rx_desc_get_msdu_rx_bw = ath11k_hw_wcn6855_rx_desc_get_msdu_rx_bw, 976 .rx_desc_get_msdu_freq = ath11k_hw_wcn6855_rx_desc_get_msdu_freq, 977 .rx_desc_get_msdu_pkt_type = ath11k_hw_wcn6855_rx_desc_get_msdu_pkt_type, 978 .rx_desc_get_msdu_nss = ath11k_hw_wcn6855_rx_desc_get_msdu_nss, 979 .rx_desc_get_mpdu_tid = ath11k_hw_wcn6855_rx_desc_get_mpdu_tid, 980 .rx_desc_get_mpdu_peer_id = ath11k_hw_wcn6855_rx_desc_get_mpdu_peer_id, 981 .rx_desc_copy_attn_end_tlv = ath11k_hw_wcn6855_rx_desc_copy_attn_end, 982 .rx_desc_get_mpdu_start_tag = ath11k_hw_wcn6855_rx_desc_get_mpdu_start_tag, 983 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_wcn6855_rx_desc_get_mpdu_ppdu_id, 984 .rx_desc_set_msdu_len = ath11k_hw_wcn6855_rx_desc_set_msdu_len, 985 .rx_desc_get_attention = ath11k_hw_wcn6855_rx_desc_get_attention, 986 .rx_desc_get_msdu_payload = ath11k_hw_wcn6855_rx_desc_get_msdu_payload, 987 .reo_setup = ath11k_hw_wcn6855_reo_setup, 988 .mpdu_info_get_peerid = ath11k_hw_wcn6855_mpdu_info_get_peerid, 989 .rx_desc_mac_addr2_valid = ath11k_hw_wcn6855_rx_desc_mac_addr2_valid, 990 .rx_desc_mpdu_start_addr2 = ath11k_hw_wcn6855_rx_desc_mpdu_start_addr2, 991 }; 992 993 #define ATH11K_TX_RING_MASK_0 0x1 994 #define ATH11K_TX_RING_MASK_1 0x2 995 #define ATH11K_TX_RING_MASK_2 0x4 996 997 #define ATH11K_RX_RING_MASK_0 0x1 998 #define ATH11K_RX_RING_MASK_1 0x2 999 #define ATH11K_RX_RING_MASK_2 0x4 1000 #define ATH11K_RX_RING_MASK_3 0x8 1001 1002 #define ATH11K_RX_ERR_RING_MASK_0 0x1 1003 1004 #define ATH11K_RX_WBM_REL_RING_MASK_0 0x1 1005 1006 #define ATH11K_REO_STATUS_RING_MASK_0 0x1 1007 1008 #define ATH11K_RXDMA2HOST_RING_MASK_0 0x1 1009 #define ATH11K_RXDMA2HOST_RING_MASK_1 0x2 1010 #define ATH11K_RXDMA2HOST_RING_MASK_2 0x4 1011 1012 #define ATH11K_HOST2RXDMA_RING_MASK_0 0x1 1013 #define ATH11K_HOST2RXDMA_RING_MASK_1 0x2 1014 #define ATH11K_HOST2RXDMA_RING_MASK_2 0x4 1015 1016 #define ATH11K_RX_MON_STATUS_RING_MASK_0 0x1 1017 #define ATH11K_RX_MON_STATUS_RING_MASK_1 0x2 1018 #define ATH11K_RX_MON_STATUS_RING_MASK_2 0x4 1019 1020 const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_ipq8074 = { 1021 .tx = { 1022 ATH11K_TX_RING_MASK_0, 1023 ATH11K_TX_RING_MASK_1, 1024 ATH11K_TX_RING_MASK_2, 1025 }, 1026 .rx_mon_status = { 1027 0, 0, 0, 0, 1028 ATH11K_RX_MON_STATUS_RING_MASK_0, 1029 ATH11K_RX_MON_STATUS_RING_MASK_1, 1030 ATH11K_RX_MON_STATUS_RING_MASK_2, 1031 }, 1032 .rx = { 1033 0, 0, 0, 0, 0, 0, 0, 1034 ATH11K_RX_RING_MASK_0, 1035 ATH11K_RX_RING_MASK_1, 1036 ATH11K_RX_RING_MASK_2, 1037 ATH11K_RX_RING_MASK_3, 1038 }, 1039 .rx_err = { 1040 ATH11K_RX_ERR_RING_MASK_0, 1041 }, 1042 .rx_wbm_rel = { 1043 ATH11K_RX_WBM_REL_RING_MASK_0, 1044 }, 1045 .reo_status = { 1046 ATH11K_REO_STATUS_RING_MASK_0, 1047 }, 1048 .rxdma2host = { 1049 ATH11K_RXDMA2HOST_RING_MASK_0, 1050 ATH11K_RXDMA2HOST_RING_MASK_1, 1051 ATH11K_RXDMA2HOST_RING_MASK_2, 1052 }, 1053 .host2rxdma = { 1054 ATH11K_HOST2RXDMA_RING_MASK_0, 1055 ATH11K_HOST2RXDMA_RING_MASK_1, 1056 ATH11K_HOST2RXDMA_RING_MASK_2, 1057 }, 1058 }; 1059 1060 const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qca6390 = { 1061 .tx = { 1062 ATH11K_TX_RING_MASK_0, 1063 ATH11K_TX_RING_MASK_1, 1064 ATH11K_TX_RING_MASK_2, 1065 }, 1066 .rx_mon_status = { 1067 0, 0, 0, 0, 1068 ATH11K_RX_MON_STATUS_RING_MASK_0, 1069 ATH11K_RX_MON_STATUS_RING_MASK_1, 1070 ATH11K_RX_MON_STATUS_RING_MASK_2, 1071 }, 1072 .rx = { 1073 0, 0, 0, 0, 0, 0, 0, 1074 ATH11K_RX_RING_MASK_0, 1075 ATH11K_RX_RING_MASK_1, 1076 ATH11K_RX_RING_MASK_2, 1077 ATH11K_RX_RING_MASK_3, 1078 }, 1079 .rx_err = { 1080 ATH11K_RX_ERR_RING_MASK_0, 1081 }, 1082 .rx_wbm_rel = { 1083 ATH11K_RX_WBM_REL_RING_MASK_0, 1084 }, 1085 .reo_status = { 1086 ATH11K_REO_STATUS_RING_MASK_0, 1087 }, 1088 .rxdma2host = { 1089 ATH11K_RXDMA2HOST_RING_MASK_0, 1090 ATH11K_RXDMA2HOST_RING_MASK_1, 1091 ATH11K_RXDMA2HOST_RING_MASK_2, 1092 }, 1093 .host2rxdma = { 1094 }, 1095 }; 1096 1097 /* Target firmware's Copy Engine configuration. */ 1098 const struct ce_pipe_config ath11k_target_ce_config_wlan_ipq8074[] = { 1099 /* CE0: host->target HTC control and raw streams */ 1100 { 1101 .pipenum = __cpu_to_le32(0), 1102 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1103 .nentries = __cpu_to_le32(32), 1104 .nbytes_max = __cpu_to_le32(2048), 1105 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1106 .reserved = __cpu_to_le32(0), 1107 }, 1108 1109 /* CE1: target->host HTT + HTC control */ 1110 { 1111 .pipenum = __cpu_to_le32(1), 1112 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1113 .nentries = __cpu_to_le32(32), 1114 .nbytes_max = __cpu_to_le32(2048), 1115 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1116 .reserved = __cpu_to_le32(0), 1117 }, 1118 1119 /* CE2: target->host WMI */ 1120 { 1121 .pipenum = __cpu_to_le32(2), 1122 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1123 .nentries = __cpu_to_le32(32), 1124 .nbytes_max = __cpu_to_le32(2048), 1125 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1126 .reserved = __cpu_to_le32(0), 1127 }, 1128 1129 /* CE3: host->target WMI */ 1130 { 1131 .pipenum = __cpu_to_le32(3), 1132 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1133 .nentries = __cpu_to_le32(32), 1134 .nbytes_max = __cpu_to_le32(2048), 1135 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1136 .reserved = __cpu_to_le32(0), 1137 }, 1138 1139 /* CE4: host->target HTT */ 1140 { 1141 .pipenum = __cpu_to_le32(4), 1142 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1143 .nentries = __cpu_to_le32(256), 1144 .nbytes_max = __cpu_to_le32(256), 1145 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1146 .reserved = __cpu_to_le32(0), 1147 }, 1148 1149 /* CE5: target->host Pktlog */ 1150 { 1151 .pipenum = __cpu_to_le32(5), 1152 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1153 .nentries = __cpu_to_le32(32), 1154 .nbytes_max = __cpu_to_le32(2048), 1155 .flags = __cpu_to_le32(0), 1156 .reserved = __cpu_to_le32(0), 1157 }, 1158 1159 /* CE6: Reserved for target autonomous hif_memcpy */ 1160 { 1161 .pipenum = __cpu_to_le32(6), 1162 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1163 .nentries = __cpu_to_le32(32), 1164 .nbytes_max = __cpu_to_le32(65535), 1165 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1166 .reserved = __cpu_to_le32(0), 1167 }, 1168 1169 /* CE7 used only by Host */ 1170 { 1171 .pipenum = __cpu_to_le32(7), 1172 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1173 .nentries = __cpu_to_le32(32), 1174 .nbytes_max = __cpu_to_le32(2048), 1175 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1176 .reserved = __cpu_to_le32(0), 1177 }, 1178 1179 /* CE8 target->host used only by IPA */ 1180 { 1181 .pipenum = __cpu_to_le32(8), 1182 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1183 .nentries = __cpu_to_le32(32), 1184 .nbytes_max = __cpu_to_le32(65535), 1185 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1186 .reserved = __cpu_to_le32(0), 1187 }, 1188 1189 /* CE9 host->target HTT */ 1190 { 1191 .pipenum = __cpu_to_le32(9), 1192 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1193 .nentries = __cpu_to_le32(32), 1194 .nbytes_max = __cpu_to_le32(2048), 1195 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1196 .reserved = __cpu_to_le32(0), 1197 }, 1198 1199 /* CE10 target->host HTT */ 1200 { 1201 .pipenum = __cpu_to_le32(10), 1202 .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H), 1203 .nentries = __cpu_to_le32(0), 1204 .nbytes_max = __cpu_to_le32(0), 1205 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1206 .reserved = __cpu_to_le32(0), 1207 }, 1208 1209 /* CE11 Not used */ 1210 }; 1211 1212 /* Map from service/endpoint to Copy Engine. 1213 * This table is derived from the CE_PCI TABLE, above. 1214 * It is passed to the Target at startup for use by firmware. 1215 */ 1216 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq8074[] = { 1217 { 1218 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1219 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1220 .pipenum = __cpu_to_le32(3), 1221 }, 1222 { 1223 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1224 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1225 .pipenum = __cpu_to_le32(2), 1226 }, 1227 { 1228 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1229 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1230 .pipenum = __cpu_to_le32(3), 1231 }, 1232 { 1233 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1234 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1235 .pipenum = __cpu_to_le32(2), 1236 }, 1237 { 1238 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1239 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1240 .pipenum = __cpu_to_le32(3), 1241 }, 1242 { 1243 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1244 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1245 .pipenum = __cpu_to_le32(2), 1246 }, 1247 { 1248 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1249 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1250 .pipenum = __cpu_to_le32(3), 1251 }, 1252 { 1253 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1254 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1255 .pipenum = __cpu_to_le32(2), 1256 }, 1257 { 1258 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1259 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1260 .pipenum = __cpu_to_le32(3), 1261 }, 1262 { 1263 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1264 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1265 .pipenum = __cpu_to_le32(2), 1266 }, 1267 { 1268 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 1269 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1270 .pipenum = __cpu_to_le32(7), 1271 }, 1272 { 1273 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 1274 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1275 .pipenum = __cpu_to_le32(2), 1276 }, 1277 { 1278 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC2), 1279 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1280 .pipenum = __cpu_to_le32(9), 1281 }, 1282 { 1283 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC2), 1284 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1285 .pipenum = __cpu_to_le32(2), 1286 }, 1287 { 1288 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1289 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1290 .pipenum = __cpu_to_le32(0), 1291 }, 1292 { 1293 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1294 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1295 .pipenum = __cpu_to_le32(1), 1296 }, 1297 { /* not used */ 1298 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1299 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1300 .pipenum = __cpu_to_le32(0), 1301 }, 1302 { /* not used */ 1303 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1304 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1305 .pipenum = __cpu_to_le32(1), 1306 }, 1307 { 1308 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1309 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1310 .pipenum = __cpu_to_le32(4), 1311 }, 1312 { 1313 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1314 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1315 .pipenum = __cpu_to_le32(1), 1316 }, 1317 { 1318 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG), 1319 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1320 .pipenum = __cpu_to_le32(5), 1321 }, 1322 1323 /* (Additions here) */ 1324 1325 { /* terminator entry */ } 1326 }; 1327 1328 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq6018[] = { 1329 { 1330 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1331 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1332 .pipenum = __cpu_to_le32(3), 1333 }, 1334 { 1335 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1336 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1337 .pipenum = __cpu_to_le32(2), 1338 }, 1339 { 1340 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1341 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1342 .pipenum = __cpu_to_le32(3), 1343 }, 1344 { 1345 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1346 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1347 .pipenum = __cpu_to_le32(2), 1348 }, 1349 { 1350 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1351 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1352 .pipenum = __cpu_to_le32(3), 1353 }, 1354 { 1355 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1356 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1357 .pipenum = __cpu_to_le32(2), 1358 }, 1359 { 1360 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1361 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1362 .pipenum = __cpu_to_le32(3), 1363 }, 1364 { 1365 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1366 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1367 .pipenum = __cpu_to_le32(2), 1368 }, 1369 { 1370 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1371 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1372 .pipenum = __cpu_to_le32(3), 1373 }, 1374 { 1375 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1376 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1377 .pipenum = __cpu_to_le32(2), 1378 }, 1379 { 1380 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 1381 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1382 .pipenum = __cpu_to_le32(7), 1383 }, 1384 { 1385 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 1386 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1387 .pipenum = __cpu_to_le32(2), 1388 }, 1389 { 1390 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1391 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1392 .pipenum = __cpu_to_le32(0), 1393 }, 1394 { 1395 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1396 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1397 .pipenum = __cpu_to_le32(1), 1398 }, 1399 { /* not used */ 1400 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1401 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1402 .pipenum = __cpu_to_le32(0), 1403 }, 1404 { /* not used */ 1405 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1406 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1407 .pipenum = __cpu_to_le32(1), 1408 }, 1409 { 1410 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1411 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1412 .pipenum = __cpu_to_le32(4), 1413 }, 1414 { 1415 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1416 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1417 .pipenum = __cpu_to_le32(1), 1418 }, 1419 { 1420 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG), 1421 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1422 .pipenum = __cpu_to_le32(5), 1423 }, 1424 1425 /* (Additions here) */ 1426 1427 { /* terminator entry */ } 1428 }; 1429 1430 /* Target firmware's Copy Engine configuration. */ 1431 const struct ce_pipe_config ath11k_target_ce_config_wlan_qca6390[] = { 1432 /* CE0: host->target HTC control and raw streams */ 1433 { 1434 .pipenum = __cpu_to_le32(0), 1435 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1436 .nentries = __cpu_to_le32(32), 1437 .nbytes_max = __cpu_to_le32(2048), 1438 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1439 .reserved = __cpu_to_le32(0), 1440 }, 1441 1442 /* CE1: target->host HTT + HTC control */ 1443 { 1444 .pipenum = __cpu_to_le32(1), 1445 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1446 .nentries = __cpu_to_le32(32), 1447 .nbytes_max = __cpu_to_le32(2048), 1448 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1449 .reserved = __cpu_to_le32(0), 1450 }, 1451 1452 /* CE2: target->host WMI */ 1453 { 1454 .pipenum = __cpu_to_le32(2), 1455 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1456 .nentries = __cpu_to_le32(32), 1457 .nbytes_max = __cpu_to_le32(2048), 1458 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1459 .reserved = __cpu_to_le32(0), 1460 }, 1461 1462 /* CE3: host->target WMI */ 1463 { 1464 .pipenum = __cpu_to_le32(3), 1465 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1466 .nentries = __cpu_to_le32(32), 1467 .nbytes_max = __cpu_to_le32(2048), 1468 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1469 .reserved = __cpu_to_le32(0), 1470 }, 1471 1472 /* CE4: host->target HTT */ 1473 { 1474 .pipenum = __cpu_to_le32(4), 1475 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1476 .nentries = __cpu_to_le32(256), 1477 .nbytes_max = __cpu_to_le32(256), 1478 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1479 .reserved = __cpu_to_le32(0), 1480 }, 1481 1482 /* CE5: target->host Pktlog */ 1483 { 1484 .pipenum = __cpu_to_le32(5), 1485 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1486 .nentries = __cpu_to_le32(32), 1487 .nbytes_max = __cpu_to_le32(2048), 1488 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1489 .reserved = __cpu_to_le32(0), 1490 }, 1491 1492 /* CE6: Reserved for target autonomous hif_memcpy */ 1493 { 1494 .pipenum = __cpu_to_le32(6), 1495 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1496 .nentries = __cpu_to_le32(32), 1497 .nbytes_max = __cpu_to_le32(16384), 1498 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1499 .reserved = __cpu_to_le32(0), 1500 }, 1501 1502 /* CE7 used only by Host */ 1503 { 1504 .pipenum = __cpu_to_le32(7), 1505 .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H), 1506 .nentries = __cpu_to_le32(0), 1507 .nbytes_max = __cpu_to_le32(0), 1508 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1509 .reserved = __cpu_to_le32(0), 1510 }, 1511 1512 /* CE8 target->host used only by IPA */ 1513 { 1514 .pipenum = __cpu_to_le32(8), 1515 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1516 .nentries = __cpu_to_le32(32), 1517 .nbytes_max = __cpu_to_le32(16384), 1518 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1519 .reserved = __cpu_to_le32(0), 1520 }, 1521 /* CE 9, 10, 11 are used by MHI driver */ 1522 }; 1523 1524 /* Map from service/endpoint to Copy Engine. 1525 * This table is derived from the CE_PCI TABLE, above. 1526 * It is passed to the Target at startup for use by firmware. 1527 */ 1528 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qca6390[] = { 1529 { 1530 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1531 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1532 __cpu_to_le32(3), 1533 }, 1534 { 1535 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1536 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1537 __cpu_to_le32(2), 1538 }, 1539 { 1540 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1541 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1542 __cpu_to_le32(3), 1543 }, 1544 { 1545 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1546 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1547 __cpu_to_le32(2), 1548 }, 1549 { 1550 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1551 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1552 __cpu_to_le32(3), 1553 }, 1554 { 1555 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1556 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1557 __cpu_to_le32(2), 1558 }, 1559 { 1560 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1561 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1562 __cpu_to_le32(3), 1563 }, 1564 { 1565 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1566 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1567 __cpu_to_le32(2), 1568 }, 1569 { 1570 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1571 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1572 __cpu_to_le32(3), 1573 }, 1574 { 1575 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1576 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1577 __cpu_to_le32(2), 1578 }, 1579 { 1580 __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1581 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1582 __cpu_to_le32(0), 1583 }, 1584 { 1585 __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1586 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1587 __cpu_to_le32(2), 1588 }, 1589 { 1590 __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1591 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1592 __cpu_to_le32(4), 1593 }, 1594 { 1595 __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1596 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1597 __cpu_to_le32(1), 1598 }, 1599 1600 /* (Additions here) */ 1601 1602 { /* must be last */ 1603 __cpu_to_le32(0), 1604 __cpu_to_le32(0), 1605 __cpu_to_le32(0), 1606 }, 1607 }; 1608 1609 /* Target firmware's Copy Engine configuration. */ 1610 const struct ce_pipe_config ath11k_target_ce_config_wlan_qcn9074[] = { 1611 /* CE0: host->target HTC control and raw streams */ 1612 { 1613 .pipenum = __cpu_to_le32(0), 1614 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1615 .nentries = __cpu_to_le32(32), 1616 .nbytes_max = __cpu_to_le32(2048), 1617 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1618 .reserved = __cpu_to_le32(0), 1619 }, 1620 1621 /* CE1: target->host HTT + HTC control */ 1622 { 1623 .pipenum = __cpu_to_le32(1), 1624 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1625 .nentries = __cpu_to_le32(32), 1626 .nbytes_max = __cpu_to_le32(2048), 1627 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1628 .reserved = __cpu_to_le32(0), 1629 }, 1630 1631 /* CE2: target->host WMI */ 1632 { 1633 .pipenum = __cpu_to_le32(2), 1634 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1635 .nentries = __cpu_to_le32(32), 1636 .nbytes_max = __cpu_to_le32(2048), 1637 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1638 .reserved = __cpu_to_le32(0), 1639 }, 1640 1641 /* CE3: host->target WMI */ 1642 { 1643 .pipenum = __cpu_to_le32(3), 1644 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1645 .nentries = __cpu_to_le32(32), 1646 .nbytes_max = __cpu_to_le32(2048), 1647 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1648 .reserved = __cpu_to_le32(0), 1649 }, 1650 1651 /* CE4: host->target HTT */ 1652 { 1653 .pipenum = __cpu_to_le32(4), 1654 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1655 .nentries = __cpu_to_le32(256), 1656 .nbytes_max = __cpu_to_le32(256), 1657 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1658 .reserved = __cpu_to_le32(0), 1659 }, 1660 1661 /* CE5: target->host Pktlog */ 1662 { 1663 .pipenum = __cpu_to_le32(5), 1664 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1665 .nentries = __cpu_to_le32(32), 1666 .nbytes_max = __cpu_to_le32(2048), 1667 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1668 .reserved = __cpu_to_le32(0), 1669 }, 1670 1671 /* CE6: Reserved for target autonomous hif_memcpy */ 1672 { 1673 .pipenum = __cpu_to_le32(6), 1674 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1675 .nentries = __cpu_to_le32(32), 1676 .nbytes_max = __cpu_to_le32(16384), 1677 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1678 .reserved = __cpu_to_le32(0), 1679 }, 1680 1681 /* CE7 used only by Host */ 1682 { 1683 .pipenum = __cpu_to_le32(7), 1684 .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H), 1685 .nentries = __cpu_to_le32(0), 1686 .nbytes_max = __cpu_to_le32(0), 1687 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1688 .reserved = __cpu_to_le32(0), 1689 }, 1690 1691 /* CE8 target->host used only by IPA */ 1692 { 1693 .pipenum = __cpu_to_le32(8), 1694 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1695 .nentries = __cpu_to_le32(32), 1696 .nbytes_max = __cpu_to_le32(16384), 1697 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1698 .reserved = __cpu_to_le32(0), 1699 }, 1700 /* CE 9, 10, 11 are used by MHI driver */ 1701 }; 1702 1703 /* Map from service/endpoint to Copy Engine. 1704 * This table is derived from the CE_PCI TABLE, above. 1705 * It is passed to the Target at startup for use by firmware. 1706 */ 1707 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qcn9074[] = { 1708 { 1709 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1710 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1711 __cpu_to_le32(3), 1712 }, 1713 { 1714 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1715 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1716 __cpu_to_le32(2), 1717 }, 1718 { 1719 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1720 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1721 __cpu_to_le32(3), 1722 }, 1723 { 1724 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1725 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1726 __cpu_to_le32(2), 1727 }, 1728 { 1729 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1730 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1731 __cpu_to_le32(3), 1732 }, 1733 { 1734 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1735 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1736 __cpu_to_le32(2), 1737 }, 1738 { 1739 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1740 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1741 __cpu_to_le32(3), 1742 }, 1743 { 1744 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1745 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1746 __cpu_to_le32(2), 1747 }, 1748 { 1749 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1750 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1751 __cpu_to_le32(3), 1752 }, 1753 { 1754 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1755 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1756 __cpu_to_le32(2), 1757 }, 1758 { 1759 __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1760 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1761 __cpu_to_le32(0), 1762 }, 1763 { 1764 __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1765 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1766 __cpu_to_le32(1), 1767 }, 1768 { 1769 __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1770 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1771 __cpu_to_le32(0), 1772 }, 1773 { 1774 __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1775 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1776 __cpu_to_le32(1), 1777 }, 1778 { 1779 __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1780 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1781 __cpu_to_le32(4), 1782 }, 1783 { 1784 __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1785 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1786 __cpu_to_le32(1), 1787 }, 1788 { 1789 __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG), 1790 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1791 __cpu_to_le32(5), 1792 }, 1793 1794 /* (Additions here) */ 1795 1796 { /* must be last */ 1797 __cpu_to_le32(0), 1798 __cpu_to_le32(0), 1799 __cpu_to_le32(0), 1800 }, 1801 }; 1802 1803 const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qcn9074 = { 1804 .tx = { 1805 ATH11K_TX_RING_MASK_0, 1806 ATH11K_TX_RING_MASK_1, 1807 ATH11K_TX_RING_MASK_2, 1808 }, 1809 .rx_mon_status = { 1810 0, 0, 0, 1811 ATH11K_RX_MON_STATUS_RING_MASK_0, 1812 ATH11K_RX_MON_STATUS_RING_MASK_1, 1813 ATH11K_RX_MON_STATUS_RING_MASK_2, 1814 }, 1815 .rx = { 1816 0, 0, 0, 0, 1817 ATH11K_RX_RING_MASK_0, 1818 ATH11K_RX_RING_MASK_1, 1819 ATH11K_RX_RING_MASK_2, 1820 ATH11K_RX_RING_MASK_3, 1821 }, 1822 .rx_err = { 1823 0, 0, 0, 1824 ATH11K_RX_ERR_RING_MASK_0, 1825 }, 1826 .rx_wbm_rel = { 1827 0, 0, 0, 1828 ATH11K_RX_WBM_REL_RING_MASK_0, 1829 }, 1830 .reo_status = { 1831 0, 0, 0, 1832 ATH11K_REO_STATUS_RING_MASK_0, 1833 }, 1834 .rxdma2host = { 1835 0, 0, 0, 1836 ATH11K_RXDMA2HOST_RING_MASK_0, 1837 }, 1838 .host2rxdma = { 1839 0, 0, 0, 1840 ATH11K_HOST2RXDMA_RING_MASK_0, 1841 }, 1842 }; 1843 1844 const struct ath11k_hw_regs ipq8074_regs = { 1845 /* SW2TCL(x) R0 ring configuration address */ 1846 .hal_tcl1_ring_base_lsb = 0x00000510, 1847 .hal_tcl1_ring_base_msb = 0x00000514, 1848 .hal_tcl1_ring_id = 0x00000518, 1849 .hal_tcl1_ring_misc = 0x00000520, 1850 .hal_tcl1_ring_tp_addr_lsb = 0x0000052c, 1851 .hal_tcl1_ring_tp_addr_msb = 0x00000530, 1852 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000540, 1853 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000544, 1854 .hal_tcl1_ring_msi1_base_lsb = 0x00000558, 1855 .hal_tcl1_ring_msi1_base_msb = 0x0000055c, 1856 .hal_tcl1_ring_msi1_data = 0x00000560, 1857 .hal_tcl2_ring_base_lsb = 0x00000568, 1858 .hal_tcl_ring_base_lsb = 0x00000618, 1859 1860 /* TCL STATUS ring address */ 1861 .hal_tcl_status_ring_base_lsb = 0x00000720, 1862 1863 /* REO2SW(x) R0 ring configuration address */ 1864 .hal_reo1_ring_base_lsb = 0x0000029c, 1865 .hal_reo1_ring_base_msb = 0x000002a0, 1866 .hal_reo1_ring_id = 0x000002a4, 1867 .hal_reo1_ring_misc = 0x000002ac, 1868 .hal_reo1_ring_hp_addr_lsb = 0x000002b0, 1869 .hal_reo1_ring_hp_addr_msb = 0x000002b4, 1870 .hal_reo1_ring_producer_int_setup = 0x000002c0, 1871 .hal_reo1_ring_msi1_base_lsb = 0x000002e4, 1872 .hal_reo1_ring_msi1_base_msb = 0x000002e8, 1873 .hal_reo1_ring_msi1_data = 0x000002ec, 1874 .hal_reo2_ring_base_lsb = 0x000002f4, 1875 .hal_reo1_aging_thresh_ix_0 = 0x00000564, 1876 .hal_reo1_aging_thresh_ix_1 = 0x00000568, 1877 .hal_reo1_aging_thresh_ix_2 = 0x0000056c, 1878 .hal_reo1_aging_thresh_ix_3 = 0x00000570, 1879 1880 /* REO2SW(x) R2 ring pointers (head/tail) address */ 1881 .hal_reo1_ring_hp = 0x00003038, 1882 .hal_reo1_ring_tp = 0x0000303c, 1883 .hal_reo2_ring_hp = 0x00003040, 1884 1885 /* REO2TCL R0 ring configuration address */ 1886 .hal_reo_tcl_ring_base_lsb = 0x000003fc, 1887 .hal_reo_tcl_ring_hp = 0x00003058, 1888 1889 /* REO status address */ 1890 .hal_reo_status_ring_base_lsb = 0x00000504, 1891 .hal_reo_status_hp = 0x00003070, 1892 1893 /* WCSS relative address */ 1894 .hal_seq_wcss_umac_ce0_src_reg = 0x00a00000, 1895 .hal_seq_wcss_umac_ce0_dst_reg = 0x00a01000, 1896 .hal_seq_wcss_umac_ce1_src_reg = 0x00a02000, 1897 .hal_seq_wcss_umac_ce1_dst_reg = 0x00a03000, 1898 1899 /* WBM Idle address */ 1900 .hal_wbm_idle_link_ring_base_lsb = 0x00000860, 1901 .hal_wbm_idle_link_ring_misc = 0x00000870, 1902 1903 /* SW2WBM release address */ 1904 .hal_wbm_release_ring_base_lsb = 0x000001d8, 1905 1906 /* WBM2SW release address */ 1907 .hal_wbm0_release_ring_base_lsb = 0x00000910, 1908 .hal_wbm1_release_ring_base_lsb = 0x00000968, 1909 1910 /* PCIe base address */ 1911 .pcie_qserdes_sysclk_en_sel = 0x0, 1912 .pcie_pcs_osc_dtct_config_base = 0x0, 1913 }; 1914 1915 const struct ath11k_hw_regs qca6390_regs = { 1916 /* SW2TCL(x) R0 ring configuration address */ 1917 .hal_tcl1_ring_base_lsb = 0x00000684, 1918 .hal_tcl1_ring_base_msb = 0x00000688, 1919 .hal_tcl1_ring_id = 0x0000068c, 1920 .hal_tcl1_ring_misc = 0x00000694, 1921 .hal_tcl1_ring_tp_addr_lsb = 0x000006a0, 1922 .hal_tcl1_ring_tp_addr_msb = 0x000006a4, 1923 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006b4, 1924 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006b8, 1925 .hal_tcl1_ring_msi1_base_lsb = 0x000006cc, 1926 .hal_tcl1_ring_msi1_base_msb = 0x000006d0, 1927 .hal_tcl1_ring_msi1_data = 0x000006d4, 1928 .hal_tcl2_ring_base_lsb = 0x000006dc, 1929 .hal_tcl_ring_base_lsb = 0x0000078c, 1930 1931 /* TCL STATUS ring address */ 1932 .hal_tcl_status_ring_base_lsb = 0x00000894, 1933 1934 /* REO2SW(x) R0 ring configuration address */ 1935 .hal_reo1_ring_base_lsb = 0x00000244, 1936 .hal_reo1_ring_base_msb = 0x00000248, 1937 .hal_reo1_ring_id = 0x0000024c, 1938 .hal_reo1_ring_misc = 0x00000254, 1939 .hal_reo1_ring_hp_addr_lsb = 0x00000258, 1940 .hal_reo1_ring_hp_addr_msb = 0x0000025c, 1941 .hal_reo1_ring_producer_int_setup = 0x00000268, 1942 .hal_reo1_ring_msi1_base_lsb = 0x0000028c, 1943 .hal_reo1_ring_msi1_base_msb = 0x00000290, 1944 .hal_reo1_ring_msi1_data = 0x00000294, 1945 .hal_reo2_ring_base_lsb = 0x0000029c, 1946 .hal_reo1_aging_thresh_ix_0 = 0x0000050c, 1947 .hal_reo1_aging_thresh_ix_1 = 0x00000510, 1948 .hal_reo1_aging_thresh_ix_2 = 0x00000514, 1949 .hal_reo1_aging_thresh_ix_3 = 0x00000518, 1950 1951 /* REO2SW(x) R2 ring pointers (head/tail) address */ 1952 .hal_reo1_ring_hp = 0x00003030, 1953 .hal_reo1_ring_tp = 0x00003034, 1954 .hal_reo2_ring_hp = 0x00003038, 1955 1956 /* REO2TCL R0 ring configuration address */ 1957 .hal_reo_tcl_ring_base_lsb = 0x000003a4, 1958 .hal_reo_tcl_ring_hp = 0x00003050, 1959 1960 /* REO status address */ 1961 .hal_reo_status_ring_base_lsb = 0x000004ac, 1962 .hal_reo_status_hp = 0x00003068, 1963 1964 /* WCSS relative address */ 1965 .hal_seq_wcss_umac_ce0_src_reg = 0x00a00000, 1966 .hal_seq_wcss_umac_ce0_dst_reg = 0x00a01000, 1967 .hal_seq_wcss_umac_ce1_src_reg = 0x00a02000, 1968 .hal_seq_wcss_umac_ce1_dst_reg = 0x00a03000, 1969 1970 /* WBM Idle address */ 1971 .hal_wbm_idle_link_ring_base_lsb = 0x00000860, 1972 .hal_wbm_idle_link_ring_misc = 0x00000870, 1973 1974 /* SW2WBM release address */ 1975 .hal_wbm_release_ring_base_lsb = 0x000001d8, 1976 1977 /* WBM2SW release address */ 1978 .hal_wbm0_release_ring_base_lsb = 0x00000910, 1979 .hal_wbm1_release_ring_base_lsb = 0x00000968, 1980 1981 /* PCIe base address */ 1982 .pcie_qserdes_sysclk_en_sel = 0x01e0c0ac, 1983 .pcie_pcs_osc_dtct_config_base = 0x01e0c628, 1984 }; 1985 1986 const struct ath11k_hw_regs qcn9074_regs = { 1987 /* SW2TCL(x) R0 ring configuration address */ 1988 .hal_tcl1_ring_base_lsb = 0x000004f0, 1989 .hal_tcl1_ring_base_msb = 0x000004f4, 1990 .hal_tcl1_ring_id = 0x000004f8, 1991 .hal_tcl1_ring_misc = 0x00000500, 1992 .hal_tcl1_ring_tp_addr_lsb = 0x0000050c, 1993 .hal_tcl1_ring_tp_addr_msb = 0x00000510, 1994 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000520, 1995 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000524, 1996 .hal_tcl1_ring_msi1_base_lsb = 0x00000538, 1997 .hal_tcl1_ring_msi1_base_msb = 0x0000053c, 1998 .hal_tcl1_ring_msi1_data = 0x00000540, 1999 .hal_tcl2_ring_base_lsb = 0x00000548, 2000 .hal_tcl_ring_base_lsb = 0x000005f8, 2001 2002 /* TCL STATUS ring address */ 2003 .hal_tcl_status_ring_base_lsb = 0x00000700, 2004 2005 /* REO2SW(x) R0 ring configuration address */ 2006 .hal_reo1_ring_base_lsb = 0x0000029c, 2007 .hal_reo1_ring_base_msb = 0x000002a0, 2008 .hal_reo1_ring_id = 0x000002a4, 2009 .hal_reo1_ring_misc = 0x000002ac, 2010 .hal_reo1_ring_hp_addr_lsb = 0x000002b0, 2011 .hal_reo1_ring_hp_addr_msb = 0x000002b4, 2012 .hal_reo1_ring_producer_int_setup = 0x000002c0, 2013 .hal_reo1_ring_msi1_base_lsb = 0x000002e4, 2014 .hal_reo1_ring_msi1_base_msb = 0x000002e8, 2015 .hal_reo1_ring_msi1_data = 0x000002ec, 2016 .hal_reo2_ring_base_lsb = 0x000002f4, 2017 .hal_reo1_aging_thresh_ix_0 = 0x00000564, 2018 .hal_reo1_aging_thresh_ix_1 = 0x00000568, 2019 .hal_reo1_aging_thresh_ix_2 = 0x0000056c, 2020 .hal_reo1_aging_thresh_ix_3 = 0x00000570, 2021 2022 /* REO2SW(x) R2 ring pointers (head/tail) address */ 2023 .hal_reo1_ring_hp = 0x00003038, 2024 .hal_reo1_ring_tp = 0x0000303c, 2025 .hal_reo2_ring_hp = 0x00003040, 2026 2027 /* REO2TCL R0 ring configuration address */ 2028 .hal_reo_tcl_ring_base_lsb = 0x000003fc, 2029 .hal_reo_tcl_ring_hp = 0x00003058, 2030 2031 /* REO status address */ 2032 .hal_reo_status_ring_base_lsb = 0x00000504, 2033 .hal_reo_status_hp = 0x00003070, 2034 2035 /* WCSS relative address */ 2036 .hal_seq_wcss_umac_ce0_src_reg = 0x01b80000, 2037 .hal_seq_wcss_umac_ce0_dst_reg = 0x01b81000, 2038 .hal_seq_wcss_umac_ce1_src_reg = 0x01b82000, 2039 .hal_seq_wcss_umac_ce1_dst_reg = 0x01b83000, 2040 2041 /* WBM Idle address */ 2042 .hal_wbm_idle_link_ring_base_lsb = 0x00000874, 2043 .hal_wbm_idle_link_ring_misc = 0x00000884, 2044 2045 /* SW2WBM release address */ 2046 .hal_wbm_release_ring_base_lsb = 0x000001ec, 2047 2048 /* WBM2SW release address */ 2049 .hal_wbm0_release_ring_base_lsb = 0x00000924, 2050 .hal_wbm1_release_ring_base_lsb = 0x0000097c, 2051 2052 /* PCIe base address */ 2053 .pcie_qserdes_sysclk_en_sel = 0x01e0e0a8, 2054 .pcie_pcs_osc_dtct_config_base = 0x01e0f45c, 2055 }; 2056 2057 const struct ath11k_hw_regs wcn6855_regs = { 2058 /* SW2TCL(x) R0 ring configuration address */ 2059 .hal_tcl1_ring_base_lsb = 0x00000690, 2060 .hal_tcl1_ring_base_msb = 0x00000694, 2061 .hal_tcl1_ring_id = 0x00000698, 2062 .hal_tcl1_ring_misc = 0x000006a0, 2063 .hal_tcl1_ring_tp_addr_lsb = 0x000006ac, 2064 .hal_tcl1_ring_tp_addr_msb = 0x000006b0, 2065 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006c0, 2066 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006c4, 2067 .hal_tcl1_ring_msi1_base_lsb = 0x000006d8, 2068 .hal_tcl1_ring_msi1_base_msb = 0x000006dc, 2069 .hal_tcl1_ring_msi1_data = 0x000006e0, 2070 .hal_tcl2_ring_base_lsb = 0x000006e8, 2071 .hal_tcl_ring_base_lsb = 0x00000798, 2072 2073 /* TCL STATUS ring address */ 2074 .hal_tcl_status_ring_base_lsb = 0x000008a0, 2075 2076 /* REO2SW(x) R0 ring configuration address */ 2077 .hal_reo1_ring_base_lsb = 0x00000244, 2078 .hal_reo1_ring_base_msb = 0x00000248, 2079 .hal_reo1_ring_id = 0x0000024c, 2080 .hal_reo1_ring_misc = 0x00000254, 2081 .hal_reo1_ring_hp_addr_lsb = 0x00000258, 2082 .hal_reo1_ring_hp_addr_msb = 0x0000025c, 2083 .hal_reo1_ring_producer_int_setup = 0x00000268, 2084 .hal_reo1_ring_msi1_base_lsb = 0x0000028c, 2085 .hal_reo1_ring_msi1_base_msb = 0x00000290, 2086 .hal_reo1_ring_msi1_data = 0x00000294, 2087 .hal_reo2_ring_base_lsb = 0x0000029c, 2088 .hal_reo1_aging_thresh_ix_0 = 0x000005bc, 2089 .hal_reo1_aging_thresh_ix_1 = 0x000005c0, 2090 .hal_reo1_aging_thresh_ix_2 = 0x000005c4, 2091 .hal_reo1_aging_thresh_ix_3 = 0x000005c8, 2092 2093 /* REO2SW(x) R2 ring pointers (head/tail) address */ 2094 .hal_reo1_ring_hp = 0x00003030, 2095 .hal_reo1_ring_tp = 0x00003034, 2096 .hal_reo2_ring_hp = 0x00003038, 2097 2098 /* REO2TCL R0 ring configuration address */ 2099 .hal_reo_tcl_ring_base_lsb = 0x00000454, 2100 .hal_reo_tcl_ring_hp = 0x00003060, 2101 2102 /* REO status address */ 2103 .hal_reo_status_ring_base_lsb = 0x0000055c, 2104 .hal_reo_status_hp = 0x00003078, 2105 2106 /* WCSS relative address */ 2107 .hal_seq_wcss_umac_ce0_src_reg = 0x1b80000, 2108 .hal_seq_wcss_umac_ce0_dst_reg = 0x1b81000, 2109 .hal_seq_wcss_umac_ce1_src_reg = 0x1b82000, 2110 .hal_seq_wcss_umac_ce1_dst_reg = 0x1b83000, 2111 2112 /* WBM Idle address */ 2113 .hal_wbm_idle_link_ring_base_lsb = 0x00000870, 2114 .hal_wbm_idle_link_ring_misc = 0x00000880, 2115 2116 /* SW2WBM release address */ 2117 .hal_wbm_release_ring_base_lsb = 0x000001e8, 2118 2119 /* WBM2SW release address */ 2120 .hal_wbm0_release_ring_base_lsb = 0x00000920, 2121 .hal_wbm1_release_ring_base_lsb = 0x00000978, 2122 2123 /* PCIe base address */ 2124 .pcie_qserdes_sysclk_en_sel = 0x01e0c0ac, 2125 .pcie_pcs_osc_dtct_config_base = 0x01e0c628, 2126 }; 2127