1d547ca4cSAnilkumar Kolli // SPDX-License-Identifier: BSD-3-Clause-Clear 2d547ca4cSAnilkumar Kolli /* 3d547ca4cSAnilkumar Kolli * Copyright (c) 2018-2020 The Linux Foundation. All rights reserved. 4d547ca4cSAnilkumar Kolli */ 5d547ca4cSAnilkumar Kolli 6d547ca4cSAnilkumar Kolli #include "core.h" 7d547ca4cSAnilkumar Kolli 8d547ca4cSAnilkumar Kolli /* Map from pdev index to hw mac index */ 9d547ca4cSAnilkumar Kolli static u8 ath11k_hw_ipq8074_mac_from_pdev_id(int pdev_idx) 10d547ca4cSAnilkumar Kolli { 11d547ca4cSAnilkumar Kolli switch (pdev_idx) { 12d547ca4cSAnilkumar Kolli case 0: 13d547ca4cSAnilkumar Kolli return 0; 14d547ca4cSAnilkumar Kolli case 1: 15d547ca4cSAnilkumar Kolli return 2; 16d547ca4cSAnilkumar Kolli case 2: 17d547ca4cSAnilkumar Kolli return 1; 18d547ca4cSAnilkumar Kolli default: 19d547ca4cSAnilkumar Kolli return ATH11K_INVALID_HW_MAC_ID; 20d547ca4cSAnilkumar Kolli } 21d547ca4cSAnilkumar Kolli } 22d547ca4cSAnilkumar Kolli 23d547ca4cSAnilkumar Kolli static u8 ath11k_hw_ipq6018_mac_from_pdev_id(int pdev_idx) 24d547ca4cSAnilkumar Kolli { 25d547ca4cSAnilkumar Kolli return pdev_idx; 26d547ca4cSAnilkumar Kolli } 27d547ca4cSAnilkumar Kolli 28d547ca4cSAnilkumar Kolli const struct ath11k_hw_ops ipq8074_ops = { 29d547ca4cSAnilkumar Kolli .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id, 30d547ca4cSAnilkumar Kolli }; 31d547ca4cSAnilkumar Kolli 32d547ca4cSAnilkumar Kolli const struct ath11k_hw_ops ipq6018_ops = { 33d547ca4cSAnilkumar Kolli .get_hw_mac_from_pdev_id = ath11k_hw_ipq6018_mac_from_pdev_id, 34d547ca4cSAnilkumar Kolli }; 359de2ad43SCarl Huang 369de2ad43SCarl Huang const struct ath11k_hw_ops qca6390_ops = { 379de2ad43SCarl Huang .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id, 389de2ad43SCarl Huang }; 39*34d5a3a8SKalle Valo 40*34d5a3a8SKalle Valo #define ATH11K_TX_RING_MASK_0 0x1 41*34d5a3a8SKalle Valo #define ATH11K_TX_RING_MASK_1 0x2 42*34d5a3a8SKalle Valo #define ATH11K_TX_RING_MASK_2 0x4 43*34d5a3a8SKalle Valo 44*34d5a3a8SKalle Valo #define ATH11K_RX_RING_MASK_0 0x1 45*34d5a3a8SKalle Valo #define ATH11K_RX_RING_MASK_1 0x2 46*34d5a3a8SKalle Valo #define ATH11K_RX_RING_MASK_2 0x4 47*34d5a3a8SKalle Valo #define ATH11K_RX_RING_MASK_3 0x8 48*34d5a3a8SKalle Valo 49*34d5a3a8SKalle Valo #define ATH11K_RX_ERR_RING_MASK_0 0x1 50*34d5a3a8SKalle Valo 51*34d5a3a8SKalle Valo #define ATH11K_RX_WBM_REL_RING_MASK_0 0x1 52*34d5a3a8SKalle Valo 53*34d5a3a8SKalle Valo #define ATH11K_REO_STATUS_RING_MASK_0 0x1 54*34d5a3a8SKalle Valo 55*34d5a3a8SKalle Valo #define ATH11K_RXDMA2HOST_RING_MASK_0 0x1 56*34d5a3a8SKalle Valo #define ATH11K_RXDMA2HOST_RING_MASK_1 0x2 57*34d5a3a8SKalle Valo #define ATH11K_RXDMA2HOST_RING_MASK_2 0x4 58*34d5a3a8SKalle Valo 59*34d5a3a8SKalle Valo #define ATH11K_HOST2RXDMA_RING_MASK_0 0x1 60*34d5a3a8SKalle Valo #define ATH11K_HOST2RXDMA_RING_MASK_1 0x2 61*34d5a3a8SKalle Valo #define ATH11K_HOST2RXDMA_RING_MASK_2 0x4 62*34d5a3a8SKalle Valo 63*34d5a3a8SKalle Valo #define ATH11K_RX_MON_STATUS_RING_MASK_0 0x1 64*34d5a3a8SKalle Valo #define ATH11K_RX_MON_STATUS_RING_MASK_1 0x2 65*34d5a3a8SKalle Valo #define ATH11K_RX_MON_STATUS_RING_MASK_2 0x4 66*34d5a3a8SKalle Valo 67*34d5a3a8SKalle Valo const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_ipq8074 = { 68*34d5a3a8SKalle Valo .tx = { 69*34d5a3a8SKalle Valo ATH11K_TX_RING_MASK_0, 70*34d5a3a8SKalle Valo ATH11K_TX_RING_MASK_1, 71*34d5a3a8SKalle Valo ATH11K_TX_RING_MASK_2, 72*34d5a3a8SKalle Valo }, 73*34d5a3a8SKalle Valo .rx_mon_status = { 74*34d5a3a8SKalle Valo 0, 0, 0, 0, 75*34d5a3a8SKalle Valo ATH11K_RX_MON_STATUS_RING_MASK_0, 76*34d5a3a8SKalle Valo ATH11K_RX_MON_STATUS_RING_MASK_1, 77*34d5a3a8SKalle Valo ATH11K_RX_MON_STATUS_RING_MASK_2, 78*34d5a3a8SKalle Valo }, 79*34d5a3a8SKalle Valo .rx = { 80*34d5a3a8SKalle Valo 0, 0, 0, 0, 0, 0, 0, 81*34d5a3a8SKalle Valo ATH11K_RX_RING_MASK_0, 82*34d5a3a8SKalle Valo ATH11K_RX_RING_MASK_1, 83*34d5a3a8SKalle Valo ATH11K_RX_RING_MASK_2, 84*34d5a3a8SKalle Valo ATH11K_RX_RING_MASK_3, 85*34d5a3a8SKalle Valo }, 86*34d5a3a8SKalle Valo .rx_err = { 87*34d5a3a8SKalle Valo ATH11K_RX_ERR_RING_MASK_0, 88*34d5a3a8SKalle Valo }, 89*34d5a3a8SKalle Valo .rx_wbm_rel = { 90*34d5a3a8SKalle Valo ATH11K_RX_WBM_REL_RING_MASK_0, 91*34d5a3a8SKalle Valo }, 92*34d5a3a8SKalle Valo .reo_status = { 93*34d5a3a8SKalle Valo ATH11K_REO_STATUS_RING_MASK_0, 94*34d5a3a8SKalle Valo }, 95*34d5a3a8SKalle Valo .rxdma2host = { 96*34d5a3a8SKalle Valo ATH11K_RXDMA2HOST_RING_MASK_0, 97*34d5a3a8SKalle Valo ATH11K_RXDMA2HOST_RING_MASK_1, 98*34d5a3a8SKalle Valo ATH11K_RXDMA2HOST_RING_MASK_2, 99*34d5a3a8SKalle Valo }, 100*34d5a3a8SKalle Valo .host2rxdma = { 101*34d5a3a8SKalle Valo ATH11K_HOST2RXDMA_RING_MASK_0, 102*34d5a3a8SKalle Valo ATH11K_HOST2RXDMA_RING_MASK_1, 103*34d5a3a8SKalle Valo ATH11K_HOST2RXDMA_RING_MASK_2, 104*34d5a3a8SKalle Valo }, 105*34d5a3a8SKalle Valo }; 106*34d5a3a8SKalle Valo 107