1d547ca4cSAnilkumar Kolli // SPDX-License-Identifier: BSD-3-Clause-Clear 2d547ca4cSAnilkumar Kolli /* 3d547ca4cSAnilkumar Kolli * Copyright (c) 2018-2020 The Linux Foundation. All rights reserved. 449890d9cSManikanta Pubbisetty * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 5d547ca4cSAnilkumar Kolli */ 6d547ca4cSAnilkumar Kolli 76976433cSCarl Huang #include <linux/types.h> 86976433cSCarl Huang #include <linux/bitops.h> 96976433cSCarl Huang #include <linux/bitfield.h> 106976433cSCarl Huang 11d547ca4cSAnilkumar Kolli #include "core.h" 12e3396b8bSCarl Huang #include "ce.h" 130d55b76fSBaochen Qiang #include "hif.h" 14734223d7SBaochen Qiang #include "hal.h" 15734223d7SBaochen Qiang #include "hw.h" 16d547ca4cSAnilkumar Kolli 17d547ca4cSAnilkumar Kolli /* Map from pdev index to hw mac index */ 18d547ca4cSAnilkumar Kolli static u8 ath11k_hw_ipq8074_mac_from_pdev_id(int pdev_idx) 19d547ca4cSAnilkumar Kolli { 20d547ca4cSAnilkumar Kolli switch (pdev_idx) { 21d547ca4cSAnilkumar Kolli case 0: 22d547ca4cSAnilkumar Kolli return 0; 23d547ca4cSAnilkumar Kolli case 1: 24d547ca4cSAnilkumar Kolli return 2; 25d547ca4cSAnilkumar Kolli case 2: 26d547ca4cSAnilkumar Kolli return 1; 27d547ca4cSAnilkumar Kolli default: 28d547ca4cSAnilkumar Kolli return ATH11K_INVALID_HW_MAC_ID; 29d547ca4cSAnilkumar Kolli } 30d547ca4cSAnilkumar Kolli } 31d547ca4cSAnilkumar Kolli 32d547ca4cSAnilkumar Kolli static u8 ath11k_hw_ipq6018_mac_from_pdev_id(int pdev_idx) 33d547ca4cSAnilkumar Kolli { 34d547ca4cSAnilkumar Kolli return pdev_idx; 35d547ca4cSAnilkumar Kolli } 36d547ca4cSAnilkumar Kolli 376fe6f68fSKarthikeyan Periyasamy static void ath11k_hw_ipq8074_tx_mesh_enable(struct ath11k_base *ab, 386fe6f68fSKarthikeyan Periyasamy struct hal_tcl_data_cmd *tcl_cmd) 396fe6f68fSKarthikeyan Periyasamy { 406fe6f68fSKarthikeyan Periyasamy tcl_cmd->info2 |= FIELD_PREP(HAL_IPQ8074_TCL_DATA_CMD_INFO2_MESH_ENABLE, 416fe6f68fSKarthikeyan Periyasamy true); 426fe6f68fSKarthikeyan Periyasamy } 436fe6f68fSKarthikeyan Periyasamy 446fe6f68fSKarthikeyan Periyasamy static void ath11k_hw_qcn9074_tx_mesh_enable(struct ath11k_base *ab, 456fe6f68fSKarthikeyan Periyasamy struct hal_tcl_data_cmd *tcl_cmd) 466fe6f68fSKarthikeyan Periyasamy { 476fe6f68fSKarthikeyan Periyasamy tcl_cmd->info3 |= FIELD_PREP(HAL_QCN9074_TCL_DATA_CMD_INFO3_MESH_ENABLE, 486fe6f68fSKarthikeyan Periyasamy true); 496fe6f68fSKarthikeyan Periyasamy } 506fe6f68fSKarthikeyan Periyasamy 51e4073430SBaochen Qiang static void ath11k_hw_wcn6855_tx_mesh_enable(struct ath11k_base *ab, 52e4073430SBaochen Qiang struct hal_tcl_data_cmd *tcl_cmd) 53e4073430SBaochen Qiang { 54e4073430SBaochen Qiang tcl_cmd->info3 |= FIELD_PREP(HAL_QCN9074_TCL_DATA_CMD_INFO3_MESH_ENABLE, 55e4073430SBaochen Qiang true); 56e4073430SBaochen Qiang } 57e4073430SBaochen Qiang 582d4bcbedSCarl Huang static void ath11k_init_wmi_config_qca6390(struct ath11k_base *ab, 592d4bcbedSCarl Huang struct target_resource_config *config) 602d4bcbedSCarl Huang { 612d4bcbedSCarl Huang config->num_vdevs = 4; 622d4bcbedSCarl Huang config->num_peers = 16; 632d4bcbedSCarl Huang config->num_tids = 32; 642d4bcbedSCarl Huang 652d4bcbedSCarl Huang config->num_offload_peers = 3; 662d4bcbedSCarl Huang config->num_offload_reorder_buffs = 3; 672d4bcbedSCarl Huang config->num_peer_keys = TARGET_NUM_PEER_KEYS; 682d4bcbedSCarl Huang config->ast_skid_limit = TARGET_AST_SKID_LIMIT; 692d4bcbedSCarl Huang config->tx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 702d4bcbedSCarl Huang config->rx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 712d4bcbedSCarl Huang config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI; 722d4bcbedSCarl Huang config->rx_timeout_pri[1] = TARGET_RX_TIMEOUT_LO_PRI; 732d4bcbedSCarl Huang config->rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI; 742d4bcbedSCarl Huang config->rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI; 752d4bcbedSCarl Huang config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI; 762d4bcbedSCarl Huang config->scan_max_pending_req = TARGET_SCAN_MAX_PENDING_REQS; 772d4bcbedSCarl Huang config->bmiss_offload_max_vdev = TARGET_BMISS_OFFLOAD_MAX_VDEV; 782d4bcbedSCarl Huang config->roam_offload_max_vdev = TARGET_ROAM_OFFLOAD_MAX_VDEV; 792d4bcbedSCarl Huang config->roam_offload_max_ap_profiles = TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES; 802d4bcbedSCarl Huang config->num_mcast_groups = 0; 812d4bcbedSCarl Huang config->num_mcast_table_elems = 0; 822d4bcbedSCarl Huang config->mcast2ucast_mode = 0; 832d4bcbedSCarl Huang config->tx_dbg_log_size = TARGET_TX_DBG_LOG_SIZE; 842d4bcbedSCarl Huang config->num_wds_entries = 0; 852d4bcbedSCarl Huang config->dma_burst_size = 0; 862d4bcbedSCarl Huang config->rx_skip_defrag_timeout_dup_detection_check = 0; 872d4bcbedSCarl Huang config->vow_config = TARGET_VOW_CONFIG; 882d4bcbedSCarl Huang config->gtk_offload_max_vdev = 2; 892d4bcbedSCarl Huang config->num_msdu_desc = 0x400; 902d4bcbedSCarl Huang config->beacon_tx_offload_max_vdev = 2; 912d4bcbedSCarl Huang config->rx_batchmode = TARGET_RX_BATCHMODE; 922d4bcbedSCarl Huang 932d4bcbedSCarl Huang config->peer_map_unmap_v2_support = 0; 942d4bcbedSCarl Huang config->use_pdev_id = 1; 952d4bcbedSCarl Huang config->max_frag_entries = 0xa; 962d4bcbedSCarl Huang config->num_tdls_vdevs = 0x1; 972d4bcbedSCarl Huang config->num_tdls_conn_table_entries = 8; 982d4bcbedSCarl Huang config->beacon_tx_offload_max_vdev = 0x2; 992d4bcbedSCarl Huang config->num_multicast_filter_entries = 0x20; 1002d4bcbedSCarl Huang config->num_wow_filters = 0x16; 1012d4bcbedSCarl Huang config->num_keep_alive_pattern = 0; 1029b4dd38bSSeevalamuthu Mariappan config->flag1 |= WMI_RSRC_CFG_FLAG1_BSS_CHANNEL_INFO_64; 1032d4bcbedSCarl Huang } 1042d4bcbedSCarl Huang 1050d55b76fSBaochen Qiang static void ath11k_hw_ipq8074_reo_setup(struct ath11k_base *ab) 1060d55b76fSBaochen Qiang { 1070d55b76fSBaochen Qiang u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG; 1080d55b76fSBaochen Qiang u32 val; 1090d55b76fSBaochen Qiang /* Each hash entry uses three bits to map to a particular ring. */ 1100d55b76fSBaochen Qiang u32 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 | 1110d55b76fSBaochen Qiang HAL_HASH_ROUTING_RING_SW2 << 3 | 1120d55b76fSBaochen Qiang HAL_HASH_ROUTING_RING_SW3 << 6 | 1130d55b76fSBaochen Qiang HAL_HASH_ROUTING_RING_SW4 << 9 | 1140d55b76fSBaochen Qiang HAL_HASH_ROUTING_RING_SW1 << 12 | 1150d55b76fSBaochen Qiang HAL_HASH_ROUTING_RING_SW2 << 15 | 1160d55b76fSBaochen Qiang HAL_HASH_ROUTING_RING_SW3 << 18 | 1170d55b76fSBaochen Qiang HAL_HASH_ROUTING_RING_SW4 << 21; 1180d55b76fSBaochen Qiang 1190d55b76fSBaochen Qiang val = ath11k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE); 1200d55b76fSBaochen Qiang 1210d55b76fSBaochen Qiang val &= ~HAL_REO1_GEN_ENABLE_FRAG_DST_RING; 1220d55b76fSBaochen Qiang val |= FIELD_PREP(HAL_REO1_GEN_ENABLE_FRAG_DST_RING, 1230d55b76fSBaochen Qiang HAL_SRNG_RING_ID_REO2SW1) | 1240d55b76fSBaochen Qiang FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE, 1) | 1250d55b76fSBaochen Qiang FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE, 1); 1260d55b76fSBaochen Qiang ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val); 1270d55b76fSBaochen Qiang 1280d55b76fSBaochen Qiang ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab), 1290d55b76fSBaochen Qiang HAL_DEFAULT_REO_TIMEOUT_USEC); 1300d55b76fSBaochen Qiang ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab), 1310d55b76fSBaochen Qiang HAL_DEFAULT_REO_TIMEOUT_USEC); 1320d55b76fSBaochen Qiang ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab), 1330d55b76fSBaochen Qiang HAL_DEFAULT_REO_TIMEOUT_USEC); 1340d55b76fSBaochen Qiang ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab), 1350d55b76fSBaochen Qiang HAL_DEFAULT_REO_TIMEOUT_USEC); 1360d55b76fSBaochen Qiang 1370d55b76fSBaochen Qiang ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_0, 1380d55b76fSBaochen Qiang FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP, 1390d55b76fSBaochen Qiang ring_hash_map)); 1400d55b76fSBaochen Qiang ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_1, 1410d55b76fSBaochen Qiang FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP, 1420d55b76fSBaochen Qiang ring_hash_map)); 1430d55b76fSBaochen Qiang ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2, 1440d55b76fSBaochen Qiang FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP, 1450d55b76fSBaochen Qiang ring_hash_map)); 1460d55b76fSBaochen Qiang ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3, 1470d55b76fSBaochen Qiang FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP, 1480d55b76fSBaochen Qiang ring_hash_map)); 1490d55b76fSBaochen Qiang } 1500d55b76fSBaochen Qiang 1512d4bcbedSCarl Huang static void ath11k_init_wmi_config_ipq8074(struct ath11k_base *ab, 1522d4bcbedSCarl Huang struct target_resource_config *config) 1532d4bcbedSCarl Huang { 154523aafd0SKalle Valo config->num_vdevs = ab->num_radios * TARGET_NUM_VDEVS(ab); 1552d4bcbedSCarl Huang 1562d4bcbedSCarl Huang if (ab->num_radios == 2) { 157523aafd0SKalle Valo config->num_peers = TARGET_NUM_PEERS(ab, DBS); 158523aafd0SKalle Valo config->num_tids = TARGET_NUM_TIDS(ab, DBS); 1592d4bcbedSCarl Huang } else if (ab->num_radios == 3) { 160523aafd0SKalle Valo config->num_peers = TARGET_NUM_PEERS(ab, DBS_SBS); 161523aafd0SKalle Valo config->num_tids = TARGET_NUM_TIDS(ab, DBS_SBS); 1622d4bcbedSCarl Huang } else { 1632d4bcbedSCarl Huang /* Control should not reach here */ 164523aafd0SKalle Valo config->num_peers = TARGET_NUM_PEERS(ab, SINGLE); 165523aafd0SKalle Valo config->num_tids = TARGET_NUM_TIDS(ab, SINGLE); 1662d4bcbedSCarl Huang } 1672d4bcbedSCarl Huang config->num_offload_peers = TARGET_NUM_OFFLD_PEERS; 1682d4bcbedSCarl Huang config->num_offload_reorder_buffs = TARGET_NUM_OFFLD_REORDER_BUFFS; 1692d4bcbedSCarl Huang config->num_peer_keys = TARGET_NUM_PEER_KEYS; 1702d4bcbedSCarl Huang config->ast_skid_limit = TARGET_AST_SKID_LIMIT; 1712d4bcbedSCarl Huang config->tx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 1722d4bcbedSCarl Huang config->rx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 1732d4bcbedSCarl Huang config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI; 1742d4bcbedSCarl Huang config->rx_timeout_pri[1] = TARGET_RX_TIMEOUT_LO_PRI; 1752d4bcbedSCarl Huang config->rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI; 1762d4bcbedSCarl Huang config->rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI; 177c695faf7SKalle Valo 178c695faf7SKalle Valo if (test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags)) 179c695faf7SKalle Valo config->rx_decap_mode = TARGET_DECAP_MODE_RAW; 180c695faf7SKalle Valo else 1812d4bcbedSCarl Huang config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI; 182c695faf7SKalle Valo 1832d4bcbedSCarl Huang config->scan_max_pending_req = TARGET_SCAN_MAX_PENDING_REQS; 1842d4bcbedSCarl Huang config->bmiss_offload_max_vdev = TARGET_BMISS_OFFLOAD_MAX_VDEV; 1852d4bcbedSCarl Huang config->roam_offload_max_vdev = TARGET_ROAM_OFFLOAD_MAX_VDEV; 1862d4bcbedSCarl Huang config->roam_offload_max_ap_profiles = TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES; 1872d4bcbedSCarl Huang config->num_mcast_groups = TARGET_NUM_MCAST_GROUPS; 1882d4bcbedSCarl Huang config->num_mcast_table_elems = TARGET_NUM_MCAST_TABLE_ELEMS; 1892d4bcbedSCarl Huang config->mcast2ucast_mode = TARGET_MCAST2UCAST_MODE; 1902d4bcbedSCarl Huang config->tx_dbg_log_size = TARGET_TX_DBG_LOG_SIZE; 1912d4bcbedSCarl Huang config->num_wds_entries = TARGET_NUM_WDS_ENTRIES; 1922d4bcbedSCarl Huang config->dma_burst_size = TARGET_DMA_BURST_SIZE; 1932d4bcbedSCarl Huang config->rx_skip_defrag_timeout_dup_detection_check = 1942d4bcbedSCarl Huang TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK; 1952d4bcbedSCarl Huang config->vow_config = TARGET_VOW_CONFIG; 1962d4bcbedSCarl Huang config->gtk_offload_max_vdev = TARGET_GTK_OFFLOAD_MAX_VDEV; 1972d4bcbedSCarl Huang config->num_msdu_desc = TARGET_NUM_MSDU_DESC; 1982d4bcbedSCarl Huang config->beacon_tx_offload_max_vdev = ab->num_radios * TARGET_MAX_BCN_OFFLD; 1992d4bcbedSCarl Huang config->rx_batchmode = TARGET_RX_BATCHMODE; 2002d4bcbedSCarl Huang config->peer_map_unmap_v2_support = 1; 20136c7c640SKarthikeyan Periyasamy config->twt_ap_pdev_count = ab->num_radios; 2022d4bcbedSCarl Huang config->twt_ap_sta_count = 1000; 2039b4dd38bSSeevalamuthu Mariappan config->flag1 |= WMI_RSRC_CFG_FLAG1_BSS_CHANNEL_INFO_64; 204*01c6c9fcSAbinaya Kalaiselvan config->flag1 |= WMI_RSRC_CFG_FLAG1_ACK_RSSI; 2052d4bcbedSCarl Huang } 2062d4bcbedSCarl Huang 2074152e420SCarl Huang static int ath11k_hw_mac_id_to_pdev_id_ipq8074(struct ath11k_hw_params *hw, 2084152e420SCarl Huang int mac_id) 2094152e420SCarl Huang { 2104152e420SCarl Huang return mac_id; 2114152e420SCarl Huang } 2124152e420SCarl Huang 2134152e420SCarl Huang static int ath11k_hw_mac_id_to_srng_id_ipq8074(struct ath11k_hw_params *hw, 2144152e420SCarl Huang int mac_id) 2154152e420SCarl Huang { 2164152e420SCarl Huang return 0; 2174152e420SCarl Huang } 2184152e420SCarl Huang 2194152e420SCarl Huang static int ath11k_hw_mac_id_to_pdev_id_qca6390(struct ath11k_hw_params *hw, 2204152e420SCarl Huang int mac_id) 2214152e420SCarl Huang { 2224152e420SCarl Huang return 0; 2234152e420SCarl Huang } 2244152e420SCarl Huang 2254152e420SCarl Huang static int ath11k_hw_mac_id_to_srng_id_qca6390(struct ath11k_hw_params *hw, 2264152e420SCarl Huang int mac_id) 2274152e420SCarl Huang { 2284152e420SCarl Huang return mac_id; 2294152e420SCarl Huang } 2304152e420SCarl Huang 231e678fbd4SKarthikeyan Periyasamy static bool ath11k_hw_ipq8074_rx_desc_get_first_msdu(struct hal_rx_desc *desc) 232e678fbd4SKarthikeyan Periyasamy { 233e678fbd4SKarthikeyan Periyasamy return !!FIELD_GET(RX_MSDU_END_INFO2_FIRST_MSDU, 234e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.ipq8074.msdu_end.info2)); 235e678fbd4SKarthikeyan Periyasamy } 236e678fbd4SKarthikeyan Periyasamy 237e678fbd4SKarthikeyan Periyasamy static bool ath11k_hw_ipq8074_rx_desc_get_last_msdu(struct hal_rx_desc *desc) 238e678fbd4SKarthikeyan Periyasamy { 239e678fbd4SKarthikeyan Periyasamy return !!FIELD_GET(RX_MSDU_END_INFO2_LAST_MSDU, 240e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.ipq8074.msdu_end.info2)); 241e678fbd4SKarthikeyan Periyasamy } 242e678fbd4SKarthikeyan Periyasamy 243e678fbd4SKarthikeyan Periyasamy static u8 ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes(struct hal_rx_desc *desc) 244e678fbd4SKarthikeyan Periyasamy { 245e678fbd4SKarthikeyan Periyasamy return FIELD_GET(RX_MSDU_END_INFO2_L3_HDR_PADDING, 246e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.ipq8074.msdu_end.info2)); 247e678fbd4SKarthikeyan Periyasamy } 248e678fbd4SKarthikeyan Periyasamy 249e678fbd4SKarthikeyan Periyasamy static u8 *ath11k_hw_ipq8074_rx_desc_get_hdr_status(struct hal_rx_desc *desc) 250e678fbd4SKarthikeyan Periyasamy { 251e678fbd4SKarthikeyan Periyasamy return desc->u.ipq8074.hdr_status; 252e678fbd4SKarthikeyan Periyasamy } 253e678fbd4SKarthikeyan Periyasamy 254e678fbd4SKarthikeyan Periyasamy static bool ath11k_hw_ipq8074_rx_desc_encrypt_valid(struct hal_rx_desc *desc) 255e678fbd4SKarthikeyan Periyasamy { 256e678fbd4SKarthikeyan Periyasamy return __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1) & 257e678fbd4SKarthikeyan Periyasamy RX_MPDU_START_INFO1_ENCRYPT_INFO_VALID; 258e678fbd4SKarthikeyan Periyasamy } 259e678fbd4SKarthikeyan Periyasamy 260e678fbd4SKarthikeyan Periyasamy static u32 ath11k_hw_ipq8074_rx_desc_get_encrypt_type(struct hal_rx_desc *desc) 261e678fbd4SKarthikeyan Periyasamy { 262e678fbd4SKarthikeyan Periyasamy return FIELD_GET(RX_MPDU_START_INFO2_ENC_TYPE, 263e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.ipq8074.mpdu_start.info2)); 264e678fbd4SKarthikeyan Periyasamy } 265e678fbd4SKarthikeyan Periyasamy 266e678fbd4SKarthikeyan Periyasamy static u8 ath11k_hw_ipq8074_rx_desc_get_decap_type(struct hal_rx_desc *desc) 267e678fbd4SKarthikeyan Periyasamy { 268e678fbd4SKarthikeyan Periyasamy return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT, 269e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.ipq8074.msdu_start.info2)); 270e678fbd4SKarthikeyan Periyasamy } 271e678fbd4SKarthikeyan Periyasamy 272e678fbd4SKarthikeyan Periyasamy static u8 ath11k_hw_ipq8074_rx_desc_get_mesh_ctl(struct hal_rx_desc *desc) 273e678fbd4SKarthikeyan Periyasamy { 274e678fbd4SKarthikeyan Periyasamy return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT, 275e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.ipq8074.msdu_start.info2)); 276e678fbd4SKarthikeyan Periyasamy } 277e678fbd4SKarthikeyan Periyasamy 278b3febdccSP Praneesh static bool ath11k_hw_ipq8074_rx_desc_get_ldpc_support(struct hal_rx_desc *desc) 279b3febdccSP Praneesh { 280b3febdccSP Praneesh return FIELD_GET(RX_MSDU_START_INFO2_LDPC, 281b3febdccSP Praneesh __le32_to_cpu(desc->u.ipq8074.msdu_start.info2)); 282b3febdccSP Praneesh } 283b3febdccSP Praneesh 284e678fbd4SKarthikeyan Periyasamy static bool ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc *desc) 285e678fbd4SKarthikeyan Periyasamy { 286e678fbd4SKarthikeyan Periyasamy return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_CTRL_VALID, 287e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1)); 288e678fbd4SKarthikeyan Periyasamy } 289e678fbd4SKarthikeyan Periyasamy 290e678fbd4SKarthikeyan Periyasamy static bool ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc *desc) 291e678fbd4SKarthikeyan Periyasamy { 292e678fbd4SKarthikeyan Periyasamy return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_FCTRL_VALID, 293e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1)); 294e678fbd4SKarthikeyan Periyasamy } 295e678fbd4SKarthikeyan Periyasamy 296e678fbd4SKarthikeyan Periyasamy static u16 ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc *desc) 297e678fbd4SKarthikeyan Periyasamy { 298e678fbd4SKarthikeyan Periyasamy return FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_NUM, 299e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1)); 300e678fbd4SKarthikeyan Periyasamy } 301e678fbd4SKarthikeyan Periyasamy 302e678fbd4SKarthikeyan Periyasamy static u16 ath11k_hw_ipq8074_rx_desc_get_msdu_len(struct hal_rx_desc *desc) 303e678fbd4SKarthikeyan Periyasamy { 304e678fbd4SKarthikeyan Periyasamy return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH, 305e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.ipq8074.msdu_start.info1)); 306e678fbd4SKarthikeyan Periyasamy } 307e678fbd4SKarthikeyan Periyasamy 308e678fbd4SKarthikeyan Periyasamy static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_sgi(struct hal_rx_desc *desc) 309e678fbd4SKarthikeyan Periyasamy { 310e678fbd4SKarthikeyan Periyasamy return FIELD_GET(RX_MSDU_START_INFO3_SGI, 311e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 312e678fbd4SKarthikeyan Periyasamy } 313e678fbd4SKarthikeyan Periyasamy 314e678fbd4SKarthikeyan Periyasamy static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc *desc) 315e678fbd4SKarthikeyan Periyasamy { 316e678fbd4SKarthikeyan Periyasamy return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS, 317e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 318e678fbd4SKarthikeyan Periyasamy } 319e678fbd4SKarthikeyan Periyasamy 320e678fbd4SKarthikeyan Periyasamy static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw(struct hal_rx_desc *desc) 321e678fbd4SKarthikeyan Periyasamy { 322e678fbd4SKarthikeyan Periyasamy return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW, 323e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 324e678fbd4SKarthikeyan Periyasamy } 325e678fbd4SKarthikeyan Periyasamy 326e678fbd4SKarthikeyan Periyasamy static u32 ath11k_hw_ipq8074_rx_desc_get_msdu_freq(struct hal_rx_desc *desc) 327e678fbd4SKarthikeyan Periyasamy { 328e678fbd4SKarthikeyan Periyasamy return __le32_to_cpu(desc->u.ipq8074.msdu_start.phy_meta_data); 329e678fbd4SKarthikeyan Periyasamy } 330e678fbd4SKarthikeyan Periyasamy 331e678fbd4SKarthikeyan Periyasamy static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type(struct hal_rx_desc *desc) 332e678fbd4SKarthikeyan Periyasamy { 333e678fbd4SKarthikeyan Periyasamy return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE, 334e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 335e678fbd4SKarthikeyan Periyasamy } 336e678fbd4SKarthikeyan Periyasamy 337e678fbd4SKarthikeyan Periyasamy static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_nss(struct hal_rx_desc *desc) 338e678fbd4SKarthikeyan Periyasamy { 339e678fbd4SKarthikeyan Periyasamy return FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP, 340e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 341e678fbd4SKarthikeyan Periyasamy } 342e678fbd4SKarthikeyan Periyasamy 343e678fbd4SKarthikeyan Periyasamy static u8 ath11k_hw_ipq8074_rx_desc_get_mpdu_tid(struct hal_rx_desc *desc) 344e678fbd4SKarthikeyan Periyasamy { 345e678fbd4SKarthikeyan Periyasamy return FIELD_GET(RX_MPDU_START_INFO2_TID, 346e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.ipq8074.mpdu_start.info2)); 347e678fbd4SKarthikeyan Periyasamy } 348e678fbd4SKarthikeyan Periyasamy 349e678fbd4SKarthikeyan Periyasamy static u16 ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc) 350e678fbd4SKarthikeyan Periyasamy { 351e678fbd4SKarthikeyan Periyasamy return __le16_to_cpu(desc->u.ipq8074.mpdu_start.sw_peer_id); 352e678fbd4SKarthikeyan Periyasamy } 353e678fbd4SKarthikeyan Periyasamy 354e678fbd4SKarthikeyan Periyasamy static void ath11k_hw_ipq8074_rx_desc_copy_attn_end(struct hal_rx_desc *fdesc, 355e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *ldesc) 356e678fbd4SKarthikeyan Periyasamy { 357e678fbd4SKarthikeyan Periyasamy memcpy((u8 *)&fdesc->u.ipq8074.msdu_end, (u8 *)&ldesc->u.ipq8074.msdu_end, 358e678fbd4SKarthikeyan Periyasamy sizeof(struct rx_msdu_end_ipq8074)); 359e678fbd4SKarthikeyan Periyasamy memcpy((u8 *)&fdesc->u.ipq8074.attention, (u8 *)&ldesc->u.ipq8074.attention, 360e678fbd4SKarthikeyan Periyasamy sizeof(struct rx_attention)); 361e678fbd4SKarthikeyan Periyasamy memcpy((u8 *)&fdesc->u.ipq8074.mpdu_end, (u8 *)&ldesc->u.ipq8074.mpdu_end, 362e678fbd4SKarthikeyan Periyasamy sizeof(struct rx_mpdu_end)); 363e678fbd4SKarthikeyan Periyasamy } 364e678fbd4SKarthikeyan Periyasamy 365e678fbd4SKarthikeyan Periyasamy static u32 ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag(struct hal_rx_desc *desc) 366e678fbd4SKarthikeyan Periyasamy { 367e678fbd4SKarthikeyan Periyasamy return FIELD_GET(HAL_TLV_HDR_TAG, 368e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.ipq8074.mpdu_start_tag)); 369e678fbd4SKarthikeyan Periyasamy } 370e678fbd4SKarthikeyan Periyasamy 371e678fbd4SKarthikeyan Periyasamy static u32 ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc *desc) 372e678fbd4SKarthikeyan Periyasamy { 373e678fbd4SKarthikeyan Periyasamy return __le16_to_cpu(desc->u.ipq8074.mpdu_start.phy_ppdu_id); 374e678fbd4SKarthikeyan Periyasamy } 375e678fbd4SKarthikeyan Periyasamy 376e678fbd4SKarthikeyan Periyasamy static void ath11k_hw_ipq8074_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len) 377e678fbd4SKarthikeyan Periyasamy { 378e678fbd4SKarthikeyan Periyasamy u32 info = __le32_to_cpu(desc->u.ipq8074.msdu_start.info1); 379e678fbd4SKarthikeyan Periyasamy 380e678fbd4SKarthikeyan Periyasamy info &= ~RX_MSDU_START_INFO1_MSDU_LENGTH; 381e678fbd4SKarthikeyan Periyasamy info |= FIELD_PREP(RX_MSDU_START_INFO1_MSDU_LENGTH, len); 382e678fbd4SKarthikeyan Periyasamy 383e678fbd4SKarthikeyan Periyasamy desc->u.ipq8074.msdu_start.info1 = __cpu_to_le32(info); 384e678fbd4SKarthikeyan Periyasamy } 385e678fbd4SKarthikeyan Periyasamy 3862167fa60SSriram R static bool ath11k_hw_ipq8074_rx_desc_mac_addr2_valid(struct hal_rx_desc *desc) 3872167fa60SSriram R { 3882167fa60SSriram R return __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1) & 3892167fa60SSriram R RX_MPDU_START_INFO1_MAC_ADDR2_VALID; 3902167fa60SSriram R } 3912167fa60SSriram R 3922167fa60SSriram R static u8 *ath11k_hw_ipq8074_rx_desc_mpdu_start_addr2(struct hal_rx_desc *desc) 3932167fa60SSriram R { 3942167fa60SSriram R return desc->u.ipq8074.mpdu_start.addr2; 3952167fa60SSriram R } 3962167fa60SSriram R 397e678fbd4SKarthikeyan Periyasamy static 398e678fbd4SKarthikeyan Periyasamy struct rx_attention *ath11k_hw_ipq8074_rx_desc_get_attention(struct hal_rx_desc *desc) 399e678fbd4SKarthikeyan Periyasamy { 400e678fbd4SKarthikeyan Periyasamy return &desc->u.ipq8074.attention; 401e678fbd4SKarthikeyan Periyasamy } 402e678fbd4SKarthikeyan Periyasamy 403e678fbd4SKarthikeyan Periyasamy static u8 *ath11k_hw_ipq8074_rx_desc_get_msdu_payload(struct hal_rx_desc *desc) 404e678fbd4SKarthikeyan Periyasamy { 405e678fbd4SKarthikeyan Periyasamy return &desc->u.ipq8074.msdu_payload[0]; 406e678fbd4SKarthikeyan Periyasamy } 407e678fbd4SKarthikeyan Periyasamy 408e678fbd4SKarthikeyan Periyasamy static bool ath11k_hw_qcn9074_rx_desc_get_first_msdu(struct hal_rx_desc *desc) 409e678fbd4SKarthikeyan Periyasamy { 410e678fbd4SKarthikeyan Periyasamy return !!FIELD_GET(RX_MSDU_END_INFO4_FIRST_MSDU, 411e678fbd4SKarthikeyan Periyasamy __le16_to_cpu(desc->u.qcn9074.msdu_end.info4)); 412e678fbd4SKarthikeyan Periyasamy } 413e678fbd4SKarthikeyan Periyasamy 414e678fbd4SKarthikeyan Periyasamy static bool ath11k_hw_qcn9074_rx_desc_get_last_msdu(struct hal_rx_desc *desc) 415e678fbd4SKarthikeyan Periyasamy { 416e678fbd4SKarthikeyan Periyasamy return !!FIELD_GET(RX_MSDU_END_INFO4_LAST_MSDU, 417e678fbd4SKarthikeyan Periyasamy __le16_to_cpu(desc->u.qcn9074.msdu_end.info4)); 418e678fbd4SKarthikeyan Periyasamy } 419e678fbd4SKarthikeyan Periyasamy 420e678fbd4SKarthikeyan Periyasamy static u8 ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes(struct hal_rx_desc *desc) 421e678fbd4SKarthikeyan Periyasamy { 422e678fbd4SKarthikeyan Periyasamy return FIELD_GET(RX_MSDU_END_INFO4_L3_HDR_PADDING, 423e678fbd4SKarthikeyan Periyasamy __le16_to_cpu(desc->u.qcn9074.msdu_end.info4)); 424e678fbd4SKarthikeyan Periyasamy } 425e678fbd4SKarthikeyan Periyasamy 426e678fbd4SKarthikeyan Periyasamy static u8 *ath11k_hw_qcn9074_rx_desc_get_hdr_status(struct hal_rx_desc *desc) 427e678fbd4SKarthikeyan Periyasamy { 428e678fbd4SKarthikeyan Periyasamy return desc->u.qcn9074.hdr_status; 429e678fbd4SKarthikeyan Periyasamy } 430e678fbd4SKarthikeyan Periyasamy 431e678fbd4SKarthikeyan Periyasamy static bool ath11k_hw_qcn9074_rx_desc_encrypt_valid(struct hal_rx_desc *desc) 432e678fbd4SKarthikeyan Periyasamy { 433e678fbd4SKarthikeyan Periyasamy return __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11) & 434e678fbd4SKarthikeyan Periyasamy RX_MPDU_START_INFO11_ENCRYPT_INFO_VALID; 435e678fbd4SKarthikeyan Periyasamy } 436e678fbd4SKarthikeyan Periyasamy 437e678fbd4SKarthikeyan Periyasamy static u32 ath11k_hw_qcn9074_rx_desc_get_encrypt_type(struct hal_rx_desc *desc) 438e678fbd4SKarthikeyan Periyasamy { 439e678fbd4SKarthikeyan Periyasamy return FIELD_GET(RX_MPDU_START_INFO9_ENC_TYPE, 440e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.qcn9074.mpdu_start.info9)); 441e678fbd4SKarthikeyan Periyasamy } 442e678fbd4SKarthikeyan Periyasamy 443e678fbd4SKarthikeyan Periyasamy static u8 ath11k_hw_qcn9074_rx_desc_get_decap_type(struct hal_rx_desc *desc) 444e678fbd4SKarthikeyan Periyasamy { 445e678fbd4SKarthikeyan Periyasamy return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT, 446e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.qcn9074.msdu_start.info2)); 447e678fbd4SKarthikeyan Periyasamy } 448e678fbd4SKarthikeyan Periyasamy 449e678fbd4SKarthikeyan Periyasamy static u8 ath11k_hw_qcn9074_rx_desc_get_mesh_ctl(struct hal_rx_desc *desc) 450e678fbd4SKarthikeyan Periyasamy { 451e678fbd4SKarthikeyan Periyasamy return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT, 452e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.qcn9074.msdu_start.info2)); 453e678fbd4SKarthikeyan Periyasamy } 454e678fbd4SKarthikeyan Periyasamy 455b3febdccSP Praneesh static bool ath11k_hw_qcn9074_rx_desc_get_ldpc_support(struct hal_rx_desc *desc) 456b3febdccSP Praneesh { 457b3febdccSP Praneesh return FIELD_GET(RX_MSDU_START_INFO2_LDPC, 458b3febdccSP Praneesh __le32_to_cpu(desc->u.qcn9074.msdu_start.info2)); 459b3febdccSP Praneesh } 460b3febdccSP Praneesh 461e678fbd4SKarthikeyan Periyasamy static bool ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc *desc) 462e678fbd4SKarthikeyan Periyasamy { 463e678fbd4SKarthikeyan Periyasamy return !!FIELD_GET(RX_MPDU_START_INFO11_MPDU_SEQ_CTRL_VALID, 464e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11)); 465e678fbd4SKarthikeyan Periyasamy } 466e678fbd4SKarthikeyan Periyasamy 467e678fbd4SKarthikeyan Periyasamy static bool ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc *desc) 468e678fbd4SKarthikeyan Periyasamy { 469e678fbd4SKarthikeyan Periyasamy return !!FIELD_GET(RX_MPDU_START_INFO11_MPDU_FCTRL_VALID, 470e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11)); 471e678fbd4SKarthikeyan Periyasamy } 472e678fbd4SKarthikeyan Periyasamy 473e678fbd4SKarthikeyan Periyasamy static u16 ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc *desc) 474e678fbd4SKarthikeyan Periyasamy { 475e678fbd4SKarthikeyan Periyasamy return FIELD_GET(RX_MPDU_START_INFO11_MPDU_SEQ_NUM, 476e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11)); 477e678fbd4SKarthikeyan Periyasamy } 478e678fbd4SKarthikeyan Periyasamy 479e678fbd4SKarthikeyan Periyasamy static u16 ath11k_hw_qcn9074_rx_desc_get_msdu_len(struct hal_rx_desc *desc) 480e678fbd4SKarthikeyan Periyasamy { 481e678fbd4SKarthikeyan Periyasamy return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH, 482e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.qcn9074.msdu_start.info1)); 483e678fbd4SKarthikeyan Periyasamy } 484e678fbd4SKarthikeyan Periyasamy 485e678fbd4SKarthikeyan Periyasamy static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_sgi(struct hal_rx_desc *desc) 486e678fbd4SKarthikeyan Periyasamy { 487e678fbd4SKarthikeyan Periyasamy return FIELD_GET(RX_MSDU_START_INFO3_SGI, 488e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 489e678fbd4SKarthikeyan Periyasamy } 490e678fbd4SKarthikeyan Periyasamy 491e678fbd4SKarthikeyan Periyasamy static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc *desc) 492e678fbd4SKarthikeyan Periyasamy { 493e678fbd4SKarthikeyan Periyasamy return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS, 494e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 495e678fbd4SKarthikeyan Periyasamy } 496e678fbd4SKarthikeyan Periyasamy 497e678fbd4SKarthikeyan Periyasamy static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw(struct hal_rx_desc *desc) 498e678fbd4SKarthikeyan Periyasamy { 499e678fbd4SKarthikeyan Periyasamy return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW, 500e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 501e678fbd4SKarthikeyan Periyasamy } 502e678fbd4SKarthikeyan Periyasamy 503e678fbd4SKarthikeyan Periyasamy static u32 ath11k_hw_qcn9074_rx_desc_get_msdu_freq(struct hal_rx_desc *desc) 504e678fbd4SKarthikeyan Periyasamy { 505e678fbd4SKarthikeyan Periyasamy return __le32_to_cpu(desc->u.qcn9074.msdu_start.phy_meta_data); 506e678fbd4SKarthikeyan Periyasamy } 507e678fbd4SKarthikeyan Periyasamy 508e678fbd4SKarthikeyan Periyasamy static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type(struct hal_rx_desc *desc) 509e678fbd4SKarthikeyan Periyasamy { 510e678fbd4SKarthikeyan Periyasamy return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE, 511e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 512e678fbd4SKarthikeyan Periyasamy } 513e678fbd4SKarthikeyan Periyasamy 514e678fbd4SKarthikeyan Periyasamy static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_nss(struct hal_rx_desc *desc) 515e678fbd4SKarthikeyan Periyasamy { 516e678fbd4SKarthikeyan Periyasamy return FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP, 517e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 518e678fbd4SKarthikeyan Periyasamy } 519e678fbd4SKarthikeyan Periyasamy 520e678fbd4SKarthikeyan Periyasamy static u8 ath11k_hw_qcn9074_rx_desc_get_mpdu_tid(struct hal_rx_desc *desc) 521e678fbd4SKarthikeyan Periyasamy { 522e678fbd4SKarthikeyan Periyasamy return FIELD_GET(RX_MPDU_START_INFO9_TID, 523e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.qcn9074.mpdu_start.info9)); 524e678fbd4SKarthikeyan Periyasamy } 525e678fbd4SKarthikeyan Periyasamy 526e678fbd4SKarthikeyan Periyasamy static u16 ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc) 527e678fbd4SKarthikeyan Periyasamy { 528e678fbd4SKarthikeyan Periyasamy return __le16_to_cpu(desc->u.qcn9074.mpdu_start.sw_peer_id); 529e678fbd4SKarthikeyan Periyasamy } 530e678fbd4SKarthikeyan Periyasamy 531e678fbd4SKarthikeyan Periyasamy static void ath11k_hw_qcn9074_rx_desc_copy_attn_end(struct hal_rx_desc *fdesc, 532e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *ldesc) 533e678fbd4SKarthikeyan Periyasamy { 534e678fbd4SKarthikeyan Periyasamy memcpy((u8 *)&fdesc->u.qcn9074.msdu_end, (u8 *)&ldesc->u.qcn9074.msdu_end, 535e678fbd4SKarthikeyan Periyasamy sizeof(struct rx_msdu_end_qcn9074)); 536e678fbd4SKarthikeyan Periyasamy memcpy((u8 *)&fdesc->u.qcn9074.attention, (u8 *)&ldesc->u.qcn9074.attention, 537e678fbd4SKarthikeyan Periyasamy sizeof(struct rx_attention)); 538e678fbd4SKarthikeyan Periyasamy memcpy((u8 *)&fdesc->u.qcn9074.mpdu_end, (u8 *)&ldesc->u.qcn9074.mpdu_end, 539e678fbd4SKarthikeyan Periyasamy sizeof(struct rx_mpdu_end)); 540e678fbd4SKarthikeyan Periyasamy } 541e678fbd4SKarthikeyan Periyasamy 542e678fbd4SKarthikeyan Periyasamy static u32 ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag(struct hal_rx_desc *desc) 543e678fbd4SKarthikeyan Periyasamy { 544e678fbd4SKarthikeyan Periyasamy return FIELD_GET(HAL_TLV_HDR_TAG, 545e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.qcn9074.mpdu_start_tag)); 546e678fbd4SKarthikeyan Periyasamy } 547e678fbd4SKarthikeyan Periyasamy 548e678fbd4SKarthikeyan Periyasamy static u32 ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc *desc) 549e678fbd4SKarthikeyan Periyasamy { 550e678fbd4SKarthikeyan Periyasamy return __le16_to_cpu(desc->u.qcn9074.mpdu_start.phy_ppdu_id); 551e678fbd4SKarthikeyan Periyasamy } 552e678fbd4SKarthikeyan Periyasamy 553e678fbd4SKarthikeyan Periyasamy static void ath11k_hw_qcn9074_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len) 554e678fbd4SKarthikeyan Periyasamy { 555e678fbd4SKarthikeyan Periyasamy u32 info = __le32_to_cpu(desc->u.qcn9074.msdu_start.info1); 556e678fbd4SKarthikeyan Periyasamy 557e678fbd4SKarthikeyan Periyasamy info &= ~RX_MSDU_START_INFO1_MSDU_LENGTH; 558e678fbd4SKarthikeyan Periyasamy info |= FIELD_PREP(RX_MSDU_START_INFO1_MSDU_LENGTH, len); 559e678fbd4SKarthikeyan Periyasamy 560e678fbd4SKarthikeyan Periyasamy desc->u.qcn9074.msdu_start.info1 = __cpu_to_le32(info); 561e678fbd4SKarthikeyan Periyasamy } 562e678fbd4SKarthikeyan Periyasamy 563e678fbd4SKarthikeyan Periyasamy static 564e678fbd4SKarthikeyan Periyasamy struct rx_attention *ath11k_hw_qcn9074_rx_desc_get_attention(struct hal_rx_desc *desc) 565e678fbd4SKarthikeyan Periyasamy { 566e678fbd4SKarthikeyan Periyasamy return &desc->u.qcn9074.attention; 567e678fbd4SKarthikeyan Periyasamy } 568e678fbd4SKarthikeyan Periyasamy 569e678fbd4SKarthikeyan Periyasamy static u8 *ath11k_hw_qcn9074_rx_desc_get_msdu_payload(struct hal_rx_desc *desc) 570e678fbd4SKarthikeyan Periyasamy { 571e678fbd4SKarthikeyan Periyasamy return &desc->u.qcn9074.msdu_payload[0]; 572e678fbd4SKarthikeyan Periyasamy } 573e678fbd4SKarthikeyan Periyasamy 5742167fa60SSriram R static bool ath11k_hw_ipq9074_rx_desc_mac_addr2_valid(struct hal_rx_desc *desc) 5752167fa60SSriram R { 5762167fa60SSriram R return __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11) & 5772167fa60SSriram R RX_MPDU_START_INFO11_MAC_ADDR2_VALID; 5782167fa60SSriram R } 5792167fa60SSriram R 5802167fa60SSriram R static u8 *ath11k_hw_ipq9074_rx_desc_mpdu_start_addr2(struct hal_rx_desc *desc) 5812167fa60SSriram R { 5822167fa60SSriram R return desc->u.qcn9074.mpdu_start.addr2; 5832167fa60SSriram R } 5842167fa60SSriram R 585e4073430SBaochen Qiang static bool ath11k_hw_wcn6855_rx_desc_get_first_msdu(struct hal_rx_desc *desc) 586e4073430SBaochen Qiang { 587e4073430SBaochen Qiang return !!FIELD_GET(RX_MSDU_END_INFO2_FIRST_MSDU_WCN6855, 588e4073430SBaochen Qiang __le32_to_cpu(desc->u.wcn6855.msdu_end.info2)); 589e4073430SBaochen Qiang } 590e4073430SBaochen Qiang 591e4073430SBaochen Qiang static bool ath11k_hw_wcn6855_rx_desc_get_last_msdu(struct hal_rx_desc *desc) 592e4073430SBaochen Qiang { 593e4073430SBaochen Qiang return !!FIELD_GET(RX_MSDU_END_INFO2_LAST_MSDU_WCN6855, 594e4073430SBaochen Qiang __le32_to_cpu(desc->u.wcn6855.msdu_end.info2)); 595e4073430SBaochen Qiang } 596e4073430SBaochen Qiang 597e4073430SBaochen Qiang static u8 ath11k_hw_wcn6855_rx_desc_get_l3_pad_bytes(struct hal_rx_desc *desc) 598e4073430SBaochen Qiang { 599e4073430SBaochen Qiang return FIELD_GET(RX_MSDU_END_INFO2_L3_HDR_PADDING, 600e4073430SBaochen Qiang __le32_to_cpu(desc->u.wcn6855.msdu_end.info2)); 601e4073430SBaochen Qiang } 602e4073430SBaochen Qiang 603e4073430SBaochen Qiang static u8 *ath11k_hw_wcn6855_rx_desc_get_hdr_status(struct hal_rx_desc *desc) 604e4073430SBaochen Qiang { 605e4073430SBaochen Qiang return desc->u.wcn6855.hdr_status; 606e4073430SBaochen Qiang } 607e4073430SBaochen Qiang 608e4073430SBaochen Qiang static bool ath11k_hw_wcn6855_rx_desc_encrypt_valid(struct hal_rx_desc *desc) 609e4073430SBaochen Qiang { 610e4073430SBaochen Qiang return __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1) & 611e4073430SBaochen Qiang RX_MPDU_START_INFO1_ENCRYPT_INFO_VALID; 612e4073430SBaochen Qiang } 613e4073430SBaochen Qiang 614e4073430SBaochen Qiang static u32 ath11k_hw_wcn6855_rx_desc_get_encrypt_type(struct hal_rx_desc *desc) 615e4073430SBaochen Qiang { 616e4073430SBaochen Qiang return FIELD_GET(RX_MPDU_START_INFO2_ENC_TYPE, 617e4073430SBaochen Qiang __le32_to_cpu(desc->u.wcn6855.mpdu_start.info2)); 618e4073430SBaochen Qiang } 619e4073430SBaochen Qiang 620e4073430SBaochen Qiang static u8 ath11k_hw_wcn6855_rx_desc_get_decap_type(struct hal_rx_desc *desc) 621e4073430SBaochen Qiang { 622e4073430SBaochen Qiang return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT, 623e4073430SBaochen Qiang __le32_to_cpu(desc->u.wcn6855.msdu_start.info2)); 624e4073430SBaochen Qiang } 625e4073430SBaochen Qiang 626e4073430SBaochen Qiang static u8 ath11k_hw_wcn6855_rx_desc_get_mesh_ctl(struct hal_rx_desc *desc) 627e4073430SBaochen Qiang { 628e4073430SBaochen Qiang return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT, 629e4073430SBaochen Qiang __le32_to_cpu(desc->u.wcn6855.msdu_start.info2)); 630e4073430SBaochen Qiang } 631e4073430SBaochen Qiang 632e4073430SBaochen Qiang static bool ath11k_hw_wcn6855_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc *desc) 633e4073430SBaochen Qiang { 634e4073430SBaochen Qiang return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_CTRL_VALID, 635e4073430SBaochen Qiang __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1)); 636e4073430SBaochen Qiang } 637e4073430SBaochen Qiang 638e4073430SBaochen Qiang static bool ath11k_hw_wcn6855_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc *desc) 639e4073430SBaochen Qiang { 640e4073430SBaochen Qiang return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_FCTRL_VALID, 641e4073430SBaochen Qiang __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1)); 642e4073430SBaochen Qiang } 643e4073430SBaochen Qiang 644e4073430SBaochen Qiang static u16 ath11k_hw_wcn6855_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc *desc) 645e4073430SBaochen Qiang { 646e4073430SBaochen Qiang return FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_NUM, 647e4073430SBaochen Qiang __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1)); 648e4073430SBaochen Qiang } 649e4073430SBaochen Qiang 650e4073430SBaochen Qiang static u16 ath11k_hw_wcn6855_rx_desc_get_msdu_len(struct hal_rx_desc *desc) 651e4073430SBaochen Qiang { 652e4073430SBaochen Qiang return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH, 653e4073430SBaochen Qiang __le32_to_cpu(desc->u.wcn6855.msdu_start.info1)); 654e4073430SBaochen Qiang } 655e4073430SBaochen Qiang 656e4073430SBaochen Qiang static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_sgi(struct hal_rx_desc *desc) 657e4073430SBaochen Qiang { 658e4073430SBaochen Qiang return FIELD_GET(RX_MSDU_START_INFO3_SGI, 659e4073430SBaochen Qiang __le32_to_cpu(desc->u.wcn6855.msdu_start.info3)); 660e4073430SBaochen Qiang } 661e4073430SBaochen Qiang 662e4073430SBaochen Qiang static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc *desc) 663e4073430SBaochen Qiang { 664e4073430SBaochen Qiang return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS, 665e4073430SBaochen Qiang __le32_to_cpu(desc->u.wcn6855.msdu_start.info3)); 666e4073430SBaochen Qiang } 667e4073430SBaochen Qiang 668e4073430SBaochen Qiang static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_rx_bw(struct hal_rx_desc *desc) 669e4073430SBaochen Qiang { 670e4073430SBaochen Qiang return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW, 671e4073430SBaochen Qiang __le32_to_cpu(desc->u.wcn6855.msdu_start.info3)); 672e4073430SBaochen Qiang } 673e4073430SBaochen Qiang 674e4073430SBaochen Qiang static u32 ath11k_hw_wcn6855_rx_desc_get_msdu_freq(struct hal_rx_desc *desc) 675e4073430SBaochen Qiang { 676e4073430SBaochen Qiang return __le32_to_cpu(desc->u.wcn6855.msdu_start.phy_meta_data); 677e4073430SBaochen Qiang } 678e4073430SBaochen Qiang 679e4073430SBaochen Qiang static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_pkt_type(struct hal_rx_desc *desc) 680e4073430SBaochen Qiang { 681e4073430SBaochen Qiang return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE, 682e4073430SBaochen Qiang __le32_to_cpu(desc->u.wcn6855.msdu_start.info3)); 683e4073430SBaochen Qiang } 684e4073430SBaochen Qiang 685e4073430SBaochen Qiang static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_nss(struct hal_rx_desc *desc) 686e4073430SBaochen Qiang { 687e4073430SBaochen Qiang return FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP, 688e4073430SBaochen Qiang __le32_to_cpu(desc->u.wcn6855.msdu_start.info3)); 689e4073430SBaochen Qiang } 690e4073430SBaochen Qiang 691e4073430SBaochen Qiang static u8 ath11k_hw_wcn6855_rx_desc_get_mpdu_tid(struct hal_rx_desc *desc) 692e4073430SBaochen Qiang { 693e4073430SBaochen Qiang return FIELD_GET(RX_MPDU_START_INFO2_TID_WCN6855, 694e4073430SBaochen Qiang __le32_to_cpu(desc->u.wcn6855.mpdu_start.info2)); 695e4073430SBaochen Qiang } 696e4073430SBaochen Qiang 697e4073430SBaochen Qiang static u16 ath11k_hw_wcn6855_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc) 698e4073430SBaochen Qiang { 699e4073430SBaochen Qiang return __le16_to_cpu(desc->u.wcn6855.mpdu_start.sw_peer_id); 700e4073430SBaochen Qiang } 701e4073430SBaochen Qiang 702e4073430SBaochen Qiang static void ath11k_hw_wcn6855_rx_desc_copy_attn_end(struct hal_rx_desc *fdesc, 703e4073430SBaochen Qiang struct hal_rx_desc *ldesc) 704e4073430SBaochen Qiang { 705e4073430SBaochen Qiang memcpy((u8 *)&fdesc->u.wcn6855.msdu_end, (u8 *)&ldesc->u.wcn6855.msdu_end, 706e4073430SBaochen Qiang sizeof(struct rx_msdu_end_wcn6855)); 707e4073430SBaochen Qiang memcpy((u8 *)&fdesc->u.wcn6855.attention, (u8 *)&ldesc->u.wcn6855.attention, 708e4073430SBaochen Qiang sizeof(struct rx_attention)); 709e4073430SBaochen Qiang memcpy((u8 *)&fdesc->u.wcn6855.mpdu_end, (u8 *)&ldesc->u.wcn6855.mpdu_end, 710e4073430SBaochen Qiang sizeof(struct rx_mpdu_end)); 711e4073430SBaochen Qiang } 712e4073430SBaochen Qiang 713e4073430SBaochen Qiang static u32 ath11k_hw_wcn6855_rx_desc_get_mpdu_start_tag(struct hal_rx_desc *desc) 714e4073430SBaochen Qiang { 715e4073430SBaochen Qiang return FIELD_GET(HAL_TLV_HDR_TAG, 716e4073430SBaochen Qiang __le32_to_cpu(desc->u.wcn6855.mpdu_start_tag)); 717e4073430SBaochen Qiang } 718e4073430SBaochen Qiang 719e4073430SBaochen Qiang static u32 ath11k_hw_wcn6855_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc *desc) 720e4073430SBaochen Qiang { 721e4073430SBaochen Qiang return __le16_to_cpu(desc->u.wcn6855.mpdu_start.phy_ppdu_id); 722e4073430SBaochen Qiang } 723e4073430SBaochen Qiang 724e4073430SBaochen Qiang static void ath11k_hw_wcn6855_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len) 725e4073430SBaochen Qiang { 726e4073430SBaochen Qiang u32 info = __le32_to_cpu(desc->u.wcn6855.msdu_start.info1); 727e4073430SBaochen Qiang 728e4073430SBaochen Qiang info &= ~RX_MSDU_START_INFO1_MSDU_LENGTH; 729e4073430SBaochen Qiang info |= FIELD_PREP(RX_MSDU_START_INFO1_MSDU_LENGTH, len); 730e4073430SBaochen Qiang 731e4073430SBaochen Qiang desc->u.wcn6855.msdu_start.info1 = __cpu_to_le32(info); 732e4073430SBaochen Qiang } 733e4073430SBaochen Qiang 734e4073430SBaochen Qiang static 735e4073430SBaochen Qiang struct rx_attention *ath11k_hw_wcn6855_rx_desc_get_attention(struct hal_rx_desc *desc) 736e4073430SBaochen Qiang { 737e4073430SBaochen Qiang return &desc->u.wcn6855.attention; 738e4073430SBaochen Qiang } 739e4073430SBaochen Qiang 740e4073430SBaochen Qiang static u8 *ath11k_hw_wcn6855_rx_desc_get_msdu_payload(struct hal_rx_desc *desc) 741e4073430SBaochen Qiang { 742e4073430SBaochen Qiang return &desc->u.wcn6855.msdu_payload[0]; 743e4073430SBaochen Qiang } 744e4073430SBaochen Qiang 7452167fa60SSriram R static bool ath11k_hw_wcn6855_rx_desc_mac_addr2_valid(struct hal_rx_desc *desc) 7462167fa60SSriram R { 7472167fa60SSriram R return __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1) & 7482167fa60SSriram R RX_MPDU_START_INFO1_MAC_ADDR2_VALID; 7492167fa60SSriram R } 7502167fa60SSriram R 7512167fa60SSriram R static u8 *ath11k_hw_wcn6855_rx_desc_mpdu_start_addr2(struct hal_rx_desc *desc) 7522167fa60SSriram R { 7532167fa60SSriram R return desc->u.wcn6855.mpdu_start.addr2; 7542167fa60SSriram R } 7552167fa60SSriram R 7560d55b76fSBaochen Qiang static void ath11k_hw_wcn6855_reo_setup(struct ath11k_base *ab) 7570d55b76fSBaochen Qiang { 7580d55b76fSBaochen Qiang u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG; 7590d55b76fSBaochen Qiang u32 val; 7600d55b76fSBaochen Qiang /* Each hash entry uses four bits to map to a particular ring. */ 7610d55b76fSBaochen Qiang u32 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 | 7620d55b76fSBaochen Qiang HAL_HASH_ROUTING_RING_SW2 << 4 | 7630d55b76fSBaochen Qiang HAL_HASH_ROUTING_RING_SW3 << 8 | 7640d55b76fSBaochen Qiang HAL_HASH_ROUTING_RING_SW4 << 12 | 7650d55b76fSBaochen Qiang HAL_HASH_ROUTING_RING_SW1 << 16 | 7660d55b76fSBaochen Qiang HAL_HASH_ROUTING_RING_SW2 << 20 | 7670d55b76fSBaochen Qiang HAL_HASH_ROUTING_RING_SW3 << 24 | 7680d55b76fSBaochen Qiang HAL_HASH_ROUTING_RING_SW4 << 28; 7690d55b76fSBaochen Qiang 7700d55b76fSBaochen Qiang val = ath11k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE); 7710d55b76fSBaochen Qiang val |= FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE, 1) | 7720d55b76fSBaochen Qiang FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE, 1); 7730d55b76fSBaochen Qiang ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val); 7740d55b76fSBaochen Qiang 77522cc6873SManikanta Pubbisetty val = ath11k_hif_read32(ab, reo_base + HAL_REO1_MISC_CTL(ab)); 7760d55b76fSBaochen Qiang val &= ~HAL_REO1_MISC_CTL_FRAGMENT_DST_RING; 7770d55b76fSBaochen Qiang val |= FIELD_PREP(HAL_REO1_MISC_CTL_FRAGMENT_DST_RING, HAL_SRNG_RING_ID_REO2SW1); 77822cc6873SManikanta Pubbisetty ath11k_hif_write32(ab, reo_base + HAL_REO1_MISC_CTL(ab), val); 7790d55b76fSBaochen Qiang 7800d55b76fSBaochen Qiang ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab), 7810d55b76fSBaochen Qiang HAL_DEFAULT_REO_TIMEOUT_USEC); 7820d55b76fSBaochen Qiang ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab), 7830d55b76fSBaochen Qiang HAL_DEFAULT_REO_TIMEOUT_USEC); 7840d55b76fSBaochen Qiang ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab), 7850d55b76fSBaochen Qiang HAL_DEFAULT_REO_TIMEOUT_USEC); 7860d55b76fSBaochen Qiang ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab), 7870d55b76fSBaochen Qiang HAL_DEFAULT_REO_TIMEOUT_USEC); 7880d55b76fSBaochen Qiang 7890d55b76fSBaochen Qiang ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2, 7900d55b76fSBaochen Qiang ring_hash_map); 7910d55b76fSBaochen Qiang ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3, 7920d55b76fSBaochen Qiang ring_hash_map); 7930d55b76fSBaochen Qiang } 7940d55b76fSBaochen Qiang 79569968f88SSriram R static void ath11k_hw_ipq5018_reo_setup(struct ath11k_base *ab) 79669968f88SSriram R { 79769968f88SSriram R u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG; 79869968f88SSriram R u32 val; 79969968f88SSriram R 80069968f88SSriram R /* Each hash entry uses three bits to map to a particular ring. */ 80169968f88SSriram R u32 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 | 80269968f88SSriram R HAL_HASH_ROUTING_RING_SW2 << 4 | 80369968f88SSriram R HAL_HASH_ROUTING_RING_SW3 << 8 | 80469968f88SSriram R HAL_HASH_ROUTING_RING_SW4 << 12 | 80569968f88SSriram R HAL_HASH_ROUTING_RING_SW1 << 16 | 80669968f88SSriram R HAL_HASH_ROUTING_RING_SW2 << 20 | 80769968f88SSriram R HAL_HASH_ROUTING_RING_SW3 << 24 | 80869968f88SSriram R HAL_HASH_ROUTING_RING_SW4 << 28; 80969968f88SSriram R 81069968f88SSriram R val = ath11k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE); 81169968f88SSriram R 81269968f88SSriram R val &= ~HAL_REO1_GEN_ENABLE_FRAG_DST_RING; 81369968f88SSriram R val |= FIELD_PREP(HAL_REO1_GEN_ENABLE_FRAG_DST_RING, 81469968f88SSriram R HAL_SRNG_RING_ID_REO2SW1) | 81569968f88SSriram R FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE, 1) | 81669968f88SSriram R FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE, 1); 81769968f88SSriram R ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val); 81869968f88SSriram R 81969968f88SSriram R ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab), 82069968f88SSriram R HAL_DEFAULT_REO_TIMEOUT_USEC); 82169968f88SSriram R ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab), 82269968f88SSriram R HAL_DEFAULT_REO_TIMEOUT_USEC); 82369968f88SSriram R ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab), 82469968f88SSriram R HAL_DEFAULT_REO_TIMEOUT_USEC); 82569968f88SSriram R ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab), 82669968f88SSriram R HAL_DEFAULT_REO_TIMEOUT_USEC); 82769968f88SSriram R 82869968f88SSriram R ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_0, 82969968f88SSriram R ring_hash_map); 83069968f88SSriram R ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_1, 83169968f88SSriram R ring_hash_map); 83269968f88SSriram R ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2, 83369968f88SSriram R ring_hash_map); 83469968f88SSriram R ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3, 83569968f88SSriram R ring_hash_map); 83669968f88SSriram R } 83769968f88SSriram R 8388845fed1SBaochen Qiang static u16 ath11k_hw_ipq8074_mpdu_info_get_peerid(u8 *tlv_data) 8398845fed1SBaochen Qiang { 8408845fed1SBaochen Qiang u16 peer_id = 0; 8418845fed1SBaochen Qiang struct hal_rx_mpdu_info *mpdu_info = 8428845fed1SBaochen Qiang (struct hal_rx_mpdu_info *)tlv_data; 8438845fed1SBaochen Qiang 8448845fed1SBaochen Qiang peer_id = FIELD_GET(HAL_RX_MPDU_INFO_INFO0_PEERID, 8458845fed1SBaochen Qiang __le32_to_cpu(mpdu_info->info0)); 8468845fed1SBaochen Qiang 8478845fed1SBaochen Qiang return peer_id; 8488845fed1SBaochen Qiang } 8498845fed1SBaochen Qiang 8508845fed1SBaochen Qiang static u16 ath11k_hw_wcn6855_mpdu_info_get_peerid(u8 *tlv_data) 8518845fed1SBaochen Qiang { 8528845fed1SBaochen Qiang u16 peer_id = 0; 8538845fed1SBaochen Qiang struct hal_rx_mpdu_info_wcn6855 *mpdu_info = 8548845fed1SBaochen Qiang (struct hal_rx_mpdu_info_wcn6855 *)tlv_data; 8558845fed1SBaochen Qiang 8568845fed1SBaochen Qiang peer_id = FIELD_GET(HAL_RX_MPDU_INFO_INFO0_PEERID_WCN6855, 8578845fed1SBaochen Qiang __le32_to_cpu(mpdu_info->info0)); 8588845fed1SBaochen Qiang return peer_id; 8598845fed1SBaochen Qiang } 8608845fed1SBaochen Qiang 861648ab472SBaochen Qiang static bool ath11k_hw_wcn6855_rx_desc_get_ldpc_support(struct hal_rx_desc *desc) 862648ab472SBaochen Qiang { 863648ab472SBaochen Qiang return FIELD_GET(RX_MSDU_START_INFO2_LDPC, 864648ab472SBaochen Qiang __le32_to_cpu(desc->u.wcn6855.msdu_start.info2)); 865648ab472SBaochen Qiang } 866648ab472SBaochen Qiang 8677636c9a6SManikanta Pubbisetty static u32 ath11k_hw_ipq8074_get_tcl_ring_selector(struct sk_buff *skb) 8687636c9a6SManikanta Pubbisetty { 8697636c9a6SManikanta Pubbisetty /* Let the default ring selection be based on current processor 8707636c9a6SManikanta Pubbisetty * number, where one of the 3 tcl rings are selected based on 8717636c9a6SManikanta Pubbisetty * the smp_processor_id(). In case that ring 8727636c9a6SManikanta Pubbisetty * is full/busy, we resort to other available rings. 8737636c9a6SManikanta Pubbisetty * If all rings are full, we drop the packet. 8747636c9a6SManikanta Pubbisetty * 8757636c9a6SManikanta Pubbisetty * TODO: Add throttling logic when all rings are full 8767636c9a6SManikanta Pubbisetty */ 8777636c9a6SManikanta Pubbisetty return smp_processor_id(); 8787636c9a6SManikanta Pubbisetty } 8797636c9a6SManikanta Pubbisetty 8807636c9a6SManikanta Pubbisetty static u32 ath11k_hw_wcn6750_get_tcl_ring_selector(struct sk_buff *skb) 8817636c9a6SManikanta Pubbisetty { 8827636c9a6SManikanta Pubbisetty /* Select the TCL ring based on the flow hash of the SKB instead 8837636c9a6SManikanta Pubbisetty * of CPU ID. Since applications pumping the traffic can be scheduled 8847636c9a6SManikanta Pubbisetty * on multiple CPUs, there is a chance that packets of the same flow 8857636c9a6SManikanta Pubbisetty * could end on different TCL rings, this could sometimes results in 8867636c9a6SManikanta Pubbisetty * an out of order arrival of the packets at the receiver. 8877636c9a6SManikanta Pubbisetty */ 8887636c9a6SManikanta Pubbisetty return skb_get_hash(skb); 8897636c9a6SManikanta Pubbisetty } 8907636c9a6SManikanta Pubbisetty 891d547ca4cSAnilkumar Kolli const struct ath11k_hw_ops ipq8074_ops = { 892d547ca4cSAnilkumar Kolli .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id, 89336c7c640SKarthikeyan Periyasamy .wmi_init_config = ath11k_init_wmi_config_ipq8074, 8944152e420SCarl Huang .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074, 8954152e420SCarl Huang .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074, 8966fe6f68fSKarthikeyan Periyasamy .tx_mesh_enable = ath11k_hw_ipq8074_tx_mesh_enable, 897e678fbd4SKarthikeyan Periyasamy .rx_desc_get_first_msdu = ath11k_hw_ipq8074_rx_desc_get_first_msdu, 898e678fbd4SKarthikeyan Periyasamy .rx_desc_get_last_msdu = ath11k_hw_ipq8074_rx_desc_get_last_msdu, 899e678fbd4SKarthikeyan Periyasamy .rx_desc_get_l3_pad_bytes = ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes, 900e678fbd4SKarthikeyan Periyasamy .rx_desc_get_hdr_status = ath11k_hw_ipq8074_rx_desc_get_hdr_status, 901e678fbd4SKarthikeyan Periyasamy .rx_desc_encrypt_valid = ath11k_hw_ipq8074_rx_desc_encrypt_valid, 902e678fbd4SKarthikeyan Periyasamy .rx_desc_get_encrypt_type = ath11k_hw_ipq8074_rx_desc_get_encrypt_type, 903e678fbd4SKarthikeyan Periyasamy .rx_desc_get_decap_type = ath11k_hw_ipq8074_rx_desc_get_decap_type, 904e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mesh_ctl = ath11k_hw_ipq8074_rx_desc_get_mesh_ctl, 905b3febdccSP Praneesh .rx_desc_get_ldpc_support = ath11k_hw_ipq8074_rx_desc_get_ldpc_support, 906e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld, 907e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_fc_valid = ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid, 908e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_start_seq_no = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no, 909e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_len = ath11k_hw_ipq8074_rx_desc_get_msdu_len, 910e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_sgi = ath11k_hw_ipq8074_rx_desc_get_msdu_sgi, 911e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_rate_mcs = ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs, 912e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_rx_bw = ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw, 913e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_freq = ath11k_hw_ipq8074_rx_desc_get_msdu_freq, 914e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_pkt_type = ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type, 915e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_nss = ath11k_hw_ipq8074_rx_desc_get_msdu_nss, 916e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_tid = ath11k_hw_ipq8074_rx_desc_get_mpdu_tid, 917e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_peer_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id, 918e678fbd4SKarthikeyan Periyasamy .rx_desc_copy_attn_end_tlv = ath11k_hw_ipq8074_rx_desc_copy_attn_end, 919e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_start_tag = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag, 920e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_ppdu_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id, 921e678fbd4SKarthikeyan Periyasamy .rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len, 922e678fbd4SKarthikeyan Periyasamy .rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention, 923e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload, 9240d55b76fSBaochen Qiang .reo_setup = ath11k_hw_ipq8074_reo_setup, 9258845fed1SBaochen Qiang .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, 9262167fa60SSriram R .rx_desc_mac_addr2_valid = ath11k_hw_ipq8074_rx_desc_mac_addr2_valid, 9272167fa60SSriram R .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq8074_rx_desc_mpdu_start_addr2, 9287636c9a6SManikanta Pubbisetty .get_ring_selector = ath11k_hw_ipq8074_get_tcl_ring_selector, 929d547ca4cSAnilkumar Kolli }; 930d547ca4cSAnilkumar Kolli 931d547ca4cSAnilkumar Kolli const struct ath11k_hw_ops ipq6018_ops = { 932d547ca4cSAnilkumar Kolli .get_hw_mac_from_pdev_id = ath11k_hw_ipq6018_mac_from_pdev_id, 9332d4bcbedSCarl Huang .wmi_init_config = ath11k_init_wmi_config_ipq8074, 9344152e420SCarl Huang .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074, 9354152e420SCarl Huang .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074, 9366fe6f68fSKarthikeyan Periyasamy .tx_mesh_enable = ath11k_hw_ipq8074_tx_mesh_enable, 937e678fbd4SKarthikeyan Periyasamy .rx_desc_get_first_msdu = ath11k_hw_ipq8074_rx_desc_get_first_msdu, 938e678fbd4SKarthikeyan Periyasamy .rx_desc_get_last_msdu = ath11k_hw_ipq8074_rx_desc_get_last_msdu, 939e678fbd4SKarthikeyan Periyasamy .rx_desc_get_l3_pad_bytes = ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes, 940e678fbd4SKarthikeyan Periyasamy .rx_desc_get_hdr_status = ath11k_hw_ipq8074_rx_desc_get_hdr_status, 941e678fbd4SKarthikeyan Periyasamy .rx_desc_encrypt_valid = ath11k_hw_ipq8074_rx_desc_encrypt_valid, 942e678fbd4SKarthikeyan Periyasamy .rx_desc_get_encrypt_type = ath11k_hw_ipq8074_rx_desc_get_encrypt_type, 943e678fbd4SKarthikeyan Periyasamy .rx_desc_get_decap_type = ath11k_hw_ipq8074_rx_desc_get_decap_type, 944e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mesh_ctl = ath11k_hw_ipq8074_rx_desc_get_mesh_ctl, 945b3febdccSP Praneesh .rx_desc_get_ldpc_support = ath11k_hw_ipq8074_rx_desc_get_ldpc_support, 946e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld, 947e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_fc_valid = ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid, 948e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_start_seq_no = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no, 949e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_len = ath11k_hw_ipq8074_rx_desc_get_msdu_len, 950e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_sgi = ath11k_hw_ipq8074_rx_desc_get_msdu_sgi, 951e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_rate_mcs = ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs, 952e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_rx_bw = ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw, 953e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_freq = ath11k_hw_ipq8074_rx_desc_get_msdu_freq, 954e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_pkt_type = ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type, 955e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_nss = ath11k_hw_ipq8074_rx_desc_get_msdu_nss, 956e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_tid = ath11k_hw_ipq8074_rx_desc_get_mpdu_tid, 957e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_peer_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id, 958e678fbd4SKarthikeyan Periyasamy .rx_desc_copy_attn_end_tlv = ath11k_hw_ipq8074_rx_desc_copy_attn_end, 959e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_start_tag = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag, 960e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_ppdu_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id, 961e678fbd4SKarthikeyan Periyasamy .rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len, 962e678fbd4SKarthikeyan Periyasamy .rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention, 963e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload, 9640d55b76fSBaochen Qiang .reo_setup = ath11k_hw_ipq8074_reo_setup, 9658845fed1SBaochen Qiang .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, 9662167fa60SSriram R .rx_desc_mac_addr2_valid = ath11k_hw_ipq8074_rx_desc_mac_addr2_valid, 9672167fa60SSriram R .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq8074_rx_desc_mpdu_start_addr2, 9687636c9a6SManikanta Pubbisetty .get_ring_selector = ath11k_hw_ipq8074_get_tcl_ring_selector, 969d547ca4cSAnilkumar Kolli }; 9709de2ad43SCarl Huang 9719de2ad43SCarl Huang const struct ath11k_hw_ops qca6390_ops = { 9729de2ad43SCarl Huang .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id, 9734152e420SCarl Huang .wmi_init_config = ath11k_init_wmi_config_qca6390, 9744152e420SCarl Huang .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390, 9754152e420SCarl Huang .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390, 9766fe6f68fSKarthikeyan Periyasamy .tx_mesh_enable = ath11k_hw_ipq8074_tx_mesh_enable, 977e678fbd4SKarthikeyan Periyasamy .rx_desc_get_first_msdu = ath11k_hw_ipq8074_rx_desc_get_first_msdu, 978e678fbd4SKarthikeyan Periyasamy .rx_desc_get_last_msdu = ath11k_hw_ipq8074_rx_desc_get_last_msdu, 979e678fbd4SKarthikeyan Periyasamy .rx_desc_get_l3_pad_bytes = ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes, 980e678fbd4SKarthikeyan Periyasamy .rx_desc_get_hdr_status = ath11k_hw_ipq8074_rx_desc_get_hdr_status, 981e678fbd4SKarthikeyan Periyasamy .rx_desc_encrypt_valid = ath11k_hw_ipq8074_rx_desc_encrypt_valid, 982e678fbd4SKarthikeyan Periyasamy .rx_desc_get_encrypt_type = ath11k_hw_ipq8074_rx_desc_get_encrypt_type, 983e678fbd4SKarthikeyan Periyasamy .rx_desc_get_decap_type = ath11k_hw_ipq8074_rx_desc_get_decap_type, 984e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mesh_ctl = ath11k_hw_ipq8074_rx_desc_get_mesh_ctl, 985b3febdccSP Praneesh .rx_desc_get_ldpc_support = ath11k_hw_ipq8074_rx_desc_get_ldpc_support, 986e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld, 987e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_fc_valid = ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid, 988e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_start_seq_no = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no, 989e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_len = ath11k_hw_ipq8074_rx_desc_get_msdu_len, 990e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_sgi = ath11k_hw_ipq8074_rx_desc_get_msdu_sgi, 991e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_rate_mcs = ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs, 992e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_rx_bw = ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw, 993e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_freq = ath11k_hw_ipq8074_rx_desc_get_msdu_freq, 994e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_pkt_type = ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type, 995e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_nss = ath11k_hw_ipq8074_rx_desc_get_msdu_nss, 996e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_tid = ath11k_hw_ipq8074_rx_desc_get_mpdu_tid, 997e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_peer_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id, 998e678fbd4SKarthikeyan Periyasamy .rx_desc_copy_attn_end_tlv = ath11k_hw_ipq8074_rx_desc_copy_attn_end, 999e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_start_tag = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag, 1000e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_ppdu_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id, 1001e678fbd4SKarthikeyan Periyasamy .rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len, 1002e678fbd4SKarthikeyan Periyasamy .rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention, 1003e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload, 10040d55b76fSBaochen Qiang .reo_setup = ath11k_hw_ipq8074_reo_setup, 10058845fed1SBaochen Qiang .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, 10062167fa60SSriram R .rx_desc_mac_addr2_valid = ath11k_hw_ipq8074_rx_desc_mac_addr2_valid, 10072167fa60SSriram R .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq8074_rx_desc_mpdu_start_addr2, 10087636c9a6SManikanta Pubbisetty .get_ring_selector = ath11k_hw_ipq8074_get_tcl_ring_selector, 10096fe6f68fSKarthikeyan Periyasamy }; 10106fe6f68fSKarthikeyan Periyasamy 10116fe6f68fSKarthikeyan Periyasamy const struct ath11k_hw_ops qcn9074_ops = { 10126fe6f68fSKarthikeyan Periyasamy .get_hw_mac_from_pdev_id = ath11k_hw_ipq6018_mac_from_pdev_id, 10136fe6f68fSKarthikeyan Periyasamy .wmi_init_config = ath11k_init_wmi_config_ipq8074, 10146fe6f68fSKarthikeyan Periyasamy .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074, 10156fe6f68fSKarthikeyan Periyasamy .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074, 10166fe6f68fSKarthikeyan Periyasamy .tx_mesh_enable = ath11k_hw_qcn9074_tx_mesh_enable, 1017e678fbd4SKarthikeyan Periyasamy .rx_desc_get_first_msdu = ath11k_hw_qcn9074_rx_desc_get_first_msdu, 1018e678fbd4SKarthikeyan Periyasamy .rx_desc_get_last_msdu = ath11k_hw_qcn9074_rx_desc_get_last_msdu, 1019e678fbd4SKarthikeyan Periyasamy .rx_desc_get_l3_pad_bytes = ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes, 1020e678fbd4SKarthikeyan Periyasamy .rx_desc_get_hdr_status = ath11k_hw_qcn9074_rx_desc_get_hdr_status, 1021e678fbd4SKarthikeyan Periyasamy .rx_desc_encrypt_valid = ath11k_hw_qcn9074_rx_desc_encrypt_valid, 1022e678fbd4SKarthikeyan Periyasamy .rx_desc_get_encrypt_type = ath11k_hw_qcn9074_rx_desc_get_encrypt_type, 1023e678fbd4SKarthikeyan Periyasamy .rx_desc_get_decap_type = ath11k_hw_qcn9074_rx_desc_get_decap_type, 1024e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mesh_ctl = ath11k_hw_qcn9074_rx_desc_get_mesh_ctl, 1025b3febdccSP Praneesh .rx_desc_get_ldpc_support = ath11k_hw_qcn9074_rx_desc_get_ldpc_support, 1026e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld, 1027e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_fc_valid = ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid, 1028e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_start_seq_no = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no, 1029e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_len = ath11k_hw_qcn9074_rx_desc_get_msdu_len, 1030e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_sgi = ath11k_hw_qcn9074_rx_desc_get_msdu_sgi, 1031e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_rate_mcs = ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs, 1032e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_rx_bw = ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw, 1033e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_freq = ath11k_hw_qcn9074_rx_desc_get_msdu_freq, 1034e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_pkt_type = ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type, 1035e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_nss = ath11k_hw_qcn9074_rx_desc_get_msdu_nss, 1036e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_tid = ath11k_hw_qcn9074_rx_desc_get_mpdu_tid, 1037e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_peer_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id, 1038e678fbd4SKarthikeyan Periyasamy .rx_desc_copy_attn_end_tlv = ath11k_hw_qcn9074_rx_desc_copy_attn_end, 1039e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_start_tag = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag, 1040e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_ppdu_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id, 1041e678fbd4SKarthikeyan Periyasamy .rx_desc_set_msdu_len = ath11k_hw_qcn9074_rx_desc_set_msdu_len, 1042e678fbd4SKarthikeyan Periyasamy .rx_desc_get_attention = ath11k_hw_qcn9074_rx_desc_get_attention, 1043e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_payload = ath11k_hw_qcn9074_rx_desc_get_msdu_payload, 10440d55b76fSBaochen Qiang .reo_setup = ath11k_hw_ipq8074_reo_setup, 10458845fed1SBaochen Qiang .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, 10462167fa60SSriram R .rx_desc_mac_addr2_valid = ath11k_hw_ipq9074_rx_desc_mac_addr2_valid, 10472167fa60SSriram R .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq9074_rx_desc_mpdu_start_addr2, 10487636c9a6SManikanta Pubbisetty .get_ring_selector = ath11k_hw_ipq8074_get_tcl_ring_selector, 10499de2ad43SCarl Huang }; 105034d5a3a8SKalle Valo 1051e4073430SBaochen Qiang const struct ath11k_hw_ops wcn6855_ops = { 1052e4073430SBaochen Qiang .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id, 1053e4073430SBaochen Qiang .wmi_init_config = ath11k_init_wmi_config_qca6390, 1054e4073430SBaochen Qiang .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390, 1055e4073430SBaochen Qiang .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390, 1056e4073430SBaochen Qiang .tx_mesh_enable = ath11k_hw_wcn6855_tx_mesh_enable, 1057e4073430SBaochen Qiang .rx_desc_get_first_msdu = ath11k_hw_wcn6855_rx_desc_get_first_msdu, 1058e4073430SBaochen Qiang .rx_desc_get_last_msdu = ath11k_hw_wcn6855_rx_desc_get_last_msdu, 1059e4073430SBaochen Qiang .rx_desc_get_l3_pad_bytes = ath11k_hw_wcn6855_rx_desc_get_l3_pad_bytes, 1060e4073430SBaochen Qiang .rx_desc_get_hdr_status = ath11k_hw_wcn6855_rx_desc_get_hdr_status, 1061e4073430SBaochen Qiang .rx_desc_encrypt_valid = ath11k_hw_wcn6855_rx_desc_encrypt_valid, 1062e4073430SBaochen Qiang .rx_desc_get_encrypt_type = ath11k_hw_wcn6855_rx_desc_get_encrypt_type, 1063e4073430SBaochen Qiang .rx_desc_get_decap_type = ath11k_hw_wcn6855_rx_desc_get_decap_type, 1064e4073430SBaochen Qiang .rx_desc_get_mesh_ctl = ath11k_hw_wcn6855_rx_desc_get_mesh_ctl, 1065648ab472SBaochen Qiang .rx_desc_get_ldpc_support = ath11k_hw_wcn6855_rx_desc_get_ldpc_support, 1066e4073430SBaochen Qiang .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_wcn6855_rx_desc_get_mpdu_seq_ctl_vld, 1067e4073430SBaochen Qiang .rx_desc_get_mpdu_fc_valid = ath11k_hw_wcn6855_rx_desc_get_mpdu_fc_valid, 1068e4073430SBaochen Qiang .rx_desc_get_mpdu_start_seq_no = ath11k_hw_wcn6855_rx_desc_get_mpdu_start_seq_no, 1069e4073430SBaochen Qiang .rx_desc_get_msdu_len = ath11k_hw_wcn6855_rx_desc_get_msdu_len, 1070e4073430SBaochen Qiang .rx_desc_get_msdu_sgi = ath11k_hw_wcn6855_rx_desc_get_msdu_sgi, 1071e4073430SBaochen Qiang .rx_desc_get_msdu_rate_mcs = ath11k_hw_wcn6855_rx_desc_get_msdu_rate_mcs, 1072e4073430SBaochen Qiang .rx_desc_get_msdu_rx_bw = ath11k_hw_wcn6855_rx_desc_get_msdu_rx_bw, 1073e4073430SBaochen Qiang .rx_desc_get_msdu_freq = ath11k_hw_wcn6855_rx_desc_get_msdu_freq, 1074e4073430SBaochen Qiang .rx_desc_get_msdu_pkt_type = ath11k_hw_wcn6855_rx_desc_get_msdu_pkt_type, 1075e4073430SBaochen Qiang .rx_desc_get_msdu_nss = ath11k_hw_wcn6855_rx_desc_get_msdu_nss, 1076e4073430SBaochen Qiang .rx_desc_get_mpdu_tid = ath11k_hw_wcn6855_rx_desc_get_mpdu_tid, 1077e4073430SBaochen Qiang .rx_desc_get_mpdu_peer_id = ath11k_hw_wcn6855_rx_desc_get_mpdu_peer_id, 1078e4073430SBaochen Qiang .rx_desc_copy_attn_end_tlv = ath11k_hw_wcn6855_rx_desc_copy_attn_end, 1079e4073430SBaochen Qiang .rx_desc_get_mpdu_start_tag = ath11k_hw_wcn6855_rx_desc_get_mpdu_start_tag, 1080e4073430SBaochen Qiang .rx_desc_get_mpdu_ppdu_id = ath11k_hw_wcn6855_rx_desc_get_mpdu_ppdu_id, 1081e4073430SBaochen Qiang .rx_desc_set_msdu_len = ath11k_hw_wcn6855_rx_desc_set_msdu_len, 1082e4073430SBaochen Qiang .rx_desc_get_attention = ath11k_hw_wcn6855_rx_desc_get_attention, 1083e4073430SBaochen Qiang .rx_desc_get_msdu_payload = ath11k_hw_wcn6855_rx_desc_get_msdu_payload, 10840d55b76fSBaochen Qiang .reo_setup = ath11k_hw_wcn6855_reo_setup, 10858845fed1SBaochen Qiang .mpdu_info_get_peerid = ath11k_hw_wcn6855_mpdu_info_get_peerid, 10862167fa60SSriram R .rx_desc_mac_addr2_valid = ath11k_hw_wcn6855_rx_desc_mac_addr2_valid, 10872167fa60SSriram R .rx_desc_mpdu_start_addr2 = ath11k_hw_wcn6855_rx_desc_mpdu_start_addr2, 10887636c9a6SManikanta Pubbisetty .get_ring_selector = ath11k_hw_ipq8074_get_tcl_ring_selector, 1089e4073430SBaochen Qiang }; 1090e4073430SBaochen Qiang 109149890d9cSManikanta Pubbisetty const struct ath11k_hw_ops wcn6750_ops = { 109249890d9cSManikanta Pubbisetty .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id, 109349890d9cSManikanta Pubbisetty .wmi_init_config = ath11k_init_wmi_config_qca6390, 109449890d9cSManikanta Pubbisetty .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390, 109549890d9cSManikanta Pubbisetty .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390, 1096e67ba197SManikanta Pubbisetty .tx_mesh_enable = ath11k_hw_qcn9074_tx_mesh_enable, 1097e67ba197SManikanta Pubbisetty .rx_desc_get_first_msdu = ath11k_hw_qcn9074_rx_desc_get_first_msdu, 1098e67ba197SManikanta Pubbisetty .rx_desc_get_last_msdu = ath11k_hw_qcn9074_rx_desc_get_last_msdu, 1099e67ba197SManikanta Pubbisetty .rx_desc_get_l3_pad_bytes = ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes, 1100e67ba197SManikanta Pubbisetty .rx_desc_get_hdr_status = ath11k_hw_qcn9074_rx_desc_get_hdr_status, 1101e67ba197SManikanta Pubbisetty .rx_desc_encrypt_valid = ath11k_hw_qcn9074_rx_desc_encrypt_valid, 1102e67ba197SManikanta Pubbisetty .rx_desc_get_encrypt_type = ath11k_hw_qcn9074_rx_desc_get_encrypt_type, 1103e67ba197SManikanta Pubbisetty .rx_desc_get_decap_type = ath11k_hw_qcn9074_rx_desc_get_decap_type, 1104e67ba197SManikanta Pubbisetty .rx_desc_get_mesh_ctl = ath11k_hw_qcn9074_rx_desc_get_mesh_ctl, 1105e67ba197SManikanta Pubbisetty .rx_desc_get_ldpc_support = ath11k_hw_qcn9074_rx_desc_get_ldpc_support, 1106e67ba197SManikanta Pubbisetty .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld, 1107e67ba197SManikanta Pubbisetty .rx_desc_get_mpdu_fc_valid = ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid, 1108e67ba197SManikanta Pubbisetty .rx_desc_get_mpdu_start_seq_no = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no, 1109e67ba197SManikanta Pubbisetty .rx_desc_get_msdu_len = ath11k_hw_qcn9074_rx_desc_get_msdu_len, 1110e67ba197SManikanta Pubbisetty .rx_desc_get_msdu_sgi = ath11k_hw_qcn9074_rx_desc_get_msdu_sgi, 1111e67ba197SManikanta Pubbisetty .rx_desc_get_msdu_rate_mcs = ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs, 1112e67ba197SManikanta Pubbisetty .rx_desc_get_msdu_rx_bw = ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw, 1113e67ba197SManikanta Pubbisetty .rx_desc_get_msdu_freq = ath11k_hw_qcn9074_rx_desc_get_msdu_freq, 1114e67ba197SManikanta Pubbisetty .rx_desc_get_msdu_pkt_type = ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type, 1115e67ba197SManikanta Pubbisetty .rx_desc_get_msdu_nss = ath11k_hw_qcn9074_rx_desc_get_msdu_nss, 1116e67ba197SManikanta Pubbisetty .rx_desc_get_mpdu_tid = ath11k_hw_qcn9074_rx_desc_get_mpdu_tid, 1117e67ba197SManikanta Pubbisetty .rx_desc_get_mpdu_peer_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id, 1118e67ba197SManikanta Pubbisetty .rx_desc_copy_attn_end_tlv = ath11k_hw_qcn9074_rx_desc_copy_attn_end, 1119e67ba197SManikanta Pubbisetty .rx_desc_get_mpdu_start_tag = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag, 1120e67ba197SManikanta Pubbisetty .rx_desc_get_mpdu_ppdu_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id, 1121e67ba197SManikanta Pubbisetty .rx_desc_set_msdu_len = ath11k_hw_qcn9074_rx_desc_set_msdu_len, 1122e67ba197SManikanta Pubbisetty .rx_desc_get_attention = ath11k_hw_qcn9074_rx_desc_get_attention, 1123e67ba197SManikanta Pubbisetty .rx_desc_get_msdu_payload = ath11k_hw_qcn9074_rx_desc_get_msdu_payload, 1124e67ba197SManikanta Pubbisetty .reo_setup = ath11k_hw_wcn6855_reo_setup, 1125e67ba197SManikanta Pubbisetty .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, 1126e67ba197SManikanta Pubbisetty .rx_desc_mac_addr2_valid = ath11k_hw_ipq9074_rx_desc_mac_addr2_valid, 1127e67ba197SManikanta Pubbisetty .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq9074_rx_desc_mpdu_start_addr2, 11287636c9a6SManikanta Pubbisetty .get_ring_selector = ath11k_hw_wcn6750_get_tcl_ring_selector, 112949890d9cSManikanta Pubbisetty }; 113049890d9cSManikanta Pubbisetty 1131ba60f279SSriram R /* IPQ5018 hw ops is similar to QCN9074 except for the dest ring remap */ 1132ba60f279SSriram R const struct ath11k_hw_ops ipq5018_ops = { 1133ba60f279SSriram R .get_hw_mac_from_pdev_id = ath11k_hw_ipq6018_mac_from_pdev_id, 1134ba60f279SSriram R .wmi_init_config = ath11k_init_wmi_config_ipq8074, 1135ba60f279SSriram R .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074, 1136ba60f279SSriram R .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074, 1137ba60f279SSriram R .tx_mesh_enable = ath11k_hw_qcn9074_tx_mesh_enable, 1138ba60f279SSriram R .rx_desc_get_first_msdu = ath11k_hw_qcn9074_rx_desc_get_first_msdu, 1139ba60f279SSriram R .rx_desc_get_last_msdu = ath11k_hw_qcn9074_rx_desc_get_last_msdu, 1140ba60f279SSriram R .rx_desc_get_l3_pad_bytes = ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes, 1141ba60f279SSriram R .rx_desc_get_hdr_status = ath11k_hw_qcn9074_rx_desc_get_hdr_status, 1142ba60f279SSriram R .rx_desc_encrypt_valid = ath11k_hw_qcn9074_rx_desc_encrypt_valid, 1143ba60f279SSriram R .rx_desc_get_encrypt_type = ath11k_hw_qcn9074_rx_desc_get_encrypt_type, 1144ba60f279SSriram R .rx_desc_get_decap_type = ath11k_hw_qcn9074_rx_desc_get_decap_type, 1145ba60f279SSriram R .rx_desc_get_mesh_ctl = ath11k_hw_qcn9074_rx_desc_get_mesh_ctl, 1146ba60f279SSriram R .rx_desc_get_ldpc_support = ath11k_hw_qcn9074_rx_desc_get_ldpc_support, 1147ba60f279SSriram R .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld, 1148ba60f279SSriram R .rx_desc_get_mpdu_fc_valid = ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid, 1149ba60f279SSriram R .rx_desc_get_mpdu_start_seq_no = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no, 1150ba60f279SSriram R .rx_desc_get_msdu_len = ath11k_hw_qcn9074_rx_desc_get_msdu_len, 1151ba60f279SSriram R .rx_desc_get_msdu_sgi = ath11k_hw_qcn9074_rx_desc_get_msdu_sgi, 1152ba60f279SSriram R .rx_desc_get_msdu_rate_mcs = ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs, 1153ba60f279SSriram R .rx_desc_get_msdu_rx_bw = ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw, 1154ba60f279SSriram R .rx_desc_get_msdu_freq = ath11k_hw_qcn9074_rx_desc_get_msdu_freq, 1155ba60f279SSriram R .rx_desc_get_msdu_pkt_type = ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type, 1156ba60f279SSriram R .rx_desc_get_msdu_nss = ath11k_hw_qcn9074_rx_desc_get_msdu_nss, 1157ba60f279SSriram R .rx_desc_get_mpdu_tid = ath11k_hw_qcn9074_rx_desc_get_mpdu_tid, 1158ba60f279SSriram R .rx_desc_get_mpdu_peer_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id, 1159ba60f279SSriram R .rx_desc_copy_attn_end_tlv = ath11k_hw_qcn9074_rx_desc_copy_attn_end, 1160ba60f279SSriram R .rx_desc_get_mpdu_start_tag = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag, 1161ba60f279SSriram R .rx_desc_get_mpdu_ppdu_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id, 1162ba60f279SSriram R .rx_desc_set_msdu_len = ath11k_hw_qcn9074_rx_desc_set_msdu_len, 1163ba60f279SSriram R .rx_desc_get_attention = ath11k_hw_qcn9074_rx_desc_get_attention, 116469968f88SSriram R .reo_setup = ath11k_hw_ipq5018_reo_setup, 1165ba60f279SSriram R .rx_desc_get_msdu_payload = ath11k_hw_qcn9074_rx_desc_get_msdu_payload, 1166ba60f279SSriram R .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, 1167ba60f279SSriram R .rx_desc_mac_addr2_valid = ath11k_hw_ipq9074_rx_desc_mac_addr2_valid, 1168ba60f279SSriram R .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq9074_rx_desc_mpdu_start_addr2, 1169ba60f279SSriram R 1170ba60f279SSriram R }; 1171ba60f279SSriram R 11727636c9a6SManikanta Pubbisetty #define ATH11K_TX_RING_MASK_0 BIT(0) 11737636c9a6SManikanta Pubbisetty #define ATH11K_TX_RING_MASK_1 BIT(1) 11747636c9a6SManikanta Pubbisetty #define ATH11K_TX_RING_MASK_2 BIT(2) 11757636c9a6SManikanta Pubbisetty #define ATH11K_TX_RING_MASK_3 BIT(3) 11767636c9a6SManikanta Pubbisetty #define ATH11K_TX_RING_MASK_4 BIT(4) 117734d5a3a8SKalle Valo 117834d5a3a8SKalle Valo #define ATH11K_RX_RING_MASK_0 0x1 117934d5a3a8SKalle Valo #define ATH11K_RX_RING_MASK_1 0x2 118034d5a3a8SKalle Valo #define ATH11K_RX_RING_MASK_2 0x4 118134d5a3a8SKalle Valo #define ATH11K_RX_RING_MASK_3 0x8 118234d5a3a8SKalle Valo 118334d5a3a8SKalle Valo #define ATH11K_RX_ERR_RING_MASK_0 0x1 118434d5a3a8SKalle Valo 118534d5a3a8SKalle Valo #define ATH11K_RX_WBM_REL_RING_MASK_0 0x1 118634d5a3a8SKalle Valo 118734d5a3a8SKalle Valo #define ATH11K_REO_STATUS_RING_MASK_0 0x1 118834d5a3a8SKalle Valo 118934d5a3a8SKalle Valo #define ATH11K_RXDMA2HOST_RING_MASK_0 0x1 119034d5a3a8SKalle Valo #define ATH11K_RXDMA2HOST_RING_MASK_1 0x2 119134d5a3a8SKalle Valo #define ATH11K_RXDMA2HOST_RING_MASK_2 0x4 119234d5a3a8SKalle Valo 119334d5a3a8SKalle Valo #define ATH11K_HOST2RXDMA_RING_MASK_0 0x1 119434d5a3a8SKalle Valo #define ATH11K_HOST2RXDMA_RING_MASK_1 0x2 119534d5a3a8SKalle Valo #define ATH11K_HOST2RXDMA_RING_MASK_2 0x4 119634d5a3a8SKalle Valo 119734d5a3a8SKalle Valo #define ATH11K_RX_MON_STATUS_RING_MASK_0 0x1 119834d5a3a8SKalle Valo #define ATH11K_RX_MON_STATUS_RING_MASK_1 0x2 119934d5a3a8SKalle Valo #define ATH11K_RX_MON_STATUS_RING_MASK_2 0x4 120034d5a3a8SKalle Valo 120134d5a3a8SKalle Valo const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_ipq8074 = { 120234d5a3a8SKalle Valo .tx = { 120334d5a3a8SKalle Valo ATH11K_TX_RING_MASK_0, 120434d5a3a8SKalle Valo ATH11K_TX_RING_MASK_1, 120534d5a3a8SKalle Valo ATH11K_TX_RING_MASK_2, 120634d5a3a8SKalle Valo }, 120734d5a3a8SKalle Valo .rx_mon_status = { 120834d5a3a8SKalle Valo 0, 0, 0, 0, 120934d5a3a8SKalle Valo ATH11K_RX_MON_STATUS_RING_MASK_0, 121034d5a3a8SKalle Valo ATH11K_RX_MON_STATUS_RING_MASK_1, 121134d5a3a8SKalle Valo ATH11K_RX_MON_STATUS_RING_MASK_2, 121234d5a3a8SKalle Valo }, 121334d5a3a8SKalle Valo .rx = { 121434d5a3a8SKalle Valo 0, 0, 0, 0, 0, 0, 0, 121534d5a3a8SKalle Valo ATH11K_RX_RING_MASK_0, 121634d5a3a8SKalle Valo ATH11K_RX_RING_MASK_1, 121734d5a3a8SKalle Valo ATH11K_RX_RING_MASK_2, 121834d5a3a8SKalle Valo ATH11K_RX_RING_MASK_3, 121934d5a3a8SKalle Valo }, 122034d5a3a8SKalle Valo .rx_err = { 122134d5a3a8SKalle Valo ATH11K_RX_ERR_RING_MASK_0, 122234d5a3a8SKalle Valo }, 122334d5a3a8SKalle Valo .rx_wbm_rel = { 122434d5a3a8SKalle Valo ATH11K_RX_WBM_REL_RING_MASK_0, 122534d5a3a8SKalle Valo }, 122634d5a3a8SKalle Valo .reo_status = { 122734d5a3a8SKalle Valo ATH11K_REO_STATUS_RING_MASK_0, 122834d5a3a8SKalle Valo }, 122934d5a3a8SKalle Valo .rxdma2host = { 123034d5a3a8SKalle Valo ATH11K_RXDMA2HOST_RING_MASK_0, 123134d5a3a8SKalle Valo ATH11K_RXDMA2HOST_RING_MASK_1, 123234d5a3a8SKalle Valo ATH11K_RXDMA2HOST_RING_MASK_2, 123334d5a3a8SKalle Valo }, 123434d5a3a8SKalle Valo .host2rxdma = { 123534d5a3a8SKalle Valo ATH11K_HOST2RXDMA_RING_MASK_0, 123634d5a3a8SKalle Valo ATH11K_HOST2RXDMA_RING_MASK_1, 123734d5a3a8SKalle Valo ATH11K_HOST2RXDMA_RING_MASK_2, 123834d5a3a8SKalle Valo }, 123934d5a3a8SKalle Valo }; 124034d5a3a8SKalle Valo 1241d4ecb90bSCarl Huang const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qca6390 = { 1242d4ecb90bSCarl Huang .tx = { 1243d4ecb90bSCarl Huang ATH11K_TX_RING_MASK_0, 1244d4ecb90bSCarl Huang }, 1245d4ecb90bSCarl Huang .rx_mon_status = { 1246d4ecb90bSCarl Huang 0, 0, 0, 0, 1247d4ecb90bSCarl Huang ATH11K_RX_MON_STATUS_RING_MASK_0, 1248d4ecb90bSCarl Huang ATH11K_RX_MON_STATUS_RING_MASK_1, 1249d4ecb90bSCarl Huang ATH11K_RX_MON_STATUS_RING_MASK_2, 1250d4ecb90bSCarl Huang }, 1251d4ecb90bSCarl Huang .rx = { 1252d4ecb90bSCarl Huang 0, 0, 0, 0, 0, 0, 0, 1253d4ecb90bSCarl Huang ATH11K_RX_RING_MASK_0, 1254d4ecb90bSCarl Huang ATH11K_RX_RING_MASK_1, 1255d4ecb90bSCarl Huang ATH11K_RX_RING_MASK_2, 1256d4ecb90bSCarl Huang ATH11K_RX_RING_MASK_3, 1257d4ecb90bSCarl Huang }, 1258d4ecb90bSCarl Huang .rx_err = { 1259d4ecb90bSCarl Huang ATH11K_RX_ERR_RING_MASK_0, 1260d4ecb90bSCarl Huang }, 1261d4ecb90bSCarl Huang .rx_wbm_rel = { 1262d4ecb90bSCarl Huang ATH11K_RX_WBM_REL_RING_MASK_0, 1263d4ecb90bSCarl Huang }, 1264d4ecb90bSCarl Huang .reo_status = { 1265d4ecb90bSCarl Huang ATH11K_REO_STATUS_RING_MASK_0, 1266d4ecb90bSCarl Huang }, 1267d4ecb90bSCarl Huang .rxdma2host = { 1268d4ecb90bSCarl Huang ATH11K_RXDMA2HOST_RING_MASK_0, 1269d4ecb90bSCarl Huang ATH11K_RXDMA2HOST_RING_MASK_1, 1270d4ecb90bSCarl Huang ATH11K_RXDMA2HOST_RING_MASK_2, 1271d4ecb90bSCarl Huang }, 1272d4ecb90bSCarl Huang .host2rxdma = { 1273d4ecb90bSCarl Huang }, 1274d4ecb90bSCarl Huang }; 1275d4ecb90bSCarl Huang 1276967c1d11SAnilkumar Kolli /* Target firmware's Copy Engine configuration. */ 1277967c1d11SAnilkumar Kolli const struct ce_pipe_config ath11k_target_ce_config_wlan_ipq8074[] = { 1278967c1d11SAnilkumar Kolli /* CE0: host->target HTC control and raw streams */ 1279967c1d11SAnilkumar Kolli { 1280967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(0), 1281967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1282967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(32), 1283967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(2048), 1284967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1285967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 1286967c1d11SAnilkumar Kolli }, 1287967c1d11SAnilkumar Kolli 1288967c1d11SAnilkumar Kolli /* CE1: target->host HTT + HTC control */ 1289967c1d11SAnilkumar Kolli { 1290967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(1), 1291967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), 1292967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(32), 1293967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(2048), 1294967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1295967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 1296967c1d11SAnilkumar Kolli }, 1297967c1d11SAnilkumar Kolli 1298967c1d11SAnilkumar Kolli /* CE2: target->host WMI */ 1299967c1d11SAnilkumar Kolli { 1300967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(2), 1301967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), 1302967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(32), 1303967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(2048), 1304967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1305967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 1306967c1d11SAnilkumar Kolli }, 1307967c1d11SAnilkumar Kolli 1308967c1d11SAnilkumar Kolli /* CE3: host->target WMI */ 1309967c1d11SAnilkumar Kolli { 1310967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(3), 1311967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1312967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(32), 1313967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(2048), 1314967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1315967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 1316967c1d11SAnilkumar Kolli }, 1317967c1d11SAnilkumar Kolli 1318967c1d11SAnilkumar Kolli /* CE4: host->target HTT */ 1319967c1d11SAnilkumar Kolli { 1320967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(4), 1321967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1322967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(256), 1323967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(256), 1324967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1325967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 1326967c1d11SAnilkumar Kolli }, 1327967c1d11SAnilkumar Kolli 1328967c1d11SAnilkumar Kolli /* CE5: target->host Pktlog */ 1329967c1d11SAnilkumar Kolli { 1330967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(5), 1331967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), 1332967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(32), 1333967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(2048), 1334967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(0), 1335967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 1336967c1d11SAnilkumar Kolli }, 1337967c1d11SAnilkumar Kolli 1338967c1d11SAnilkumar Kolli /* CE6: Reserved for target autonomous hif_memcpy */ 1339967c1d11SAnilkumar Kolli { 1340967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(6), 1341967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1342967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(32), 1343967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(65535), 1344967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1345967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 1346967c1d11SAnilkumar Kolli }, 1347967c1d11SAnilkumar Kolli 1348967c1d11SAnilkumar Kolli /* CE7 used only by Host */ 1349967c1d11SAnilkumar Kolli { 1350967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(7), 1351967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1352967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(32), 1353967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(2048), 1354967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1355967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 1356967c1d11SAnilkumar Kolli }, 1357967c1d11SAnilkumar Kolli 1358967c1d11SAnilkumar Kolli /* CE8 target->host used only by IPA */ 1359967c1d11SAnilkumar Kolli { 1360967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(8), 1361967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1362967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(32), 1363967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(65535), 1364967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1365967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 1366967c1d11SAnilkumar Kolli }, 1367967c1d11SAnilkumar Kolli 1368967c1d11SAnilkumar Kolli /* CE9 host->target HTT */ 1369967c1d11SAnilkumar Kolli { 1370967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(9), 1371967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1372967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(32), 1373967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(2048), 1374967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1375967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 1376967c1d11SAnilkumar Kolli }, 1377967c1d11SAnilkumar Kolli 1378967c1d11SAnilkumar Kolli /* CE10 target->host HTT */ 1379967c1d11SAnilkumar Kolli { 1380967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(10), 1381967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H), 1382967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(0), 1383967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(0), 1384967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1385967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 1386967c1d11SAnilkumar Kolli }, 1387967c1d11SAnilkumar Kolli 1388967c1d11SAnilkumar Kolli /* CE11 Not used */ 1389967c1d11SAnilkumar Kolli }; 1390967c1d11SAnilkumar Kolli 1391967c1d11SAnilkumar Kolli /* Map from service/endpoint to Copy Engine. 1392967c1d11SAnilkumar Kolli * This table is derived from the CE_PCI TABLE, above. 1393967c1d11SAnilkumar Kolli * It is passed to the Target at startup for use by firmware. 1394967c1d11SAnilkumar Kolli */ 1395967c1d11SAnilkumar Kolli const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq8074[] = { 1396967c1d11SAnilkumar Kolli { 1397967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1398967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1399967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(3), 1400967c1d11SAnilkumar Kolli }, 1401967c1d11SAnilkumar Kolli { 1402967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1403967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1404967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(2), 1405967c1d11SAnilkumar Kolli }, 1406967c1d11SAnilkumar Kolli { 1407967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1408967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1409967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(3), 1410967c1d11SAnilkumar Kolli }, 1411967c1d11SAnilkumar Kolli { 1412967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1413967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1414967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(2), 1415967c1d11SAnilkumar Kolli }, 1416967c1d11SAnilkumar Kolli { 1417967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1418967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1419967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(3), 1420967c1d11SAnilkumar Kolli }, 1421967c1d11SAnilkumar Kolli { 1422967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1423967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1424967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(2), 1425967c1d11SAnilkumar Kolli }, 1426967c1d11SAnilkumar Kolli { 1427967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1428967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1429967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(3), 1430967c1d11SAnilkumar Kolli }, 1431967c1d11SAnilkumar Kolli { 1432967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1433967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1434967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(2), 1435967c1d11SAnilkumar Kolli }, 1436967c1d11SAnilkumar Kolli { 1437967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1438967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1439967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(3), 1440967c1d11SAnilkumar Kolli }, 1441967c1d11SAnilkumar Kolli { 1442967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1443967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1444967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(2), 1445967c1d11SAnilkumar Kolli }, 1446967c1d11SAnilkumar Kolli { 1447967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 1448967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1449967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(7), 1450967c1d11SAnilkumar Kolli }, 1451967c1d11SAnilkumar Kolli { 1452967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 1453967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1454967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(2), 1455967c1d11SAnilkumar Kolli }, 1456967c1d11SAnilkumar Kolli { 1457967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC2), 1458967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1459967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(9), 1460967c1d11SAnilkumar Kolli }, 1461967c1d11SAnilkumar Kolli { 1462967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC2), 1463967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1464967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(2), 1465967c1d11SAnilkumar Kolli }, 1466967c1d11SAnilkumar Kolli { 1467967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1468967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1469967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(0), 1470967c1d11SAnilkumar Kolli }, 1471967c1d11SAnilkumar Kolli { 1472967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1473967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1474967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(1), 1475967c1d11SAnilkumar Kolli }, 1476967c1d11SAnilkumar Kolli { /* not used */ 1477967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1478967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1479967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(0), 1480967c1d11SAnilkumar Kolli }, 1481967c1d11SAnilkumar Kolli { /* not used */ 1482967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1483967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1484967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(1), 1485967c1d11SAnilkumar Kolli }, 1486967c1d11SAnilkumar Kolli { 1487967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1488967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1489967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(4), 1490967c1d11SAnilkumar Kolli }, 1491967c1d11SAnilkumar Kolli { 1492967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1493967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1494967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(1), 1495967c1d11SAnilkumar Kolli }, 1496967c1d11SAnilkumar Kolli { 1497967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG), 1498967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1499967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(5), 1500967c1d11SAnilkumar Kolli }, 1501967c1d11SAnilkumar Kolli 1502967c1d11SAnilkumar Kolli /* (Additions here) */ 1503967c1d11SAnilkumar Kolli 1504967c1d11SAnilkumar Kolli { /* terminator entry */ } 1505967c1d11SAnilkumar Kolli }; 1506967c1d11SAnilkumar Kolli 1507b129699aSAnilkumar Kolli const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq6018[] = { 1508b129699aSAnilkumar Kolli { 1509b129699aSAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1510b129699aSAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1511b129699aSAnilkumar Kolli .pipenum = __cpu_to_le32(3), 1512b129699aSAnilkumar Kolli }, 1513b129699aSAnilkumar Kolli { 1514b129699aSAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1515b129699aSAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1516b129699aSAnilkumar Kolli .pipenum = __cpu_to_le32(2), 1517b129699aSAnilkumar Kolli }, 1518b129699aSAnilkumar Kolli { 1519b129699aSAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1520b129699aSAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1521b129699aSAnilkumar Kolli .pipenum = __cpu_to_le32(3), 1522b129699aSAnilkumar Kolli }, 1523b129699aSAnilkumar Kolli { 1524b129699aSAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1525b129699aSAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1526b129699aSAnilkumar Kolli .pipenum = __cpu_to_le32(2), 1527b129699aSAnilkumar Kolli }, 1528b129699aSAnilkumar Kolli { 1529b129699aSAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1530b129699aSAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1531b129699aSAnilkumar Kolli .pipenum = __cpu_to_le32(3), 1532b129699aSAnilkumar Kolli }, 1533b129699aSAnilkumar Kolli { 1534b129699aSAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1535b129699aSAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1536b129699aSAnilkumar Kolli .pipenum = __cpu_to_le32(2), 1537b129699aSAnilkumar Kolli }, 1538b129699aSAnilkumar Kolli { 1539b129699aSAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1540b129699aSAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1541b129699aSAnilkumar Kolli .pipenum = __cpu_to_le32(3), 1542b129699aSAnilkumar Kolli }, 1543b129699aSAnilkumar Kolli { 1544b129699aSAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1545b129699aSAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1546b129699aSAnilkumar Kolli .pipenum = __cpu_to_le32(2), 1547b129699aSAnilkumar Kolli }, 1548b129699aSAnilkumar Kolli { 1549b129699aSAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1550b129699aSAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1551b129699aSAnilkumar Kolli .pipenum = __cpu_to_le32(3), 1552b129699aSAnilkumar Kolli }, 1553b129699aSAnilkumar Kolli { 1554b129699aSAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1555b129699aSAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1556b129699aSAnilkumar Kolli .pipenum = __cpu_to_le32(2), 1557b129699aSAnilkumar Kolli }, 1558b129699aSAnilkumar Kolli { 1559b129699aSAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 1560b129699aSAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1561b129699aSAnilkumar Kolli .pipenum = __cpu_to_le32(7), 1562b129699aSAnilkumar Kolli }, 1563b129699aSAnilkumar Kolli { 1564b129699aSAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 1565b129699aSAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1566b129699aSAnilkumar Kolli .pipenum = __cpu_to_le32(2), 1567b129699aSAnilkumar Kolli }, 1568b129699aSAnilkumar Kolli { 1569b129699aSAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1570b129699aSAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1571b129699aSAnilkumar Kolli .pipenum = __cpu_to_le32(0), 1572b129699aSAnilkumar Kolli }, 1573b129699aSAnilkumar Kolli { 1574b129699aSAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1575b129699aSAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1576b129699aSAnilkumar Kolli .pipenum = __cpu_to_le32(1), 1577b129699aSAnilkumar Kolli }, 1578b129699aSAnilkumar Kolli { /* not used */ 1579b129699aSAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1580b129699aSAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1581b129699aSAnilkumar Kolli .pipenum = __cpu_to_le32(0), 1582b129699aSAnilkumar Kolli }, 1583b129699aSAnilkumar Kolli { /* not used */ 1584b129699aSAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1585b129699aSAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1586b129699aSAnilkumar Kolli .pipenum = __cpu_to_le32(1), 1587b129699aSAnilkumar Kolli }, 1588b129699aSAnilkumar Kolli { 1589b129699aSAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1590b129699aSAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1591b129699aSAnilkumar Kolli .pipenum = __cpu_to_le32(4), 1592b129699aSAnilkumar Kolli }, 1593b129699aSAnilkumar Kolli { 1594b129699aSAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1595b129699aSAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1596b129699aSAnilkumar Kolli .pipenum = __cpu_to_le32(1), 1597b129699aSAnilkumar Kolli }, 1598b129699aSAnilkumar Kolli { 1599b129699aSAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG), 1600b129699aSAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1601b129699aSAnilkumar Kolli .pipenum = __cpu_to_le32(5), 1602b129699aSAnilkumar Kolli }, 1603b129699aSAnilkumar Kolli 1604b129699aSAnilkumar Kolli /* (Additions here) */ 1605b129699aSAnilkumar Kolli 1606b129699aSAnilkumar Kolli { /* terminator entry */ } 1607b129699aSAnilkumar Kolli }; 1608b129699aSAnilkumar Kolli 1609967c1d11SAnilkumar Kolli /* Target firmware's Copy Engine configuration. */ 1610967c1d11SAnilkumar Kolli const struct ce_pipe_config ath11k_target_ce_config_wlan_qca6390[] = { 1611967c1d11SAnilkumar Kolli /* CE0: host->target HTC control and raw streams */ 1612967c1d11SAnilkumar Kolli { 1613967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(0), 1614967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1615967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(32), 1616967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(2048), 1617967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1618967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 1619967c1d11SAnilkumar Kolli }, 1620967c1d11SAnilkumar Kolli 1621967c1d11SAnilkumar Kolli /* CE1: target->host HTT + HTC control */ 1622967c1d11SAnilkumar Kolli { 1623967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(1), 1624967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), 1625967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(32), 1626967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(2048), 1627967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1628967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 1629967c1d11SAnilkumar Kolli }, 1630967c1d11SAnilkumar Kolli 1631967c1d11SAnilkumar Kolli /* CE2: target->host WMI */ 1632967c1d11SAnilkumar Kolli { 1633967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(2), 1634967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), 1635967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(32), 1636967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(2048), 1637967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1638967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 1639967c1d11SAnilkumar Kolli }, 1640967c1d11SAnilkumar Kolli 1641967c1d11SAnilkumar Kolli /* CE3: host->target WMI */ 1642967c1d11SAnilkumar Kolli { 1643967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(3), 1644967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1645967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(32), 1646967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(2048), 1647967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1648967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 1649967c1d11SAnilkumar Kolli }, 1650967c1d11SAnilkumar Kolli 1651967c1d11SAnilkumar Kolli /* CE4: host->target HTT */ 1652967c1d11SAnilkumar Kolli { 1653967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(4), 1654967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1655967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(256), 1656967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(256), 1657967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1658967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 1659967c1d11SAnilkumar Kolli }, 1660967c1d11SAnilkumar Kolli 1661967c1d11SAnilkumar Kolli /* CE5: target->host Pktlog */ 1662967c1d11SAnilkumar Kolli { 1663967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(5), 1664967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), 1665967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(32), 1666967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(2048), 1667967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1668967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 1669967c1d11SAnilkumar Kolli }, 1670967c1d11SAnilkumar Kolli 1671967c1d11SAnilkumar Kolli /* CE6: Reserved for target autonomous hif_memcpy */ 1672967c1d11SAnilkumar Kolli { 1673967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(6), 1674967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1675967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(32), 1676967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(16384), 1677967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1678967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 1679967c1d11SAnilkumar Kolli }, 1680967c1d11SAnilkumar Kolli 1681967c1d11SAnilkumar Kolli /* CE7 used only by Host */ 1682967c1d11SAnilkumar Kolli { 1683967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(7), 1684967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H), 1685967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(0), 1686967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(0), 1687967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1688967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 1689967c1d11SAnilkumar Kolli }, 1690967c1d11SAnilkumar Kolli 1691967c1d11SAnilkumar Kolli /* CE8 target->host used only by IPA */ 1692967c1d11SAnilkumar Kolli { 1693967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(8), 1694967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1695967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(32), 1696967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(16384), 1697967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1698967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 1699967c1d11SAnilkumar Kolli }, 1700967c1d11SAnilkumar Kolli /* CE 9, 10, 11 are used by MHI driver */ 1701967c1d11SAnilkumar Kolli }; 1702967c1d11SAnilkumar Kolli 1703967c1d11SAnilkumar Kolli /* Map from service/endpoint to Copy Engine. 1704967c1d11SAnilkumar Kolli * This table is derived from the CE_PCI TABLE, above. 1705967c1d11SAnilkumar Kolli * It is passed to the Target at startup for use by firmware. 1706967c1d11SAnilkumar Kolli */ 1707967c1d11SAnilkumar Kolli const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qca6390[] = { 1708967c1d11SAnilkumar Kolli { 1709967c1d11SAnilkumar Kolli __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1710967c1d11SAnilkumar Kolli __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1711967c1d11SAnilkumar Kolli __cpu_to_le32(3), 1712967c1d11SAnilkumar Kolli }, 1713967c1d11SAnilkumar Kolli { 1714967c1d11SAnilkumar Kolli __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1715967c1d11SAnilkumar Kolli __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1716967c1d11SAnilkumar Kolli __cpu_to_le32(2), 1717967c1d11SAnilkumar Kolli }, 1718967c1d11SAnilkumar Kolli { 1719967c1d11SAnilkumar Kolli __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1720967c1d11SAnilkumar Kolli __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1721967c1d11SAnilkumar Kolli __cpu_to_le32(3), 1722967c1d11SAnilkumar Kolli }, 1723967c1d11SAnilkumar Kolli { 1724967c1d11SAnilkumar Kolli __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1725967c1d11SAnilkumar Kolli __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1726967c1d11SAnilkumar Kolli __cpu_to_le32(2), 1727967c1d11SAnilkumar Kolli }, 1728967c1d11SAnilkumar Kolli { 1729967c1d11SAnilkumar Kolli __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1730967c1d11SAnilkumar Kolli __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1731967c1d11SAnilkumar Kolli __cpu_to_le32(3), 1732967c1d11SAnilkumar Kolli }, 1733967c1d11SAnilkumar Kolli { 1734967c1d11SAnilkumar Kolli __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1735967c1d11SAnilkumar Kolli __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1736967c1d11SAnilkumar Kolli __cpu_to_le32(2), 1737967c1d11SAnilkumar Kolli }, 1738967c1d11SAnilkumar Kolli { 1739967c1d11SAnilkumar Kolli __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1740967c1d11SAnilkumar Kolli __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1741967c1d11SAnilkumar Kolli __cpu_to_le32(3), 1742967c1d11SAnilkumar Kolli }, 1743967c1d11SAnilkumar Kolli { 1744967c1d11SAnilkumar Kolli __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1745967c1d11SAnilkumar Kolli __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1746967c1d11SAnilkumar Kolli __cpu_to_le32(2), 1747967c1d11SAnilkumar Kolli }, 1748967c1d11SAnilkumar Kolli { 1749967c1d11SAnilkumar Kolli __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1750967c1d11SAnilkumar Kolli __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1751967c1d11SAnilkumar Kolli __cpu_to_le32(3), 1752967c1d11SAnilkumar Kolli }, 1753967c1d11SAnilkumar Kolli { 1754967c1d11SAnilkumar Kolli __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1755967c1d11SAnilkumar Kolli __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1756967c1d11SAnilkumar Kolli __cpu_to_le32(2), 1757967c1d11SAnilkumar Kolli }, 1758967c1d11SAnilkumar Kolli { 1759967c1d11SAnilkumar Kolli __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1760967c1d11SAnilkumar Kolli __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1761967c1d11SAnilkumar Kolli __cpu_to_le32(0), 1762967c1d11SAnilkumar Kolli }, 1763967c1d11SAnilkumar Kolli { 1764967c1d11SAnilkumar Kolli __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1765967c1d11SAnilkumar Kolli __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1766967c1d11SAnilkumar Kolli __cpu_to_le32(2), 1767967c1d11SAnilkumar Kolli }, 1768967c1d11SAnilkumar Kolli { 1769967c1d11SAnilkumar Kolli __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1770967c1d11SAnilkumar Kolli __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1771967c1d11SAnilkumar Kolli __cpu_to_le32(4), 1772967c1d11SAnilkumar Kolli }, 1773967c1d11SAnilkumar Kolli { 1774967c1d11SAnilkumar Kolli __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1775967c1d11SAnilkumar Kolli __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1776967c1d11SAnilkumar Kolli __cpu_to_le32(1), 1777967c1d11SAnilkumar Kolli }, 1778967c1d11SAnilkumar Kolli 1779967c1d11SAnilkumar Kolli /* (Additions here) */ 1780967c1d11SAnilkumar Kolli 1781967c1d11SAnilkumar Kolli { /* must be last */ 1782967c1d11SAnilkumar Kolli __cpu_to_le32(0), 1783967c1d11SAnilkumar Kolli __cpu_to_le32(0), 1784967c1d11SAnilkumar Kolli __cpu_to_le32(0), 1785967c1d11SAnilkumar Kolli }, 1786967c1d11SAnilkumar Kolli }; 1787967c1d11SAnilkumar Kolli 17886289ac2bSKarthikeyan Periyasamy /* Target firmware's Copy Engine configuration. */ 17896289ac2bSKarthikeyan Periyasamy const struct ce_pipe_config ath11k_target_ce_config_wlan_qcn9074[] = { 17906289ac2bSKarthikeyan Periyasamy /* CE0: host->target HTC control and raw streams */ 17916289ac2bSKarthikeyan Periyasamy { 17926289ac2bSKarthikeyan Periyasamy .pipenum = __cpu_to_le32(0), 17936289ac2bSKarthikeyan Periyasamy .pipedir = __cpu_to_le32(PIPEDIR_OUT), 17946289ac2bSKarthikeyan Periyasamy .nentries = __cpu_to_le32(32), 17956289ac2bSKarthikeyan Periyasamy .nbytes_max = __cpu_to_le32(2048), 17966289ac2bSKarthikeyan Periyasamy .flags = __cpu_to_le32(CE_ATTR_FLAGS), 17976289ac2bSKarthikeyan Periyasamy .reserved = __cpu_to_le32(0), 17986289ac2bSKarthikeyan Periyasamy }, 17996289ac2bSKarthikeyan Periyasamy 18006289ac2bSKarthikeyan Periyasamy /* CE1: target->host HTT + HTC control */ 18016289ac2bSKarthikeyan Periyasamy { 18026289ac2bSKarthikeyan Periyasamy .pipenum = __cpu_to_le32(1), 18036289ac2bSKarthikeyan Periyasamy .pipedir = __cpu_to_le32(PIPEDIR_IN), 18046289ac2bSKarthikeyan Periyasamy .nentries = __cpu_to_le32(32), 18056289ac2bSKarthikeyan Periyasamy .nbytes_max = __cpu_to_le32(2048), 18066289ac2bSKarthikeyan Periyasamy .flags = __cpu_to_le32(CE_ATTR_FLAGS), 18076289ac2bSKarthikeyan Periyasamy .reserved = __cpu_to_le32(0), 18086289ac2bSKarthikeyan Periyasamy }, 18096289ac2bSKarthikeyan Periyasamy 18106289ac2bSKarthikeyan Periyasamy /* CE2: target->host WMI */ 18116289ac2bSKarthikeyan Periyasamy { 18126289ac2bSKarthikeyan Periyasamy .pipenum = __cpu_to_le32(2), 18136289ac2bSKarthikeyan Periyasamy .pipedir = __cpu_to_le32(PIPEDIR_IN), 18146289ac2bSKarthikeyan Periyasamy .nentries = __cpu_to_le32(32), 18156289ac2bSKarthikeyan Periyasamy .nbytes_max = __cpu_to_le32(2048), 18166289ac2bSKarthikeyan Periyasamy .flags = __cpu_to_le32(CE_ATTR_FLAGS), 18176289ac2bSKarthikeyan Periyasamy .reserved = __cpu_to_le32(0), 18186289ac2bSKarthikeyan Periyasamy }, 18196289ac2bSKarthikeyan Periyasamy 18206289ac2bSKarthikeyan Periyasamy /* CE3: host->target WMI */ 18216289ac2bSKarthikeyan Periyasamy { 18226289ac2bSKarthikeyan Periyasamy .pipenum = __cpu_to_le32(3), 18236289ac2bSKarthikeyan Periyasamy .pipedir = __cpu_to_le32(PIPEDIR_OUT), 18246289ac2bSKarthikeyan Periyasamy .nentries = __cpu_to_le32(32), 18256289ac2bSKarthikeyan Periyasamy .nbytes_max = __cpu_to_le32(2048), 18266289ac2bSKarthikeyan Periyasamy .flags = __cpu_to_le32(CE_ATTR_FLAGS), 18276289ac2bSKarthikeyan Periyasamy .reserved = __cpu_to_le32(0), 18286289ac2bSKarthikeyan Periyasamy }, 18296289ac2bSKarthikeyan Periyasamy 18306289ac2bSKarthikeyan Periyasamy /* CE4: host->target HTT */ 18316289ac2bSKarthikeyan Periyasamy { 18326289ac2bSKarthikeyan Periyasamy .pipenum = __cpu_to_le32(4), 18336289ac2bSKarthikeyan Periyasamy .pipedir = __cpu_to_le32(PIPEDIR_OUT), 18346289ac2bSKarthikeyan Periyasamy .nentries = __cpu_to_le32(256), 18356289ac2bSKarthikeyan Periyasamy .nbytes_max = __cpu_to_le32(256), 18366289ac2bSKarthikeyan Periyasamy .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 18376289ac2bSKarthikeyan Periyasamy .reserved = __cpu_to_le32(0), 18386289ac2bSKarthikeyan Periyasamy }, 18396289ac2bSKarthikeyan Periyasamy 18406289ac2bSKarthikeyan Periyasamy /* CE5: target->host Pktlog */ 18416289ac2bSKarthikeyan Periyasamy { 18426289ac2bSKarthikeyan Periyasamy .pipenum = __cpu_to_le32(5), 18436289ac2bSKarthikeyan Periyasamy .pipedir = __cpu_to_le32(PIPEDIR_IN), 18446289ac2bSKarthikeyan Periyasamy .nentries = __cpu_to_le32(32), 18456289ac2bSKarthikeyan Periyasamy .nbytes_max = __cpu_to_le32(2048), 18466289ac2bSKarthikeyan Periyasamy .flags = __cpu_to_le32(CE_ATTR_FLAGS), 18476289ac2bSKarthikeyan Periyasamy .reserved = __cpu_to_le32(0), 18486289ac2bSKarthikeyan Periyasamy }, 18496289ac2bSKarthikeyan Periyasamy 18506289ac2bSKarthikeyan Periyasamy /* CE6: Reserved for target autonomous hif_memcpy */ 18516289ac2bSKarthikeyan Periyasamy { 18526289ac2bSKarthikeyan Periyasamy .pipenum = __cpu_to_le32(6), 18536289ac2bSKarthikeyan Periyasamy .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 18546289ac2bSKarthikeyan Periyasamy .nentries = __cpu_to_le32(32), 18556289ac2bSKarthikeyan Periyasamy .nbytes_max = __cpu_to_le32(16384), 18566289ac2bSKarthikeyan Periyasamy .flags = __cpu_to_le32(CE_ATTR_FLAGS), 18576289ac2bSKarthikeyan Periyasamy .reserved = __cpu_to_le32(0), 18586289ac2bSKarthikeyan Periyasamy }, 18596289ac2bSKarthikeyan Periyasamy 18606289ac2bSKarthikeyan Periyasamy /* CE7 used only by Host */ 18616289ac2bSKarthikeyan Periyasamy { 18626289ac2bSKarthikeyan Periyasamy .pipenum = __cpu_to_le32(7), 18636289ac2bSKarthikeyan Periyasamy .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H), 18646289ac2bSKarthikeyan Periyasamy .nentries = __cpu_to_le32(0), 18656289ac2bSKarthikeyan Periyasamy .nbytes_max = __cpu_to_le32(0), 18666289ac2bSKarthikeyan Periyasamy .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 18676289ac2bSKarthikeyan Periyasamy .reserved = __cpu_to_le32(0), 18686289ac2bSKarthikeyan Periyasamy }, 18696289ac2bSKarthikeyan Periyasamy 18706289ac2bSKarthikeyan Periyasamy /* CE8 target->host used only by IPA */ 18716289ac2bSKarthikeyan Periyasamy { 18726289ac2bSKarthikeyan Periyasamy .pipenum = __cpu_to_le32(8), 18736289ac2bSKarthikeyan Periyasamy .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 18746289ac2bSKarthikeyan Periyasamy .nentries = __cpu_to_le32(32), 18756289ac2bSKarthikeyan Periyasamy .nbytes_max = __cpu_to_le32(16384), 18766289ac2bSKarthikeyan Periyasamy .flags = __cpu_to_le32(CE_ATTR_FLAGS), 18776289ac2bSKarthikeyan Periyasamy .reserved = __cpu_to_le32(0), 18786289ac2bSKarthikeyan Periyasamy }, 18796289ac2bSKarthikeyan Periyasamy /* CE 9, 10, 11 are used by MHI driver */ 18806289ac2bSKarthikeyan Periyasamy }; 18816289ac2bSKarthikeyan Periyasamy 18826289ac2bSKarthikeyan Periyasamy /* Map from service/endpoint to Copy Engine. 18836289ac2bSKarthikeyan Periyasamy * This table is derived from the CE_PCI TABLE, above. 18846289ac2bSKarthikeyan Periyasamy * It is passed to the Target at startup for use by firmware. 18856289ac2bSKarthikeyan Periyasamy */ 18866289ac2bSKarthikeyan Periyasamy const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qcn9074[] = { 18876289ac2bSKarthikeyan Periyasamy { 18886289ac2bSKarthikeyan Periyasamy __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 18896289ac2bSKarthikeyan Periyasamy __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 18906289ac2bSKarthikeyan Periyasamy __cpu_to_le32(3), 18916289ac2bSKarthikeyan Periyasamy }, 18926289ac2bSKarthikeyan Periyasamy { 18936289ac2bSKarthikeyan Periyasamy __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 18946289ac2bSKarthikeyan Periyasamy __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 18956289ac2bSKarthikeyan Periyasamy __cpu_to_le32(2), 18966289ac2bSKarthikeyan Periyasamy }, 18976289ac2bSKarthikeyan Periyasamy { 18986289ac2bSKarthikeyan Periyasamy __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 18996289ac2bSKarthikeyan Periyasamy __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 19006289ac2bSKarthikeyan Periyasamy __cpu_to_le32(3), 19016289ac2bSKarthikeyan Periyasamy }, 19026289ac2bSKarthikeyan Periyasamy { 19036289ac2bSKarthikeyan Periyasamy __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 19046289ac2bSKarthikeyan Periyasamy __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 19056289ac2bSKarthikeyan Periyasamy __cpu_to_le32(2), 19066289ac2bSKarthikeyan Periyasamy }, 19076289ac2bSKarthikeyan Periyasamy { 19086289ac2bSKarthikeyan Periyasamy __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 19096289ac2bSKarthikeyan Periyasamy __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 19106289ac2bSKarthikeyan Periyasamy __cpu_to_le32(3), 19116289ac2bSKarthikeyan Periyasamy }, 19126289ac2bSKarthikeyan Periyasamy { 19136289ac2bSKarthikeyan Periyasamy __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 19146289ac2bSKarthikeyan Periyasamy __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 19156289ac2bSKarthikeyan Periyasamy __cpu_to_le32(2), 19166289ac2bSKarthikeyan Periyasamy }, 19176289ac2bSKarthikeyan Periyasamy { 19186289ac2bSKarthikeyan Periyasamy __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 19196289ac2bSKarthikeyan Periyasamy __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 19206289ac2bSKarthikeyan Periyasamy __cpu_to_le32(3), 19216289ac2bSKarthikeyan Periyasamy }, 19226289ac2bSKarthikeyan Periyasamy { 19236289ac2bSKarthikeyan Periyasamy __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 19246289ac2bSKarthikeyan Periyasamy __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 19256289ac2bSKarthikeyan Periyasamy __cpu_to_le32(2), 19266289ac2bSKarthikeyan Periyasamy }, 19276289ac2bSKarthikeyan Periyasamy { 19286289ac2bSKarthikeyan Periyasamy __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 19296289ac2bSKarthikeyan Periyasamy __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 19306289ac2bSKarthikeyan Periyasamy __cpu_to_le32(3), 19316289ac2bSKarthikeyan Periyasamy }, 19326289ac2bSKarthikeyan Periyasamy { 19336289ac2bSKarthikeyan Periyasamy __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 19346289ac2bSKarthikeyan Periyasamy __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 19356289ac2bSKarthikeyan Periyasamy __cpu_to_le32(2), 19366289ac2bSKarthikeyan Periyasamy }, 19376289ac2bSKarthikeyan Periyasamy { 19386289ac2bSKarthikeyan Periyasamy __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 19396289ac2bSKarthikeyan Periyasamy __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 19406289ac2bSKarthikeyan Periyasamy __cpu_to_le32(0), 19416289ac2bSKarthikeyan Periyasamy }, 19426289ac2bSKarthikeyan Periyasamy { 19436289ac2bSKarthikeyan Periyasamy __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 19446289ac2bSKarthikeyan Periyasamy __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 19456289ac2bSKarthikeyan Periyasamy __cpu_to_le32(1), 19466289ac2bSKarthikeyan Periyasamy }, 19476289ac2bSKarthikeyan Periyasamy { 19486289ac2bSKarthikeyan Periyasamy __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 19496289ac2bSKarthikeyan Periyasamy __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 19506289ac2bSKarthikeyan Periyasamy __cpu_to_le32(0), 19516289ac2bSKarthikeyan Periyasamy }, 19526289ac2bSKarthikeyan Periyasamy { 19536289ac2bSKarthikeyan Periyasamy __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 19546289ac2bSKarthikeyan Periyasamy __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 19556289ac2bSKarthikeyan Periyasamy __cpu_to_le32(1), 19566289ac2bSKarthikeyan Periyasamy }, 19576289ac2bSKarthikeyan Periyasamy { 19586289ac2bSKarthikeyan Periyasamy __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 19596289ac2bSKarthikeyan Periyasamy __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 19606289ac2bSKarthikeyan Periyasamy __cpu_to_le32(4), 19616289ac2bSKarthikeyan Periyasamy }, 19626289ac2bSKarthikeyan Periyasamy { 19636289ac2bSKarthikeyan Periyasamy __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 19646289ac2bSKarthikeyan Periyasamy __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 19656289ac2bSKarthikeyan Periyasamy __cpu_to_le32(1), 19666289ac2bSKarthikeyan Periyasamy }, 19676289ac2bSKarthikeyan Periyasamy { 19686289ac2bSKarthikeyan Periyasamy __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG), 19696289ac2bSKarthikeyan Periyasamy __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 19706289ac2bSKarthikeyan Periyasamy __cpu_to_le32(5), 19716289ac2bSKarthikeyan Periyasamy }, 19726289ac2bSKarthikeyan Periyasamy 19736289ac2bSKarthikeyan Periyasamy /* (Additions here) */ 19746289ac2bSKarthikeyan Periyasamy 19756289ac2bSKarthikeyan Periyasamy { /* must be last */ 19766289ac2bSKarthikeyan Periyasamy __cpu_to_le32(0), 19776289ac2bSKarthikeyan Periyasamy __cpu_to_le32(0), 19786289ac2bSKarthikeyan Periyasamy __cpu_to_le32(0), 19796289ac2bSKarthikeyan Periyasamy }, 19806289ac2bSKarthikeyan Periyasamy }; 19816289ac2bSKarthikeyan Periyasamy 19827dc67af0SKarthikeyan Periyasamy const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qcn9074 = { 19837dc67af0SKarthikeyan Periyasamy .tx = { 19847dc67af0SKarthikeyan Periyasamy ATH11K_TX_RING_MASK_0, 19857dc67af0SKarthikeyan Periyasamy ATH11K_TX_RING_MASK_1, 19867dc67af0SKarthikeyan Periyasamy ATH11K_TX_RING_MASK_2, 19877dc67af0SKarthikeyan Periyasamy }, 19887dc67af0SKarthikeyan Periyasamy .rx_mon_status = { 19897dc67af0SKarthikeyan Periyasamy 0, 0, 0, 19907dc67af0SKarthikeyan Periyasamy ATH11K_RX_MON_STATUS_RING_MASK_0, 19917dc67af0SKarthikeyan Periyasamy ATH11K_RX_MON_STATUS_RING_MASK_1, 19927dc67af0SKarthikeyan Periyasamy ATH11K_RX_MON_STATUS_RING_MASK_2, 19937dc67af0SKarthikeyan Periyasamy }, 19947dc67af0SKarthikeyan Periyasamy .rx = { 19957dc67af0SKarthikeyan Periyasamy 0, 0, 0, 0, 19967dc67af0SKarthikeyan Periyasamy ATH11K_RX_RING_MASK_0, 19977dc67af0SKarthikeyan Periyasamy ATH11K_RX_RING_MASK_1, 19987dc67af0SKarthikeyan Periyasamy ATH11K_RX_RING_MASK_2, 19997dc67af0SKarthikeyan Periyasamy ATH11K_RX_RING_MASK_3, 20007dc67af0SKarthikeyan Periyasamy }, 20017dc67af0SKarthikeyan Periyasamy .rx_err = { 20027dc67af0SKarthikeyan Periyasamy 0, 0, 0, 20037dc67af0SKarthikeyan Periyasamy ATH11K_RX_ERR_RING_MASK_0, 20047dc67af0SKarthikeyan Periyasamy }, 20057dc67af0SKarthikeyan Periyasamy .rx_wbm_rel = { 20067dc67af0SKarthikeyan Periyasamy 0, 0, 0, 20077dc67af0SKarthikeyan Periyasamy ATH11K_RX_WBM_REL_RING_MASK_0, 20087dc67af0SKarthikeyan Periyasamy }, 20097dc67af0SKarthikeyan Periyasamy .reo_status = { 20107dc67af0SKarthikeyan Periyasamy 0, 0, 0, 20117dc67af0SKarthikeyan Periyasamy ATH11K_REO_STATUS_RING_MASK_0, 20127dc67af0SKarthikeyan Periyasamy }, 20137dc67af0SKarthikeyan Periyasamy .rxdma2host = { 20147dc67af0SKarthikeyan Periyasamy 0, 0, 0, 20157dc67af0SKarthikeyan Periyasamy ATH11K_RXDMA2HOST_RING_MASK_0, 20167dc67af0SKarthikeyan Periyasamy }, 20177dc67af0SKarthikeyan Periyasamy .host2rxdma = { 20187dc67af0SKarthikeyan Periyasamy 0, 0, 0, 20197dc67af0SKarthikeyan Periyasamy ATH11K_HOST2RXDMA_RING_MASK_0, 20207dc67af0SKarthikeyan Periyasamy }, 20217dc67af0SKarthikeyan Periyasamy }; 20227dc67af0SKarthikeyan Periyasamy 20237636c9a6SManikanta Pubbisetty const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_wcn6750 = { 20247636c9a6SManikanta Pubbisetty .tx = { 20257636c9a6SManikanta Pubbisetty ATH11K_TX_RING_MASK_0, 20267636c9a6SManikanta Pubbisetty 0, 20277636c9a6SManikanta Pubbisetty ATH11K_TX_RING_MASK_2, 20287636c9a6SManikanta Pubbisetty 0, 20297636c9a6SManikanta Pubbisetty ATH11K_TX_RING_MASK_4, 20307636c9a6SManikanta Pubbisetty }, 20317636c9a6SManikanta Pubbisetty .rx_mon_status = { 20327636c9a6SManikanta Pubbisetty 0, 0, 0, 0, 0, 0, 20337636c9a6SManikanta Pubbisetty ATH11K_RX_MON_STATUS_RING_MASK_0, 20347636c9a6SManikanta Pubbisetty }, 20357636c9a6SManikanta Pubbisetty .rx = { 20367636c9a6SManikanta Pubbisetty 0, 0, 0, 0, 0, 0, 0, 20377636c9a6SManikanta Pubbisetty ATH11K_RX_RING_MASK_0, 20387636c9a6SManikanta Pubbisetty ATH11K_RX_RING_MASK_1, 20397636c9a6SManikanta Pubbisetty ATH11K_RX_RING_MASK_2, 20407636c9a6SManikanta Pubbisetty ATH11K_RX_RING_MASK_3, 20417636c9a6SManikanta Pubbisetty }, 20427636c9a6SManikanta Pubbisetty .rx_err = { 20437636c9a6SManikanta Pubbisetty 0, ATH11K_RX_ERR_RING_MASK_0, 20447636c9a6SManikanta Pubbisetty }, 20457636c9a6SManikanta Pubbisetty .rx_wbm_rel = { 20467636c9a6SManikanta Pubbisetty 0, ATH11K_RX_WBM_REL_RING_MASK_0, 20477636c9a6SManikanta Pubbisetty }, 20487636c9a6SManikanta Pubbisetty .reo_status = { 20497636c9a6SManikanta Pubbisetty 0, ATH11K_REO_STATUS_RING_MASK_0, 20507636c9a6SManikanta Pubbisetty }, 20517636c9a6SManikanta Pubbisetty .rxdma2host = { 20527636c9a6SManikanta Pubbisetty ATH11K_RXDMA2HOST_RING_MASK_0, 20537636c9a6SManikanta Pubbisetty ATH11K_RXDMA2HOST_RING_MASK_1, 20547636c9a6SManikanta Pubbisetty ATH11K_RXDMA2HOST_RING_MASK_2, 20557636c9a6SManikanta Pubbisetty }, 20567636c9a6SManikanta Pubbisetty .host2rxdma = { 20577636c9a6SManikanta Pubbisetty }, 20587636c9a6SManikanta Pubbisetty }; 20597636c9a6SManikanta Pubbisetty 206026af7aabSSriram R /* Target firmware's Copy Engine configuration for IPQ5018 */ 206126af7aabSSriram R const struct ce_pipe_config ath11k_target_ce_config_wlan_ipq5018[] = { 206226af7aabSSriram R /* CE0: host->target HTC control and raw streams */ 206326af7aabSSriram R { 206426af7aabSSriram R .pipenum = __cpu_to_le32(0), 206526af7aabSSriram R .pipedir = __cpu_to_le32(PIPEDIR_OUT), 206626af7aabSSriram R .nentries = __cpu_to_le32(32), 206726af7aabSSriram R .nbytes_max = __cpu_to_le32(2048), 206826af7aabSSriram R .flags = __cpu_to_le32(CE_ATTR_FLAGS), 206926af7aabSSriram R .reserved = __cpu_to_le32(0), 207026af7aabSSriram R }, 207126af7aabSSriram R 207226af7aabSSriram R /* CE1: target->host HTT + HTC control */ 207326af7aabSSriram R { 207426af7aabSSriram R .pipenum = __cpu_to_le32(1), 207526af7aabSSriram R .pipedir = __cpu_to_le32(PIPEDIR_IN), 207626af7aabSSriram R .nentries = __cpu_to_le32(32), 207726af7aabSSriram R .nbytes_max = __cpu_to_le32(2048), 207826af7aabSSriram R .flags = __cpu_to_le32(CE_ATTR_FLAGS), 207926af7aabSSriram R .reserved = __cpu_to_le32(0), 208026af7aabSSriram R }, 208126af7aabSSriram R 208226af7aabSSriram R /* CE2: target->host WMI */ 208326af7aabSSriram R { 208426af7aabSSriram R .pipenum = __cpu_to_le32(2), 208526af7aabSSriram R .pipedir = __cpu_to_le32(PIPEDIR_IN), 208626af7aabSSriram R .nentries = __cpu_to_le32(32), 208726af7aabSSriram R .nbytes_max = __cpu_to_le32(2048), 208826af7aabSSriram R .flags = __cpu_to_le32(CE_ATTR_FLAGS), 208926af7aabSSriram R .reserved = __cpu_to_le32(0), 209026af7aabSSriram R }, 209126af7aabSSriram R 209226af7aabSSriram R /* CE3: host->target WMI */ 209326af7aabSSriram R { 209426af7aabSSriram R .pipenum = __cpu_to_le32(3), 209526af7aabSSriram R .pipedir = __cpu_to_le32(PIPEDIR_OUT), 209626af7aabSSriram R .nentries = __cpu_to_le32(32), 209726af7aabSSriram R .nbytes_max = __cpu_to_le32(2048), 209826af7aabSSriram R .flags = __cpu_to_le32(CE_ATTR_FLAGS), 209926af7aabSSriram R .reserved = __cpu_to_le32(0), 210026af7aabSSriram R }, 210126af7aabSSriram R 210226af7aabSSriram R /* CE4: host->target HTT */ 210326af7aabSSriram R { 210426af7aabSSriram R .pipenum = __cpu_to_le32(4), 210526af7aabSSriram R .pipedir = __cpu_to_le32(PIPEDIR_OUT), 210626af7aabSSriram R .nentries = __cpu_to_le32(256), 210726af7aabSSriram R .nbytes_max = __cpu_to_le32(256), 210826af7aabSSriram R .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 210926af7aabSSriram R .reserved = __cpu_to_le32(0), 211026af7aabSSriram R }, 211126af7aabSSriram R 211226af7aabSSriram R /* CE5: target->host Pktlog */ 211326af7aabSSriram R { 211426af7aabSSriram R .pipenum = __cpu_to_le32(5), 211526af7aabSSriram R .pipedir = __cpu_to_le32(PIPEDIR_IN), 211626af7aabSSriram R .nentries = __cpu_to_le32(32), 211726af7aabSSriram R .nbytes_max = __cpu_to_le32(2048), 211826af7aabSSriram R .flags = __cpu_to_le32(CE_ATTR_FLAGS), 211926af7aabSSriram R .reserved = __cpu_to_le32(0), 212026af7aabSSriram R }, 212126af7aabSSriram R 212226af7aabSSriram R /* CE6: Reserved for target autonomous hif_memcpy */ 212326af7aabSSriram R { 212426af7aabSSriram R .pipenum = __cpu_to_le32(6), 212526af7aabSSriram R .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 212626af7aabSSriram R .nentries = __cpu_to_le32(32), 212726af7aabSSriram R .nbytes_max = __cpu_to_le32(16384), 212826af7aabSSriram R .flags = __cpu_to_le32(CE_ATTR_FLAGS), 212926af7aabSSriram R .reserved = __cpu_to_le32(0), 213026af7aabSSriram R }, 213126af7aabSSriram R 213226af7aabSSriram R /* CE7 used only by Host */ 213326af7aabSSriram R { 213426af7aabSSriram R .pipenum = __cpu_to_le32(7), 213526af7aabSSriram R .pipedir = __cpu_to_le32(PIPEDIR_OUT), 213626af7aabSSriram R .nentries = __cpu_to_le32(32), 213726af7aabSSriram R .nbytes_max = __cpu_to_le32(2048), 213826af7aabSSriram R .flags = __cpu_to_le32(0x2000), 213926af7aabSSriram R .reserved = __cpu_to_le32(0), 214026af7aabSSriram R }, 214126af7aabSSriram R 214226af7aabSSriram R /* CE8 target->host used only by IPA */ 214326af7aabSSriram R { 214426af7aabSSriram R .pipenum = __cpu_to_le32(8), 214526af7aabSSriram R .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 214626af7aabSSriram R .nentries = __cpu_to_le32(32), 214726af7aabSSriram R .nbytes_max = __cpu_to_le32(16384), 214826af7aabSSriram R .flags = __cpu_to_le32(CE_ATTR_FLAGS), 214926af7aabSSriram R .reserved = __cpu_to_le32(0), 215026af7aabSSriram R }, 215126af7aabSSriram R }; 215226af7aabSSriram R 215326af7aabSSriram R /* Map from service/endpoint to Copy Engine for IPQ5018. 215426af7aabSSriram R * This table is derived from the CE TABLE, above. 215526af7aabSSriram R * It is passed to the Target at startup for use by firmware. 215626af7aabSSriram R */ 215726af7aabSSriram R const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq5018[] = { 215826af7aabSSriram R { 215926af7aabSSriram R .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 216026af7aabSSriram R .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 216126af7aabSSriram R .pipenum = __cpu_to_le32(3), 216226af7aabSSriram R }, 216326af7aabSSriram R { 216426af7aabSSriram R .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 216526af7aabSSriram R .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 216626af7aabSSriram R .pipenum = __cpu_to_le32(2), 216726af7aabSSriram R }, 216826af7aabSSriram R { 216926af7aabSSriram R .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 217026af7aabSSriram R .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 217126af7aabSSriram R .pipenum = __cpu_to_le32(3), 217226af7aabSSriram R }, 217326af7aabSSriram R { 217426af7aabSSriram R .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 217526af7aabSSriram R .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 217626af7aabSSriram R .pipenum = __cpu_to_le32(2), 217726af7aabSSriram R }, 217826af7aabSSriram R { 217926af7aabSSriram R .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 218026af7aabSSriram R .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 218126af7aabSSriram R .pipenum = __cpu_to_le32(3), 218226af7aabSSriram R }, 218326af7aabSSriram R { 218426af7aabSSriram R .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 218526af7aabSSriram R .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 218626af7aabSSriram R .pipenum = __cpu_to_le32(2), 218726af7aabSSriram R }, 218826af7aabSSriram R { 218926af7aabSSriram R .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 219026af7aabSSriram R .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 219126af7aabSSriram R .pipenum = __cpu_to_le32(3), 219226af7aabSSriram R }, 219326af7aabSSriram R { 219426af7aabSSriram R .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 219526af7aabSSriram R .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 219626af7aabSSriram R .pipenum = __cpu_to_le32(2), 219726af7aabSSriram R }, 219826af7aabSSriram R { 219926af7aabSSriram R .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 220026af7aabSSriram R .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 220126af7aabSSriram R .pipenum = __cpu_to_le32(3), 220226af7aabSSriram R }, 220326af7aabSSriram R { 220426af7aabSSriram R .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 220526af7aabSSriram R .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 220626af7aabSSriram R .pipenum = __cpu_to_le32(2), 220726af7aabSSriram R }, 220826af7aabSSriram R 220926af7aabSSriram R { 221026af7aabSSriram R .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 221126af7aabSSriram R .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 221226af7aabSSriram R .pipenum = __cpu_to_le32(0), 221326af7aabSSriram R }, 221426af7aabSSriram R { 221526af7aabSSriram R .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 221626af7aabSSriram R .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 221726af7aabSSriram R .pipenum = __cpu_to_le32(1), 221826af7aabSSriram R }, 221926af7aabSSriram R 222026af7aabSSriram R { 222126af7aabSSriram R .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 222226af7aabSSriram R .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 222326af7aabSSriram R .pipenum = __cpu_to_le32(0), 222426af7aabSSriram R }, 222526af7aabSSriram R { 222626af7aabSSriram R .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 222726af7aabSSriram R .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 222826af7aabSSriram R .pipenum = __cpu_to_le32(1), 222926af7aabSSriram R }, 223026af7aabSSriram R { 223126af7aabSSriram R .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 223226af7aabSSriram R .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 223326af7aabSSriram R .pipenum = __cpu_to_le32(4), 223426af7aabSSriram R }, 223526af7aabSSriram R { 223626af7aabSSriram R .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 223726af7aabSSriram R .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 223826af7aabSSriram R .pipenum = __cpu_to_le32(1), 223926af7aabSSriram R }, 224026af7aabSSriram R { 224126af7aabSSriram R .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG), 224226af7aabSSriram R .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 224326af7aabSSriram R .pipenum = __cpu_to_le32(5), 224426af7aabSSriram R }, 224526af7aabSSriram R 224626af7aabSSriram R /* (Additions here) */ 224726af7aabSSriram R 224826af7aabSSriram R { /* terminator entry */ } 224926af7aabSSriram R }; 225026af7aabSSriram R 2251b42b3678SSriram R const struct ce_ie_addr ath11k_ce_ie_addr_ipq8074 = { 2252b42b3678SSriram R .ie1_reg_addr = CE_HOST_IE_ADDRESS, 2253b42b3678SSriram R .ie2_reg_addr = CE_HOST_IE_2_ADDRESS, 2254b42b3678SSriram R .ie3_reg_addr = CE_HOST_IE_3_ADDRESS, 2255b42b3678SSriram R }; 2256b42b3678SSriram R 2257b42b3678SSriram R const struct ce_ie_addr ath11k_ce_ie_addr_ipq5018 = { 2258b42b3678SSriram R .ie1_reg_addr = CE_HOST_IPQ5018_IE_ADDRESS - HAL_IPQ5018_CE_WFSS_REG_BASE, 2259b42b3678SSriram R .ie2_reg_addr = CE_HOST_IPQ5018_IE_2_ADDRESS - HAL_IPQ5018_CE_WFSS_REG_BASE, 2260b42b3678SSriram R .ie3_reg_addr = CE_HOST_IPQ5018_IE_3_ADDRESS - HAL_IPQ5018_CE_WFSS_REG_BASE, 2261b42b3678SSriram R }; 2262b42b3678SSriram R 2263b42b3678SSriram R const struct ce_remap ath11k_ce_remap_ipq5018 = { 2264b42b3678SSriram R .base = HAL_IPQ5018_CE_WFSS_REG_BASE, 2265b42b3678SSriram R .size = HAL_IPQ5018_CE_SIZE, 2266b42b3678SSriram R }; 2267b42b3678SSriram R 22686976433cSCarl Huang const struct ath11k_hw_regs ipq8074_regs = { 22696976433cSCarl Huang /* SW2TCL(x) R0 ring configuration address */ 22706976433cSCarl Huang .hal_tcl1_ring_base_lsb = 0x00000510, 22716976433cSCarl Huang .hal_tcl1_ring_base_msb = 0x00000514, 22726976433cSCarl Huang .hal_tcl1_ring_id = 0x00000518, 22736976433cSCarl Huang .hal_tcl1_ring_misc = 0x00000520, 22746976433cSCarl Huang .hal_tcl1_ring_tp_addr_lsb = 0x0000052c, 22756976433cSCarl Huang .hal_tcl1_ring_tp_addr_msb = 0x00000530, 22766976433cSCarl Huang .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000540, 22776976433cSCarl Huang .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000544, 22786976433cSCarl Huang .hal_tcl1_ring_msi1_base_lsb = 0x00000558, 22796976433cSCarl Huang .hal_tcl1_ring_msi1_base_msb = 0x0000055c, 22806976433cSCarl Huang .hal_tcl1_ring_msi1_data = 0x00000560, 22816976433cSCarl Huang .hal_tcl2_ring_base_lsb = 0x00000568, 22826976433cSCarl Huang .hal_tcl_ring_base_lsb = 0x00000618, 22836976433cSCarl Huang 22846976433cSCarl Huang /* TCL STATUS ring address */ 22856976433cSCarl Huang .hal_tcl_status_ring_base_lsb = 0x00000720, 22866976433cSCarl Huang 22876976433cSCarl Huang /* REO2SW(x) R0 ring configuration address */ 22886976433cSCarl Huang .hal_reo1_ring_base_lsb = 0x0000029c, 22896976433cSCarl Huang .hal_reo1_ring_base_msb = 0x000002a0, 22906976433cSCarl Huang .hal_reo1_ring_id = 0x000002a4, 22916976433cSCarl Huang .hal_reo1_ring_misc = 0x000002ac, 22926976433cSCarl Huang .hal_reo1_ring_hp_addr_lsb = 0x000002b0, 22936976433cSCarl Huang .hal_reo1_ring_hp_addr_msb = 0x000002b4, 22946976433cSCarl Huang .hal_reo1_ring_producer_int_setup = 0x000002c0, 22956976433cSCarl Huang .hal_reo1_ring_msi1_base_lsb = 0x000002e4, 22966976433cSCarl Huang .hal_reo1_ring_msi1_base_msb = 0x000002e8, 22976976433cSCarl Huang .hal_reo1_ring_msi1_data = 0x000002ec, 22986976433cSCarl Huang .hal_reo2_ring_base_lsb = 0x000002f4, 22996976433cSCarl Huang .hal_reo1_aging_thresh_ix_0 = 0x00000564, 23006976433cSCarl Huang .hal_reo1_aging_thresh_ix_1 = 0x00000568, 23016976433cSCarl Huang .hal_reo1_aging_thresh_ix_2 = 0x0000056c, 23026976433cSCarl Huang .hal_reo1_aging_thresh_ix_3 = 0x00000570, 23036976433cSCarl Huang 23046976433cSCarl Huang /* REO2SW(x) R2 ring pointers (head/tail) address */ 23056976433cSCarl Huang .hal_reo1_ring_hp = 0x00003038, 23066976433cSCarl Huang .hal_reo1_ring_tp = 0x0000303c, 23076976433cSCarl Huang .hal_reo2_ring_hp = 0x00003040, 23086976433cSCarl Huang 23096976433cSCarl Huang /* REO2TCL R0 ring configuration address */ 23106976433cSCarl Huang .hal_reo_tcl_ring_base_lsb = 0x000003fc, 23116976433cSCarl Huang .hal_reo_tcl_ring_hp = 0x00003058, 23126976433cSCarl Huang 231349890d9cSManikanta Pubbisetty /* REO CMD ring address */ 231449890d9cSManikanta Pubbisetty .hal_reo_cmd_ring_base_lsb = 0x00000194, 231549890d9cSManikanta Pubbisetty .hal_reo_cmd_ring_hp = 0x00003020, 231649890d9cSManikanta Pubbisetty 23176976433cSCarl Huang /* REO status address */ 23186976433cSCarl Huang .hal_reo_status_ring_base_lsb = 0x00000504, 23196976433cSCarl Huang .hal_reo_status_hp = 0x00003070, 23206976433cSCarl Huang 232149890d9cSManikanta Pubbisetty /* SW2REO ring address */ 232249890d9cSManikanta Pubbisetty .hal_sw2reo_ring_base_lsb = 0x000001ec, 232349890d9cSManikanta Pubbisetty .hal_sw2reo_ring_hp = 0x00003028, 232449890d9cSManikanta Pubbisetty 23256fe6f68fSKarthikeyan Periyasamy /* WCSS relative address */ 23266fe6f68fSKarthikeyan Periyasamy .hal_seq_wcss_umac_ce0_src_reg = 0x00a00000, 23276fe6f68fSKarthikeyan Periyasamy .hal_seq_wcss_umac_ce0_dst_reg = 0x00a01000, 23286fe6f68fSKarthikeyan Periyasamy .hal_seq_wcss_umac_ce1_src_reg = 0x00a02000, 23296fe6f68fSKarthikeyan Periyasamy .hal_seq_wcss_umac_ce1_dst_reg = 0x00a03000, 23306fe6f68fSKarthikeyan Periyasamy 23316fe6f68fSKarthikeyan Periyasamy /* WBM Idle address */ 23326fe6f68fSKarthikeyan Periyasamy .hal_wbm_idle_link_ring_base_lsb = 0x00000860, 23336fe6f68fSKarthikeyan Periyasamy .hal_wbm_idle_link_ring_misc = 0x00000870, 23346fe6f68fSKarthikeyan Periyasamy 23356fe6f68fSKarthikeyan Periyasamy /* SW2WBM release address */ 23366fe6f68fSKarthikeyan Periyasamy .hal_wbm_release_ring_base_lsb = 0x000001d8, 23376fe6f68fSKarthikeyan Periyasamy 23386fe6f68fSKarthikeyan Periyasamy /* WBM2SW release address */ 23396fe6f68fSKarthikeyan Periyasamy .hal_wbm0_release_ring_base_lsb = 0x00000910, 23406fe6f68fSKarthikeyan Periyasamy .hal_wbm1_release_ring_base_lsb = 0x00000968, 23416fe6f68fSKarthikeyan Periyasamy 23426fe6f68fSKarthikeyan Periyasamy /* PCIe base address */ 23436fe6f68fSKarthikeyan Periyasamy .pcie_qserdes_sysclk_en_sel = 0x0, 23446fe6f68fSKarthikeyan Periyasamy .pcie_pcs_osc_dtct_config_base = 0x0, 234549890d9cSManikanta Pubbisetty 234649890d9cSManikanta Pubbisetty /* Shadow register area */ 234749890d9cSManikanta Pubbisetty .hal_shadow_base_addr = 0x0, 234822cc6873SManikanta Pubbisetty 234922cc6873SManikanta Pubbisetty /* REO misc control register, not used in IPQ8074 */ 235022cc6873SManikanta Pubbisetty .hal_reo1_misc_ctl = 0x0, 23516976433cSCarl Huang }; 23526976433cSCarl Huang 23536976433cSCarl Huang const struct ath11k_hw_regs qca6390_regs = { 23546976433cSCarl Huang /* SW2TCL(x) R0 ring configuration address */ 23556976433cSCarl Huang .hal_tcl1_ring_base_lsb = 0x00000684, 23566976433cSCarl Huang .hal_tcl1_ring_base_msb = 0x00000688, 23576976433cSCarl Huang .hal_tcl1_ring_id = 0x0000068c, 23586976433cSCarl Huang .hal_tcl1_ring_misc = 0x00000694, 23596976433cSCarl Huang .hal_tcl1_ring_tp_addr_lsb = 0x000006a0, 23606976433cSCarl Huang .hal_tcl1_ring_tp_addr_msb = 0x000006a4, 23616976433cSCarl Huang .hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006b4, 23626976433cSCarl Huang .hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006b8, 23636976433cSCarl Huang .hal_tcl1_ring_msi1_base_lsb = 0x000006cc, 23646976433cSCarl Huang .hal_tcl1_ring_msi1_base_msb = 0x000006d0, 23656976433cSCarl Huang .hal_tcl1_ring_msi1_data = 0x000006d4, 23666976433cSCarl Huang .hal_tcl2_ring_base_lsb = 0x000006dc, 23676976433cSCarl Huang .hal_tcl_ring_base_lsb = 0x0000078c, 23686976433cSCarl Huang 23696976433cSCarl Huang /* TCL STATUS ring address */ 23706976433cSCarl Huang .hal_tcl_status_ring_base_lsb = 0x00000894, 23716976433cSCarl Huang 23726976433cSCarl Huang /* REO2SW(x) R0 ring configuration address */ 23736976433cSCarl Huang .hal_reo1_ring_base_lsb = 0x00000244, 23746976433cSCarl Huang .hal_reo1_ring_base_msb = 0x00000248, 23756976433cSCarl Huang .hal_reo1_ring_id = 0x0000024c, 23766976433cSCarl Huang .hal_reo1_ring_misc = 0x00000254, 23776976433cSCarl Huang .hal_reo1_ring_hp_addr_lsb = 0x00000258, 23786976433cSCarl Huang .hal_reo1_ring_hp_addr_msb = 0x0000025c, 23796976433cSCarl Huang .hal_reo1_ring_producer_int_setup = 0x00000268, 23806976433cSCarl Huang .hal_reo1_ring_msi1_base_lsb = 0x0000028c, 23816976433cSCarl Huang .hal_reo1_ring_msi1_base_msb = 0x00000290, 23826976433cSCarl Huang .hal_reo1_ring_msi1_data = 0x00000294, 23836976433cSCarl Huang .hal_reo2_ring_base_lsb = 0x0000029c, 23846976433cSCarl Huang .hal_reo1_aging_thresh_ix_0 = 0x0000050c, 23856976433cSCarl Huang .hal_reo1_aging_thresh_ix_1 = 0x00000510, 23866976433cSCarl Huang .hal_reo1_aging_thresh_ix_2 = 0x00000514, 23876976433cSCarl Huang .hal_reo1_aging_thresh_ix_3 = 0x00000518, 23886976433cSCarl Huang 23896976433cSCarl Huang /* REO2SW(x) R2 ring pointers (head/tail) address */ 23906976433cSCarl Huang .hal_reo1_ring_hp = 0x00003030, 23916976433cSCarl Huang .hal_reo1_ring_tp = 0x00003034, 23926976433cSCarl Huang .hal_reo2_ring_hp = 0x00003038, 23936976433cSCarl Huang 23946976433cSCarl Huang /* REO2TCL R0 ring configuration address */ 23956976433cSCarl Huang .hal_reo_tcl_ring_base_lsb = 0x000003a4, 23966976433cSCarl Huang .hal_reo_tcl_ring_hp = 0x00003050, 23976976433cSCarl Huang 239849890d9cSManikanta Pubbisetty /* REO CMD ring address */ 239949890d9cSManikanta Pubbisetty .hal_reo_cmd_ring_base_lsb = 0x00000194, 240049890d9cSManikanta Pubbisetty .hal_reo_cmd_ring_hp = 0x00003020, 240149890d9cSManikanta Pubbisetty 24026976433cSCarl Huang /* REO status address */ 24036976433cSCarl Huang .hal_reo_status_ring_base_lsb = 0x000004ac, 24046976433cSCarl Huang .hal_reo_status_hp = 0x00003068, 24056fe6f68fSKarthikeyan Periyasamy 240649890d9cSManikanta Pubbisetty /* SW2REO ring address */ 240749890d9cSManikanta Pubbisetty .hal_sw2reo_ring_base_lsb = 0x000001ec, 240849890d9cSManikanta Pubbisetty .hal_sw2reo_ring_hp = 0x00003028, 240949890d9cSManikanta Pubbisetty 24106fe6f68fSKarthikeyan Periyasamy /* WCSS relative address */ 24116fe6f68fSKarthikeyan Periyasamy .hal_seq_wcss_umac_ce0_src_reg = 0x00a00000, 24126fe6f68fSKarthikeyan Periyasamy .hal_seq_wcss_umac_ce0_dst_reg = 0x00a01000, 24136fe6f68fSKarthikeyan Periyasamy .hal_seq_wcss_umac_ce1_src_reg = 0x00a02000, 24146fe6f68fSKarthikeyan Periyasamy .hal_seq_wcss_umac_ce1_dst_reg = 0x00a03000, 24156fe6f68fSKarthikeyan Periyasamy 24166fe6f68fSKarthikeyan Periyasamy /* WBM Idle address */ 24176fe6f68fSKarthikeyan Periyasamy .hal_wbm_idle_link_ring_base_lsb = 0x00000860, 24186fe6f68fSKarthikeyan Periyasamy .hal_wbm_idle_link_ring_misc = 0x00000870, 24196fe6f68fSKarthikeyan Periyasamy 24206fe6f68fSKarthikeyan Periyasamy /* SW2WBM release address */ 24216fe6f68fSKarthikeyan Periyasamy .hal_wbm_release_ring_base_lsb = 0x000001d8, 24226fe6f68fSKarthikeyan Periyasamy 24236fe6f68fSKarthikeyan Periyasamy /* WBM2SW release address */ 24246fe6f68fSKarthikeyan Periyasamy .hal_wbm0_release_ring_base_lsb = 0x00000910, 24256fe6f68fSKarthikeyan Periyasamy .hal_wbm1_release_ring_base_lsb = 0x00000968, 24266fe6f68fSKarthikeyan Periyasamy 24276fe6f68fSKarthikeyan Periyasamy /* PCIe base address */ 24286fe6f68fSKarthikeyan Periyasamy .pcie_qserdes_sysclk_en_sel = 0x01e0c0ac, 24296fe6f68fSKarthikeyan Periyasamy .pcie_pcs_osc_dtct_config_base = 0x01e0c628, 243049890d9cSManikanta Pubbisetty 243149890d9cSManikanta Pubbisetty /* Shadow register area */ 243249890d9cSManikanta Pubbisetty .hal_shadow_base_addr = 0x000008fc, 243322cc6873SManikanta Pubbisetty 243422cc6873SManikanta Pubbisetty /* REO misc control register, not used in QCA6390 */ 243522cc6873SManikanta Pubbisetty .hal_reo1_misc_ctl = 0x0, 24366fe6f68fSKarthikeyan Periyasamy }; 24376fe6f68fSKarthikeyan Periyasamy 24386fe6f68fSKarthikeyan Periyasamy const struct ath11k_hw_regs qcn9074_regs = { 24396fe6f68fSKarthikeyan Periyasamy /* SW2TCL(x) R0 ring configuration address */ 24406fe6f68fSKarthikeyan Periyasamy .hal_tcl1_ring_base_lsb = 0x000004f0, 24416fe6f68fSKarthikeyan Periyasamy .hal_tcl1_ring_base_msb = 0x000004f4, 24426fe6f68fSKarthikeyan Periyasamy .hal_tcl1_ring_id = 0x000004f8, 24436fe6f68fSKarthikeyan Periyasamy .hal_tcl1_ring_misc = 0x00000500, 24446fe6f68fSKarthikeyan Periyasamy .hal_tcl1_ring_tp_addr_lsb = 0x0000050c, 24456fe6f68fSKarthikeyan Periyasamy .hal_tcl1_ring_tp_addr_msb = 0x00000510, 24466fe6f68fSKarthikeyan Periyasamy .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000520, 24476fe6f68fSKarthikeyan Periyasamy .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000524, 24486fe6f68fSKarthikeyan Periyasamy .hal_tcl1_ring_msi1_base_lsb = 0x00000538, 24496fe6f68fSKarthikeyan Periyasamy .hal_tcl1_ring_msi1_base_msb = 0x0000053c, 24506fe6f68fSKarthikeyan Periyasamy .hal_tcl1_ring_msi1_data = 0x00000540, 24516fe6f68fSKarthikeyan Periyasamy .hal_tcl2_ring_base_lsb = 0x00000548, 24526fe6f68fSKarthikeyan Periyasamy .hal_tcl_ring_base_lsb = 0x000005f8, 24536fe6f68fSKarthikeyan Periyasamy 24546fe6f68fSKarthikeyan Periyasamy /* TCL STATUS ring address */ 24556fe6f68fSKarthikeyan Periyasamy .hal_tcl_status_ring_base_lsb = 0x00000700, 24566fe6f68fSKarthikeyan Periyasamy 24576fe6f68fSKarthikeyan Periyasamy /* REO2SW(x) R0 ring configuration address */ 24586fe6f68fSKarthikeyan Periyasamy .hal_reo1_ring_base_lsb = 0x0000029c, 24596fe6f68fSKarthikeyan Periyasamy .hal_reo1_ring_base_msb = 0x000002a0, 24606fe6f68fSKarthikeyan Periyasamy .hal_reo1_ring_id = 0x000002a4, 24616fe6f68fSKarthikeyan Periyasamy .hal_reo1_ring_misc = 0x000002ac, 24626fe6f68fSKarthikeyan Periyasamy .hal_reo1_ring_hp_addr_lsb = 0x000002b0, 24636fe6f68fSKarthikeyan Periyasamy .hal_reo1_ring_hp_addr_msb = 0x000002b4, 24646fe6f68fSKarthikeyan Periyasamy .hal_reo1_ring_producer_int_setup = 0x000002c0, 24656fe6f68fSKarthikeyan Periyasamy .hal_reo1_ring_msi1_base_lsb = 0x000002e4, 24666fe6f68fSKarthikeyan Periyasamy .hal_reo1_ring_msi1_base_msb = 0x000002e8, 24676fe6f68fSKarthikeyan Periyasamy .hal_reo1_ring_msi1_data = 0x000002ec, 24686fe6f68fSKarthikeyan Periyasamy .hal_reo2_ring_base_lsb = 0x000002f4, 24696fe6f68fSKarthikeyan Periyasamy .hal_reo1_aging_thresh_ix_0 = 0x00000564, 24706fe6f68fSKarthikeyan Periyasamy .hal_reo1_aging_thresh_ix_1 = 0x00000568, 24716fe6f68fSKarthikeyan Periyasamy .hal_reo1_aging_thresh_ix_2 = 0x0000056c, 24726fe6f68fSKarthikeyan Periyasamy .hal_reo1_aging_thresh_ix_3 = 0x00000570, 24736fe6f68fSKarthikeyan Periyasamy 24746fe6f68fSKarthikeyan Periyasamy /* REO2SW(x) R2 ring pointers (head/tail) address */ 24756fe6f68fSKarthikeyan Periyasamy .hal_reo1_ring_hp = 0x00003038, 24766fe6f68fSKarthikeyan Periyasamy .hal_reo1_ring_tp = 0x0000303c, 24776fe6f68fSKarthikeyan Periyasamy .hal_reo2_ring_hp = 0x00003040, 24786fe6f68fSKarthikeyan Periyasamy 24796fe6f68fSKarthikeyan Periyasamy /* REO2TCL R0 ring configuration address */ 24806fe6f68fSKarthikeyan Periyasamy .hal_reo_tcl_ring_base_lsb = 0x000003fc, 24816fe6f68fSKarthikeyan Periyasamy .hal_reo_tcl_ring_hp = 0x00003058, 24826fe6f68fSKarthikeyan Periyasamy 248349890d9cSManikanta Pubbisetty /* REO CMD ring address */ 248449890d9cSManikanta Pubbisetty .hal_reo_cmd_ring_base_lsb = 0x00000194, 248549890d9cSManikanta Pubbisetty .hal_reo_cmd_ring_hp = 0x00003020, 248649890d9cSManikanta Pubbisetty 24876fe6f68fSKarthikeyan Periyasamy /* REO status address */ 24886fe6f68fSKarthikeyan Periyasamy .hal_reo_status_ring_base_lsb = 0x00000504, 24896fe6f68fSKarthikeyan Periyasamy .hal_reo_status_hp = 0x00003070, 24906fe6f68fSKarthikeyan Periyasamy 249149890d9cSManikanta Pubbisetty /* SW2REO ring address */ 249249890d9cSManikanta Pubbisetty .hal_sw2reo_ring_base_lsb = 0x000001ec, 249349890d9cSManikanta Pubbisetty .hal_sw2reo_ring_hp = 0x00003028, 249449890d9cSManikanta Pubbisetty 24956fe6f68fSKarthikeyan Periyasamy /* WCSS relative address */ 24966fe6f68fSKarthikeyan Periyasamy .hal_seq_wcss_umac_ce0_src_reg = 0x01b80000, 24976fe6f68fSKarthikeyan Periyasamy .hal_seq_wcss_umac_ce0_dst_reg = 0x01b81000, 24986fe6f68fSKarthikeyan Periyasamy .hal_seq_wcss_umac_ce1_src_reg = 0x01b82000, 24996fe6f68fSKarthikeyan Periyasamy .hal_seq_wcss_umac_ce1_dst_reg = 0x01b83000, 25006fe6f68fSKarthikeyan Periyasamy 25016fe6f68fSKarthikeyan Periyasamy /* WBM Idle address */ 25026fe6f68fSKarthikeyan Periyasamy .hal_wbm_idle_link_ring_base_lsb = 0x00000874, 25036fe6f68fSKarthikeyan Periyasamy .hal_wbm_idle_link_ring_misc = 0x00000884, 25046fe6f68fSKarthikeyan Periyasamy 25056fe6f68fSKarthikeyan Periyasamy /* SW2WBM release address */ 25066fe6f68fSKarthikeyan Periyasamy .hal_wbm_release_ring_base_lsb = 0x000001ec, 25076fe6f68fSKarthikeyan Periyasamy 25086fe6f68fSKarthikeyan Periyasamy /* WBM2SW release address */ 25096fe6f68fSKarthikeyan Periyasamy .hal_wbm0_release_ring_base_lsb = 0x00000924, 25106fe6f68fSKarthikeyan Periyasamy .hal_wbm1_release_ring_base_lsb = 0x0000097c, 25116fe6f68fSKarthikeyan Periyasamy 25126fe6f68fSKarthikeyan Periyasamy /* PCIe base address */ 25136fe6f68fSKarthikeyan Periyasamy .pcie_qserdes_sysclk_en_sel = 0x01e0e0a8, 25146fe6f68fSKarthikeyan Periyasamy .pcie_pcs_osc_dtct_config_base = 0x01e0f45c, 251549890d9cSManikanta Pubbisetty 251649890d9cSManikanta Pubbisetty /* Shadow register area */ 251749890d9cSManikanta Pubbisetty .hal_shadow_base_addr = 0x0, 251822cc6873SManikanta Pubbisetty 251922cc6873SManikanta Pubbisetty /* REO misc control register, not used in QCN9074 */ 252022cc6873SManikanta Pubbisetty .hal_reo1_misc_ctl = 0x0, 25216976433cSCarl Huang }; 2522755b1f73SBaochen Qiang 2523755b1f73SBaochen Qiang const struct ath11k_hw_regs wcn6855_regs = { 2524755b1f73SBaochen Qiang /* SW2TCL(x) R0 ring configuration address */ 2525755b1f73SBaochen Qiang .hal_tcl1_ring_base_lsb = 0x00000690, 2526755b1f73SBaochen Qiang .hal_tcl1_ring_base_msb = 0x00000694, 2527755b1f73SBaochen Qiang .hal_tcl1_ring_id = 0x00000698, 2528755b1f73SBaochen Qiang .hal_tcl1_ring_misc = 0x000006a0, 2529755b1f73SBaochen Qiang .hal_tcl1_ring_tp_addr_lsb = 0x000006ac, 2530755b1f73SBaochen Qiang .hal_tcl1_ring_tp_addr_msb = 0x000006b0, 2531755b1f73SBaochen Qiang .hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006c0, 2532755b1f73SBaochen Qiang .hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006c4, 2533755b1f73SBaochen Qiang .hal_tcl1_ring_msi1_base_lsb = 0x000006d8, 2534755b1f73SBaochen Qiang .hal_tcl1_ring_msi1_base_msb = 0x000006dc, 2535755b1f73SBaochen Qiang .hal_tcl1_ring_msi1_data = 0x000006e0, 2536755b1f73SBaochen Qiang .hal_tcl2_ring_base_lsb = 0x000006e8, 2537755b1f73SBaochen Qiang .hal_tcl_ring_base_lsb = 0x00000798, 2538755b1f73SBaochen Qiang 2539755b1f73SBaochen Qiang /* TCL STATUS ring address */ 2540755b1f73SBaochen Qiang .hal_tcl_status_ring_base_lsb = 0x000008a0, 2541755b1f73SBaochen Qiang 2542755b1f73SBaochen Qiang /* REO2SW(x) R0 ring configuration address */ 2543755b1f73SBaochen Qiang .hal_reo1_ring_base_lsb = 0x00000244, 2544755b1f73SBaochen Qiang .hal_reo1_ring_base_msb = 0x00000248, 2545755b1f73SBaochen Qiang .hal_reo1_ring_id = 0x0000024c, 2546755b1f73SBaochen Qiang .hal_reo1_ring_misc = 0x00000254, 2547755b1f73SBaochen Qiang .hal_reo1_ring_hp_addr_lsb = 0x00000258, 2548755b1f73SBaochen Qiang .hal_reo1_ring_hp_addr_msb = 0x0000025c, 2549755b1f73SBaochen Qiang .hal_reo1_ring_producer_int_setup = 0x00000268, 2550755b1f73SBaochen Qiang .hal_reo1_ring_msi1_base_lsb = 0x0000028c, 2551755b1f73SBaochen Qiang .hal_reo1_ring_msi1_base_msb = 0x00000290, 2552755b1f73SBaochen Qiang .hal_reo1_ring_msi1_data = 0x00000294, 2553755b1f73SBaochen Qiang .hal_reo2_ring_base_lsb = 0x0000029c, 2554755b1f73SBaochen Qiang .hal_reo1_aging_thresh_ix_0 = 0x000005bc, 2555755b1f73SBaochen Qiang .hal_reo1_aging_thresh_ix_1 = 0x000005c0, 2556755b1f73SBaochen Qiang .hal_reo1_aging_thresh_ix_2 = 0x000005c4, 2557755b1f73SBaochen Qiang .hal_reo1_aging_thresh_ix_3 = 0x000005c8, 2558755b1f73SBaochen Qiang 2559755b1f73SBaochen Qiang /* REO2SW(x) R2 ring pointers (head/tail) address */ 2560755b1f73SBaochen Qiang .hal_reo1_ring_hp = 0x00003030, 2561755b1f73SBaochen Qiang .hal_reo1_ring_tp = 0x00003034, 2562755b1f73SBaochen Qiang .hal_reo2_ring_hp = 0x00003038, 2563755b1f73SBaochen Qiang 2564755b1f73SBaochen Qiang /* REO2TCL R0 ring configuration address */ 2565755b1f73SBaochen Qiang .hal_reo_tcl_ring_base_lsb = 0x00000454, 2566755b1f73SBaochen Qiang .hal_reo_tcl_ring_hp = 0x00003060, 2567755b1f73SBaochen Qiang 256849890d9cSManikanta Pubbisetty /* REO CMD ring address */ 256949890d9cSManikanta Pubbisetty .hal_reo_cmd_ring_base_lsb = 0x00000194, 257049890d9cSManikanta Pubbisetty .hal_reo_cmd_ring_hp = 0x00003020, 257149890d9cSManikanta Pubbisetty 2572755b1f73SBaochen Qiang /* REO status address */ 2573755b1f73SBaochen Qiang .hal_reo_status_ring_base_lsb = 0x0000055c, 2574755b1f73SBaochen Qiang .hal_reo_status_hp = 0x00003078, 2575755b1f73SBaochen Qiang 257649890d9cSManikanta Pubbisetty /* SW2REO ring address */ 257749890d9cSManikanta Pubbisetty .hal_sw2reo_ring_base_lsb = 0x000001ec, 257849890d9cSManikanta Pubbisetty .hal_sw2reo_ring_hp = 0x00003028, 257949890d9cSManikanta Pubbisetty 2580755b1f73SBaochen Qiang /* WCSS relative address */ 2581755b1f73SBaochen Qiang .hal_seq_wcss_umac_ce0_src_reg = 0x1b80000, 2582755b1f73SBaochen Qiang .hal_seq_wcss_umac_ce0_dst_reg = 0x1b81000, 2583755b1f73SBaochen Qiang .hal_seq_wcss_umac_ce1_src_reg = 0x1b82000, 2584755b1f73SBaochen Qiang .hal_seq_wcss_umac_ce1_dst_reg = 0x1b83000, 2585755b1f73SBaochen Qiang 2586755b1f73SBaochen Qiang /* WBM Idle address */ 2587755b1f73SBaochen Qiang .hal_wbm_idle_link_ring_base_lsb = 0x00000870, 2588755b1f73SBaochen Qiang .hal_wbm_idle_link_ring_misc = 0x00000880, 2589755b1f73SBaochen Qiang 2590755b1f73SBaochen Qiang /* SW2WBM release address */ 2591755b1f73SBaochen Qiang .hal_wbm_release_ring_base_lsb = 0x000001e8, 2592755b1f73SBaochen Qiang 2593755b1f73SBaochen Qiang /* WBM2SW release address */ 2594755b1f73SBaochen Qiang .hal_wbm0_release_ring_base_lsb = 0x00000920, 2595755b1f73SBaochen Qiang .hal_wbm1_release_ring_base_lsb = 0x00000978, 2596755b1f73SBaochen Qiang 2597755b1f73SBaochen Qiang /* PCIe base address */ 2598755b1f73SBaochen Qiang .pcie_qserdes_sysclk_en_sel = 0x01e0c0ac, 2599755b1f73SBaochen Qiang .pcie_pcs_osc_dtct_config_base = 0x01e0c628, 260049890d9cSManikanta Pubbisetty 260149890d9cSManikanta Pubbisetty /* Shadow register area */ 260249890d9cSManikanta Pubbisetty .hal_shadow_base_addr = 0x000008fc, 260322cc6873SManikanta Pubbisetty 260422cc6873SManikanta Pubbisetty /* REO misc control register, used for fragment 260522cc6873SManikanta Pubbisetty * destination ring config in WCN6855. 260622cc6873SManikanta Pubbisetty */ 260722cc6873SManikanta Pubbisetty .hal_reo1_misc_ctl = 0x00000630, 260849890d9cSManikanta Pubbisetty }; 260949890d9cSManikanta Pubbisetty 261049890d9cSManikanta Pubbisetty const struct ath11k_hw_regs wcn6750_regs = { 261149890d9cSManikanta Pubbisetty /* SW2TCL(x) R0 ring configuration address */ 261249890d9cSManikanta Pubbisetty .hal_tcl1_ring_base_lsb = 0x00000694, 261349890d9cSManikanta Pubbisetty .hal_tcl1_ring_base_msb = 0x00000698, 261449890d9cSManikanta Pubbisetty .hal_tcl1_ring_id = 0x0000069c, 261549890d9cSManikanta Pubbisetty .hal_tcl1_ring_misc = 0x000006a4, 261649890d9cSManikanta Pubbisetty .hal_tcl1_ring_tp_addr_lsb = 0x000006b0, 261749890d9cSManikanta Pubbisetty .hal_tcl1_ring_tp_addr_msb = 0x000006b4, 261849890d9cSManikanta Pubbisetty .hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006c4, 261949890d9cSManikanta Pubbisetty .hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006c8, 262049890d9cSManikanta Pubbisetty .hal_tcl1_ring_msi1_base_lsb = 0x000006dc, 262149890d9cSManikanta Pubbisetty .hal_tcl1_ring_msi1_base_msb = 0x000006e0, 262249890d9cSManikanta Pubbisetty .hal_tcl1_ring_msi1_data = 0x000006e4, 262349890d9cSManikanta Pubbisetty .hal_tcl2_ring_base_lsb = 0x000006ec, 262449890d9cSManikanta Pubbisetty .hal_tcl_ring_base_lsb = 0x0000079c, 262549890d9cSManikanta Pubbisetty 262649890d9cSManikanta Pubbisetty /* TCL STATUS ring address */ 262749890d9cSManikanta Pubbisetty .hal_tcl_status_ring_base_lsb = 0x000008a4, 262849890d9cSManikanta Pubbisetty 262949890d9cSManikanta Pubbisetty /* REO2SW(x) R0 ring configuration address */ 263049890d9cSManikanta Pubbisetty .hal_reo1_ring_base_lsb = 0x000001ec, 263149890d9cSManikanta Pubbisetty .hal_reo1_ring_base_msb = 0x000001f0, 263249890d9cSManikanta Pubbisetty .hal_reo1_ring_id = 0x000001f4, 263349890d9cSManikanta Pubbisetty .hal_reo1_ring_misc = 0x000001fc, 263449890d9cSManikanta Pubbisetty .hal_reo1_ring_hp_addr_lsb = 0x00000200, 263549890d9cSManikanta Pubbisetty .hal_reo1_ring_hp_addr_msb = 0x00000204, 263649890d9cSManikanta Pubbisetty .hal_reo1_ring_producer_int_setup = 0x00000210, 263749890d9cSManikanta Pubbisetty .hal_reo1_ring_msi1_base_lsb = 0x00000234, 263849890d9cSManikanta Pubbisetty .hal_reo1_ring_msi1_base_msb = 0x00000238, 263949890d9cSManikanta Pubbisetty .hal_reo1_ring_msi1_data = 0x0000023c, 264049890d9cSManikanta Pubbisetty .hal_reo2_ring_base_lsb = 0x00000244, 264149890d9cSManikanta Pubbisetty .hal_reo1_aging_thresh_ix_0 = 0x00000564, 264249890d9cSManikanta Pubbisetty .hal_reo1_aging_thresh_ix_1 = 0x00000568, 264349890d9cSManikanta Pubbisetty .hal_reo1_aging_thresh_ix_2 = 0x0000056c, 264449890d9cSManikanta Pubbisetty .hal_reo1_aging_thresh_ix_3 = 0x00000570, 264549890d9cSManikanta Pubbisetty 264649890d9cSManikanta Pubbisetty /* REO2SW(x) R2 ring pointers (head/tail) address */ 264749890d9cSManikanta Pubbisetty .hal_reo1_ring_hp = 0x00003028, 264849890d9cSManikanta Pubbisetty .hal_reo1_ring_tp = 0x0000302c, 264949890d9cSManikanta Pubbisetty .hal_reo2_ring_hp = 0x00003030, 265049890d9cSManikanta Pubbisetty 265149890d9cSManikanta Pubbisetty /* REO2TCL R0 ring configuration address */ 265249890d9cSManikanta Pubbisetty .hal_reo_tcl_ring_base_lsb = 0x000003fc, 265349890d9cSManikanta Pubbisetty .hal_reo_tcl_ring_hp = 0x00003058, 265449890d9cSManikanta Pubbisetty 265549890d9cSManikanta Pubbisetty /* REO CMD ring address */ 265649890d9cSManikanta Pubbisetty .hal_reo_cmd_ring_base_lsb = 0x000000e4, 265749890d9cSManikanta Pubbisetty .hal_reo_cmd_ring_hp = 0x00003010, 265849890d9cSManikanta Pubbisetty 265949890d9cSManikanta Pubbisetty /* REO status address */ 266049890d9cSManikanta Pubbisetty .hal_reo_status_ring_base_lsb = 0x00000504, 266149890d9cSManikanta Pubbisetty .hal_reo_status_hp = 0x00003070, 266249890d9cSManikanta Pubbisetty 266349890d9cSManikanta Pubbisetty /* SW2REO ring address */ 266449890d9cSManikanta Pubbisetty .hal_sw2reo_ring_base_lsb = 0x0000013c, 266549890d9cSManikanta Pubbisetty .hal_sw2reo_ring_hp = 0x00003018, 266649890d9cSManikanta Pubbisetty 266749890d9cSManikanta Pubbisetty /* WCSS relative address */ 266849890d9cSManikanta Pubbisetty .hal_seq_wcss_umac_ce0_src_reg = 0x01b80000, 266949890d9cSManikanta Pubbisetty .hal_seq_wcss_umac_ce0_dst_reg = 0x01b81000, 267049890d9cSManikanta Pubbisetty .hal_seq_wcss_umac_ce1_src_reg = 0x01b82000, 267149890d9cSManikanta Pubbisetty .hal_seq_wcss_umac_ce1_dst_reg = 0x01b83000, 267249890d9cSManikanta Pubbisetty 267349890d9cSManikanta Pubbisetty /* WBM Idle address */ 267449890d9cSManikanta Pubbisetty .hal_wbm_idle_link_ring_base_lsb = 0x00000874, 267549890d9cSManikanta Pubbisetty .hal_wbm_idle_link_ring_misc = 0x00000884, 267649890d9cSManikanta Pubbisetty 267749890d9cSManikanta Pubbisetty /* SW2WBM release address */ 267849890d9cSManikanta Pubbisetty .hal_wbm_release_ring_base_lsb = 0x000001ec, 267949890d9cSManikanta Pubbisetty 268049890d9cSManikanta Pubbisetty /* WBM2SW release address */ 268149890d9cSManikanta Pubbisetty .hal_wbm0_release_ring_base_lsb = 0x00000924, 268249890d9cSManikanta Pubbisetty .hal_wbm1_release_ring_base_lsb = 0x0000097c, 268349890d9cSManikanta Pubbisetty 268449890d9cSManikanta Pubbisetty /* PCIe base address */ 268549890d9cSManikanta Pubbisetty .pcie_qserdes_sysclk_en_sel = 0x0, 268649890d9cSManikanta Pubbisetty .pcie_pcs_osc_dtct_config_base = 0x0, 268749890d9cSManikanta Pubbisetty 268849890d9cSManikanta Pubbisetty /* Shadow register area */ 268949890d9cSManikanta Pubbisetty .hal_shadow_base_addr = 0x00000504, 269022cc6873SManikanta Pubbisetty 269122cc6873SManikanta Pubbisetty /* REO misc control register, used for fragment 269222cc6873SManikanta Pubbisetty * destination ring config in WCN6750. 269322cc6873SManikanta Pubbisetty */ 269422cc6873SManikanta Pubbisetty .hal_reo1_misc_ctl = 0x000005d8, 2695755b1f73SBaochen Qiang }; 2696734223d7SBaochen Qiang 26977636c9a6SManikanta Pubbisetty static const struct ath11k_hw_tcl2wbm_rbm_map ath11k_hw_tcl2wbm_rbm_map_ipq8074[] = { 26987636c9a6SManikanta Pubbisetty { 26997636c9a6SManikanta Pubbisetty .tcl_ring_num = 0, 27007636c9a6SManikanta Pubbisetty .wbm_ring_num = 0, 27017636c9a6SManikanta Pubbisetty .rbm_id = HAL_RX_BUF_RBM_SW0_BM, 27027636c9a6SManikanta Pubbisetty }, 27037636c9a6SManikanta Pubbisetty { 27047636c9a6SManikanta Pubbisetty .tcl_ring_num = 1, 27057636c9a6SManikanta Pubbisetty .wbm_ring_num = 1, 27067636c9a6SManikanta Pubbisetty .rbm_id = HAL_RX_BUF_RBM_SW1_BM, 27077636c9a6SManikanta Pubbisetty }, 27087636c9a6SManikanta Pubbisetty { 27097636c9a6SManikanta Pubbisetty .tcl_ring_num = 2, 27107636c9a6SManikanta Pubbisetty .wbm_ring_num = 2, 27117636c9a6SManikanta Pubbisetty .rbm_id = HAL_RX_BUF_RBM_SW2_BM, 27127636c9a6SManikanta Pubbisetty }, 27137636c9a6SManikanta Pubbisetty }; 27147636c9a6SManikanta Pubbisetty 27157636c9a6SManikanta Pubbisetty static const struct ath11k_hw_tcl2wbm_rbm_map ath11k_hw_tcl2wbm_rbm_map_wcn6750[] = { 27167636c9a6SManikanta Pubbisetty { 27177636c9a6SManikanta Pubbisetty .tcl_ring_num = 0, 27187636c9a6SManikanta Pubbisetty .wbm_ring_num = 0, 27197636c9a6SManikanta Pubbisetty .rbm_id = HAL_RX_BUF_RBM_SW0_BM, 27207636c9a6SManikanta Pubbisetty }, 27217636c9a6SManikanta Pubbisetty { 27227636c9a6SManikanta Pubbisetty .tcl_ring_num = 1, 27237636c9a6SManikanta Pubbisetty .wbm_ring_num = 4, 27247636c9a6SManikanta Pubbisetty .rbm_id = HAL_RX_BUF_RBM_SW4_BM, 27257636c9a6SManikanta Pubbisetty }, 27267636c9a6SManikanta Pubbisetty { 27277636c9a6SManikanta Pubbisetty .tcl_ring_num = 2, 27287636c9a6SManikanta Pubbisetty .wbm_ring_num = 2, 27297636c9a6SManikanta Pubbisetty .rbm_id = HAL_RX_BUF_RBM_SW2_BM, 27307636c9a6SManikanta Pubbisetty }, 27317636c9a6SManikanta Pubbisetty }; 27327636c9a6SManikanta Pubbisetty 2733711b80acSSriram R const struct ath11k_hw_regs ipq5018_regs = { 2734711b80acSSriram R /* SW2TCL(x) R0 ring configuration address */ 2735711b80acSSriram R .hal_tcl1_ring_base_lsb = 0x00000694, 2736711b80acSSriram R .hal_tcl1_ring_base_msb = 0x00000698, 2737711b80acSSriram R .hal_tcl1_ring_id = 0x0000069c, 2738711b80acSSriram R .hal_tcl1_ring_misc = 0x000006a4, 2739711b80acSSriram R .hal_tcl1_ring_tp_addr_lsb = 0x000006b0, 2740711b80acSSriram R .hal_tcl1_ring_tp_addr_msb = 0x000006b4, 2741711b80acSSriram R .hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006c4, 2742711b80acSSriram R .hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006c8, 2743711b80acSSriram R .hal_tcl1_ring_msi1_base_lsb = 0x000006dc, 2744711b80acSSriram R .hal_tcl1_ring_msi1_base_msb = 0x000006e0, 2745711b80acSSriram R .hal_tcl1_ring_msi1_data = 0x000006e4, 2746711b80acSSriram R .hal_tcl2_ring_base_lsb = 0x000006ec, 2747711b80acSSriram R .hal_tcl_ring_base_lsb = 0x0000079c, 2748711b80acSSriram R 2749711b80acSSriram R /* TCL STATUS ring address */ 2750711b80acSSriram R .hal_tcl_status_ring_base_lsb = 0x000008a4, 2751711b80acSSriram R 2752711b80acSSriram R /* REO2SW(x) R0 ring configuration address */ 2753711b80acSSriram R .hal_reo1_ring_base_lsb = 0x000001ec, 2754711b80acSSriram R .hal_reo1_ring_base_msb = 0x000001f0, 2755711b80acSSriram R .hal_reo1_ring_id = 0x000001f4, 2756711b80acSSriram R .hal_reo1_ring_misc = 0x000001fc, 2757711b80acSSriram R .hal_reo1_ring_hp_addr_lsb = 0x00000200, 2758711b80acSSriram R .hal_reo1_ring_hp_addr_msb = 0x00000204, 2759711b80acSSriram R .hal_reo1_ring_producer_int_setup = 0x00000210, 2760711b80acSSriram R .hal_reo1_ring_msi1_base_lsb = 0x00000234, 2761711b80acSSriram R .hal_reo1_ring_msi1_base_msb = 0x00000238, 2762711b80acSSriram R .hal_reo1_ring_msi1_data = 0x0000023c, 2763711b80acSSriram R .hal_reo2_ring_base_lsb = 0x00000244, 2764711b80acSSriram R .hal_reo1_aging_thresh_ix_0 = 0x00000564, 2765711b80acSSriram R .hal_reo1_aging_thresh_ix_1 = 0x00000568, 2766711b80acSSriram R .hal_reo1_aging_thresh_ix_2 = 0x0000056c, 2767711b80acSSriram R .hal_reo1_aging_thresh_ix_3 = 0x00000570, 2768711b80acSSriram R 2769711b80acSSriram R /* REO2SW(x) R2 ring pointers (head/tail) address */ 2770711b80acSSriram R .hal_reo1_ring_hp = 0x00003028, 2771711b80acSSriram R .hal_reo1_ring_tp = 0x0000302c, 2772711b80acSSriram R .hal_reo2_ring_hp = 0x00003030, 2773711b80acSSriram R 2774711b80acSSriram R /* REO2TCL R0 ring configuration address */ 2775711b80acSSriram R .hal_reo_tcl_ring_base_lsb = 0x000003fc, 2776711b80acSSriram R .hal_reo_tcl_ring_hp = 0x00003058, 2777711b80acSSriram R 2778711b80acSSriram R /* SW2REO ring address */ 2779711b80acSSriram R .hal_sw2reo_ring_base_lsb = 0x0000013c, 2780711b80acSSriram R .hal_sw2reo_ring_hp = 0x00003018, 2781711b80acSSriram R 2782711b80acSSriram R /* REO CMD ring address */ 2783711b80acSSriram R .hal_reo_cmd_ring_base_lsb = 0x000000e4, 2784711b80acSSriram R .hal_reo_cmd_ring_hp = 0x00003010, 2785711b80acSSriram R 2786711b80acSSriram R /* REO status address */ 2787711b80acSSriram R .hal_reo_status_ring_base_lsb = 0x00000504, 2788711b80acSSriram R .hal_reo_status_hp = 0x00003070, 2789711b80acSSriram R 2790711b80acSSriram R /* WCSS relative address */ 2791711b80acSSriram R .hal_seq_wcss_umac_ce0_src_reg = 0x08400000 2792711b80acSSriram R - HAL_IPQ5018_CE_WFSS_REG_BASE, 2793711b80acSSriram R .hal_seq_wcss_umac_ce0_dst_reg = 0x08401000 2794711b80acSSriram R - HAL_IPQ5018_CE_WFSS_REG_BASE, 2795711b80acSSriram R .hal_seq_wcss_umac_ce1_src_reg = 0x08402000 2796711b80acSSriram R - HAL_IPQ5018_CE_WFSS_REG_BASE, 2797711b80acSSriram R .hal_seq_wcss_umac_ce1_dst_reg = 0x08403000 2798711b80acSSriram R - HAL_IPQ5018_CE_WFSS_REG_BASE, 2799711b80acSSriram R 2800711b80acSSriram R /* WBM Idle address */ 2801711b80acSSriram R .hal_wbm_idle_link_ring_base_lsb = 0x00000874, 2802711b80acSSriram R .hal_wbm_idle_link_ring_misc = 0x00000884, 2803711b80acSSriram R 2804711b80acSSriram R /* SW2WBM release address */ 2805711b80acSSriram R .hal_wbm_release_ring_base_lsb = 0x000001ec, 2806711b80acSSriram R 2807711b80acSSriram R /* WBM2SW release address */ 2808711b80acSSriram R .hal_wbm0_release_ring_base_lsb = 0x00000924, 2809711b80acSSriram R .hal_wbm1_release_ring_base_lsb = 0x0000097c, 2810711b80acSSriram R }; 2811711b80acSSriram R 2812734223d7SBaochen Qiang const struct ath11k_hw_hal_params ath11k_hw_hal_params_ipq8074 = { 2813734223d7SBaochen Qiang .rx_buf_rbm = HAL_RX_BUF_RBM_SW3_BM, 28147636c9a6SManikanta Pubbisetty .tcl2wbm_rbm_map = ath11k_hw_tcl2wbm_rbm_map_ipq8074, 2815734223d7SBaochen Qiang }; 2816734223d7SBaochen Qiang 2817734223d7SBaochen Qiang const struct ath11k_hw_hal_params ath11k_hw_hal_params_qca6390 = { 2818734223d7SBaochen Qiang .rx_buf_rbm = HAL_RX_BUF_RBM_SW1_BM, 28197636c9a6SManikanta Pubbisetty .tcl2wbm_rbm_map = ath11k_hw_tcl2wbm_rbm_map_ipq8074, 28207636c9a6SManikanta Pubbisetty }; 28217636c9a6SManikanta Pubbisetty 28227636c9a6SManikanta Pubbisetty const struct ath11k_hw_hal_params ath11k_hw_hal_params_wcn6750 = { 28237636c9a6SManikanta Pubbisetty .rx_buf_rbm = HAL_RX_BUF_RBM_SW1_BM, 28247636c9a6SManikanta Pubbisetty .tcl2wbm_rbm_map = ath11k_hw_tcl2wbm_rbm_map_wcn6750, 2825734223d7SBaochen Qiang }; 2826652f69edSBaochen Qiang 2827652f69edSBaochen Qiang static const struct cfg80211_sar_freq_ranges ath11k_hw_sar_freq_ranges_wcn6855[] = { 2828652f69edSBaochen Qiang {.start_freq = 2402, .end_freq = 2482 }, /* 2G ch1~ch13 */ 2829652f69edSBaochen Qiang {.start_freq = 5150, .end_freq = 5250 }, /* 5G UNII-1 ch32~ch48 */ 2830652f69edSBaochen Qiang {.start_freq = 5250, .end_freq = 5725 }, /* 5G UNII-2 ch50~ch144 */ 2831652f69edSBaochen Qiang {.start_freq = 5725, .end_freq = 5810 }, /* 5G UNII-3 ch149~ch161 */ 2832652f69edSBaochen Qiang {.start_freq = 5815, .end_freq = 5895 }, /* 5G UNII-4 ch163~ch177 */ 2833652f69edSBaochen Qiang {.start_freq = 5925, .end_freq = 6165 }, /* 6G UNII-5 Ch1, Ch2 ~ Ch41 */ 2834652f69edSBaochen Qiang {.start_freq = 6165, .end_freq = 6425 }, /* 6G UNII-5 ch45~ch93 */ 2835652f69edSBaochen Qiang {.start_freq = 6425, .end_freq = 6525 }, /* 6G UNII-6 ch97~ch113 */ 2836652f69edSBaochen Qiang {.start_freq = 6525, .end_freq = 6705 }, /* 6G UNII-7 ch117~ch149 */ 2837652f69edSBaochen Qiang {.start_freq = 6705, .end_freq = 6875 }, /* 6G UNII-7 ch153~ch185 */ 2838652f69edSBaochen Qiang {.start_freq = 6875, .end_freq = 7125 }, /* 6G UNII-8 ch189~ch233 */ 2839652f69edSBaochen Qiang }; 2840652f69edSBaochen Qiang 2841652f69edSBaochen Qiang const struct cfg80211_sar_capa ath11k_hw_sar_capa_wcn6855 = { 2842652f69edSBaochen Qiang .type = NL80211_SAR_TYPE_POWER, 2843652f69edSBaochen Qiang .num_freq_ranges = (ARRAY_SIZE(ath11k_hw_sar_freq_ranges_wcn6855)), 2844652f69edSBaochen Qiang .freq_ranges = ath11k_hw_sar_freq_ranges_wcn6855, 2845652f69edSBaochen Qiang }; 2846