xref: /linux/drivers/net/wireless/ath/ath11k/hal_rx.h (revision 64b14a184e83eb62ea0615e31a409956049d40e7) 
1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /*
3  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4  */
5 
6 #ifndef ATH11K_HAL_RX_H
7 #define ATH11K_HAL_RX_H
8 
9 struct hal_rx_wbm_rel_info {
10 	u32 cookie;
11 	enum hal_wbm_rel_src_module err_rel_src;
12 	enum hal_reo_dest_ring_push_reason push_reason;
13 	u32 err_code;
14 	bool first_msdu;
15 	bool last_msdu;
16 };
17 
18 #define HAL_INVALID_PEERID 0xffff
19 #define VHT_SIG_SU_NSS_MASK 0x7
20 
21 #define HAL_RX_MAX_MCS 12
22 #define HAL_RX_MAX_NSS 8
23 
24 struct hal_rx_mon_status_tlv_hdr {
25 	u32 hdr;
26 	u8 value[];
27 };
28 
29 enum hal_rx_su_mu_coding {
30 	HAL_RX_SU_MU_CODING_BCC,
31 	HAL_RX_SU_MU_CODING_LDPC,
32 	HAL_RX_SU_MU_CODING_MAX,
33 };
34 
35 enum hal_rx_gi {
36 	HAL_RX_GI_0_8_US,
37 	HAL_RX_GI_0_4_US,
38 	HAL_RX_GI_1_6_US,
39 	HAL_RX_GI_3_2_US,
40 	HAL_RX_GI_MAX,
41 };
42 
43 enum hal_rx_bw {
44 	HAL_RX_BW_20MHZ,
45 	HAL_RX_BW_40MHZ,
46 	HAL_RX_BW_80MHZ,
47 	HAL_RX_BW_160MHZ,
48 	HAL_RX_BW_MAX,
49 };
50 
51 enum hal_rx_preamble {
52 	HAL_RX_PREAMBLE_11A,
53 	HAL_RX_PREAMBLE_11B,
54 	HAL_RX_PREAMBLE_11N,
55 	HAL_RX_PREAMBLE_11AC,
56 	HAL_RX_PREAMBLE_11AX,
57 	HAL_RX_PREAMBLE_MAX,
58 };
59 
60 enum hal_rx_reception_type {
61 	HAL_RX_RECEPTION_TYPE_SU,
62 	HAL_RX_RECEPTION_TYPE_MU_MIMO,
63 	HAL_RX_RECEPTION_TYPE_MU_OFDMA,
64 	HAL_RX_RECEPTION_TYPE_MU_OFDMA_MIMO,
65 	HAL_RX_RECEPTION_TYPE_MAX,
66 };
67 
68 #define HAL_TLV_STATUS_PPDU_NOT_DONE            0
69 #define HAL_TLV_STATUS_PPDU_DONE                1
70 #define HAL_TLV_STATUS_BUF_DONE                 2
71 #define HAL_TLV_STATUS_PPDU_NON_STD_DONE        3
72 #define HAL_RX_FCS_LEN                          4
73 
74 enum hal_rx_mon_status {
75 	HAL_RX_MON_STATUS_PPDU_NOT_DONE,
76 	HAL_RX_MON_STATUS_PPDU_DONE,
77 	HAL_RX_MON_STATUS_BUF_DONE,
78 };
79 
80 struct hal_sw_mon_ring_entries {
81 	dma_addr_t mon_dst_paddr;
82 	dma_addr_t mon_status_paddr;
83 	u32 mon_dst_sw_cookie;
84 	u32 mon_status_sw_cookie;
85 	void *dst_buf_addr_info;
86 	void *status_buf_addr_info;
87 	u16 ppdu_id;
88 	u8 status_buf_count;
89 	u8 msdu_cnt;
90 	bool end_of_ppdu;
91 	bool drop_ppdu;
92 };
93 
94 struct hal_rx_mon_ppdu_info {
95 	u32 ppdu_id;
96 	u32 ppdu_ts;
97 	u32 num_mpdu_fcs_ok;
98 	u32 num_mpdu_fcs_err;
99 	u32 preamble_type;
100 	u16 chan_num;
101 	u16 tcp_msdu_count;
102 	u16 tcp_ack_msdu_count;
103 	u16 udp_msdu_count;
104 	u16 other_msdu_count;
105 	u16 peer_id;
106 	u8 rate;
107 	u8 mcs;
108 	u8 nss;
109 	u8 bw;
110 	u8 is_stbc;
111 	u8 gi;
112 	u8 ldpc;
113 	u8 beamformed;
114 	u8 rssi_comb;
115 	u8 rssi_chain_pri20[HAL_RX_MAX_NSS];
116 	u8 tid;
117 	u8 dcm;
118 	u8 ru_alloc;
119 	u8 reception_type;
120 	u64 rx_duration;
121 };
122 
123 #define HAL_RX_PPDU_START_INFO0_PPDU_ID		GENMASK(15, 0)
124 
125 struct hal_rx_ppdu_start {
126 	__le32 info0;
127 	__le32 chan_num;
128 	__le32 ppdu_start_ts;
129 } __packed;
130 
131 #define HAL_RX_PPDU_END_USER_STATS_INFO0_MPDU_CNT_FCS_ERR	GENMASK(25, 16)
132 
133 #define HAL_RX_PPDU_END_USER_STATS_INFO1_MPDU_CNT_FCS_OK	GENMASK(8, 0)
134 #define HAL_RX_PPDU_END_USER_STATS_INFO1_FC_VALID		BIT(9)
135 #define HAL_RX_PPDU_END_USER_STATS_INFO1_QOS_CTRL_VALID		BIT(10)
136 #define HAL_RX_PPDU_END_USER_STATS_INFO1_HT_CTRL_VALID		BIT(11)
137 #define HAL_RX_PPDU_END_USER_STATS_INFO1_PKT_TYPE		GENMASK(23, 20)
138 
139 #define HAL_RX_PPDU_END_USER_STATS_INFO2_AST_INDEX		GENMASK(15, 0)
140 #define HAL_RX_PPDU_END_USER_STATS_INFO2_FRAME_CTRL		GENMASK(31, 16)
141 
142 #define HAL_RX_PPDU_END_USER_STATS_INFO3_QOS_CTRL		GENMASK(31, 16)
143 
144 #define HAL_RX_PPDU_END_USER_STATS_INFO4_UDP_MSDU_CNT		GENMASK(15, 0)
145 #define HAL_RX_PPDU_END_USER_STATS_INFO4_TCP_MSDU_CNT		GENMASK(31, 16)
146 
147 #define HAL_RX_PPDU_END_USER_STATS_INFO5_OTHER_MSDU_CNT		GENMASK(15, 0)
148 #define HAL_RX_PPDU_END_USER_STATS_INFO5_TCP_ACK_MSDU_CNT	GENMASK(31, 16)
149 
150 #define HAL_RX_PPDU_END_USER_STATS_INFO6_TID_BITMAP		GENMASK(15, 0)
151 #define HAL_RX_PPDU_END_USER_STATS_INFO6_TID_EOSP_BITMAP	GENMASK(31, 16)
152 
153 struct hal_rx_ppdu_end_user_stats {
154 	__le32 rsvd0[2];
155 	__le32 info0;
156 	__le32 info1;
157 	__le32 info2;
158 	__le32 info3;
159 	__le32 ht_ctrl;
160 	__le32 rsvd1[2];
161 	__le32 info4;
162 	__le32 info5;
163 	__le32 info6;
164 	__le32 rsvd2[11];
165 } __packed;
166 
167 #define HAL_RX_HT_SIG_INFO_INFO0_MCS		GENMASK(6, 0)
168 #define HAL_RX_HT_SIG_INFO_INFO0_BW		BIT(7)
169 
170 #define HAL_RX_HT_SIG_INFO_INFO1_STBC		GENMASK(5, 4)
171 #define HAL_RX_HT_SIG_INFO_INFO1_FEC_CODING	BIT(6)
172 #define HAL_RX_HT_SIG_INFO_INFO1_GI		BIT(7)
173 
174 struct hal_rx_ht_sig_info {
175 	__le32 info0;
176 	__le32 info1;
177 } __packed;
178 
179 #define HAL_RX_LSIG_B_INFO_INFO0_RATE	GENMASK(3, 0)
180 #define HAL_RX_LSIG_B_INFO_INFO0_LEN	GENMASK(15, 4)
181 
182 struct hal_rx_lsig_b_info {
183 	__le32 info0;
184 } __packed;
185 
186 #define HAL_RX_LSIG_A_INFO_INFO0_RATE		GENMASK(3, 0)
187 #define HAL_RX_LSIG_A_INFO_INFO0_LEN		GENMASK(16, 5)
188 #define HAL_RX_LSIG_A_INFO_INFO0_PKT_TYPE	GENMASK(27, 24)
189 
190 struct hal_rx_lsig_a_info {
191 	__le32 info0;
192 } __packed;
193 
194 #define HAL_RX_VHT_SIG_A_INFO_INFO0_BW		GENMASK(1, 0)
195 #define HAL_RX_VHT_SIG_A_INFO_INFO0_STBC	BIT(3)
196 #define HAL_RX_VHT_SIG_A_INFO_INFO0_GROUP_ID	GENMASK(9, 4)
197 #define HAL_RX_VHT_SIG_A_INFO_INFO0_NSTS	GENMASK(21, 10)
198 
199 #define HAL_RX_VHT_SIG_A_INFO_INFO1_GI_SETTING		GENMASK(1, 0)
200 #define HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING	BIT(2)
201 #define HAL_RX_VHT_SIG_A_INFO_INFO1_MCS			GENMASK(7, 4)
202 #define HAL_RX_VHT_SIG_A_INFO_INFO1_BEAMFORMED		BIT(8)
203 
204 struct hal_rx_vht_sig_a_info {
205 	__le32 info0;
206 	__le32 info1;
207 } __packed;
208 
209 enum hal_rx_vht_sig_a_gi_setting {
210 	HAL_RX_VHT_SIG_A_NORMAL_GI = 0,
211 	HAL_RX_VHT_SIG_A_SHORT_GI = 1,
212 	HAL_RX_VHT_SIG_A_SHORT_GI_AMBIGUITY = 3,
213 };
214 
215 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS	GENMASK(6, 3)
216 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM		BIT(7)
217 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW	GENMASK(20, 19)
218 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_CP_LTF_SIZE	GENMASK(22, 21)
219 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS		GENMASK(25, 23)
220 
221 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_CODING		BIT(7)
222 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_STBC		BIT(9)
223 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXBF		BIT(10)
224 
225 struct hal_rx_he_sig_a_su_info {
226 	__le32 info0;
227 	__le32 info1;
228 } __packed;
229 
230 #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_TRANSMIT_BW	GENMASK(17, 15)
231 #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_CP_LTF_SIZE	GENMASK(24, 23)
232 
233 #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_STBC		BIT(12)
234 
235 struct hal_rx_he_sig_a_mu_dl_info {
236 	__le32 info0;
237 	__le32 info1;
238 } __packed;
239 
240 #define HAL_RX_HE_SIG_B1_MU_INFO_INFO0_RU_ALLOCATION	GENMASK(7, 0)
241 
242 struct hal_rx_he_sig_b1_mu_info {
243 	__le32 info0;
244 } __packed;
245 
246 #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_MCS		GENMASK(18, 15)
247 #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_CODING	BIT(20)
248 #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_NSTS		GENMASK(31, 29)
249 
250 struct hal_rx_he_sig_b2_mu_info {
251 	__le32 info0;
252 } __packed;
253 
254 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_NSTS	GENMASK(13, 11)
255 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_TXBF	BIT(19)
256 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_MCS	GENMASK(18, 15)
257 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_DCM	BIT(19)
258 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_CODING	BIT(20)
259 
260 struct hal_rx_he_sig_b2_ofdma_info {
261 	__le32 info0;
262 } __packed;
263 
264 #define HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO1_RSSI_COMB	GENMASK(15, 8)
265 
266 #define HAL_RX_PHYRX_RSSI_PREAMBLE_PRI20	GENMASK(7, 0)
267 
268 struct hal_rx_phyrx_chain_rssi {
269 	__le32 rssi_2040;
270 	__le32 rssi_80;
271 } __packed;
272 
273 struct hal_rx_phyrx_rssi_legacy_info {
274 	__le32 rsvd[3];
275 	struct hal_rx_phyrx_chain_rssi pre_rssi[HAL_RX_MAX_NSS];
276 	struct hal_rx_phyrx_chain_rssi preamble[HAL_RX_MAX_NSS];
277 	__le32 info0;
278 } __packed;
279 
280 #define HAL_RX_MPDU_INFO_INFO0_PEERID	GENMASK(31, 16)
281 #define HAL_RX_MPDU_INFO_INFO0_PEERID_WCN6855	GENMASK(15, 0)
282 
283 struct hal_rx_mpdu_info {
284 	__le32 rsvd0;
285 	__le32 info0;
286 	__le32 rsvd1[21];
287 } __packed;
288 
289 struct hal_rx_mpdu_info_wcn6855 {
290 	__le32 rsvd0[8];
291 	__le32 info0;
292 	__le32 rsvd1[14];
293 } __packed;
294 
295 #define HAL_RX_PPDU_END_DURATION	GENMASK(23, 0)
296 struct hal_rx_ppdu_end_duration {
297 	__le32 rsvd0[9];
298 	__le32 info0;
299 	__le32 rsvd1[4];
300 } __packed;
301 
302 struct hal_rx_rxpcu_classification_overview {
303 	u32 rsvd0;
304 } __packed;
305 
306 struct hal_rx_msdu_desc_info {
307 	u32 msdu_flags;
308 	u16 msdu_len; /* 14 bits for length */
309 };
310 
311 #define HAL_RX_NUM_MSDU_DESC 6
312 struct hal_rx_msdu_list {
313 	struct hal_rx_msdu_desc_info msdu_info[HAL_RX_NUM_MSDU_DESC];
314 	u32 sw_cookie[HAL_RX_NUM_MSDU_DESC];
315 	u8 rbm[HAL_RX_NUM_MSDU_DESC];
316 };
317 
318 void ath11k_hal_reo_status_queue_stats(struct ath11k_base *ab, u32 *reo_desc,
319 				       struct hal_reo_status *status);
320 void ath11k_hal_reo_flush_queue_status(struct ath11k_base *ab, u32 *reo_desc,
321 				       struct hal_reo_status *status);
322 void ath11k_hal_reo_flush_cache_status(struct ath11k_base *ab, u32 *reo_desc,
323 				       struct hal_reo_status *status);
324 void ath11k_hal_reo_flush_cache_status(struct ath11k_base *ab, u32 *reo_desc,
325 				       struct hal_reo_status *status);
326 void ath11k_hal_reo_unblk_cache_status(struct ath11k_base *ab, u32 *reo_desc,
327 				       struct hal_reo_status *status);
328 void ath11k_hal_reo_flush_timeout_list_status(struct ath11k_base *ab,
329 					      u32 *reo_desc,
330 					      struct hal_reo_status *status);
331 void ath11k_hal_reo_desc_thresh_reached_status(struct ath11k_base *ab,
332 					       u32 *reo_desc,
333 					       struct hal_reo_status *status);
334 void ath11k_hal_reo_update_rx_reo_queue_status(struct ath11k_base *ab,
335 					       u32 *reo_desc,
336 					       struct hal_reo_status *status);
337 int ath11k_hal_reo_process_status(u8 *reo_desc, u8 *status);
338 void ath11k_hal_rx_msdu_link_info_get(void *link_desc, u32 *num_msdus,
339 				      u32 *msdu_cookies,
340 				      enum hal_rx_buf_return_buf_manager *rbm);
341 void ath11k_hal_rx_msdu_link_desc_set(struct ath11k_base *ab, void *desc,
342 				      void *link_desc,
343 				      enum hal_wbm_rel_bm_act action);
344 void ath11k_hal_rx_buf_addr_info_set(void *desc, dma_addr_t paddr,
345 				     u32 cookie, u8 manager);
346 void ath11k_hal_rx_buf_addr_info_get(void *desc, dma_addr_t *paddr,
347 				     u32 *cookie, u8 *rbm);
348 int ath11k_hal_desc_reo_parse_err(struct ath11k_base *ab, u32 *rx_desc,
349 				  dma_addr_t *paddr, u32 *desc_bank);
350 int ath11k_hal_wbm_desc_parse_err(struct ath11k_base *ab, void *desc,
351 				  struct hal_rx_wbm_rel_info *rel_info);
352 void ath11k_hal_rx_reo_ent_paddr_get(struct ath11k_base *ab, void *desc,
353 				     dma_addr_t *paddr, u32 *desc_bank);
354 void ath11k_hal_rx_reo_ent_buf_paddr_get(void *rx_desc,
355 					 dma_addr_t *paddr, u32 *sw_cookie,
356 					 void **pp_buf_addr_info, u8 *rbm,
357 					 u32 *msdu_cnt);
358 void
359 ath11k_hal_rx_sw_mon_ring_buf_paddr_get(void *rx_desc,
360 					struct hal_sw_mon_ring_entries *sw_mon_ent);
361 enum hal_rx_mon_status
362 ath11k_hal_rx_parse_mon_status(struct ath11k_base *ab,
363 			       struct hal_rx_mon_ppdu_info *ppdu_info,
364 			       struct sk_buff *skb);
365 
366 #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_0 0xDDBEEF
367 #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_1 0xADBEEF
368 #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_2 0xBDBEEF
369 #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_3 0xCDBEEF
370 #endif
371