1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 */ 5 6 #include "debug.h" 7 #include "hal.h" 8 #include "hal_tx.h" 9 #include "hal_rx.h" 10 #include "hal_desc.h" 11 #include "hif.h" 12 13 static void ath11k_hal_reo_set_desc_hdr(struct hal_desc_header *hdr, 14 u8 owner, u8 buffer_type, u32 magic) 15 { 16 hdr->info0 = FIELD_PREP(HAL_DESC_HDR_INFO0_OWNER, owner) | 17 FIELD_PREP(HAL_DESC_HDR_INFO0_BUF_TYPE, buffer_type); 18 19 /* Magic pattern in reserved bits for debugging */ 20 hdr->info0 |= FIELD_PREP(HAL_DESC_HDR_INFO0_DBG_RESERVED, magic); 21 } 22 23 static int ath11k_hal_reo_cmd_queue_stats(struct hal_tlv_hdr *tlv, 24 struct ath11k_hal_reo_cmd *cmd) 25 { 26 struct hal_reo_get_queue_stats *desc; 27 28 tlv->tl = FIELD_PREP(HAL_TLV_HDR_TAG, HAL_REO_GET_QUEUE_STATS) | 29 FIELD_PREP(HAL_TLV_HDR_LEN, sizeof(*desc)); 30 31 desc = (struct hal_reo_get_queue_stats *)tlv->value; 32 memset_startat(desc, 0, queue_addr_lo); 33 34 desc->cmd.info0 &= ~HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED; 35 if (cmd->flag & HAL_REO_CMD_FLG_NEED_STATUS) 36 desc->cmd.info0 |= HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED; 37 38 desc->queue_addr_lo = cmd->addr_lo; 39 desc->info0 = FIELD_PREP(HAL_REO_GET_QUEUE_STATS_INFO0_QUEUE_ADDR_HI, 40 cmd->addr_hi); 41 if (cmd->flag & HAL_REO_CMD_FLG_STATS_CLEAR) 42 desc->info0 |= HAL_REO_GET_QUEUE_STATS_INFO0_CLEAR_STATS; 43 44 return FIELD_GET(HAL_REO_CMD_HDR_INFO0_CMD_NUMBER, desc->cmd.info0); 45 } 46 47 static int ath11k_hal_reo_cmd_flush_cache(struct ath11k_hal *hal, struct hal_tlv_hdr *tlv, 48 struct ath11k_hal_reo_cmd *cmd) 49 { 50 struct hal_reo_flush_cache *desc; 51 u8 avail_slot = ffz(hal->avail_blk_resource); 52 53 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_BLOCK_LATER) { 54 if (avail_slot >= HAL_MAX_AVAIL_BLK_RES) 55 return -ENOSPC; 56 57 hal->current_blk_index = avail_slot; 58 } 59 60 tlv->tl = FIELD_PREP(HAL_TLV_HDR_TAG, HAL_REO_FLUSH_CACHE) | 61 FIELD_PREP(HAL_TLV_HDR_LEN, sizeof(*desc)); 62 63 desc = (struct hal_reo_flush_cache *)tlv->value; 64 memset_startat(desc, 0, cache_addr_lo); 65 66 desc->cmd.info0 &= ~HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED; 67 if (cmd->flag & HAL_REO_CMD_FLG_NEED_STATUS) 68 desc->cmd.info0 |= HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED; 69 70 desc->cache_addr_lo = cmd->addr_lo; 71 desc->info0 = FIELD_PREP(HAL_REO_FLUSH_CACHE_INFO0_CACHE_ADDR_HI, 72 cmd->addr_hi); 73 74 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_FWD_ALL_MPDUS) 75 desc->info0 |= HAL_REO_FLUSH_CACHE_INFO0_FWD_ALL_MPDUS; 76 77 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_BLOCK_LATER) { 78 desc->info0 |= HAL_REO_FLUSH_CACHE_INFO0_BLOCK_CACHE_USAGE; 79 desc->info0 |= 80 FIELD_PREP(HAL_REO_FLUSH_CACHE_INFO0_BLOCK_RESRC_IDX, 81 avail_slot); 82 } 83 84 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_NO_INVAL) 85 desc->info0 |= HAL_REO_FLUSH_CACHE_INFO0_FLUSH_WO_INVALIDATE; 86 87 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_ALL) 88 desc->info0 |= HAL_REO_FLUSH_CACHE_INFO0_FLUSH_ALL; 89 90 return FIELD_GET(HAL_REO_CMD_HDR_INFO0_CMD_NUMBER, desc->cmd.info0); 91 } 92 93 static int ath11k_hal_reo_cmd_update_rx_queue(struct hal_tlv_hdr *tlv, 94 struct ath11k_hal_reo_cmd *cmd) 95 { 96 struct hal_reo_update_rx_queue *desc; 97 98 tlv->tl = FIELD_PREP(HAL_TLV_HDR_TAG, HAL_REO_UPDATE_RX_REO_QUEUE) | 99 FIELD_PREP(HAL_TLV_HDR_LEN, sizeof(*desc)); 100 101 desc = (struct hal_reo_update_rx_queue *)tlv->value; 102 memset_startat(desc, 0, queue_addr_lo); 103 104 desc->cmd.info0 &= ~HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED; 105 if (cmd->flag & HAL_REO_CMD_FLG_NEED_STATUS) 106 desc->cmd.info0 |= HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED; 107 108 desc->queue_addr_lo = cmd->addr_lo; 109 desc->info0 = 110 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_QUEUE_ADDR_HI, 111 cmd->addr_hi) | 112 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RX_QUEUE_NUM, 113 !!(cmd->upd0 & HAL_REO_CMD_UPD0_RX_QUEUE_NUM)) | 114 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_VLD, 115 !!(cmd->upd0 & HAL_REO_CMD_UPD0_VLD)) | 116 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_ASSOC_LNK_DESC_CNT, 117 !!(cmd->upd0 & HAL_REO_CMD_UPD0_ALDC)) | 118 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_DIS_DUP_DETECTION, 119 !!(cmd->upd0 & HAL_REO_CMD_UPD0_DIS_DUP_DETECTION)) | 120 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SOFT_REORDER_EN, 121 !!(cmd->upd0 & HAL_REO_CMD_UPD0_SOFT_REORDER_EN)) | 122 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_AC, 123 !!(cmd->upd0 & HAL_REO_CMD_UPD0_AC)) | 124 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BAR, 125 !!(cmd->upd0 & HAL_REO_CMD_UPD0_BAR)) | 126 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RETRY, 127 !!(cmd->upd0 & HAL_REO_CMD_UPD0_RETRY)) | 128 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_CHECK_2K_MODE, 129 !!(cmd->upd0 & HAL_REO_CMD_UPD0_CHECK_2K_MODE)) | 130 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_OOR_MODE, 131 !!(cmd->upd0 & HAL_REO_CMD_UPD0_OOR_MODE)) | 132 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BA_WINDOW_SIZE, 133 !!(cmd->upd0 & HAL_REO_CMD_UPD0_BA_WINDOW_SIZE)) | 134 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_CHECK, 135 !!(cmd->upd0 & HAL_REO_CMD_UPD0_PN_CHECK)) | 136 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_EVEN_PN, 137 !!(cmd->upd0 & HAL_REO_CMD_UPD0_EVEN_PN)) | 138 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_UNEVEN_PN, 139 !!(cmd->upd0 & HAL_REO_CMD_UPD0_UNEVEN_PN)) | 140 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_HANDLE_ENABLE, 141 !!(cmd->upd0 & HAL_REO_CMD_UPD0_PN_HANDLE_ENABLE)) | 142 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_SIZE, 143 !!(cmd->upd0 & HAL_REO_CMD_UPD0_PN_SIZE)) | 144 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_IGNORE_AMPDU_FLG, 145 !!(cmd->upd0 & HAL_REO_CMD_UPD0_IGNORE_AMPDU_FLG)) | 146 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SVLD, 147 !!(cmd->upd0 & HAL_REO_CMD_UPD0_SVLD)) | 148 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SSN, 149 !!(cmd->upd0 & HAL_REO_CMD_UPD0_SSN)) | 150 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SEQ_2K_ERR, 151 !!(cmd->upd0 & HAL_REO_CMD_UPD0_SEQ_2K_ERR)) | 152 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_VALID, 153 !!(cmd->upd0 & HAL_REO_CMD_UPD0_PN_VALID)) | 154 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN, 155 !!(cmd->upd0 & HAL_REO_CMD_UPD0_PN)); 156 157 desc->info1 = 158 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_RX_QUEUE_NUMBER, 159 cmd->rx_queue_num) | 160 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_VLD, 161 !!(cmd->upd1 & HAL_REO_CMD_UPD1_VLD)) | 162 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_ASSOC_LNK_DESC_COUNTER, 163 FIELD_GET(HAL_REO_CMD_UPD1_ALDC, cmd->upd1)) | 164 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_DIS_DUP_DETECTION, 165 !!(cmd->upd1 & HAL_REO_CMD_UPD1_DIS_DUP_DETECTION)) | 166 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_SOFT_REORDER_EN, 167 !!(cmd->upd1 & HAL_REO_CMD_UPD1_SOFT_REORDER_EN)) | 168 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_AC, 169 FIELD_GET(HAL_REO_CMD_UPD1_AC, cmd->upd1)) | 170 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_BAR, 171 !!(cmd->upd1 & HAL_REO_CMD_UPD1_BAR)) | 172 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_CHECK_2K_MODE, 173 !!(cmd->upd1 & HAL_REO_CMD_UPD1_CHECK_2K_MODE)) | 174 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_RETRY, 175 !!(cmd->upd1 & HAL_REO_CMD_UPD1_RETRY)) | 176 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_OOR_MODE, 177 !!(cmd->upd1 & HAL_REO_CMD_UPD1_OOR_MODE)) | 178 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_PN_CHECK, 179 !!(cmd->upd1 & HAL_REO_CMD_UPD1_PN_CHECK)) | 180 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_EVEN_PN, 181 !!(cmd->upd1 & HAL_REO_CMD_UPD1_EVEN_PN)) | 182 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_UNEVEN_PN, 183 !!(cmd->upd1 & HAL_REO_CMD_UPD1_UNEVEN_PN)) | 184 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_PN_HANDLE_ENABLE, 185 !!(cmd->upd1 & HAL_REO_CMD_UPD1_PN_HANDLE_ENABLE)) | 186 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_IGNORE_AMPDU_FLG, 187 !!(cmd->upd1 & HAL_REO_CMD_UPD1_IGNORE_AMPDU_FLG)); 188 189 if (cmd->pn_size == 24) 190 cmd->pn_size = HAL_RX_REO_QUEUE_PN_SIZE_24; 191 else if (cmd->pn_size == 48) 192 cmd->pn_size = HAL_RX_REO_QUEUE_PN_SIZE_48; 193 else if (cmd->pn_size == 128) 194 cmd->pn_size = HAL_RX_REO_QUEUE_PN_SIZE_128; 195 196 if (cmd->ba_window_size < 1) 197 cmd->ba_window_size = 1; 198 199 if (cmd->ba_window_size == 1) 200 cmd->ba_window_size++; 201 202 desc->info2 = 203 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO2_BA_WINDOW_SIZE, 204 cmd->ba_window_size - 1) | 205 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO2_PN_SIZE, cmd->pn_size) | 206 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO2_SVLD, 207 !!(cmd->upd2 & HAL_REO_CMD_UPD2_SVLD)) | 208 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO2_SSN, 209 FIELD_GET(HAL_REO_CMD_UPD2_SSN, cmd->upd2)) | 210 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO2_SEQ_2K_ERR, 211 !!(cmd->upd2 & HAL_REO_CMD_UPD2_SEQ_2K_ERR)) | 212 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO2_PN_ERR, 213 !!(cmd->upd2 & HAL_REO_CMD_UPD2_PN_ERR)); 214 215 return FIELD_GET(HAL_REO_CMD_HDR_INFO0_CMD_NUMBER, desc->cmd.info0); 216 } 217 218 int ath11k_hal_reo_cmd_send(struct ath11k_base *ab, struct hal_srng *srng, 219 enum hal_reo_cmd_type type, 220 struct ath11k_hal_reo_cmd *cmd) 221 { 222 struct hal_tlv_hdr *reo_desc; 223 int ret; 224 225 spin_lock_bh(&srng->lock); 226 227 ath11k_hal_srng_access_begin(ab, srng); 228 reo_desc = (struct hal_tlv_hdr *)ath11k_hal_srng_src_get_next_entry(ab, srng); 229 if (!reo_desc) { 230 ret = -ENOBUFS; 231 goto out; 232 } 233 234 switch (type) { 235 case HAL_REO_CMD_GET_QUEUE_STATS: 236 ret = ath11k_hal_reo_cmd_queue_stats(reo_desc, cmd); 237 break; 238 case HAL_REO_CMD_FLUSH_CACHE: 239 ret = ath11k_hal_reo_cmd_flush_cache(&ab->hal, reo_desc, cmd); 240 break; 241 case HAL_REO_CMD_UPDATE_RX_QUEUE: 242 ret = ath11k_hal_reo_cmd_update_rx_queue(reo_desc, cmd); 243 break; 244 case HAL_REO_CMD_FLUSH_QUEUE: 245 case HAL_REO_CMD_UNBLOCK_CACHE: 246 case HAL_REO_CMD_FLUSH_TIMEOUT_LIST: 247 ath11k_warn(ab, "Unsupported reo command %d\n", type); 248 ret = -ENOTSUPP; 249 break; 250 default: 251 ath11k_warn(ab, "Unknown reo command %d\n", type); 252 ret = -EINVAL; 253 break; 254 } 255 256 ath11k_dp_shadow_start_timer(ab, srng, &ab->dp.reo_cmd_timer); 257 258 out: 259 ath11k_hal_srng_access_end(ab, srng); 260 spin_unlock_bh(&srng->lock); 261 262 return ret; 263 } 264 265 void ath11k_hal_rx_buf_addr_info_set(void *desc, dma_addr_t paddr, 266 u32 cookie, u8 manager) 267 { 268 struct ath11k_buffer_addr *binfo = desc; 269 u32 paddr_lo, paddr_hi; 270 271 paddr_lo = lower_32_bits(paddr); 272 paddr_hi = upper_32_bits(paddr); 273 binfo->info0 = FIELD_PREP(BUFFER_ADDR_INFO0_ADDR, paddr_lo); 274 binfo->info1 = FIELD_PREP(BUFFER_ADDR_INFO1_ADDR, paddr_hi) | 275 FIELD_PREP(BUFFER_ADDR_INFO1_SW_COOKIE, cookie) | 276 FIELD_PREP(BUFFER_ADDR_INFO1_RET_BUF_MGR, manager); 277 } 278 279 void ath11k_hal_rx_buf_addr_info_get(void *desc, dma_addr_t *paddr, 280 u32 *cookie, u8 *rbm) 281 { 282 struct ath11k_buffer_addr *binfo = desc; 283 284 *paddr = 285 (((u64)FIELD_GET(BUFFER_ADDR_INFO1_ADDR, binfo->info1)) << 32) | 286 FIELD_GET(BUFFER_ADDR_INFO0_ADDR, binfo->info0); 287 *cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, binfo->info1); 288 *rbm = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR, binfo->info1); 289 } 290 291 void ath11k_hal_rx_msdu_link_info_get(void *link_desc, u32 *num_msdus, 292 u32 *msdu_cookies, 293 enum hal_rx_buf_return_buf_manager *rbm) 294 { 295 struct hal_rx_msdu_link *link = link_desc; 296 struct hal_rx_msdu_details *msdu; 297 int i; 298 299 *num_msdus = HAL_NUM_RX_MSDUS_PER_LINK_DESC; 300 301 msdu = &link->msdu_link[0]; 302 *rbm = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR, 303 msdu->buf_addr_info.info1); 304 305 for (i = 0; i < *num_msdus; i++) { 306 msdu = &link->msdu_link[i]; 307 308 if (!FIELD_GET(BUFFER_ADDR_INFO0_ADDR, 309 msdu->buf_addr_info.info0)) { 310 *num_msdus = i; 311 break; 312 } 313 *msdu_cookies = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, 314 msdu->buf_addr_info.info1); 315 msdu_cookies++; 316 } 317 } 318 319 int ath11k_hal_desc_reo_parse_err(struct ath11k_base *ab, u32 *rx_desc, 320 dma_addr_t *paddr, u32 *desc_bank) 321 { 322 struct hal_reo_dest_ring *desc = (struct hal_reo_dest_ring *)rx_desc; 323 enum hal_reo_dest_ring_push_reason push_reason; 324 enum hal_reo_dest_ring_error_code err_code; 325 326 push_reason = FIELD_GET(HAL_REO_DEST_RING_INFO0_PUSH_REASON, 327 desc->info0); 328 err_code = FIELD_GET(HAL_REO_DEST_RING_INFO0_ERROR_CODE, 329 desc->info0); 330 ab->soc_stats.reo_error[err_code]++; 331 332 if (push_reason != HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED && 333 push_reason != HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION) { 334 ath11k_warn(ab, "expected error push reason code, received %d\n", 335 push_reason); 336 return -EINVAL; 337 } 338 339 if (FIELD_GET(HAL_REO_DEST_RING_INFO0_BUFFER_TYPE, desc->info0) != 340 HAL_REO_DEST_RING_BUFFER_TYPE_LINK_DESC) { 341 ath11k_warn(ab, "expected buffer type link_desc"); 342 return -EINVAL; 343 } 344 345 ath11k_hal_rx_reo_ent_paddr_get(ab, rx_desc, paddr, desc_bank); 346 347 return 0; 348 } 349 350 int ath11k_hal_wbm_desc_parse_err(struct ath11k_base *ab, void *desc, 351 struct hal_rx_wbm_rel_info *rel_info) 352 { 353 struct hal_wbm_release_ring *wbm_desc = desc; 354 enum hal_wbm_rel_desc_type type; 355 enum hal_wbm_rel_src_module rel_src; 356 enum hal_rx_buf_return_buf_manager ret_buf_mgr; 357 358 type = FIELD_GET(HAL_WBM_RELEASE_INFO0_DESC_TYPE, 359 wbm_desc->info0); 360 /* We expect only WBM_REL buffer type */ 361 if (type != HAL_WBM_REL_DESC_TYPE_REL_MSDU) { 362 WARN_ON(1); 363 return -EINVAL; 364 } 365 366 rel_src = FIELD_GET(HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE, 367 wbm_desc->info0); 368 if (rel_src != HAL_WBM_REL_SRC_MODULE_RXDMA && 369 rel_src != HAL_WBM_REL_SRC_MODULE_REO) 370 return -EINVAL; 371 372 ret_buf_mgr = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR, 373 wbm_desc->buf_addr_info.info1); 374 if (ret_buf_mgr != HAL_RX_BUF_RBM_SW3_BM) { 375 ab->soc_stats.invalid_rbm++; 376 return -EINVAL; 377 } 378 379 rel_info->cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, 380 wbm_desc->buf_addr_info.info1); 381 rel_info->err_rel_src = rel_src; 382 if (rel_src == HAL_WBM_REL_SRC_MODULE_REO) { 383 rel_info->push_reason = 384 FIELD_GET(HAL_WBM_RELEASE_INFO0_REO_PUSH_REASON, 385 wbm_desc->info0); 386 rel_info->err_code = 387 FIELD_GET(HAL_WBM_RELEASE_INFO0_REO_ERROR_CODE, 388 wbm_desc->info0); 389 } else { 390 rel_info->push_reason = 391 FIELD_GET(HAL_WBM_RELEASE_INFO0_RXDMA_PUSH_REASON, 392 wbm_desc->info0); 393 rel_info->err_code = 394 FIELD_GET(HAL_WBM_RELEASE_INFO0_RXDMA_ERROR_CODE, 395 wbm_desc->info0); 396 } 397 398 rel_info->first_msdu = FIELD_GET(HAL_WBM_RELEASE_INFO2_FIRST_MSDU, 399 wbm_desc->info2); 400 rel_info->last_msdu = FIELD_GET(HAL_WBM_RELEASE_INFO2_LAST_MSDU, 401 wbm_desc->info2); 402 return 0; 403 } 404 405 void ath11k_hal_rx_reo_ent_paddr_get(struct ath11k_base *ab, void *desc, 406 dma_addr_t *paddr, u32 *desc_bank) 407 { 408 struct ath11k_buffer_addr *buff_addr = desc; 409 410 *paddr = ((u64)(FIELD_GET(BUFFER_ADDR_INFO1_ADDR, buff_addr->info1)) << 32) | 411 FIELD_GET(BUFFER_ADDR_INFO0_ADDR, buff_addr->info0); 412 413 *desc_bank = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, buff_addr->info1); 414 } 415 416 void ath11k_hal_rx_msdu_link_desc_set(struct ath11k_base *ab, void *desc, 417 void *link_desc, 418 enum hal_wbm_rel_bm_act action) 419 { 420 struct hal_wbm_release_ring *dst_desc = desc; 421 struct hal_wbm_release_ring *src_desc = link_desc; 422 423 dst_desc->buf_addr_info = src_desc->buf_addr_info; 424 dst_desc->info0 |= FIELD_PREP(HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE, 425 HAL_WBM_REL_SRC_MODULE_SW) | 426 FIELD_PREP(HAL_WBM_RELEASE_INFO0_BM_ACTION, action) | 427 FIELD_PREP(HAL_WBM_RELEASE_INFO0_DESC_TYPE, 428 HAL_WBM_REL_DESC_TYPE_MSDU_LINK); 429 } 430 431 void ath11k_hal_reo_status_queue_stats(struct ath11k_base *ab, u32 *reo_desc, 432 struct hal_reo_status *status) 433 { 434 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc; 435 struct hal_reo_get_queue_stats_status *desc = 436 (struct hal_reo_get_queue_stats_status *)tlv->value; 437 438 status->uniform_hdr.cmd_num = 439 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM, 440 desc->hdr.info0); 441 status->uniform_hdr.cmd_status = 442 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS, 443 desc->hdr.info0); 444 445 ath11k_dbg(ab, ATH11K_DBG_HAL, "Queue stats status:\n"); 446 ath11k_dbg(ab, ATH11K_DBG_HAL, "header: cmd_num %d status %d\n", 447 status->uniform_hdr.cmd_num, 448 status->uniform_hdr.cmd_status); 449 ath11k_dbg(ab, ATH11K_DBG_HAL, "ssn %ld cur_idx %ld\n", 450 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_SSN, 451 desc->info0), 452 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_CUR_IDX, 453 desc->info0)); 454 ath11k_dbg(ab, ATH11K_DBG_HAL, "pn = [%08x, %08x, %08x, %08x]\n", 455 desc->pn[0], desc->pn[1], desc->pn[2], desc->pn[3]); 456 ath11k_dbg(ab, ATH11K_DBG_HAL, 457 "last_rx: enqueue_tstamp %08x dequeue_tstamp %08x\n", 458 desc->last_rx_enqueue_timestamp, 459 desc->last_rx_dequeue_timestamp); 460 ath11k_dbg(ab, ATH11K_DBG_HAL, 461 "rx_bitmap [%08x %08x %08x %08x %08x %08x %08x %08x]\n", 462 desc->rx_bitmap[0], desc->rx_bitmap[1], desc->rx_bitmap[2], 463 desc->rx_bitmap[3], desc->rx_bitmap[4], desc->rx_bitmap[5], 464 desc->rx_bitmap[6], desc->rx_bitmap[7]); 465 ath11k_dbg(ab, ATH11K_DBG_HAL, "count: cur_mpdu %ld cur_msdu %ld\n", 466 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MPDU_COUNT, 467 desc->info1), 468 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MSDU_COUNT, 469 desc->info1)); 470 ath11k_dbg(ab, ATH11K_DBG_HAL, "fwd_timeout %ld fwd_bar %ld dup_count %ld\n", 471 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_TIMEOUT_COUNT, 472 desc->info2), 473 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_FDTB_COUNT, 474 desc->info2), 475 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_DUPLICATE_COUNT, 476 desc->info2)); 477 ath11k_dbg(ab, ATH11K_DBG_HAL, "frames_in_order %ld bar_rcvd %ld\n", 478 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_FIO_COUNT, 479 desc->info3), 480 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_BAR_RCVD_CNT, 481 desc->info3)); 482 ath11k_dbg(ab, ATH11K_DBG_HAL, "num_mpdus %d num_msdus %d total_bytes %d\n", 483 desc->num_mpdu_frames, desc->num_msdu_frames, 484 desc->total_bytes); 485 ath11k_dbg(ab, ATH11K_DBG_HAL, "late_rcvd %ld win_jump_2k %ld hole_cnt %ld\n", 486 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_LATE_RX_MPDU, 487 desc->info4), 488 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_WINDOW_JMP2K, 489 desc->info4), 490 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_HOLE_COUNT, 491 desc->info4)); 492 ath11k_dbg(ab, ATH11K_DBG_HAL, "looping count %ld\n", 493 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO5_LOOPING_CNT, 494 desc->info5)); 495 } 496 497 int ath11k_hal_reo_process_status(u8 *reo_desc, u8 *status) 498 { 499 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc; 500 struct hal_reo_status_hdr *hdr; 501 502 hdr = (struct hal_reo_status_hdr *)tlv->value; 503 *status = FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS, hdr->info0); 504 505 return FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM, hdr->info0); 506 } 507 508 void ath11k_hal_reo_flush_queue_status(struct ath11k_base *ab, u32 *reo_desc, 509 struct hal_reo_status *status) 510 { 511 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc; 512 struct hal_reo_flush_queue_status *desc = 513 (struct hal_reo_flush_queue_status *)tlv->value; 514 515 status->uniform_hdr.cmd_num = 516 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM, 517 desc->hdr.info0); 518 status->uniform_hdr.cmd_status = 519 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS, 520 desc->hdr.info0); 521 status->u.flush_queue.err_detected = 522 FIELD_GET(HAL_REO_FLUSH_QUEUE_INFO0_ERR_DETECTED, 523 desc->info0); 524 } 525 526 void ath11k_hal_reo_flush_cache_status(struct ath11k_base *ab, u32 *reo_desc, 527 struct hal_reo_status *status) 528 { 529 struct ath11k_hal *hal = &ab->hal; 530 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc; 531 struct hal_reo_flush_cache_status *desc = 532 (struct hal_reo_flush_cache_status *)tlv->value; 533 534 status->uniform_hdr.cmd_num = 535 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM, 536 desc->hdr.info0); 537 status->uniform_hdr.cmd_status = 538 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS, 539 desc->hdr.info0); 540 541 status->u.flush_cache.err_detected = 542 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_IS_ERR, 543 desc->info0); 544 status->u.flush_cache.err_code = 545 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_BLOCK_ERR_CODE, 546 desc->info0); 547 if (!status->u.flush_cache.err_code) 548 hal->avail_blk_resource |= BIT(hal->current_blk_index); 549 550 status->u.flush_cache.cache_controller_flush_status_hit = 551 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_STATUS_HIT, 552 desc->info0); 553 554 status->u.flush_cache.cache_controller_flush_status_desc_type = 555 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_DESC_TYPE, 556 desc->info0); 557 status->u.flush_cache.cache_controller_flush_status_client_id = 558 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_CLIENT_ID, 559 desc->info0); 560 status->u.flush_cache.cache_controller_flush_status_err = 561 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_ERR, 562 desc->info0); 563 status->u.flush_cache.cache_controller_flush_status_cnt = 564 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_COUNT, 565 desc->info0); 566 } 567 568 void ath11k_hal_reo_unblk_cache_status(struct ath11k_base *ab, u32 *reo_desc, 569 struct hal_reo_status *status) 570 { 571 struct ath11k_hal *hal = &ab->hal; 572 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc; 573 struct hal_reo_unblock_cache_status *desc = 574 (struct hal_reo_unblock_cache_status *)tlv->value; 575 576 status->uniform_hdr.cmd_num = 577 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM, 578 desc->hdr.info0); 579 status->uniform_hdr.cmd_status = 580 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS, 581 desc->hdr.info0); 582 583 status->u.unblock_cache.err_detected = 584 FIELD_GET(HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_IS_ERR, 585 desc->info0); 586 status->u.unblock_cache.unblock_type = 587 FIELD_GET(HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_TYPE, 588 desc->info0); 589 590 if (!status->u.unblock_cache.err_detected && 591 status->u.unblock_cache.unblock_type == 592 HAL_REO_STATUS_UNBLOCK_BLOCKING_RESOURCE) 593 hal->avail_blk_resource &= ~BIT(hal->current_blk_index); 594 } 595 596 void ath11k_hal_reo_flush_timeout_list_status(struct ath11k_base *ab, 597 u32 *reo_desc, 598 struct hal_reo_status *status) 599 { 600 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc; 601 struct hal_reo_flush_timeout_list_status *desc = 602 (struct hal_reo_flush_timeout_list_status *)tlv->value; 603 604 status->uniform_hdr.cmd_num = 605 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM, 606 desc->hdr.info0); 607 status->uniform_hdr.cmd_status = 608 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS, 609 desc->hdr.info0); 610 611 status->u.timeout_list.err_detected = 612 FIELD_GET(HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_IS_ERR, 613 desc->info0); 614 status->u.timeout_list.list_empty = 615 FIELD_GET(HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_LIST_EMPTY, 616 desc->info0); 617 618 status->u.timeout_list.release_desc_cnt = 619 FIELD_GET(HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_REL_DESC_COUNT, 620 desc->info1); 621 status->u.timeout_list.fwd_buf_cnt = 622 FIELD_GET(HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_FWD_BUF_COUNT, 623 desc->info1); 624 } 625 626 void ath11k_hal_reo_desc_thresh_reached_status(struct ath11k_base *ab, 627 u32 *reo_desc, 628 struct hal_reo_status *status) 629 { 630 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc; 631 struct hal_reo_desc_thresh_reached_status *desc = 632 (struct hal_reo_desc_thresh_reached_status *)tlv->value; 633 634 status->uniform_hdr.cmd_num = 635 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM, 636 desc->hdr.info0); 637 status->uniform_hdr.cmd_status = 638 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS, 639 desc->hdr.info0); 640 641 status->u.desc_thresh_reached.threshold_idx = 642 FIELD_GET(HAL_REO_DESC_THRESH_STATUS_INFO0_THRESH_INDEX, 643 desc->info0); 644 645 status->u.desc_thresh_reached.link_desc_counter0 = 646 FIELD_GET(HAL_REO_DESC_THRESH_STATUS_INFO1_LINK_DESC_COUNTER0, 647 desc->info1); 648 649 status->u.desc_thresh_reached.link_desc_counter1 = 650 FIELD_GET(HAL_REO_DESC_THRESH_STATUS_INFO2_LINK_DESC_COUNTER1, 651 desc->info2); 652 653 status->u.desc_thresh_reached.link_desc_counter2 = 654 FIELD_GET(HAL_REO_DESC_THRESH_STATUS_INFO3_LINK_DESC_COUNTER2, 655 desc->info3); 656 657 status->u.desc_thresh_reached.link_desc_counter_sum = 658 FIELD_GET(HAL_REO_DESC_THRESH_STATUS_INFO4_LINK_DESC_COUNTER_SUM, 659 desc->info4); 660 } 661 662 void ath11k_hal_reo_update_rx_reo_queue_status(struct ath11k_base *ab, 663 u32 *reo_desc, 664 struct hal_reo_status *status) 665 { 666 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc; 667 struct hal_reo_status_hdr *desc = 668 (struct hal_reo_status_hdr *)tlv->value; 669 670 status->uniform_hdr.cmd_num = 671 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM, 672 desc->info0); 673 status->uniform_hdr.cmd_status = 674 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS, 675 desc->info0); 676 } 677 678 u32 ath11k_hal_reo_qdesc_size(u32 ba_window_size, u8 tid) 679 { 680 u32 num_ext_desc; 681 682 if (ba_window_size <= 1) { 683 if (tid != HAL_DESC_REO_NON_QOS_TID) 684 num_ext_desc = 1; 685 else 686 num_ext_desc = 0; 687 } else if (ba_window_size <= 105) { 688 num_ext_desc = 1; 689 } else if (ba_window_size <= 210) { 690 num_ext_desc = 2; 691 } else { 692 num_ext_desc = 3; 693 } 694 695 return sizeof(struct hal_rx_reo_queue) + 696 (num_ext_desc * sizeof(struct hal_rx_reo_queue_ext)); 697 } 698 699 void ath11k_hal_reo_qdesc_setup(void *vaddr, int tid, u32 ba_window_size, 700 u32 start_seq, enum hal_pn_type type) 701 { 702 struct hal_rx_reo_queue *qdesc = vaddr; 703 struct hal_rx_reo_queue_ext *ext_desc; 704 705 memset(qdesc, 0, sizeof(*qdesc)); 706 707 ath11k_hal_reo_set_desc_hdr(&qdesc->desc_hdr, HAL_DESC_REO_OWNED, 708 HAL_DESC_REO_QUEUE_DESC, 709 REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_0); 710 711 qdesc->rx_queue_num = FIELD_PREP(HAL_RX_REO_QUEUE_RX_QUEUE_NUMBER, tid); 712 713 qdesc->info0 = 714 FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_VLD, 1) | 715 FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_ASSOC_LNK_DESC_COUNTER, 1) | 716 FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_AC, ath11k_tid_to_ac(tid)); 717 718 if (ba_window_size < 1) 719 ba_window_size = 1; 720 721 if (ba_window_size == 1 && tid != HAL_DESC_REO_NON_QOS_TID) 722 ba_window_size++; 723 724 if (ba_window_size == 1) 725 qdesc->info0 |= FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_RETRY, 1); 726 727 qdesc->info0 |= FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_BA_WINDOW_SIZE, 728 ba_window_size - 1); 729 switch (type) { 730 case HAL_PN_TYPE_NONE: 731 case HAL_PN_TYPE_WAPI_EVEN: 732 case HAL_PN_TYPE_WAPI_UNEVEN: 733 break; 734 case HAL_PN_TYPE_WPA: 735 qdesc->info0 |= 736 FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_PN_CHECK, 1) | 737 FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_PN_SIZE, 738 HAL_RX_REO_QUEUE_PN_SIZE_48); 739 break; 740 } 741 742 /* TODO: Set Ignore ampdu flags based on BA window size and/or 743 * AMPDU capabilities 744 */ 745 qdesc->info0 |= FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_IGNORE_AMPDU_FLG, 1); 746 747 qdesc->info1 |= FIELD_PREP(HAL_RX_REO_QUEUE_INFO1_SVLD, 0); 748 749 if (start_seq <= 0xfff) 750 qdesc->info1 = FIELD_PREP(HAL_RX_REO_QUEUE_INFO1_SSN, 751 start_seq); 752 753 if (tid == HAL_DESC_REO_NON_QOS_TID) 754 return; 755 756 ext_desc = qdesc->ext_desc; 757 758 /* TODO: HW queue descriptors are currently allocated for max BA 759 * window size for all QOS TIDs so that same descriptor can be used 760 * later when ADDBA request is received. This should be changed to 761 * allocate HW queue descriptors based on BA window size being 762 * negotiated (0 for non BA cases), and reallocate when BA window 763 * size changes and also send WMI message to FW to change the REO 764 * queue descriptor in Rx peer entry as part of dp_rx_tid_update. 765 */ 766 memset(ext_desc, 0, sizeof(*ext_desc)); 767 ath11k_hal_reo_set_desc_hdr(&ext_desc->desc_hdr, HAL_DESC_REO_OWNED, 768 HAL_DESC_REO_QUEUE_EXT_DESC, 769 REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_1); 770 ext_desc++; 771 memset(ext_desc, 0, sizeof(*ext_desc)); 772 ath11k_hal_reo_set_desc_hdr(&ext_desc->desc_hdr, HAL_DESC_REO_OWNED, 773 HAL_DESC_REO_QUEUE_EXT_DESC, 774 REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_2); 775 ext_desc++; 776 memset(ext_desc, 0, sizeof(*ext_desc)); 777 ath11k_hal_reo_set_desc_hdr(&ext_desc->desc_hdr, HAL_DESC_REO_OWNED, 778 HAL_DESC_REO_QUEUE_EXT_DESC, 779 REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_3); 780 } 781 782 void ath11k_hal_reo_init_cmd_ring(struct ath11k_base *ab, 783 struct hal_srng *srng) 784 { 785 struct hal_srng_params params; 786 struct hal_tlv_hdr *tlv; 787 struct hal_reo_get_queue_stats *desc; 788 int i, cmd_num = 1; 789 int entry_size; 790 u8 *entry; 791 792 memset(¶ms, 0, sizeof(params)); 793 794 entry_size = ath11k_hal_srng_get_entrysize(ab, HAL_REO_CMD); 795 ath11k_hal_srng_get_params(ab, srng, ¶ms); 796 entry = (u8 *)params.ring_base_vaddr; 797 798 for (i = 0; i < params.num_entries; i++) { 799 tlv = (struct hal_tlv_hdr *)entry; 800 desc = (struct hal_reo_get_queue_stats *)tlv->value; 801 desc->cmd.info0 = 802 FIELD_PREP(HAL_REO_CMD_HDR_INFO0_CMD_NUMBER, cmd_num++); 803 entry += entry_size; 804 } 805 } 806 807 #define HAL_MAX_UL_MU_USERS 37 808 static inline void 809 ath11k_hal_rx_handle_ofdma_info(void *rx_tlv, 810 struct hal_rx_user_status *rx_user_status) 811 { 812 struct hal_rx_ppdu_end_user_stats *ppdu_end_user = rx_tlv; 813 814 rx_user_status->ul_ofdma_user_v0_word0 = __le32_to_cpu(ppdu_end_user->info6); 815 816 rx_user_status->ul_ofdma_user_v0_word1 = __le32_to_cpu(ppdu_end_user->info10); 817 } 818 819 static inline void 820 ath11k_hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo, 821 struct hal_rx_user_status *rx_user_status) 822 { 823 struct hal_rx_ppdu_end_user_stats *ppdu_end_user = rx_tlv; 824 825 rx_user_status->mpdu_ok_byte_count = 826 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO8_MPDU_OK_BYTE_COUNT, 827 __le32_to_cpu(ppdu_end_user->info8)); 828 rx_user_status->mpdu_err_byte_count = 829 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO9_MPDU_ERR_BYTE_COUNT, 830 __le32_to_cpu(ppdu_end_user->info9)); 831 } 832 833 static inline void 834 ath11k_hal_rx_populate_mu_user_info(void *rx_tlv, struct hal_rx_mon_ppdu_info *ppdu_info, 835 struct hal_rx_user_status *rx_user_status) 836 { 837 rx_user_status->ast_index = ppdu_info->ast_index; 838 rx_user_status->tid = ppdu_info->tid; 839 rx_user_status->tcp_msdu_count = 840 ppdu_info->tcp_msdu_count; 841 rx_user_status->udp_msdu_count = 842 ppdu_info->udp_msdu_count; 843 rx_user_status->other_msdu_count = 844 ppdu_info->other_msdu_count; 845 rx_user_status->frame_control = ppdu_info->frame_control; 846 rx_user_status->frame_control_info_valid = 847 ppdu_info->frame_control_info_valid; 848 rx_user_status->data_sequence_control_info_valid = 849 ppdu_info->data_sequence_control_info_valid; 850 rx_user_status->first_data_seq_ctrl = 851 ppdu_info->first_data_seq_ctrl; 852 rx_user_status->preamble_type = ppdu_info->preamble_type; 853 rx_user_status->ht_flags = ppdu_info->ht_flags; 854 rx_user_status->vht_flags = ppdu_info->vht_flags; 855 rx_user_status->he_flags = ppdu_info->he_flags; 856 rx_user_status->rs_flags = ppdu_info->rs_flags; 857 858 rx_user_status->mpdu_cnt_fcs_ok = 859 ppdu_info->num_mpdu_fcs_ok; 860 rx_user_status->mpdu_cnt_fcs_err = 861 ppdu_info->num_mpdu_fcs_err; 862 863 ath11k_hal_rx_populate_byte_count(rx_tlv, ppdu_info, rx_user_status); 864 } 865 866 static u16 ath11k_hal_rx_mpduinfo_get_peerid(struct ath11k_base *ab, 867 struct hal_rx_mpdu_info *mpdu_info) 868 { 869 return ab->hw_params.hw_ops->mpdu_info_get_peerid(mpdu_info); 870 } 871 872 static enum hal_rx_mon_status 873 ath11k_hal_rx_parse_mon_status_tlv(struct ath11k_base *ab, 874 struct hal_rx_mon_ppdu_info *ppdu_info, 875 u32 tlv_tag, u8 *tlv_data, u32 userid) 876 { 877 u32 info0, info1, value; 878 u8 he_dcm = 0, he_stbc = 0; 879 u16 he_gi = 0, he_ltf = 0; 880 881 switch (tlv_tag) { 882 case HAL_RX_PPDU_START: { 883 struct hal_rx_ppdu_start *ppdu_start = 884 (struct hal_rx_ppdu_start *)tlv_data; 885 886 ppdu_info->ppdu_id = 887 FIELD_GET(HAL_RX_PPDU_START_INFO0_PPDU_ID, 888 __le32_to_cpu(ppdu_start->info0)); 889 ppdu_info->chan_num = __le32_to_cpu(ppdu_start->chan_num); 890 ppdu_info->ppdu_ts = __le32_to_cpu(ppdu_start->ppdu_start_ts); 891 break; 892 } 893 case HAL_RX_PPDU_END_USER_STATS: { 894 struct hal_rx_ppdu_end_user_stats *eu_stats = 895 (struct hal_rx_ppdu_end_user_stats *)tlv_data; 896 897 info0 = __le32_to_cpu(eu_stats->info0); 898 info1 = __le32_to_cpu(eu_stats->info1); 899 900 ppdu_info->ast_index = 901 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO2_AST_INDEX, 902 __le32_to_cpu(eu_stats->info2)); 903 ppdu_info->tid = 904 ffs(FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO7_TID_BITMAP, 905 __le32_to_cpu(eu_stats->info7))) - 1; 906 ppdu_info->tcp_msdu_count = 907 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO4_TCP_MSDU_CNT, 908 __le32_to_cpu(eu_stats->info4)); 909 ppdu_info->udp_msdu_count = 910 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO4_UDP_MSDU_CNT, 911 __le32_to_cpu(eu_stats->info4)); 912 ppdu_info->other_msdu_count = 913 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO5_OTHER_MSDU_CNT, 914 __le32_to_cpu(eu_stats->info5)); 915 ppdu_info->tcp_ack_msdu_count = 916 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO5_TCP_ACK_MSDU_CNT, 917 __le32_to_cpu(eu_stats->info5)); 918 ppdu_info->preamble_type = 919 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO1_PKT_TYPE, info1); 920 ppdu_info->num_mpdu_fcs_ok = 921 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO1_MPDU_CNT_FCS_OK, 922 info1); 923 ppdu_info->num_mpdu_fcs_err = 924 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO0_MPDU_CNT_FCS_ERR, 925 info0); 926 switch (ppdu_info->preamble_type) { 927 case HAL_RX_PREAMBLE_11N: 928 ppdu_info->ht_flags = 1; 929 break; 930 case HAL_RX_PREAMBLE_11AC: 931 ppdu_info->vht_flags = 1; 932 break; 933 case HAL_RX_PREAMBLE_11AX: 934 ppdu_info->he_flags = 1; 935 break; 936 default: 937 break; 938 } 939 940 if (userid < HAL_MAX_UL_MU_USERS) { 941 struct hal_rx_user_status *rxuser_stats = 942 &ppdu_info->userstats; 943 944 ath11k_hal_rx_handle_ofdma_info(tlv_data, rxuser_stats); 945 ath11k_hal_rx_populate_mu_user_info(tlv_data, ppdu_info, 946 rxuser_stats); 947 } 948 ppdu_info->userstats.mpdu_fcs_ok_bitmap[0] = 949 __le32_to_cpu(eu_stats->rsvd1[0]); 950 ppdu_info->userstats.mpdu_fcs_ok_bitmap[1] = 951 __le32_to_cpu(eu_stats->rsvd1[1]); 952 953 break; 954 } 955 case HAL_RX_PPDU_END_USER_STATS_EXT: { 956 struct hal_rx_ppdu_end_user_stats_ext *eu_stats = 957 (struct hal_rx_ppdu_end_user_stats_ext *)tlv_data; 958 ppdu_info->userstats.mpdu_fcs_ok_bitmap[2] = eu_stats->info1; 959 ppdu_info->userstats.mpdu_fcs_ok_bitmap[3] = eu_stats->info2; 960 ppdu_info->userstats.mpdu_fcs_ok_bitmap[4] = eu_stats->info3; 961 ppdu_info->userstats.mpdu_fcs_ok_bitmap[5] = eu_stats->info4; 962 ppdu_info->userstats.mpdu_fcs_ok_bitmap[6] = eu_stats->info5; 963 ppdu_info->userstats.mpdu_fcs_ok_bitmap[7] = eu_stats->info6; 964 break; 965 } 966 case HAL_PHYRX_HT_SIG: { 967 struct hal_rx_ht_sig_info *ht_sig = 968 (struct hal_rx_ht_sig_info *)tlv_data; 969 970 info0 = __le32_to_cpu(ht_sig->info0); 971 info1 = __le32_to_cpu(ht_sig->info1); 972 973 ppdu_info->mcs = FIELD_GET(HAL_RX_HT_SIG_INFO_INFO0_MCS, info0); 974 ppdu_info->bw = FIELD_GET(HAL_RX_HT_SIG_INFO_INFO0_BW, info0); 975 ppdu_info->is_stbc = FIELD_GET(HAL_RX_HT_SIG_INFO_INFO1_STBC, 976 info1); 977 ppdu_info->ldpc = FIELD_GET(HAL_RX_HT_SIG_INFO_INFO1_FEC_CODING, info1); 978 ppdu_info->gi = info1 & HAL_RX_HT_SIG_INFO_INFO1_GI; 979 980 switch (ppdu_info->mcs) { 981 case 0 ... 7: 982 ppdu_info->nss = 1; 983 break; 984 case 8 ... 15: 985 ppdu_info->nss = 2; 986 break; 987 case 16 ... 23: 988 ppdu_info->nss = 3; 989 break; 990 case 24 ... 31: 991 ppdu_info->nss = 4; 992 break; 993 } 994 995 if (ppdu_info->nss > 1) 996 ppdu_info->mcs = ppdu_info->mcs % 8; 997 998 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU; 999 break; 1000 } 1001 case HAL_PHYRX_L_SIG_B: { 1002 struct hal_rx_lsig_b_info *lsigb = 1003 (struct hal_rx_lsig_b_info *)tlv_data; 1004 1005 ppdu_info->rate = FIELD_GET(HAL_RX_LSIG_B_INFO_INFO0_RATE, 1006 __le32_to_cpu(lsigb->info0)); 1007 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU; 1008 break; 1009 } 1010 case HAL_PHYRX_L_SIG_A: { 1011 struct hal_rx_lsig_a_info *lsiga = 1012 (struct hal_rx_lsig_a_info *)tlv_data; 1013 1014 ppdu_info->rate = FIELD_GET(HAL_RX_LSIG_A_INFO_INFO0_RATE, 1015 __le32_to_cpu(lsiga->info0)); 1016 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU; 1017 break; 1018 } 1019 case HAL_PHYRX_VHT_SIG_A: { 1020 struct hal_rx_vht_sig_a_info *vht_sig = 1021 (struct hal_rx_vht_sig_a_info *)tlv_data; 1022 u32 nsts; 1023 u32 group_id; 1024 u8 gi_setting; 1025 1026 info0 = __le32_to_cpu(vht_sig->info0); 1027 info1 = __le32_to_cpu(vht_sig->info1); 1028 1029 ppdu_info->ldpc = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING, 1030 info1); 1031 ppdu_info->mcs = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO1_MCS, 1032 info1); 1033 gi_setting = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO1_GI_SETTING, 1034 info1); 1035 switch (gi_setting) { 1036 case HAL_RX_VHT_SIG_A_NORMAL_GI: 1037 ppdu_info->gi = HAL_RX_GI_0_8_US; 1038 break; 1039 case HAL_RX_VHT_SIG_A_SHORT_GI: 1040 case HAL_RX_VHT_SIG_A_SHORT_GI_AMBIGUITY: 1041 ppdu_info->gi = HAL_RX_GI_0_4_US; 1042 break; 1043 } 1044 1045 ppdu_info->is_stbc = info0 & HAL_RX_VHT_SIG_A_INFO_INFO0_STBC; 1046 nsts = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO0_NSTS, info0); 1047 if (ppdu_info->is_stbc && nsts > 0) 1048 nsts = ((nsts + 1) >> 1) - 1; 1049 1050 ppdu_info->nss = (nsts & VHT_SIG_SU_NSS_MASK) + 1; 1051 ppdu_info->bw = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO0_BW, 1052 info0); 1053 ppdu_info->beamformed = info1 & 1054 HAL_RX_VHT_SIG_A_INFO_INFO1_BEAMFORMED; 1055 group_id = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO0_GROUP_ID, 1056 info0); 1057 if (group_id == 0 || group_id == 63) 1058 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU; 1059 else 1060 ppdu_info->reception_type = 1061 HAL_RX_RECEPTION_TYPE_MU_MIMO; 1062 ppdu_info->vht_flag_values5 = group_id; 1063 ppdu_info->vht_flag_values3[0] = (((ppdu_info->mcs) << 4) | 1064 ppdu_info->nss); 1065 ppdu_info->vht_flag_values2 = ppdu_info->bw; 1066 ppdu_info->vht_flag_values4 = 1067 FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING, info1); 1068 break; 1069 } 1070 case HAL_PHYRX_HE_SIG_A_SU: { 1071 struct hal_rx_he_sig_a_su_info *he_sig_a = 1072 (struct hal_rx_he_sig_a_su_info *)tlv_data; 1073 1074 ppdu_info->he_flags = 1; 1075 info0 = __le32_to_cpu(he_sig_a->info0); 1076 info1 = __le32_to_cpu(he_sig_a->info1); 1077 1078 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_FORMAT_IND, info0); 1079 1080 if (value == 0) 1081 ppdu_info->he_data1 = IEEE80211_RADIOTAP_HE_DATA1_FORMAT_TRIG; 1082 else 1083 ppdu_info->he_data1 = IEEE80211_RADIOTAP_HE_DATA1_FORMAT_SU; 1084 1085 ppdu_info->he_data1 |= 1086 IEEE80211_RADIOTAP_HE_DATA1_BSS_COLOR_KNOWN | 1087 IEEE80211_RADIOTAP_HE_DATA1_BEAM_CHANGE_KNOWN | 1088 IEEE80211_RADIOTAP_HE_DATA1_UL_DL_KNOWN | 1089 IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN | 1090 IEEE80211_RADIOTAP_HE_DATA1_DATA_DCM_KNOWN | 1091 IEEE80211_RADIOTAP_HE_DATA1_CODING_KNOWN | 1092 IEEE80211_RADIOTAP_HE_DATA1_LDPC_XSYMSEG_KNOWN | 1093 IEEE80211_RADIOTAP_HE_DATA1_STBC_KNOWN | 1094 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN | 1095 IEEE80211_RADIOTAP_HE_DATA1_DOPPLER_KNOWN; 1096 1097 ppdu_info->he_data2 |= 1098 IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN | 1099 IEEE80211_RADIOTAP_HE_DATA2_TXBF_KNOWN | 1100 IEEE80211_RADIOTAP_HE_DATA2_PE_DISAMBIG_KNOWN | 1101 IEEE80211_RADIOTAP_HE_DATA2_TXOP_KNOWN | 1102 IEEE80211_RADIOTAP_HE_DATA2_NUM_LTF_SYMS_KNOWN | 1103 IEEE80211_RADIOTAP_HE_DATA2_PRE_FEC_PAD_KNOWN | 1104 IEEE80211_RADIOTAP_HE_DATA2_MIDAMBLE_KNOWN; 1105 1106 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_BSS_COLOR, info0); 1107 ppdu_info->he_data3 = 1108 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_BSS_COLOR, value); 1109 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_BEAM_CHANGE, info0); 1110 ppdu_info->he_data3 |= 1111 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_BEAM_CHANGE, value); 1112 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_DL_UL_FLAG, info0); 1113 ppdu_info->he_data3 |= 1114 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_UL_DL, value); 1115 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS, info0); 1116 ppdu_info->mcs = value; 1117 ppdu_info->he_data3 |= 1118 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_DATA_MCS, value); 1119 1120 he_dcm = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM, info0); 1121 ppdu_info->dcm = he_dcm; 1122 ppdu_info->he_data3 |= 1123 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_DATA_DCM, he_dcm); 1124 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO1_CODING, info1); 1125 ppdu_info->ldpc = (value == HAL_RX_SU_MU_CODING_LDPC) ? 1 : 0; 1126 ppdu_info->he_data3 |= 1127 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_CODING, value); 1128 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO1_LDPC_EXTRA, info1); 1129 ppdu_info->he_data3 |= 1130 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_LDPC_XSYMSEG, value); 1131 he_stbc = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO1_STBC, info1); 1132 ppdu_info->is_stbc = he_stbc; 1133 ppdu_info->he_data3 |= 1134 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_STBC, he_stbc); 1135 1136 /* data4 */ 1137 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_SPATIAL_REUSE, info0); 1138 ppdu_info->he_data4 = 1139 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA4_SU_MU_SPTL_REUSE, value); 1140 1141 /* data5 */ 1142 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW, info0); 1143 ppdu_info->bw = value; 1144 ppdu_info->he_data5 = 1145 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC, value); 1146 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_CP_LTF_SIZE, info0); 1147 switch (value) { 1148 case 0: 1149 he_gi = HE_GI_0_8; 1150 he_ltf = HE_LTF_1_X; 1151 break; 1152 case 1: 1153 he_gi = HE_GI_0_8; 1154 he_ltf = HE_LTF_2_X; 1155 break; 1156 case 2: 1157 he_gi = HE_GI_1_6; 1158 he_ltf = HE_LTF_2_X; 1159 break; 1160 case 3: 1161 if (he_dcm && he_stbc) { 1162 he_gi = HE_GI_0_8; 1163 he_ltf = HE_LTF_4_X; 1164 } else { 1165 he_gi = HE_GI_3_2; 1166 he_ltf = HE_LTF_4_X; 1167 } 1168 break; 1169 } 1170 ppdu_info->gi = he_gi; 1171 he_gi = (he_gi != 0) ? he_gi - 1 : 0; 1172 ppdu_info->he_data5 |= FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_GI, he_gi); 1173 ppdu_info->ltf_size = he_ltf; 1174 ppdu_info->he_data5 |= 1175 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE, 1176 (he_ltf == HE_LTF_4_X) ? he_ltf - 1 : he_ltf); 1177 1178 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS, info0); 1179 ppdu_info->he_data5 |= 1180 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_NUM_LTF_SYMS, value); 1181 1182 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_FACTOR, info1); 1183 ppdu_info->he_data5 |= 1184 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_PRE_FEC_PAD, value); 1185 1186 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXBF, info1); 1187 ppdu_info->beamformed = value; 1188 ppdu_info->he_data5 |= 1189 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_TXBF, value); 1190 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_PE_DISAM, info1); 1191 ppdu_info->he_data5 |= 1192 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_PE_DISAMBIG, value); 1193 1194 /* data6 */ 1195 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS, info0); 1196 value++; 1197 ppdu_info->nss = value; 1198 ppdu_info->he_data6 = 1199 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA6_NSTS, value); 1200 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO1_DOPPLER_IND, info1); 1201 ppdu_info->he_data6 |= 1202 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA6_DOPPLER, value); 1203 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXOP_DURATION, info1); 1204 ppdu_info->he_data6 |= 1205 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA6_TXOP, value); 1206 1207 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU; 1208 break; 1209 } 1210 case HAL_PHYRX_HE_SIG_A_MU_DL: { 1211 struct hal_rx_he_sig_a_mu_dl_info *he_sig_a_mu_dl = 1212 (struct hal_rx_he_sig_a_mu_dl_info *)tlv_data; 1213 1214 info0 = __le32_to_cpu(he_sig_a_mu_dl->info0); 1215 info1 = __le32_to_cpu(he_sig_a_mu_dl->info1); 1216 1217 ppdu_info->he_mu_flags = 1; 1218 1219 ppdu_info->he_data1 = IEEE80211_RADIOTAP_HE_DATA1_FORMAT_MU; 1220 ppdu_info->he_data1 |= 1221 IEEE80211_RADIOTAP_HE_DATA1_BSS_COLOR_KNOWN | 1222 IEEE80211_RADIOTAP_HE_DATA1_UL_DL_KNOWN | 1223 IEEE80211_RADIOTAP_HE_DATA1_LDPC_XSYMSEG_KNOWN | 1224 IEEE80211_RADIOTAP_HE_DATA1_STBC_KNOWN | 1225 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN | 1226 IEEE80211_RADIOTAP_HE_DATA1_DOPPLER_KNOWN; 1227 1228 ppdu_info->he_data2 = 1229 IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN | 1230 IEEE80211_RADIOTAP_HE_DATA2_NUM_LTF_SYMS_KNOWN | 1231 IEEE80211_RADIOTAP_HE_DATA2_PRE_FEC_PAD_KNOWN | 1232 IEEE80211_RADIOTAP_HE_DATA2_PE_DISAMBIG_KNOWN | 1233 IEEE80211_RADIOTAP_HE_DATA2_TXOP_KNOWN | 1234 IEEE80211_RADIOTAP_HE_DATA2_MIDAMBLE_KNOWN; 1235 1236 /*data3*/ 1237 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_BSS_COLOR, info0); 1238 ppdu_info->he_data3 = 1239 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_BSS_COLOR, value); 1240 1241 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_UL_FLAG, info0); 1242 ppdu_info->he_data3 |= 1243 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_UL_DL, value); 1244 1245 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_LDPC_EXTRA, info1); 1246 ppdu_info->he_data3 |= 1247 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_LDPC_XSYMSEG, value); 1248 1249 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_STBC, info1); 1250 he_stbc = value; 1251 ppdu_info->he_data3 |= 1252 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_STBC, value); 1253 1254 /*data4*/ 1255 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_SPATIAL_REUSE, info0); 1256 ppdu_info->he_data4 = 1257 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA4_SU_MU_SPTL_REUSE, value); 1258 1259 /*data5*/ 1260 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_TRANSMIT_BW, info0); 1261 ppdu_info->bw = value; 1262 ppdu_info->he_data5 = 1263 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC, value); 1264 1265 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_CP_LTF_SIZE, info0); 1266 switch (value) { 1267 case 0: 1268 he_gi = HE_GI_0_8; 1269 he_ltf = HE_LTF_4_X; 1270 break; 1271 case 1: 1272 he_gi = HE_GI_0_8; 1273 he_ltf = HE_LTF_2_X; 1274 break; 1275 case 2: 1276 he_gi = HE_GI_1_6; 1277 he_ltf = HE_LTF_2_X; 1278 break; 1279 case 3: 1280 he_gi = HE_GI_3_2; 1281 he_ltf = HE_LTF_4_X; 1282 break; 1283 } 1284 ppdu_info->gi = he_gi; 1285 he_gi = (he_gi != 0) ? he_gi - 1 : 0; 1286 ppdu_info->he_data5 |= FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_GI, he_gi); 1287 ppdu_info->ltf_size = he_ltf; 1288 ppdu_info->he_data5 |= 1289 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE, 1290 (he_ltf == HE_LTF_4_X) ? he_ltf - 1 : he_ltf); 1291 1292 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_NUM_LTF_SYMB, info1); 1293 ppdu_info->he_data5 |= 1294 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_NUM_LTF_SYMS, value); 1295 1296 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_PKT_EXT_FACTOR, 1297 info1); 1298 ppdu_info->he_data5 |= 1299 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_PRE_FEC_PAD, value); 1300 1301 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_PKT_EXT_PE_DISAM, 1302 info1); 1303 ppdu_info->he_data5 |= 1304 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_PE_DISAMBIG, value); 1305 1306 /*data6*/ 1307 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_DOPPLER_INDICATION, 1308 info0); 1309 ppdu_info->he_data6 |= 1310 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA6_DOPPLER, value); 1311 1312 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_TXOP_DURATION, info1); 1313 ppdu_info->he_data6 |= 1314 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA6_TXOP, value); 1315 1316 /* HE-MU Flags */ 1317 /* HE-MU-flags1 */ 1318 ppdu_info->he_flags1 = 1319 IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_MCS_KNOWN | 1320 IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_DCM_KNOWN | 1321 IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_COMP_KNOWN | 1322 IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_SYMS_USERS_KNOWN | 1323 IEEE80211_RADIOTAP_HE_MU_FLAGS1_CH1_RU_KNOWN; 1324 1325 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_MCS_OF_SIGB, info0); 1326 ppdu_info->he_flags1 |= 1327 FIELD_PREP(IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_MCS_KNOWN, 1328 value); 1329 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_DCM_OF_SIGB, info0); 1330 ppdu_info->he_flags1 |= 1331 FIELD_PREP(IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_DCM_KNOWN, 1332 value); 1333 1334 /* HE-MU-flags2 */ 1335 ppdu_info->he_flags2 = 1336 IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW_KNOWN; 1337 1338 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_TRANSMIT_BW, info0); 1339 ppdu_info->he_flags2 |= 1340 FIELD_PREP(IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW, 1341 value); 1342 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_COMP_MODE_SIGB, info0); 1343 ppdu_info->he_flags2 |= 1344 FIELD_PREP(IEEE80211_RADIOTAP_HE_MU_FLAGS2_SIG_B_COMP, value); 1345 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_NUM_SIGB_SYMB, info0); 1346 value = value - 1; 1347 ppdu_info->he_flags2 |= 1348 FIELD_PREP(IEEE80211_RADIOTAP_HE_MU_FLAGS2_SIG_B_SYMS_USERS, 1349 value); 1350 1351 ppdu_info->is_stbc = info1 & 1352 HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_STBC; 1353 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO; 1354 break; 1355 } 1356 case HAL_PHYRX_HE_SIG_B1_MU: { 1357 struct hal_rx_he_sig_b1_mu_info *he_sig_b1_mu = 1358 (struct hal_rx_he_sig_b1_mu_info *)tlv_data; 1359 u16 ru_tones; 1360 1361 info0 = __le32_to_cpu(he_sig_b1_mu->info0); 1362 1363 ru_tones = FIELD_GET(HAL_RX_HE_SIG_B1_MU_INFO_INFO0_RU_ALLOCATION, 1364 info0); 1365 ppdu_info->ru_alloc = 1366 ath11k_mac_phy_he_ru_to_nl80211_he_ru_alloc(ru_tones); 1367 ppdu_info->he_RU[0] = ru_tones; 1368 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO; 1369 break; 1370 } 1371 case HAL_PHYRX_HE_SIG_B2_MU: { 1372 struct hal_rx_he_sig_b2_mu_info *he_sig_b2_mu = 1373 (struct hal_rx_he_sig_b2_mu_info *)tlv_data; 1374 1375 info0 = __le32_to_cpu(he_sig_b2_mu->info0); 1376 1377 ppdu_info->he_data1 |= IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN | 1378 IEEE80211_RADIOTAP_HE_DATA1_CODING_KNOWN; 1379 1380 ppdu_info->mcs = 1381 FIELD_GET(HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_MCS, info0); 1382 ppdu_info->he_data3 |= 1383 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_DATA_MCS, ppdu_info->mcs); 1384 1385 value = FIELD_GET(HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_CODING, info0); 1386 ppdu_info->ldpc = value; 1387 ppdu_info->he_data3 |= 1388 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_CODING, value); 1389 1390 value = FIELD_GET(HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_ID, info0); 1391 ppdu_info->he_data4 |= 1392 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA4_MU_STA_ID, value); 1393 1394 ppdu_info->nss = 1395 FIELD_GET(HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_NSTS, info0) + 1; 1396 break; 1397 } 1398 case HAL_PHYRX_HE_SIG_B2_OFDMA: { 1399 struct hal_rx_he_sig_b2_ofdma_info *he_sig_b2_ofdma = 1400 (struct hal_rx_he_sig_b2_ofdma_info *)tlv_data; 1401 1402 info0 = __le32_to_cpu(he_sig_b2_ofdma->info0); 1403 1404 ppdu_info->he_data1 |= 1405 IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN | 1406 IEEE80211_RADIOTAP_HE_DATA1_DATA_DCM_KNOWN | 1407 IEEE80211_RADIOTAP_HE_DATA1_CODING_KNOWN; 1408 1409 /* HE-data2 */ 1410 ppdu_info->he_data2 |= IEEE80211_RADIOTAP_HE_DATA2_TXBF_KNOWN; 1411 1412 ppdu_info->mcs = 1413 FIELD_GET(HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_MCS, 1414 info0); 1415 ppdu_info->he_data3 |= 1416 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_DATA_MCS, ppdu_info->mcs); 1417 1418 value = FIELD_GET(HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_DCM, info0); 1419 he_dcm = value; 1420 ppdu_info->he_data3 |= 1421 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_DATA_DCM, value); 1422 1423 value = FIELD_GET(HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_CODING, info0); 1424 ppdu_info->ldpc = value; 1425 ppdu_info->he_data3 |= 1426 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_CODING, value); 1427 1428 /* HE-data4 */ 1429 value = FIELD_GET(HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_ID, info0); 1430 ppdu_info->he_data4 |= 1431 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA4_MU_STA_ID, value); 1432 1433 ppdu_info->nss = 1434 FIELD_GET(HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_NSTS, 1435 info0) + 1; 1436 ppdu_info->beamformed = 1437 info0 & HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_TXBF; 1438 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_OFDMA; 1439 break; 1440 } 1441 case HAL_PHYRX_RSSI_LEGACY: { 1442 int i; 1443 bool db2dbm = test_bit(WMI_TLV_SERVICE_HW_DB2DBM_CONVERSION_SUPPORT, 1444 ab->wmi_ab.svc_map); 1445 struct hal_rx_phyrx_rssi_legacy_info *rssi = 1446 (struct hal_rx_phyrx_rssi_legacy_info *)tlv_data; 1447 1448 /* TODO: Please note that the combined rssi will not be accurate 1449 * in MU case. Rssi in MU needs to be retrieved from 1450 * PHYRX_OTHER_RECEIVE_INFO TLV. 1451 */ 1452 ppdu_info->rssi_comb = 1453 FIELD_GET(HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO0_RSSI_COMB, 1454 __le32_to_cpu(rssi->info0)); 1455 1456 if (db2dbm) { 1457 for (i = 0; i < ARRAY_SIZE(rssi->preamble); i++) { 1458 ppdu_info->rssi_chain_pri20[i] = 1459 le32_get_bits(rssi->preamble[i].rssi_2040, 1460 HAL_RX_PHYRX_RSSI_PREAMBLE_PRI20); 1461 } 1462 } 1463 break; 1464 } 1465 case HAL_RX_MPDU_START: { 1466 struct hal_rx_mpdu_info *mpdu_info = 1467 (struct hal_rx_mpdu_info *)tlv_data; 1468 u16 peer_id; 1469 1470 peer_id = ath11k_hal_rx_mpduinfo_get_peerid(ab, mpdu_info); 1471 if (peer_id) 1472 ppdu_info->peer_id = peer_id; 1473 break; 1474 } 1475 case HAL_RXPCU_PPDU_END_INFO: { 1476 struct hal_rx_ppdu_end_duration *ppdu_rx_duration = 1477 (struct hal_rx_ppdu_end_duration *)tlv_data; 1478 ppdu_info->rx_duration = 1479 FIELD_GET(HAL_RX_PPDU_END_DURATION, 1480 __le32_to_cpu(ppdu_rx_duration->info0)); 1481 ppdu_info->tsft = __le32_to_cpu(ppdu_rx_duration->rsvd0[1]); 1482 ppdu_info->tsft = (ppdu_info->tsft << 32) | 1483 __le32_to_cpu(ppdu_rx_duration->rsvd0[0]); 1484 break; 1485 } 1486 case HAL_DUMMY: 1487 return HAL_RX_MON_STATUS_BUF_DONE; 1488 case HAL_RX_PPDU_END_STATUS_DONE: 1489 case 0: 1490 return HAL_RX_MON_STATUS_PPDU_DONE; 1491 default: 1492 break; 1493 } 1494 1495 return HAL_RX_MON_STATUS_PPDU_NOT_DONE; 1496 } 1497 1498 enum hal_rx_mon_status 1499 ath11k_hal_rx_parse_mon_status(struct ath11k_base *ab, 1500 struct hal_rx_mon_ppdu_info *ppdu_info, 1501 struct sk_buff *skb) 1502 { 1503 struct hal_tlv_hdr *tlv; 1504 enum hal_rx_mon_status hal_status = HAL_RX_MON_STATUS_BUF_DONE; 1505 u16 tlv_tag; 1506 u16 tlv_len; 1507 u32 tlv_userid = 0; 1508 u8 *ptr = skb->data; 1509 1510 do { 1511 tlv = (struct hal_tlv_hdr *)ptr; 1512 tlv_tag = FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl); 1513 tlv_len = FIELD_GET(HAL_TLV_HDR_LEN, tlv->tl); 1514 tlv_userid = FIELD_GET(HAL_TLV_USR_ID, tlv->tl); 1515 ptr += sizeof(*tlv); 1516 1517 /* The actual length of PPDU_END is the combined length of many PHY 1518 * TLVs that follow. Skip the TLV header and 1519 * rx_rxpcu_classification_overview that follows the header to get to 1520 * next TLV. 1521 */ 1522 if (tlv_tag == HAL_RX_PPDU_END) 1523 tlv_len = sizeof(struct hal_rx_rxpcu_classification_overview); 1524 1525 hal_status = ath11k_hal_rx_parse_mon_status_tlv(ab, ppdu_info, 1526 tlv_tag, ptr, tlv_userid); 1527 ptr += tlv_len; 1528 ptr = PTR_ALIGN(ptr, HAL_TLV_ALIGN); 1529 1530 if ((ptr - skb->data) >= DP_RX_BUFFER_SIZE) 1531 break; 1532 } while (hal_status == HAL_RX_MON_STATUS_PPDU_NOT_DONE); 1533 1534 return hal_status; 1535 } 1536 1537 void ath11k_hal_rx_reo_ent_buf_paddr_get(void *rx_desc, dma_addr_t *paddr, 1538 u32 *sw_cookie, void **pp_buf_addr, 1539 u8 *rbm, u32 *msdu_cnt) 1540 { 1541 struct hal_reo_entrance_ring *reo_ent_ring = rx_desc; 1542 struct ath11k_buffer_addr *buf_addr_info; 1543 struct rx_mpdu_desc *rx_mpdu_desc_info_details; 1544 1545 rx_mpdu_desc_info_details = 1546 (struct rx_mpdu_desc *)&reo_ent_ring->rx_mpdu_info; 1547 1548 *msdu_cnt = FIELD_GET(RX_MPDU_DESC_INFO0_MSDU_COUNT, 1549 rx_mpdu_desc_info_details->info0); 1550 1551 buf_addr_info = (struct ath11k_buffer_addr *)&reo_ent_ring->buf_addr_info; 1552 1553 *paddr = (((u64)FIELD_GET(BUFFER_ADDR_INFO1_ADDR, 1554 buf_addr_info->info1)) << 32) | 1555 FIELD_GET(BUFFER_ADDR_INFO0_ADDR, 1556 buf_addr_info->info0); 1557 1558 *sw_cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, 1559 buf_addr_info->info1); 1560 *rbm = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR, 1561 buf_addr_info->info1); 1562 1563 *pp_buf_addr = (void *)buf_addr_info; 1564 } 1565 1566 void 1567 ath11k_hal_rx_sw_mon_ring_buf_paddr_get(void *rx_desc, 1568 struct hal_sw_mon_ring_entries *sw_mon_entries) 1569 { 1570 struct hal_sw_monitor_ring *sw_mon_ring = rx_desc; 1571 struct ath11k_buffer_addr *buf_addr_info; 1572 struct ath11k_buffer_addr *status_buf_addr_info; 1573 struct rx_mpdu_desc *rx_mpdu_desc_info_details; 1574 1575 rx_mpdu_desc_info_details = &sw_mon_ring->rx_mpdu_info; 1576 1577 sw_mon_entries->msdu_cnt = FIELD_GET(RX_MPDU_DESC_INFO0_MSDU_COUNT, 1578 rx_mpdu_desc_info_details->info0); 1579 1580 buf_addr_info = &sw_mon_ring->buf_addr_info; 1581 status_buf_addr_info = &sw_mon_ring->status_buf_addr_info; 1582 1583 sw_mon_entries->mon_dst_paddr = (((u64)FIELD_GET(BUFFER_ADDR_INFO1_ADDR, 1584 buf_addr_info->info1)) << 32) | 1585 FIELD_GET(BUFFER_ADDR_INFO0_ADDR, 1586 buf_addr_info->info0); 1587 1588 sw_mon_entries->mon_status_paddr = 1589 (((u64)FIELD_GET(BUFFER_ADDR_INFO1_ADDR, 1590 status_buf_addr_info->info1)) << 32) | 1591 FIELD_GET(BUFFER_ADDR_INFO0_ADDR, 1592 status_buf_addr_info->info0); 1593 1594 sw_mon_entries->mon_dst_sw_cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, 1595 buf_addr_info->info1); 1596 1597 sw_mon_entries->mon_status_sw_cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, 1598 status_buf_addr_info->info1); 1599 1600 sw_mon_entries->status_buf_count = FIELD_GET(HAL_SW_MON_RING_INFO0_STATUS_BUF_CNT, 1601 sw_mon_ring->info0); 1602 1603 sw_mon_entries->dst_buf_addr_info = buf_addr_info; 1604 sw_mon_entries->status_buf_addr_info = status_buf_addr_info; 1605 1606 sw_mon_entries->ppdu_id = 1607 FIELD_GET(HAL_SW_MON_RING_INFO1_PHY_PPDU_ID, sw_mon_ring->info1); 1608 } 1609