1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 #include <linux/dma-mapping.h> 7 #include "hal_tx.h" 8 #include "debug.h" 9 #include "hal_desc.h" 10 #include "hif.h" 11 12 static const struct hal_srng_config hw_srng_config_template[] = { 13 /* TODO: max_rings can populated by querying HW capabilities */ 14 { /* REO_DST */ 15 .start_ring_id = HAL_SRNG_RING_ID_REO2SW1, 16 .max_rings = 4, 17 .entry_size = sizeof(struct hal_reo_dest_ring) >> 2, 18 .lmac_ring = false, 19 .ring_dir = HAL_SRNG_DIR_DST, 20 .max_size = HAL_REO_REO2SW1_RING_BASE_MSB_RING_SIZE, 21 }, 22 { /* REO_EXCEPTION */ 23 /* Designating REO2TCL ring as exception ring. This ring is 24 * similar to other REO2SW rings though it is named as REO2TCL. 25 * Any of theREO2SW rings can be used as exception ring. 26 */ 27 .start_ring_id = HAL_SRNG_RING_ID_REO2TCL, 28 .max_rings = 1, 29 .entry_size = sizeof(struct hal_reo_dest_ring) >> 2, 30 .lmac_ring = false, 31 .ring_dir = HAL_SRNG_DIR_DST, 32 .max_size = HAL_REO_REO2TCL_RING_BASE_MSB_RING_SIZE, 33 }, 34 { /* REO_REINJECT */ 35 .start_ring_id = HAL_SRNG_RING_ID_SW2REO, 36 .max_rings = 1, 37 .entry_size = sizeof(struct hal_reo_entrance_ring) >> 2, 38 .lmac_ring = false, 39 .ring_dir = HAL_SRNG_DIR_SRC, 40 .max_size = HAL_REO_SW2REO_RING_BASE_MSB_RING_SIZE, 41 }, 42 { /* REO_CMD */ 43 .start_ring_id = HAL_SRNG_RING_ID_REO_CMD, 44 .max_rings = 1, 45 .entry_size = (sizeof(struct hal_tlv_hdr) + 46 sizeof(struct hal_reo_get_queue_stats)) >> 2, 47 .lmac_ring = false, 48 .ring_dir = HAL_SRNG_DIR_SRC, 49 .max_size = HAL_REO_CMD_RING_BASE_MSB_RING_SIZE, 50 }, 51 { /* REO_STATUS */ 52 .start_ring_id = HAL_SRNG_RING_ID_REO_STATUS, 53 .max_rings = 1, 54 .entry_size = (sizeof(struct hal_tlv_hdr) + 55 sizeof(struct hal_reo_get_queue_stats_status)) >> 2, 56 .lmac_ring = false, 57 .ring_dir = HAL_SRNG_DIR_DST, 58 .max_size = HAL_REO_STATUS_RING_BASE_MSB_RING_SIZE, 59 }, 60 { /* TCL_DATA */ 61 .start_ring_id = HAL_SRNG_RING_ID_SW2TCL1, 62 .max_rings = 3, 63 .entry_size = (sizeof(struct hal_tlv_hdr) + 64 sizeof(struct hal_tcl_data_cmd)) >> 2, 65 .lmac_ring = false, 66 .ring_dir = HAL_SRNG_DIR_SRC, 67 .max_size = HAL_SW2TCL1_RING_BASE_MSB_RING_SIZE, 68 }, 69 { /* TCL_CMD */ 70 .start_ring_id = HAL_SRNG_RING_ID_SW2TCL_CMD, 71 .max_rings = 1, 72 .entry_size = (sizeof(struct hal_tlv_hdr) + 73 sizeof(struct hal_tcl_gse_cmd)) >> 2, 74 .lmac_ring = false, 75 .ring_dir = HAL_SRNG_DIR_SRC, 76 .max_size = HAL_SW2TCL1_CMD_RING_BASE_MSB_RING_SIZE, 77 }, 78 { /* TCL_STATUS */ 79 .start_ring_id = HAL_SRNG_RING_ID_TCL_STATUS, 80 .max_rings = 1, 81 .entry_size = (sizeof(struct hal_tlv_hdr) + 82 sizeof(struct hal_tcl_status_ring)) >> 2, 83 .lmac_ring = false, 84 .ring_dir = HAL_SRNG_DIR_DST, 85 .max_size = HAL_TCL_STATUS_RING_BASE_MSB_RING_SIZE, 86 }, 87 { /* CE_SRC */ 88 .start_ring_id = HAL_SRNG_RING_ID_CE0_SRC, 89 .max_rings = 12, 90 .entry_size = sizeof(struct hal_ce_srng_src_desc) >> 2, 91 .lmac_ring = false, 92 .ring_dir = HAL_SRNG_DIR_SRC, 93 .max_size = HAL_CE_SRC_RING_BASE_MSB_RING_SIZE, 94 }, 95 { /* CE_DST */ 96 .start_ring_id = HAL_SRNG_RING_ID_CE0_DST, 97 .max_rings = 12, 98 .entry_size = sizeof(struct hal_ce_srng_dest_desc) >> 2, 99 .lmac_ring = false, 100 .ring_dir = HAL_SRNG_DIR_SRC, 101 .max_size = HAL_CE_DST_RING_BASE_MSB_RING_SIZE, 102 }, 103 { /* CE_DST_STATUS */ 104 .start_ring_id = HAL_SRNG_RING_ID_CE0_DST_STATUS, 105 .max_rings = 12, 106 .entry_size = sizeof(struct hal_ce_srng_dst_status_desc) >> 2, 107 .lmac_ring = false, 108 .ring_dir = HAL_SRNG_DIR_DST, 109 .max_size = HAL_CE_DST_STATUS_RING_BASE_MSB_RING_SIZE, 110 }, 111 { /* WBM_IDLE_LINK */ 112 .start_ring_id = HAL_SRNG_RING_ID_WBM_IDLE_LINK, 113 .max_rings = 1, 114 .entry_size = sizeof(struct hal_wbm_link_desc) >> 2, 115 .lmac_ring = false, 116 .ring_dir = HAL_SRNG_DIR_SRC, 117 .max_size = HAL_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE, 118 }, 119 { /* SW2WBM_RELEASE */ 120 .start_ring_id = HAL_SRNG_RING_ID_WBM_SW_RELEASE, 121 .max_rings = 1, 122 .entry_size = sizeof(struct hal_wbm_release_ring) >> 2, 123 .lmac_ring = false, 124 .ring_dir = HAL_SRNG_DIR_SRC, 125 .max_size = HAL_SW2WBM_RELEASE_RING_BASE_MSB_RING_SIZE, 126 }, 127 { /* WBM2SW_RELEASE */ 128 .start_ring_id = HAL_SRNG_RING_ID_WBM2SW0_RELEASE, 129 .max_rings = 5, 130 .entry_size = sizeof(struct hal_wbm_release_ring) >> 2, 131 .lmac_ring = false, 132 .ring_dir = HAL_SRNG_DIR_DST, 133 .max_size = HAL_WBM2SW_RELEASE_RING_BASE_MSB_RING_SIZE, 134 }, 135 { /* RXDMA_BUF */ 136 .start_ring_id = HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_BUF, 137 .max_rings = 2, 138 .entry_size = sizeof(struct hal_wbm_buffer_ring) >> 2, 139 .lmac_ring = true, 140 .ring_dir = HAL_SRNG_DIR_SRC, 141 .max_size = HAL_RXDMA_RING_MAX_SIZE, 142 }, 143 { /* RXDMA_DST */ 144 .start_ring_id = HAL_SRNG_RING_ID_WMAC1_RXDMA2SW0, 145 .max_rings = 1, 146 .entry_size = sizeof(struct hal_reo_entrance_ring) >> 2, 147 .lmac_ring = true, 148 .ring_dir = HAL_SRNG_DIR_DST, 149 .max_size = HAL_RXDMA_RING_MAX_SIZE, 150 }, 151 { /* RXDMA_MONITOR_BUF */ 152 .start_ring_id = HAL_SRNG_RING_ID_WMAC1_SW2RXDMA2_BUF, 153 .max_rings = 1, 154 .entry_size = sizeof(struct hal_wbm_buffer_ring) >> 2, 155 .lmac_ring = true, 156 .ring_dir = HAL_SRNG_DIR_SRC, 157 .max_size = HAL_RXDMA_RING_MAX_SIZE, 158 }, 159 { /* RXDMA_MONITOR_STATUS */ 160 .start_ring_id = HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_STATBUF, 161 .max_rings = 1, 162 .entry_size = sizeof(struct hal_wbm_buffer_ring) >> 2, 163 .lmac_ring = true, 164 .ring_dir = HAL_SRNG_DIR_SRC, 165 .max_size = HAL_RXDMA_RING_MAX_SIZE, 166 }, 167 { /* RXDMA_MONITOR_DST */ 168 .start_ring_id = HAL_SRNG_RING_ID_WMAC1_RXDMA2SW1, 169 .max_rings = 1, 170 .entry_size = sizeof(struct hal_reo_entrance_ring) >> 2, 171 .lmac_ring = true, 172 .ring_dir = HAL_SRNG_DIR_DST, 173 .max_size = HAL_RXDMA_RING_MAX_SIZE, 174 }, 175 { /* RXDMA_MONITOR_DESC */ 176 .start_ring_id = HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_DESC, 177 .max_rings = 1, 178 .entry_size = sizeof(struct hal_wbm_buffer_ring) >> 2, 179 .lmac_ring = true, 180 .ring_dir = HAL_SRNG_DIR_SRC, 181 .max_size = HAL_RXDMA_RING_MAX_SIZE, 182 }, 183 { /* RXDMA DIR BUF */ 184 .start_ring_id = HAL_SRNG_RING_ID_RXDMA_DIR_BUF, 185 .max_rings = 1, 186 .entry_size = 8 >> 2, /* TODO: Define the struct */ 187 .lmac_ring = true, 188 .ring_dir = HAL_SRNG_DIR_SRC, 189 .max_size = HAL_RXDMA_RING_MAX_SIZE, 190 }, 191 }; 192 193 static int ath11k_hal_alloc_cont_rdp(struct ath11k_base *ab) 194 { 195 struct ath11k_hal *hal = &ab->hal; 196 size_t size; 197 198 size = sizeof(u32) * HAL_SRNG_RING_ID_MAX; 199 hal->rdp.vaddr = dma_alloc_coherent(ab->dev, size, &hal->rdp.paddr, 200 GFP_KERNEL); 201 if (!hal->rdp.vaddr) 202 return -ENOMEM; 203 204 return 0; 205 } 206 207 static void ath11k_hal_free_cont_rdp(struct ath11k_base *ab) 208 { 209 struct ath11k_hal *hal = &ab->hal; 210 size_t size; 211 212 if (!hal->rdp.vaddr) 213 return; 214 215 size = sizeof(u32) * HAL_SRNG_RING_ID_MAX; 216 dma_free_coherent(ab->dev, size, 217 hal->rdp.vaddr, hal->rdp.paddr); 218 hal->rdp.vaddr = NULL; 219 } 220 221 static int ath11k_hal_alloc_cont_wrp(struct ath11k_base *ab) 222 { 223 struct ath11k_hal *hal = &ab->hal; 224 size_t size; 225 226 size = sizeof(u32) * HAL_SRNG_NUM_LMAC_RINGS; 227 hal->wrp.vaddr = dma_alloc_coherent(ab->dev, size, &hal->wrp.paddr, 228 GFP_KERNEL); 229 if (!hal->wrp.vaddr) 230 return -ENOMEM; 231 232 return 0; 233 } 234 235 static void ath11k_hal_free_cont_wrp(struct ath11k_base *ab) 236 { 237 struct ath11k_hal *hal = &ab->hal; 238 size_t size; 239 240 if (!hal->wrp.vaddr) 241 return; 242 243 size = sizeof(u32) * HAL_SRNG_NUM_LMAC_RINGS; 244 dma_free_coherent(ab->dev, size, 245 hal->wrp.vaddr, hal->wrp.paddr); 246 hal->wrp.vaddr = NULL; 247 } 248 249 static void ath11k_hal_ce_dst_setup(struct ath11k_base *ab, 250 struct hal_srng *srng, int ring_num) 251 { 252 struct hal_srng_config *srng_config = &ab->hal.srng_config[HAL_CE_DST]; 253 u32 addr; 254 u32 val; 255 256 addr = HAL_CE_DST_RING_CTRL + 257 srng_config->reg_start[HAL_SRNG_REG_GRP_R0] + 258 ring_num * srng_config->reg_size[HAL_SRNG_REG_GRP_R0]; 259 260 val = ath11k_hif_read32(ab, addr); 261 val &= ~HAL_CE_DST_R0_DEST_CTRL_MAX_LEN; 262 val |= FIELD_PREP(HAL_CE_DST_R0_DEST_CTRL_MAX_LEN, 263 srng->u.dst_ring.max_buffer_length); 264 ath11k_hif_write32(ab, addr, val); 265 } 266 267 static void ath11k_hal_srng_dst_hw_init(struct ath11k_base *ab, 268 struct hal_srng *srng) 269 { 270 struct ath11k_hal *hal = &ab->hal; 271 u32 val; 272 u64 hp_addr; 273 u32 reg_base; 274 275 reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R0]; 276 277 if (srng->flags & HAL_SRNG_FLAGS_MSI_INTR) { 278 ath11k_hif_write32(ab, reg_base + 279 HAL_REO1_RING_MSI1_BASE_LSB_OFFSET(ab), 280 srng->msi_addr); 281 282 val = FIELD_PREP(HAL_REO1_RING_MSI1_BASE_MSB_ADDR, 283 ((u64)srng->msi_addr >> 284 HAL_ADDR_MSB_REG_SHIFT)) | 285 HAL_REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE; 286 ath11k_hif_write32(ab, reg_base + 287 HAL_REO1_RING_MSI1_BASE_MSB_OFFSET(ab), val); 288 289 ath11k_hif_write32(ab, 290 reg_base + HAL_REO1_RING_MSI1_DATA_OFFSET(ab), 291 srng->msi_data); 292 } 293 294 ath11k_hif_write32(ab, reg_base, srng->ring_base_paddr); 295 296 val = FIELD_PREP(HAL_REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB, 297 ((u64)srng->ring_base_paddr >> 298 HAL_ADDR_MSB_REG_SHIFT)) | 299 FIELD_PREP(HAL_REO1_RING_BASE_MSB_RING_SIZE, 300 (srng->entry_size * srng->num_entries)); 301 ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_BASE_MSB_OFFSET(ab), val); 302 303 val = FIELD_PREP(HAL_REO1_RING_ID_RING_ID, srng->ring_id) | 304 FIELD_PREP(HAL_REO1_RING_ID_ENTRY_SIZE, srng->entry_size); 305 ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_ID_OFFSET(ab), val); 306 307 /* interrupt setup */ 308 val = FIELD_PREP(HAL_REO1_RING_PRDR_INT_SETUP_INTR_TMR_THOLD, 309 (srng->intr_timer_thres_us >> 3)); 310 311 val |= FIELD_PREP(HAL_REO1_RING_PRDR_INT_SETUP_BATCH_COUNTER_THOLD, 312 (srng->intr_batch_cntr_thres_entries * 313 srng->entry_size)); 314 315 ath11k_hif_write32(ab, 316 reg_base + HAL_REO1_RING_PRODUCER_INT_SETUP_OFFSET(ab), 317 val); 318 319 hp_addr = hal->rdp.paddr + 320 ((unsigned long)srng->u.dst_ring.hp_addr - 321 (unsigned long)hal->rdp.vaddr); 322 ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_HP_ADDR_LSB_OFFSET(ab), 323 hp_addr & HAL_ADDR_LSB_REG_MASK); 324 ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_HP_ADDR_MSB_OFFSET(ab), 325 hp_addr >> HAL_ADDR_MSB_REG_SHIFT); 326 327 /* Initialize head and tail pointers to indicate ring is empty */ 328 reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R2]; 329 ath11k_hif_write32(ab, reg_base, 0); 330 ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_TP_OFFSET(ab), 0); 331 *srng->u.dst_ring.hp_addr = 0; 332 333 reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R0]; 334 val = 0; 335 if (srng->flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP) 336 val |= HAL_REO1_RING_MISC_DATA_TLV_SWAP; 337 if (srng->flags & HAL_SRNG_FLAGS_RING_PTR_SWAP) 338 val |= HAL_REO1_RING_MISC_HOST_FW_SWAP; 339 if (srng->flags & HAL_SRNG_FLAGS_MSI_SWAP) 340 val |= HAL_REO1_RING_MISC_MSI_SWAP; 341 val |= HAL_REO1_RING_MISC_SRNG_ENABLE; 342 343 ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_MISC_OFFSET(ab), val); 344 } 345 346 static void ath11k_hal_srng_src_hw_init(struct ath11k_base *ab, 347 struct hal_srng *srng) 348 { 349 struct ath11k_hal *hal = &ab->hal; 350 u32 val; 351 u64 tp_addr; 352 u32 reg_base; 353 354 reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R0]; 355 356 if (srng->flags & HAL_SRNG_FLAGS_MSI_INTR) { 357 ath11k_hif_write32(ab, reg_base + 358 HAL_TCL1_RING_MSI1_BASE_LSB_OFFSET(ab), 359 srng->msi_addr); 360 361 val = FIELD_PREP(HAL_TCL1_RING_MSI1_BASE_MSB_ADDR, 362 ((u64)srng->msi_addr >> 363 HAL_ADDR_MSB_REG_SHIFT)) | 364 HAL_TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE; 365 ath11k_hif_write32(ab, reg_base + 366 HAL_TCL1_RING_MSI1_BASE_MSB_OFFSET(ab), 367 val); 368 369 ath11k_hif_write32(ab, reg_base + 370 HAL_TCL1_RING_MSI1_DATA_OFFSET(ab), 371 srng->msi_data); 372 } 373 374 ath11k_hif_write32(ab, reg_base, srng->ring_base_paddr); 375 376 val = FIELD_PREP(HAL_TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB, 377 ((u64)srng->ring_base_paddr >> 378 HAL_ADDR_MSB_REG_SHIFT)) | 379 FIELD_PREP(HAL_TCL1_RING_BASE_MSB_RING_SIZE, 380 (srng->entry_size * srng->num_entries)); 381 ath11k_hif_write32(ab, reg_base + HAL_TCL1_RING_BASE_MSB_OFFSET(ab), val); 382 383 val = FIELD_PREP(HAL_REO1_RING_ID_ENTRY_SIZE, srng->entry_size); 384 ath11k_hif_write32(ab, reg_base + HAL_TCL1_RING_ID_OFFSET(ab), val); 385 386 if (srng->ring_id == HAL_SRNG_RING_ID_WBM_IDLE_LINK) { 387 ath11k_hif_write32(ab, reg_base, (u32)srng->ring_base_paddr); 388 val = FIELD_PREP(HAL_TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB, 389 ((u64)srng->ring_base_paddr >> 390 HAL_ADDR_MSB_REG_SHIFT)) | 391 FIELD_PREP(HAL_TCL1_RING_BASE_MSB_RING_SIZE, 392 (srng->entry_size * srng->num_entries)); 393 ath11k_hif_write32(ab, reg_base + HAL_TCL1_RING_BASE_MSB_OFFSET(ab), val); 394 } 395 396 /* interrupt setup */ 397 /* NOTE: IPQ8074 v2 requires the interrupt timer threshold in the 398 * unit of 8 usecs instead of 1 usec (as required by v1). 399 */ 400 val = FIELD_PREP(HAL_TCL1_RING_CONSR_INT_SETUP_IX0_INTR_TMR_THOLD, 401 srng->intr_timer_thres_us); 402 403 val |= FIELD_PREP(HAL_TCL1_RING_CONSR_INT_SETUP_IX0_BATCH_COUNTER_THOLD, 404 (srng->intr_batch_cntr_thres_entries * 405 srng->entry_size)); 406 407 ath11k_hif_write32(ab, 408 reg_base + HAL_TCL1_RING_CONSR_INT_SETUP_IX0_OFFSET(ab), 409 val); 410 411 val = 0; 412 if (srng->flags & HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN) { 413 val |= FIELD_PREP(HAL_TCL1_RING_CONSR_INT_SETUP_IX1_LOW_THOLD, 414 srng->u.src_ring.low_threshold); 415 } 416 ath11k_hif_write32(ab, 417 reg_base + HAL_TCL1_RING_CONSR_INT_SETUP_IX1_OFFSET(ab), 418 val); 419 420 if (srng->ring_id != HAL_SRNG_RING_ID_WBM_IDLE_LINK) { 421 tp_addr = hal->rdp.paddr + 422 ((unsigned long)srng->u.src_ring.tp_addr - 423 (unsigned long)hal->rdp.vaddr); 424 ath11k_hif_write32(ab, 425 reg_base + HAL_TCL1_RING_TP_ADDR_LSB_OFFSET(ab), 426 tp_addr & HAL_ADDR_LSB_REG_MASK); 427 ath11k_hif_write32(ab, 428 reg_base + HAL_TCL1_RING_TP_ADDR_MSB_OFFSET(ab), 429 tp_addr >> HAL_ADDR_MSB_REG_SHIFT); 430 } 431 432 /* Initialize head and tail pointers to indicate ring is empty */ 433 reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R2]; 434 ath11k_hif_write32(ab, reg_base, 0); 435 ath11k_hif_write32(ab, reg_base + HAL_TCL1_RING_TP_OFFSET, 0); 436 *srng->u.src_ring.tp_addr = 0; 437 438 reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R0]; 439 val = 0; 440 if (srng->flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP) 441 val |= HAL_TCL1_RING_MISC_DATA_TLV_SWAP; 442 if (srng->flags & HAL_SRNG_FLAGS_RING_PTR_SWAP) 443 val |= HAL_TCL1_RING_MISC_HOST_FW_SWAP; 444 if (srng->flags & HAL_SRNG_FLAGS_MSI_SWAP) 445 val |= HAL_TCL1_RING_MISC_MSI_SWAP; 446 447 /* Loop count is not used for SRC rings */ 448 val |= HAL_TCL1_RING_MISC_MSI_LOOPCNT_DISABLE; 449 450 val |= HAL_TCL1_RING_MISC_SRNG_ENABLE; 451 452 ath11k_hif_write32(ab, reg_base + HAL_TCL1_RING_MISC_OFFSET(ab), val); 453 } 454 455 static void ath11k_hal_srng_hw_init(struct ath11k_base *ab, 456 struct hal_srng *srng) 457 { 458 if (srng->ring_dir == HAL_SRNG_DIR_SRC) 459 ath11k_hal_srng_src_hw_init(ab, srng); 460 else 461 ath11k_hal_srng_dst_hw_init(ab, srng); 462 } 463 464 static int ath11k_hal_srng_get_ring_id(struct ath11k_base *ab, 465 enum hal_ring_type type, 466 int ring_num, int mac_id) 467 { 468 struct hal_srng_config *srng_config = &ab->hal.srng_config[type]; 469 int ring_id; 470 471 if (ring_num >= srng_config->max_rings) { 472 ath11k_warn(ab, "invalid ring number :%d\n", ring_num); 473 return -EINVAL; 474 } 475 476 ring_id = srng_config->start_ring_id + ring_num; 477 if (srng_config->lmac_ring) 478 ring_id += mac_id * HAL_SRNG_RINGS_PER_LMAC; 479 480 if (WARN_ON(ring_id >= HAL_SRNG_RING_ID_MAX)) 481 return -EINVAL; 482 483 return ring_id; 484 } 485 486 int ath11k_hal_srng_get_entrysize(struct ath11k_base *ab, u32 ring_type) 487 { 488 struct hal_srng_config *srng_config; 489 490 if (WARN_ON(ring_type >= HAL_MAX_RING_TYPES)) 491 return -EINVAL; 492 493 srng_config = &ab->hal.srng_config[ring_type]; 494 495 return (srng_config->entry_size << 2); 496 } 497 498 int ath11k_hal_srng_get_max_entries(struct ath11k_base *ab, u32 ring_type) 499 { 500 struct hal_srng_config *srng_config; 501 502 if (WARN_ON(ring_type >= HAL_MAX_RING_TYPES)) 503 return -EINVAL; 504 505 srng_config = &ab->hal.srng_config[ring_type]; 506 507 return (srng_config->max_size / srng_config->entry_size); 508 } 509 510 void ath11k_hal_srng_get_params(struct ath11k_base *ab, struct hal_srng *srng, 511 struct hal_srng_params *params) 512 { 513 params->ring_base_paddr = srng->ring_base_paddr; 514 params->ring_base_vaddr = srng->ring_base_vaddr; 515 params->num_entries = srng->num_entries; 516 params->intr_timer_thres_us = srng->intr_timer_thres_us; 517 params->intr_batch_cntr_thres_entries = 518 srng->intr_batch_cntr_thres_entries; 519 params->low_threshold = srng->u.src_ring.low_threshold; 520 params->msi_addr = srng->msi_addr; 521 params->msi_data = srng->msi_data; 522 params->flags = srng->flags; 523 } 524 525 dma_addr_t ath11k_hal_srng_get_hp_addr(struct ath11k_base *ab, 526 struct hal_srng *srng) 527 { 528 if (!(srng->flags & HAL_SRNG_FLAGS_LMAC_RING)) 529 return 0; 530 531 if (srng->ring_dir == HAL_SRNG_DIR_SRC) 532 return ab->hal.wrp.paddr + 533 ((unsigned long)srng->u.src_ring.hp_addr - 534 (unsigned long)ab->hal.wrp.vaddr); 535 else 536 return ab->hal.rdp.paddr + 537 ((unsigned long)srng->u.dst_ring.hp_addr - 538 (unsigned long)ab->hal.rdp.vaddr); 539 } 540 541 dma_addr_t ath11k_hal_srng_get_tp_addr(struct ath11k_base *ab, 542 struct hal_srng *srng) 543 { 544 if (!(srng->flags & HAL_SRNG_FLAGS_LMAC_RING)) 545 return 0; 546 547 if (srng->ring_dir == HAL_SRNG_DIR_SRC) 548 return ab->hal.rdp.paddr + 549 ((unsigned long)srng->u.src_ring.tp_addr - 550 (unsigned long)ab->hal.rdp.vaddr); 551 else 552 return ab->hal.wrp.paddr + 553 ((unsigned long)srng->u.dst_ring.tp_addr - 554 (unsigned long)ab->hal.wrp.vaddr); 555 } 556 557 u32 ath11k_hal_ce_get_desc_size(enum hal_ce_desc type) 558 { 559 switch (type) { 560 case HAL_CE_DESC_SRC: 561 return sizeof(struct hal_ce_srng_src_desc); 562 case HAL_CE_DESC_DST: 563 return sizeof(struct hal_ce_srng_dest_desc); 564 case HAL_CE_DESC_DST_STATUS: 565 return sizeof(struct hal_ce_srng_dst_status_desc); 566 } 567 568 return 0; 569 } 570 571 void ath11k_hal_ce_src_set_desc(void *buf, dma_addr_t paddr, u32 len, u32 id, 572 u8 byte_swap_data) 573 { 574 struct hal_ce_srng_src_desc *desc = buf; 575 576 desc->buffer_addr_low = paddr & HAL_ADDR_LSB_REG_MASK; 577 desc->buffer_addr_info = 578 FIELD_PREP(HAL_CE_SRC_DESC_ADDR_INFO_ADDR_HI, 579 ((u64)paddr >> HAL_ADDR_MSB_REG_SHIFT)) | 580 FIELD_PREP(HAL_CE_SRC_DESC_ADDR_INFO_BYTE_SWAP, 581 byte_swap_data) | 582 FIELD_PREP(HAL_CE_SRC_DESC_ADDR_INFO_GATHER, 0) | 583 FIELD_PREP(HAL_CE_SRC_DESC_ADDR_INFO_LEN, len); 584 desc->meta_info = FIELD_PREP(HAL_CE_SRC_DESC_META_INFO_DATA, id); 585 } 586 587 void ath11k_hal_ce_dst_set_desc(void *buf, dma_addr_t paddr) 588 { 589 struct hal_ce_srng_dest_desc *desc = buf; 590 591 desc->buffer_addr_low = paddr & HAL_ADDR_LSB_REG_MASK; 592 desc->buffer_addr_info = 593 FIELD_PREP(HAL_CE_DEST_DESC_ADDR_INFO_ADDR_HI, 594 ((u64)paddr >> HAL_ADDR_MSB_REG_SHIFT)); 595 } 596 597 u32 ath11k_hal_ce_dst_status_get_length(void *buf) 598 { 599 struct hal_ce_srng_dst_status_desc *desc = buf; 600 u32 len; 601 602 len = FIELD_GET(HAL_CE_DST_STATUS_DESC_FLAGS_LEN, desc->flags); 603 desc->flags &= ~HAL_CE_DST_STATUS_DESC_FLAGS_LEN; 604 605 return len; 606 } 607 608 void ath11k_hal_set_link_desc_addr(struct hal_wbm_link_desc *desc, u32 cookie, 609 dma_addr_t paddr) 610 { 611 desc->buf_addr_info.info0 = FIELD_PREP(BUFFER_ADDR_INFO0_ADDR, 612 (paddr & HAL_ADDR_LSB_REG_MASK)); 613 desc->buf_addr_info.info1 = FIELD_PREP(BUFFER_ADDR_INFO1_ADDR, 614 ((u64)paddr >> HAL_ADDR_MSB_REG_SHIFT)) | 615 FIELD_PREP(BUFFER_ADDR_INFO1_RET_BUF_MGR, 1) | 616 FIELD_PREP(BUFFER_ADDR_INFO1_SW_COOKIE, cookie); 617 } 618 619 u32 *ath11k_hal_srng_dst_peek(struct ath11k_base *ab, struct hal_srng *srng) 620 { 621 lockdep_assert_held(&srng->lock); 622 623 if (srng->u.dst_ring.tp != srng->u.dst_ring.cached_hp) 624 return (srng->ring_base_vaddr + srng->u.dst_ring.tp); 625 626 return NULL; 627 } 628 629 static void ath11k_hal_srng_prefetch_desc(struct ath11k_base *ab, 630 struct hal_srng *srng) 631 { 632 u32 *desc; 633 634 /* prefetch only if desc is available */ 635 desc = ath11k_hal_srng_dst_peek(ab, srng); 636 if (likely(desc)) { 637 dma_sync_single_for_cpu(ab->dev, virt_to_phys(desc), 638 (srng->entry_size * sizeof(u32)), 639 DMA_FROM_DEVICE); 640 prefetch(desc); 641 } 642 } 643 644 u32 *ath11k_hal_srng_dst_get_next_entry(struct ath11k_base *ab, 645 struct hal_srng *srng) 646 { 647 u32 *desc; 648 649 lockdep_assert_held(&srng->lock); 650 651 if (srng->u.dst_ring.tp == srng->u.dst_ring.cached_hp) 652 return NULL; 653 654 desc = srng->ring_base_vaddr + srng->u.dst_ring.tp; 655 656 srng->u.dst_ring.tp += srng->entry_size; 657 658 /* wrap around to start of ring*/ 659 if (srng->u.dst_ring.tp == srng->ring_size) 660 srng->u.dst_ring.tp = 0; 661 662 /* Try to prefetch the next descriptor in the ring */ 663 if (srng->flags & HAL_SRNG_FLAGS_CACHED) 664 ath11k_hal_srng_prefetch_desc(ab, srng); 665 666 return desc; 667 } 668 669 int ath11k_hal_srng_dst_num_free(struct ath11k_base *ab, struct hal_srng *srng, 670 bool sync_hw_ptr) 671 { 672 u32 tp, hp; 673 674 lockdep_assert_held(&srng->lock); 675 676 tp = srng->u.dst_ring.tp; 677 678 if (sync_hw_ptr) { 679 hp = *srng->u.dst_ring.hp_addr; 680 srng->u.dst_ring.cached_hp = hp; 681 } else { 682 hp = srng->u.dst_ring.cached_hp; 683 } 684 685 if (hp >= tp) 686 return (hp - tp) / srng->entry_size; 687 else 688 return (srng->ring_size - tp + hp) / srng->entry_size; 689 } 690 691 /* Returns number of available entries in src ring */ 692 int ath11k_hal_srng_src_num_free(struct ath11k_base *ab, struct hal_srng *srng, 693 bool sync_hw_ptr) 694 { 695 u32 tp, hp; 696 697 lockdep_assert_held(&srng->lock); 698 699 hp = srng->u.src_ring.hp; 700 701 if (sync_hw_ptr) { 702 tp = *srng->u.src_ring.tp_addr; 703 srng->u.src_ring.cached_tp = tp; 704 } else { 705 tp = srng->u.src_ring.cached_tp; 706 } 707 708 if (tp > hp) 709 return ((tp - hp) / srng->entry_size) - 1; 710 else 711 return ((srng->ring_size - hp + tp) / srng->entry_size) - 1; 712 } 713 714 u32 *ath11k_hal_srng_src_get_next_entry(struct ath11k_base *ab, 715 struct hal_srng *srng) 716 { 717 u32 *desc; 718 u32 next_hp; 719 720 lockdep_assert_held(&srng->lock); 721 722 /* TODO: Using % is expensive, but we have to do this since size of some 723 * SRNG rings is not power of 2 (due to descriptor sizes). Need to see 724 * if separate function is defined for rings having power of 2 ring size 725 * (TCL2SW, REO2SW, SW2RXDMA and CE rings) so that we can avoid the 726 * overhead of % by using mask (with &). 727 */ 728 next_hp = (srng->u.src_ring.hp + srng->entry_size) % srng->ring_size; 729 730 if (next_hp == srng->u.src_ring.cached_tp) 731 return NULL; 732 733 desc = srng->ring_base_vaddr + srng->u.src_ring.hp; 734 srng->u.src_ring.hp = next_hp; 735 736 /* TODO: Reap functionality is not used by all rings. If particular 737 * ring does not use reap functionality, we need not update reap_hp 738 * with next_hp pointer. Need to make sure a separate function is used 739 * before doing any optimization by removing below code updating 740 * reap_hp. 741 */ 742 srng->u.src_ring.reap_hp = next_hp; 743 744 return desc; 745 } 746 747 u32 *ath11k_hal_srng_src_reap_next(struct ath11k_base *ab, 748 struct hal_srng *srng) 749 { 750 u32 *desc; 751 u32 next_reap_hp; 752 753 lockdep_assert_held(&srng->lock); 754 755 next_reap_hp = (srng->u.src_ring.reap_hp + srng->entry_size) % 756 srng->ring_size; 757 758 if (next_reap_hp == srng->u.src_ring.cached_tp) 759 return NULL; 760 761 desc = srng->ring_base_vaddr + next_reap_hp; 762 srng->u.src_ring.reap_hp = next_reap_hp; 763 764 return desc; 765 } 766 767 u32 *ath11k_hal_srng_src_get_next_reaped(struct ath11k_base *ab, 768 struct hal_srng *srng) 769 { 770 u32 *desc; 771 772 lockdep_assert_held(&srng->lock); 773 774 if (srng->u.src_ring.hp == srng->u.src_ring.reap_hp) 775 return NULL; 776 777 desc = srng->ring_base_vaddr + srng->u.src_ring.hp; 778 srng->u.src_ring.hp = (srng->u.src_ring.hp + srng->entry_size) % 779 srng->ring_size; 780 781 return desc; 782 } 783 784 u32 *ath11k_hal_srng_src_peek(struct ath11k_base *ab, struct hal_srng *srng) 785 { 786 lockdep_assert_held(&srng->lock); 787 788 if (((srng->u.src_ring.hp + srng->entry_size) % srng->ring_size) == 789 srng->u.src_ring.cached_tp) 790 return NULL; 791 792 return srng->ring_base_vaddr + srng->u.src_ring.hp; 793 } 794 795 void ath11k_hal_srng_access_begin(struct ath11k_base *ab, struct hal_srng *srng) 796 { 797 lockdep_assert_held(&srng->lock); 798 799 if (srng->ring_dir == HAL_SRNG_DIR_SRC) { 800 srng->u.src_ring.cached_tp = 801 *(volatile u32 *)srng->u.src_ring.tp_addr; 802 } else { 803 srng->u.dst_ring.cached_hp = *srng->u.dst_ring.hp_addr; 804 805 /* Try to prefetch the next descriptor in the ring */ 806 if (srng->flags & HAL_SRNG_FLAGS_CACHED) 807 ath11k_hal_srng_prefetch_desc(ab, srng); 808 } 809 } 810 811 /* Update cached ring head/tail pointers to HW. ath11k_hal_srng_access_begin() 812 * should have been called before this. 813 */ 814 void ath11k_hal_srng_access_end(struct ath11k_base *ab, struct hal_srng *srng) 815 { 816 lockdep_assert_held(&srng->lock); 817 818 /* TODO: See if we need a write memory barrier here */ 819 if (srng->flags & HAL_SRNG_FLAGS_LMAC_RING) { 820 /* For LMAC rings, ring pointer updates are done through FW and 821 * hence written to a shared memory location that is read by FW 822 */ 823 if (srng->ring_dir == HAL_SRNG_DIR_SRC) { 824 srng->u.src_ring.last_tp = 825 *(volatile u32 *)srng->u.src_ring.tp_addr; 826 *srng->u.src_ring.hp_addr = srng->u.src_ring.hp; 827 } else { 828 srng->u.dst_ring.last_hp = *srng->u.dst_ring.hp_addr; 829 *srng->u.dst_ring.tp_addr = srng->u.dst_ring.tp; 830 } 831 } else { 832 if (srng->ring_dir == HAL_SRNG_DIR_SRC) { 833 srng->u.src_ring.last_tp = 834 *(volatile u32 *)srng->u.src_ring.tp_addr; 835 ath11k_hif_write32(ab, 836 (unsigned long)srng->u.src_ring.hp_addr - 837 (unsigned long)ab->mem, 838 srng->u.src_ring.hp); 839 } else { 840 srng->u.dst_ring.last_hp = *srng->u.dst_ring.hp_addr; 841 ath11k_hif_write32(ab, 842 (unsigned long)srng->u.dst_ring.tp_addr - 843 (unsigned long)ab->mem, 844 srng->u.dst_ring.tp); 845 } 846 } 847 848 srng->timestamp = jiffies; 849 } 850 851 void ath11k_hal_setup_link_idle_list(struct ath11k_base *ab, 852 struct hal_wbm_idle_scatter_list *sbuf, 853 u32 nsbufs, u32 tot_link_desc, 854 u32 end_offset) 855 { 856 struct ath11k_buffer_addr *link_addr; 857 int i; 858 u32 reg_scatter_buf_sz = HAL_WBM_IDLE_SCATTER_BUF_SIZE / 64; 859 860 link_addr = (void *)sbuf[0].vaddr + HAL_WBM_IDLE_SCATTER_BUF_SIZE; 861 862 for (i = 1; i < nsbufs; i++) { 863 link_addr->info0 = sbuf[i].paddr & HAL_ADDR_LSB_REG_MASK; 864 link_addr->info1 = FIELD_PREP( 865 HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_39_32, 866 (u64)sbuf[i].paddr >> HAL_ADDR_MSB_REG_SHIFT) | 867 FIELD_PREP( 868 HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_MATCH_TAG, 869 BASE_ADDR_MATCH_TAG_VAL); 870 871 link_addr = (void *)sbuf[i].vaddr + 872 HAL_WBM_IDLE_SCATTER_BUF_SIZE; 873 } 874 875 ath11k_hif_write32(ab, 876 HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_R0_IDLE_LIST_CONTROL_ADDR, 877 FIELD_PREP(HAL_WBM_SCATTER_BUFFER_SIZE, reg_scatter_buf_sz) | 878 FIELD_PREP(HAL_WBM_LINK_DESC_IDLE_LIST_MODE, 0x1)); 879 ath11k_hif_write32(ab, 880 HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_R0_IDLE_LIST_SIZE_ADDR, 881 FIELD_PREP(HAL_WBM_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST, 882 reg_scatter_buf_sz * nsbufs)); 883 ath11k_hif_write32(ab, 884 HAL_SEQ_WCSS_UMAC_WBM_REG + 885 HAL_WBM_SCATTERED_RING_BASE_LSB, 886 FIELD_PREP(BUFFER_ADDR_INFO0_ADDR, 887 sbuf[0].paddr & HAL_ADDR_LSB_REG_MASK)); 888 ath11k_hif_write32(ab, 889 HAL_SEQ_WCSS_UMAC_WBM_REG + 890 HAL_WBM_SCATTERED_RING_BASE_MSB, 891 FIELD_PREP( 892 HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_39_32, 893 (u64)sbuf[0].paddr >> HAL_ADDR_MSB_REG_SHIFT) | 894 FIELD_PREP( 895 HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_MATCH_TAG, 896 BASE_ADDR_MATCH_TAG_VAL)); 897 898 /* Setup head and tail pointers for the idle list */ 899 ath11k_hif_write32(ab, 900 HAL_SEQ_WCSS_UMAC_WBM_REG + 901 HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX0, 902 FIELD_PREP(BUFFER_ADDR_INFO0_ADDR, 903 sbuf[nsbufs - 1].paddr)); 904 ath11k_hif_write32(ab, 905 HAL_SEQ_WCSS_UMAC_WBM_REG + 906 HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX1, 907 FIELD_PREP( 908 HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_39_32, 909 ((u64)sbuf[nsbufs - 1].paddr >> 910 HAL_ADDR_MSB_REG_SHIFT)) | 911 FIELD_PREP(HAL_WBM_SCATTERED_DESC_HEAD_P_OFFSET_IX1, 912 (end_offset >> 2))); 913 ath11k_hif_write32(ab, 914 HAL_SEQ_WCSS_UMAC_WBM_REG + 915 HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX0, 916 FIELD_PREP(BUFFER_ADDR_INFO0_ADDR, 917 sbuf[0].paddr)); 918 919 ath11k_hif_write32(ab, 920 HAL_SEQ_WCSS_UMAC_WBM_REG + 921 HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX0, 922 FIELD_PREP(BUFFER_ADDR_INFO0_ADDR, 923 sbuf[0].paddr)); 924 ath11k_hif_write32(ab, 925 HAL_SEQ_WCSS_UMAC_WBM_REG + 926 HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX1, 927 FIELD_PREP( 928 HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_39_32, 929 ((u64)sbuf[0].paddr >> HAL_ADDR_MSB_REG_SHIFT)) | 930 FIELD_PREP(HAL_WBM_SCATTERED_DESC_TAIL_P_OFFSET_IX1, 931 0)); 932 ath11k_hif_write32(ab, 933 HAL_SEQ_WCSS_UMAC_WBM_REG + 934 HAL_WBM_SCATTERED_DESC_PTR_HP_ADDR, 935 2 * tot_link_desc); 936 937 /* Enable the SRNG */ 938 ath11k_hif_write32(ab, 939 HAL_SEQ_WCSS_UMAC_WBM_REG + 940 HAL_WBM_IDLE_LINK_RING_MISC_ADDR(ab), 0x40); 941 } 942 943 int ath11k_hal_srng_setup(struct ath11k_base *ab, enum hal_ring_type type, 944 int ring_num, int mac_id, 945 struct hal_srng_params *params) 946 { 947 struct ath11k_hal *hal = &ab->hal; 948 struct hal_srng_config *srng_config = &ab->hal.srng_config[type]; 949 struct hal_srng *srng; 950 int ring_id; 951 u32 lmac_idx; 952 int i; 953 u32 reg_base; 954 955 ring_id = ath11k_hal_srng_get_ring_id(ab, type, ring_num, mac_id); 956 if (ring_id < 0) 957 return ring_id; 958 959 srng = &hal->srng_list[ring_id]; 960 961 srng->ring_id = ring_id; 962 srng->ring_dir = srng_config->ring_dir; 963 srng->ring_base_paddr = params->ring_base_paddr; 964 srng->ring_base_vaddr = params->ring_base_vaddr; 965 srng->entry_size = srng_config->entry_size; 966 srng->num_entries = params->num_entries; 967 srng->ring_size = srng->entry_size * srng->num_entries; 968 srng->intr_batch_cntr_thres_entries = 969 params->intr_batch_cntr_thres_entries; 970 srng->intr_timer_thres_us = params->intr_timer_thres_us; 971 srng->flags = params->flags; 972 srng->msi_addr = params->msi_addr; 973 srng->msi_data = params->msi_data; 974 srng->initialized = 1; 975 spin_lock_init(&srng->lock); 976 lockdep_set_class(&srng->lock, hal->srng_key + ring_id); 977 978 for (i = 0; i < HAL_SRNG_NUM_REG_GRP; i++) { 979 srng->hwreg_base[i] = srng_config->reg_start[i] + 980 (ring_num * srng_config->reg_size[i]); 981 } 982 983 memset(srng->ring_base_vaddr, 0, 984 (srng->entry_size * srng->num_entries) << 2); 985 986 /* TODO: Add comments on these swap configurations */ 987 if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 988 srng->flags |= HAL_SRNG_FLAGS_MSI_SWAP | HAL_SRNG_FLAGS_DATA_TLV_SWAP | 989 HAL_SRNG_FLAGS_RING_PTR_SWAP; 990 991 reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R2]; 992 993 if (srng->ring_dir == HAL_SRNG_DIR_SRC) { 994 srng->u.src_ring.hp = 0; 995 srng->u.src_ring.cached_tp = 0; 996 srng->u.src_ring.reap_hp = srng->ring_size - srng->entry_size; 997 srng->u.src_ring.tp_addr = (void *)(hal->rdp.vaddr + ring_id); 998 srng->u.src_ring.low_threshold = params->low_threshold * 999 srng->entry_size; 1000 if (srng_config->lmac_ring) { 1001 lmac_idx = ring_id - HAL_SRNG_RING_ID_LMAC1_ID_START; 1002 srng->u.src_ring.hp_addr = (void *)(hal->wrp.vaddr + 1003 lmac_idx); 1004 srng->flags |= HAL_SRNG_FLAGS_LMAC_RING; 1005 } else { 1006 if (!ab->hw_params.supports_shadow_regs) 1007 srng->u.src_ring.hp_addr = 1008 (u32 *)((unsigned long)ab->mem + reg_base); 1009 else 1010 ath11k_dbg(ab, ATH11K_DBG_HAL, 1011 "type %d ring_num %d reg_base 0x%x shadow 0x%lx\n", 1012 type, ring_num, 1013 reg_base, 1014 (unsigned long)srng->u.src_ring.hp_addr - 1015 (unsigned long)ab->mem); 1016 } 1017 } else { 1018 /* During initialization loop count in all the descriptors 1019 * will be set to zero, and HW will set it to 1 on completing 1020 * descriptor update in first loop, and increments it by 1 on 1021 * subsequent loops (loop count wraps around after reaching 1022 * 0xffff). The 'loop_cnt' in SW ring state is the expected 1023 * loop count in descriptors updated by HW (to be processed 1024 * by SW). 1025 */ 1026 srng->u.dst_ring.loop_cnt = 1; 1027 srng->u.dst_ring.tp = 0; 1028 srng->u.dst_ring.cached_hp = 0; 1029 srng->u.dst_ring.hp_addr = (void *)(hal->rdp.vaddr + ring_id); 1030 if (srng_config->lmac_ring) { 1031 /* For LMAC rings, tail pointer updates will be done 1032 * through FW by writing to a shared memory location 1033 */ 1034 lmac_idx = ring_id - HAL_SRNG_RING_ID_LMAC1_ID_START; 1035 srng->u.dst_ring.tp_addr = (void *)(hal->wrp.vaddr + 1036 lmac_idx); 1037 srng->flags |= HAL_SRNG_FLAGS_LMAC_RING; 1038 } else { 1039 if (!ab->hw_params.supports_shadow_regs) 1040 srng->u.dst_ring.tp_addr = 1041 (u32 *)((unsigned long)ab->mem + reg_base + 1042 (HAL_REO1_RING_TP(ab) - HAL_REO1_RING_HP(ab))); 1043 else 1044 ath11k_dbg(ab, ATH11K_DBG_HAL, 1045 "type %d ring_num %d target_reg 0x%x shadow 0x%lx\n", 1046 type, ring_num, 1047 reg_base + (HAL_REO1_RING_TP(ab) - 1048 HAL_REO1_RING_HP(ab)), 1049 (unsigned long)srng->u.dst_ring.tp_addr - 1050 (unsigned long)ab->mem); 1051 } 1052 } 1053 1054 if (srng_config->lmac_ring) 1055 return ring_id; 1056 1057 ath11k_hal_srng_hw_init(ab, srng); 1058 1059 if (type == HAL_CE_DST) { 1060 srng->u.dst_ring.max_buffer_length = params->max_buffer_len; 1061 ath11k_hal_ce_dst_setup(ab, srng, ring_num); 1062 } 1063 1064 return ring_id; 1065 } 1066 1067 static void ath11k_hal_srng_update_hp_tp_addr(struct ath11k_base *ab, 1068 int shadow_cfg_idx, 1069 enum hal_ring_type ring_type, 1070 int ring_num) 1071 { 1072 struct hal_srng *srng; 1073 struct ath11k_hal *hal = &ab->hal; 1074 int ring_id; 1075 struct hal_srng_config *srng_config = &hal->srng_config[ring_type]; 1076 1077 ring_id = ath11k_hal_srng_get_ring_id(ab, ring_type, ring_num, 0); 1078 if (ring_id < 0) 1079 return; 1080 1081 srng = &hal->srng_list[ring_id]; 1082 1083 if (srng_config->ring_dir == HAL_SRNG_DIR_DST) 1084 srng->u.dst_ring.tp_addr = (u32 *)(HAL_SHADOW_REG(ab, shadow_cfg_idx) + 1085 (unsigned long)ab->mem); 1086 else 1087 srng->u.src_ring.hp_addr = (u32 *)(HAL_SHADOW_REG(ab, shadow_cfg_idx) + 1088 (unsigned long)ab->mem); 1089 } 1090 1091 int ath11k_hal_srng_update_shadow_config(struct ath11k_base *ab, 1092 enum hal_ring_type ring_type, 1093 int ring_num) 1094 { 1095 struct ath11k_hal *hal = &ab->hal; 1096 struct hal_srng_config *srng_config = &hal->srng_config[ring_type]; 1097 int shadow_cfg_idx = hal->num_shadow_reg_configured; 1098 u32 target_reg; 1099 1100 if (shadow_cfg_idx >= HAL_SHADOW_NUM_REGS) 1101 return -EINVAL; 1102 1103 hal->num_shadow_reg_configured++; 1104 1105 target_reg = srng_config->reg_start[HAL_HP_OFFSET_IN_REG_START]; 1106 target_reg += srng_config->reg_size[HAL_HP_OFFSET_IN_REG_START] * 1107 ring_num; 1108 1109 /* For destination ring, shadow the TP */ 1110 if (srng_config->ring_dir == HAL_SRNG_DIR_DST) 1111 target_reg += HAL_OFFSET_FROM_HP_TO_TP; 1112 1113 hal->shadow_reg_addr[shadow_cfg_idx] = target_reg; 1114 1115 /* update hp/tp addr to hal structure*/ 1116 ath11k_hal_srng_update_hp_tp_addr(ab, shadow_cfg_idx, ring_type, 1117 ring_num); 1118 1119 ath11k_dbg(ab, ATH11K_DBG_HAL, 1120 "update shadow config target_reg %x shadow reg 0x%x shadow_idx 0x%x ring_type %d ring num %d", 1121 target_reg, 1122 HAL_SHADOW_REG(ab, shadow_cfg_idx), 1123 shadow_cfg_idx, 1124 ring_type, ring_num); 1125 1126 return 0; 1127 } 1128 1129 void ath11k_hal_srng_shadow_config(struct ath11k_base *ab) 1130 { 1131 struct ath11k_hal *hal = &ab->hal; 1132 int ring_type, ring_num; 1133 1134 /* update all the non-CE srngs. */ 1135 for (ring_type = 0; ring_type < HAL_MAX_RING_TYPES; ring_type++) { 1136 struct hal_srng_config *srng_config = &hal->srng_config[ring_type]; 1137 1138 if (ring_type == HAL_CE_SRC || 1139 ring_type == HAL_CE_DST || 1140 ring_type == HAL_CE_DST_STATUS) 1141 continue; 1142 1143 if (srng_config->lmac_ring) 1144 continue; 1145 1146 for (ring_num = 0; ring_num < srng_config->max_rings; ring_num++) 1147 ath11k_hal_srng_update_shadow_config(ab, ring_type, ring_num); 1148 } 1149 } 1150 1151 void ath11k_hal_srng_get_shadow_config(struct ath11k_base *ab, 1152 u32 **cfg, u32 *len) 1153 { 1154 struct ath11k_hal *hal = &ab->hal; 1155 1156 *len = hal->num_shadow_reg_configured; 1157 *cfg = hal->shadow_reg_addr; 1158 } 1159 1160 void ath11k_hal_srng_shadow_update_hp_tp(struct ath11k_base *ab, 1161 struct hal_srng *srng) 1162 { 1163 lockdep_assert_held(&srng->lock); 1164 1165 /* check whether the ring is empty. Update the shadow 1166 * HP only when then ring isn't empty. 1167 */ 1168 if (srng->ring_dir == HAL_SRNG_DIR_SRC && 1169 *srng->u.src_ring.tp_addr != srng->u.src_ring.hp) 1170 ath11k_hal_srng_access_end(ab, srng); 1171 } 1172 1173 static int ath11k_hal_srng_create_config(struct ath11k_base *ab) 1174 { 1175 struct ath11k_hal *hal = &ab->hal; 1176 struct hal_srng_config *s; 1177 1178 hal->srng_config = kmemdup(hw_srng_config_template, 1179 sizeof(hw_srng_config_template), 1180 GFP_KERNEL); 1181 if (!hal->srng_config) 1182 return -ENOMEM; 1183 1184 s = &hal->srng_config[HAL_REO_DST]; 1185 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_RING_BASE_LSB(ab); 1186 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_RING_HP(ab); 1187 s->reg_size[0] = HAL_REO2_RING_BASE_LSB(ab) - HAL_REO1_RING_BASE_LSB(ab); 1188 s->reg_size[1] = HAL_REO2_RING_HP(ab) - HAL_REO1_RING_HP(ab); 1189 1190 s = &hal->srng_config[HAL_REO_EXCEPTION]; 1191 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_TCL_RING_BASE_LSB(ab); 1192 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_TCL_RING_HP(ab); 1193 1194 s = &hal->srng_config[HAL_REO_REINJECT]; 1195 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_BASE_LSB(ab); 1196 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_HP(ab); 1197 1198 s = &hal->srng_config[HAL_REO_CMD]; 1199 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_RING_BASE_LSB(ab); 1200 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_HP(ab); 1201 1202 s = &hal->srng_config[HAL_REO_STATUS]; 1203 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_STATUS_RING_BASE_LSB(ab); 1204 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_STATUS_HP(ab); 1205 1206 s = &hal->srng_config[HAL_TCL_DATA]; 1207 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_BASE_LSB(ab); 1208 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_HP; 1209 s->reg_size[0] = HAL_TCL2_RING_BASE_LSB(ab) - HAL_TCL1_RING_BASE_LSB(ab); 1210 s->reg_size[1] = HAL_TCL2_RING_HP - HAL_TCL1_RING_HP; 1211 1212 s = &hal->srng_config[HAL_TCL_CMD]; 1213 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_RING_BASE_LSB(ab); 1214 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_RING_HP; 1215 1216 s = &hal->srng_config[HAL_TCL_STATUS]; 1217 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_STATUS_RING_BASE_LSB(ab); 1218 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_STATUS_RING_HP; 1219 1220 s = &hal->srng_config[HAL_CE_SRC]; 1221 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab) + HAL_CE_DST_RING_BASE_LSB + 1222 ATH11K_CE_OFFSET(ab); 1223 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab) + HAL_CE_DST_RING_HP + 1224 ATH11K_CE_OFFSET(ab); 1225 s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_SRC_REG(ab) - 1226 HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab); 1227 s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_SRC_REG(ab) - 1228 HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab); 1229 1230 s = &hal->srng_config[HAL_CE_DST]; 1231 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + HAL_CE_DST_RING_BASE_LSB + 1232 ATH11K_CE_OFFSET(ab); 1233 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + HAL_CE_DST_RING_HP + 1234 ATH11K_CE_OFFSET(ab); 1235 s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) - 1236 HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab); 1237 s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) - 1238 HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab); 1239 1240 s = &hal->srng_config[HAL_CE_DST_STATUS]; 1241 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + 1242 HAL_CE_DST_STATUS_RING_BASE_LSB + ATH11K_CE_OFFSET(ab); 1243 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + HAL_CE_DST_STATUS_RING_HP + 1244 ATH11K_CE_OFFSET(ab); 1245 s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) - 1246 HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab); 1247 s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) - 1248 HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab); 1249 1250 s = &hal->srng_config[HAL_WBM_IDLE_LINK]; 1251 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_BASE_LSB(ab); 1252 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_HP; 1253 1254 s = &hal->srng_config[HAL_SW2WBM_RELEASE]; 1255 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_RELEASE_RING_BASE_LSB(ab); 1256 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_RELEASE_RING_HP; 1257 1258 s = &hal->srng_config[HAL_WBM2SW_RELEASE]; 1259 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM0_RELEASE_RING_BASE_LSB(ab); 1260 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM0_RELEASE_RING_HP; 1261 s->reg_size[0] = HAL_WBM1_RELEASE_RING_BASE_LSB(ab) - 1262 HAL_WBM0_RELEASE_RING_BASE_LSB(ab); 1263 s->reg_size[1] = HAL_WBM1_RELEASE_RING_HP - HAL_WBM0_RELEASE_RING_HP; 1264 1265 return 0; 1266 } 1267 1268 static void ath11k_hal_register_srng_key(struct ath11k_base *ab) 1269 { 1270 struct ath11k_hal *hal = &ab->hal; 1271 u32 ring_id; 1272 1273 for (ring_id = 0; ring_id < HAL_SRNG_RING_ID_MAX; ring_id++) 1274 lockdep_register_key(hal->srng_key + ring_id); 1275 } 1276 1277 static void ath11k_hal_unregister_srng_key(struct ath11k_base *ab) 1278 { 1279 struct ath11k_hal *hal = &ab->hal; 1280 u32 ring_id; 1281 1282 for (ring_id = 0; ring_id < HAL_SRNG_RING_ID_MAX; ring_id++) 1283 lockdep_unregister_key(hal->srng_key + ring_id); 1284 } 1285 1286 int ath11k_hal_srng_init(struct ath11k_base *ab) 1287 { 1288 struct ath11k_hal *hal = &ab->hal; 1289 int ret; 1290 1291 memset(hal, 0, sizeof(*hal)); 1292 1293 ret = ath11k_hal_srng_create_config(ab); 1294 if (ret) 1295 goto err_hal; 1296 1297 ret = ath11k_hal_alloc_cont_rdp(ab); 1298 if (ret) 1299 goto err_hal; 1300 1301 ret = ath11k_hal_alloc_cont_wrp(ab); 1302 if (ret) 1303 goto err_free_cont_rdp; 1304 1305 ath11k_hal_register_srng_key(ab); 1306 1307 return 0; 1308 1309 err_free_cont_rdp: 1310 ath11k_hal_free_cont_rdp(ab); 1311 1312 err_hal: 1313 return ret; 1314 } 1315 EXPORT_SYMBOL(ath11k_hal_srng_init); 1316 1317 void ath11k_hal_srng_deinit(struct ath11k_base *ab) 1318 { 1319 struct ath11k_hal *hal = &ab->hal; 1320 1321 ath11k_hal_unregister_srng_key(ab); 1322 ath11k_hal_free_cont_rdp(ab); 1323 ath11k_hal_free_cont_wrp(ab); 1324 kfree(hal->srng_config); 1325 } 1326 EXPORT_SYMBOL(ath11k_hal_srng_deinit); 1327 1328 void ath11k_hal_dump_srng_stats(struct ath11k_base *ab) 1329 { 1330 struct hal_srng *srng; 1331 struct ath11k_ext_irq_grp *irq_grp; 1332 struct ath11k_ce_pipe *ce_pipe; 1333 int i; 1334 1335 ath11k_err(ab, "Last interrupt received for each CE:\n"); 1336 for (i = 0; i < ab->hw_params.ce_count; i++) { 1337 ce_pipe = &ab->ce.ce_pipe[i]; 1338 1339 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 1340 continue; 1341 1342 ath11k_err(ab, "CE_id %d pipe_num %d %ums before\n", 1343 i, ce_pipe->pipe_num, 1344 jiffies_to_msecs(jiffies - ce_pipe->timestamp)); 1345 } 1346 1347 ath11k_err(ab, "\nLast interrupt received for each group:\n"); 1348 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) { 1349 irq_grp = &ab->ext_irq_grp[i]; 1350 ath11k_err(ab, "group_id %d %ums before\n", 1351 irq_grp->grp_id, 1352 jiffies_to_msecs(jiffies - irq_grp->timestamp)); 1353 } 1354 1355 for (i = 0; i < HAL_SRNG_RING_ID_MAX; i++) { 1356 srng = &ab->hal.srng_list[i]; 1357 1358 if (!srng->initialized) 1359 continue; 1360 1361 if (srng->ring_dir == HAL_SRNG_DIR_SRC) 1362 ath11k_err(ab, 1363 "src srng id %u hp %u, reap_hp %u, cur tp %u, cached tp %u last tp %u napi processed before %ums\n", 1364 srng->ring_id, srng->u.src_ring.hp, 1365 srng->u.src_ring.reap_hp, 1366 *srng->u.src_ring.tp_addr, srng->u.src_ring.cached_tp, 1367 srng->u.src_ring.last_tp, 1368 jiffies_to_msecs(jiffies - srng->timestamp)); 1369 else if (srng->ring_dir == HAL_SRNG_DIR_DST) 1370 ath11k_err(ab, 1371 "dst srng id %u tp %u, cur hp %u, cached hp %u last hp %u napi processed before %ums\n", 1372 srng->ring_id, srng->u.dst_ring.tp, 1373 *srng->u.dst_ring.hp_addr, 1374 srng->u.dst_ring.cached_hp, 1375 srng->u.dst_ring.last_hp, 1376 jiffies_to_msecs(jiffies - srng->timestamp)); 1377 } 1378 } 1379