1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 */ 5 6 #include "core.h" 7 #include "dp_tx.h" 8 #include "debug.h" 9 #include "debugfs_sta.h" 10 #include "hw.h" 11 #include "peer.h" 12 13 static enum hal_tcl_encap_type 14 ath11k_dp_tx_get_encap_type(struct ath11k_vif *arvif, struct sk_buff *skb) 15 { 16 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 17 struct ath11k_base *ab = arvif->ar->ab; 18 19 if (test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags)) 20 return HAL_TCL_ENCAP_TYPE_RAW; 21 22 if (tx_info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) 23 return HAL_TCL_ENCAP_TYPE_ETHERNET; 24 25 return HAL_TCL_ENCAP_TYPE_NATIVE_WIFI; 26 } 27 28 static void ath11k_dp_tx_encap_nwifi(struct sk_buff *skb) 29 { 30 struct ieee80211_hdr *hdr = (void *)skb->data; 31 u8 *qos_ctl; 32 33 if (!ieee80211_is_data_qos(hdr->frame_control)) 34 return; 35 36 qos_ctl = ieee80211_get_qos_ctl(hdr); 37 memmove(skb->data + IEEE80211_QOS_CTL_LEN, 38 skb->data, (void *)qos_ctl - (void *)skb->data); 39 skb_pull(skb, IEEE80211_QOS_CTL_LEN); 40 41 hdr = (void *)skb->data; 42 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_STYPE_QOS_DATA); 43 } 44 45 static u8 ath11k_dp_tx_get_tid(struct sk_buff *skb) 46 { 47 struct ieee80211_hdr *hdr = (void *)skb->data; 48 struct ath11k_skb_cb *cb = ATH11K_SKB_CB(skb); 49 50 if (cb->flags & ATH11K_SKB_HW_80211_ENCAP) 51 return skb->priority & IEEE80211_QOS_CTL_TID_MASK; 52 else if (!ieee80211_is_data_qos(hdr->frame_control)) 53 return HAL_DESC_REO_NON_QOS_TID; 54 else 55 return skb->priority & IEEE80211_QOS_CTL_TID_MASK; 56 } 57 58 enum hal_encrypt_type ath11k_dp_tx_get_encrypt_type(u32 cipher) 59 { 60 switch (cipher) { 61 case WLAN_CIPHER_SUITE_WEP40: 62 return HAL_ENCRYPT_TYPE_WEP_40; 63 case WLAN_CIPHER_SUITE_WEP104: 64 return HAL_ENCRYPT_TYPE_WEP_104; 65 case WLAN_CIPHER_SUITE_TKIP: 66 return HAL_ENCRYPT_TYPE_TKIP_MIC; 67 case WLAN_CIPHER_SUITE_CCMP: 68 return HAL_ENCRYPT_TYPE_CCMP_128; 69 case WLAN_CIPHER_SUITE_CCMP_256: 70 return HAL_ENCRYPT_TYPE_CCMP_256; 71 case WLAN_CIPHER_SUITE_GCMP: 72 return HAL_ENCRYPT_TYPE_GCMP_128; 73 case WLAN_CIPHER_SUITE_GCMP_256: 74 return HAL_ENCRYPT_TYPE_AES_GCMP_256; 75 default: 76 return HAL_ENCRYPT_TYPE_OPEN; 77 } 78 } 79 80 int ath11k_dp_tx(struct ath11k *ar, struct ath11k_vif *arvif, 81 struct ath11k_sta *arsta, struct sk_buff *skb) 82 { 83 struct ath11k_base *ab = ar->ab; 84 struct ath11k_dp *dp = &ab->dp; 85 struct hal_tx_info ti = {0}; 86 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 87 struct ath11k_skb_cb *skb_cb = ATH11K_SKB_CB(skb); 88 struct hal_srng *tcl_ring; 89 struct ieee80211_hdr *hdr = (void *)skb->data; 90 struct dp_tx_ring *tx_ring; 91 void *hal_tcl_desc; 92 u8 pool_id; 93 u8 hal_ring_id; 94 int ret; 95 u8 ring_selector = 0, ring_map = 0; 96 bool tcl_ring_retry; 97 98 if (unlikely(test_bit(ATH11K_FLAG_CRASH_FLUSH, &ar->ab->dev_flags))) 99 return -ESHUTDOWN; 100 101 if (unlikely(!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) && 102 !ieee80211_is_data(hdr->frame_control))) 103 return -ENOTSUPP; 104 105 pool_id = skb_get_queue_mapping(skb) & (ATH11K_HW_MAX_QUEUES - 1); 106 107 /* Let the default ring selection be based on current processor 108 * number, where one of the 3 tcl rings are selected based on 109 * the smp_processor_id(). In case that ring 110 * is full/busy, we resort to other available rings. 111 * If all rings are full, we drop the packet. 112 * //TODO Add throttling logic when all rings are full 113 */ 114 ring_selector = smp_processor_id(); 115 116 tcl_ring_sel: 117 tcl_ring_retry = false; 118 119 ti.ring_id = ring_selector % ab->hw_params.max_tx_ring; 120 121 ring_map |= BIT(ti.ring_id); 122 123 tx_ring = &dp->tx_ring[ti.ring_id]; 124 125 spin_lock_bh(&tx_ring->tx_idr_lock); 126 ret = idr_alloc(&tx_ring->txbuf_idr, skb, 0, 127 DP_TX_IDR_SIZE - 1, GFP_ATOMIC); 128 spin_unlock_bh(&tx_ring->tx_idr_lock); 129 130 if (unlikely(ret < 0)) { 131 if (ring_map == (BIT(ab->hw_params.max_tx_ring) - 1)) { 132 atomic_inc(&ab->soc_stats.tx_err.misc_fail); 133 return -ENOSPC; 134 } 135 136 /* Check if the next ring is available */ 137 ring_selector++; 138 goto tcl_ring_sel; 139 } 140 141 ti.desc_id = FIELD_PREP(DP_TX_DESC_ID_MAC_ID, ar->pdev_idx) | 142 FIELD_PREP(DP_TX_DESC_ID_MSDU_ID, ret) | 143 FIELD_PREP(DP_TX_DESC_ID_POOL_ID, pool_id); 144 ti.encap_type = ath11k_dp_tx_get_encap_type(arvif, skb); 145 146 if (ieee80211_has_a4(hdr->frame_control) && 147 is_multicast_ether_addr(hdr->addr3) && arsta && 148 arsta->use_4addr_set) { 149 ti.meta_data_flags = arsta->tcl_metadata; 150 ti.flags0 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TO_FW, 1); 151 } else { 152 ti.meta_data_flags = arvif->tcl_metadata; 153 } 154 155 if (unlikely(ti.encap_type == HAL_TCL_ENCAP_TYPE_RAW)) { 156 if (skb_cb->flags & ATH11K_SKB_CIPHER_SET) { 157 ti.encrypt_type = 158 ath11k_dp_tx_get_encrypt_type(skb_cb->cipher); 159 160 if (ieee80211_has_protected(hdr->frame_control)) 161 skb_put(skb, IEEE80211_CCMP_MIC_LEN); 162 } else { 163 ti.encrypt_type = HAL_ENCRYPT_TYPE_OPEN; 164 } 165 } 166 167 ti.addr_search_flags = arvif->hal_addr_search_flags; 168 ti.search_type = arvif->search_type; 169 ti.type = HAL_TCL_DESC_TYPE_BUFFER; 170 ti.pkt_offset = 0; 171 ti.lmac_id = ar->lmac_id; 172 ti.bss_ast_hash = arvif->ast_hash; 173 ti.bss_ast_idx = arvif->ast_idx; 174 ti.dscp_tid_tbl_idx = 0; 175 176 if (likely(skb->ip_summed == CHECKSUM_PARTIAL && 177 ti.encap_type != HAL_TCL_ENCAP_TYPE_RAW)) { 178 ti.flags0 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_IP4_CKSUM_EN, 1) | 179 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_UDP4_CKSUM_EN, 1) | 180 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_UDP6_CKSUM_EN, 1) | 181 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TCP4_CKSUM_EN, 1) | 182 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TCP6_CKSUM_EN, 1); 183 } 184 185 if (ieee80211_vif_is_mesh(arvif->vif)) 186 ti.enable_mesh = true; 187 188 ti.flags1 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO2_TID_OVERWRITE, 1); 189 190 ti.tid = ath11k_dp_tx_get_tid(skb); 191 192 switch (ti.encap_type) { 193 case HAL_TCL_ENCAP_TYPE_NATIVE_WIFI: 194 ath11k_dp_tx_encap_nwifi(skb); 195 break; 196 case HAL_TCL_ENCAP_TYPE_RAW: 197 if (!test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags)) { 198 ret = -EINVAL; 199 goto fail_remove_idr; 200 } 201 break; 202 case HAL_TCL_ENCAP_TYPE_ETHERNET: 203 /* no need to encap */ 204 break; 205 case HAL_TCL_ENCAP_TYPE_802_3: 206 default: 207 /* TODO: Take care of other encap modes as well */ 208 ret = -EINVAL; 209 atomic_inc(&ab->soc_stats.tx_err.misc_fail); 210 goto fail_remove_idr; 211 } 212 213 ti.paddr = dma_map_single(ab->dev, skb->data, skb->len, DMA_TO_DEVICE); 214 if (unlikely(dma_mapping_error(ab->dev, ti.paddr))) { 215 atomic_inc(&ab->soc_stats.tx_err.misc_fail); 216 ath11k_warn(ab, "failed to DMA map data Tx buffer\n"); 217 ret = -ENOMEM; 218 goto fail_remove_idr; 219 } 220 221 ti.data_len = skb->len; 222 skb_cb->paddr = ti.paddr; 223 skb_cb->vif = arvif->vif; 224 skb_cb->ar = ar; 225 226 hal_ring_id = tx_ring->tcl_data_ring.ring_id; 227 tcl_ring = &ab->hal.srng_list[hal_ring_id]; 228 229 spin_lock_bh(&tcl_ring->lock); 230 231 ath11k_hal_srng_access_begin(ab, tcl_ring); 232 233 hal_tcl_desc = (void *)ath11k_hal_srng_src_get_next_entry(ab, tcl_ring); 234 if (unlikely(!hal_tcl_desc)) { 235 /* NOTE: It is highly unlikely we'll be running out of tcl_ring 236 * desc because the desc is directly enqueued onto hw queue. 237 */ 238 ath11k_hal_srng_access_end(ab, tcl_ring); 239 ab->soc_stats.tx_err.desc_na[ti.ring_id]++; 240 spin_unlock_bh(&tcl_ring->lock); 241 ret = -ENOMEM; 242 243 /* Checking for available tcl descritors in another ring in 244 * case of failure due to full tcl ring now, is better than 245 * checking this ring earlier for each pkt tx. 246 * Restart ring selection if some rings are not checked yet. 247 */ 248 if (unlikely(ring_map != (BIT(ab->hw_params.max_tx_ring)) - 1) && 249 ab->hw_params.max_tx_ring > 1) { 250 tcl_ring_retry = true; 251 ring_selector++; 252 } 253 254 goto fail_unmap_dma; 255 } 256 257 ath11k_hal_tx_cmd_desc_setup(ab, hal_tcl_desc + 258 sizeof(struct hal_tlv_hdr), &ti); 259 260 ath11k_hal_srng_access_end(ab, tcl_ring); 261 262 ath11k_dp_shadow_start_timer(ab, tcl_ring, &dp->tx_ring_timer[ti.ring_id]); 263 264 spin_unlock_bh(&tcl_ring->lock); 265 266 ath11k_dbg_dump(ab, ATH11K_DBG_DP_TX, NULL, "dp tx msdu: ", 267 skb->data, skb->len); 268 269 atomic_inc(&ar->dp.num_tx_pending); 270 271 return 0; 272 273 fail_unmap_dma: 274 dma_unmap_single(ab->dev, ti.paddr, ti.data_len, DMA_TO_DEVICE); 275 276 fail_remove_idr: 277 spin_lock_bh(&tx_ring->tx_idr_lock); 278 idr_remove(&tx_ring->txbuf_idr, 279 FIELD_GET(DP_TX_DESC_ID_MSDU_ID, ti.desc_id)); 280 spin_unlock_bh(&tx_ring->tx_idr_lock); 281 282 if (tcl_ring_retry) 283 goto tcl_ring_sel; 284 285 return ret; 286 } 287 288 static void ath11k_dp_tx_free_txbuf(struct ath11k_base *ab, u8 mac_id, 289 int msdu_id, 290 struct dp_tx_ring *tx_ring) 291 { 292 struct ath11k *ar; 293 struct sk_buff *msdu; 294 struct ath11k_skb_cb *skb_cb; 295 296 spin_lock(&tx_ring->tx_idr_lock); 297 msdu = idr_remove(&tx_ring->txbuf_idr, msdu_id); 298 spin_unlock(&tx_ring->tx_idr_lock); 299 300 if (unlikely(!msdu)) { 301 ath11k_warn(ab, "tx completion for unknown msdu_id %d\n", 302 msdu_id); 303 return; 304 } 305 306 skb_cb = ATH11K_SKB_CB(msdu); 307 308 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 309 dev_kfree_skb_any(msdu); 310 311 ar = ab->pdevs[mac_id].ar; 312 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 313 wake_up(&ar->dp.tx_empty_waitq); 314 } 315 316 static void 317 ath11k_dp_tx_htt_tx_complete_buf(struct ath11k_base *ab, 318 struct dp_tx_ring *tx_ring, 319 struct ath11k_dp_htt_wbm_tx_status *ts) 320 { 321 struct sk_buff *msdu; 322 struct ieee80211_tx_info *info; 323 struct ath11k_skb_cb *skb_cb; 324 struct ath11k *ar; 325 326 spin_lock(&tx_ring->tx_idr_lock); 327 msdu = idr_remove(&tx_ring->txbuf_idr, ts->msdu_id); 328 spin_unlock(&tx_ring->tx_idr_lock); 329 330 if (unlikely(!msdu)) { 331 ath11k_warn(ab, "htt tx completion for unknown msdu_id %d\n", 332 ts->msdu_id); 333 return; 334 } 335 336 skb_cb = ATH11K_SKB_CB(msdu); 337 info = IEEE80211_SKB_CB(msdu); 338 339 ar = skb_cb->ar; 340 341 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 342 wake_up(&ar->dp.tx_empty_waitq); 343 344 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 345 346 memset(&info->status, 0, sizeof(info->status)); 347 348 if (ts->acked) { 349 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { 350 info->flags |= IEEE80211_TX_STAT_ACK; 351 info->status.ack_signal = ATH11K_DEFAULT_NOISE_FLOOR + 352 ts->ack_rssi; 353 info->status.is_valid_ack_signal = true; 354 } else { 355 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 356 } 357 } 358 359 ieee80211_tx_status(ar->hw, msdu); 360 } 361 362 static void 363 ath11k_dp_tx_process_htt_tx_complete(struct ath11k_base *ab, 364 void *desc, u8 mac_id, 365 u32 msdu_id, struct dp_tx_ring *tx_ring) 366 { 367 struct htt_tx_wbm_completion *status_desc; 368 struct ath11k_dp_htt_wbm_tx_status ts = {0}; 369 enum hal_wbm_htt_tx_comp_status wbm_status; 370 371 status_desc = desc + HTT_TX_WBM_COMP_STATUS_OFFSET; 372 373 wbm_status = FIELD_GET(HTT_TX_WBM_COMP_INFO0_STATUS, 374 status_desc->info0); 375 switch (wbm_status) { 376 case HAL_WBM_REL_HTT_TX_COMP_STATUS_OK: 377 case HAL_WBM_REL_HTT_TX_COMP_STATUS_DROP: 378 case HAL_WBM_REL_HTT_TX_COMP_STATUS_TTL: 379 ts.acked = (wbm_status == HAL_WBM_REL_HTT_TX_COMP_STATUS_OK); 380 ts.msdu_id = msdu_id; 381 ts.ack_rssi = FIELD_GET(HTT_TX_WBM_COMP_INFO1_ACK_RSSI, 382 status_desc->info1); 383 ath11k_dp_tx_htt_tx_complete_buf(ab, tx_ring, &ts); 384 break; 385 case HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ: 386 case HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT: 387 ath11k_dp_tx_free_txbuf(ab, mac_id, msdu_id, tx_ring); 388 break; 389 case HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY: 390 /* This event is to be handled only when the driver decides to 391 * use WDS offload functionality. 392 */ 393 break; 394 default: 395 ath11k_warn(ab, "Unknown htt tx status %d\n", wbm_status); 396 break; 397 } 398 } 399 400 static void ath11k_dp_tx_cache_peer_stats(struct ath11k *ar, 401 struct sk_buff *msdu, 402 struct hal_tx_status *ts) 403 { 404 struct ath11k_per_peer_tx_stats *peer_stats = &ar->cached_stats; 405 406 if (ts->try_cnt > 1) { 407 peer_stats->retry_pkts += ts->try_cnt - 1; 408 peer_stats->retry_bytes += (ts->try_cnt - 1) * msdu->len; 409 410 if (ts->status != HAL_WBM_TQM_REL_REASON_FRAME_ACKED) { 411 peer_stats->failed_pkts += 1; 412 peer_stats->failed_bytes += msdu->len; 413 } 414 } 415 } 416 417 static void ath11k_dp_tx_complete_msdu(struct ath11k *ar, 418 struct sk_buff *msdu, 419 struct hal_tx_status *ts) 420 { 421 struct ath11k_base *ab = ar->ab; 422 struct ieee80211_tx_info *info; 423 struct ath11k_skb_cb *skb_cb; 424 425 if (WARN_ON_ONCE(ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM)) { 426 /* Must not happen */ 427 return; 428 } 429 430 skb_cb = ATH11K_SKB_CB(msdu); 431 432 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 433 434 if (unlikely(!rcu_access_pointer(ab->pdevs_active[ar->pdev_idx]))) { 435 dev_kfree_skb_any(msdu); 436 return; 437 } 438 439 if (unlikely(!skb_cb->vif)) { 440 dev_kfree_skb_any(msdu); 441 return; 442 } 443 444 info = IEEE80211_SKB_CB(msdu); 445 memset(&info->status, 0, sizeof(info->status)); 446 447 /* skip tx rate update from ieee80211_status*/ 448 info->status.rates[0].idx = -1; 449 450 if (ts->status == HAL_WBM_TQM_REL_REASON_FRAME_ACKED && 451 !(info->flags & IEEE80211_TX_CTL_NO_ACK)) { 452 info->flags |= IEEE80211_TX_STAT_ACK; 453 info->status.ack_signal = ATH11K_DEFAULT_NOISE_FLOOR + 454 ts->ack_rssi; 455 info->status.is_valid_ack_signal = true; 456 } 457 458 if (ts->status == HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX && 459 (info->flags & IEEE80211_TX_CTL_NO_ACK)) 460 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 461 462 if (unlikely(ath11k_debugfs_is_extd_tx_stats_enabled(ar))) { 463 if (ts->flags & HAL_TX_STATUS_FLAGS_FIRST_MSDU) { 464 if (ar->last_ppdu_id == 0) { 465 ar->last_ppdu_id = ts->ppdu_id; 466 } else if (ar->last_ppdu_id == ts->ppdu_id || 467 ar->cached_ppdu_id == ar->last_ppdu_id) { 468 ar->cached_ppdu_id = ar->last_ppdu_id; 469 ar->cached_stats.is_ampdu = true; 470 ath11k_debugfs_sta_update_txcompl(ar, msdu, ts); 471 memset(&ar->cached_stats, 0, 472 sizeof(struct ath11k_per_peer_tx_stats)); 473 } else { 474 ar->cached_stats.is_ampdu = false; 475 ath11k_debugfs_sta_update_txcompl(ar, msdu, ts); 476 memset(&ar->cached_stats, 0, 477 sizeof(struct ath11k_per_peer_tx_stats)); 478 } 479 ar->last_ppdu_id = ts->ppdu_id; 480 } 481 482 ath11k_dp_tx_cache_peer_stats(ar, msdu, ts); 483 } 484 485 /* NOTE: Tx rate status reporting. Tx completion status does not have 486 * necessary information (for example nss) to build the tx rate. 487 * Might end up reporting it out-of-band from HTT stats. 488 */ 489 490 ieee80211_tx_status(ar->hw, msdu); 491 } 492 493 static inline void ath11k_dp_tx_status_parse(struct ath11k_base *ab, 494 struct hal_wbm_release_ring *desc, 495 struct hal_tx_status *ts) 496 { 497 ts->buf_rel_source = 498 FIELD_GET(HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE, desc->info0); 499 if (unlikely(ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_FW && 500 ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM)) 501 return; 502 503 if (unlikely(ts->buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW)) 504 return; 505 506 ts->status = FIELD_GET(HAL_WBM_RELEASE_INFO0_TQM_RELEASE_REASON, 507 desc->info0); 508 ts->ppdu_id = FIELD_GET(HAL_WBM_RELEASE_INFO1_TQM_STATUS_NUMBER, 509 desc->info1); 510 ts->try_cnt = FIELD_GET(HAL_WBM_RELEASE_INFO1_TRANSMIT_COUNT, 511 desc->info1); 512 ts->ack_rssi = FIELD_GET(HAL_WBM_RELEASE_INFO2_ACK_FRAME_RSSI, 513 desc->info2); 514 if (desc->info2 & HAL_WBM_RELEASE_INFO2_FIRST_MSDU) 515 ts->flags |= HAL_TX_STATUS_FLAGS_FIRST_MSDU; 516 ts->peer_id = FIELD_GET(HAL_WBM_RELEASE_INFO3_PEER_ID, desc->info3); 517 ts->tid = FIELD_GET(HAL_WBM_RELEASE_INFO3_TID, desc->info3); 518 if (desc->rate_stats.info0 & HAL_TX_RATE_STATS_INFO0_VALID) 519 ts->rate_stats = desc->rate_stats.info0; 520 else 521 ts->rate_stats = 0; 522 } 523 524 void ath11k_dp_tx_completion_handler(struct ath11k_base *ab, int ring_id) 525 { 526 struct ath11k *ar; 527 struct ath11k_dp *dp = &ab->dp; 528 int hal_ring_id = dp->tx_ring[ring_id].tcl_comp_ring.ring_id; 529 struct hal_srng *status_ring = &ab->hal.srng_list[hal_ring_id]; 530 struct sk_buff *msdu; 531 struct hal_tx_status ts = { 0 }; 532 struct dp_tx_ring *tx_ring = &dp->tx_ring[ring_id]; 533 u32 *desc; 534 u32 msdu_id; 535 u8 mac_id; 536 537 spin_lock_bh(&status_ring->lock); 538 539 ath11k_hal_srng_access_begin(ab, status_ring); 540 541 while ((ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head) != 542 tx_ring->tx_status_tail) && 543 (desc = ath11k_hal_srng_dst_get_next_entry(ab, status_ring))) { 544 memcpy(&tx_ring->tx_status[tx_ring->tx_status_head], 545 desc, sizeof(struct hal_wbm_release_ring)); 546 tx_ring->tx_status_head = 547 ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head); 548 } 549 550 if (unlikely((ath11k_hal_srng_dst_peek(ab, status_ring) != NULL) && 551 (ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head) == 552 tx_ring->tx_status_tail))) { 553 /* TODO: Process pending tx_status messages when kfifo_is_full() */ 554 ath11k_warn(ab, "Unable to process some of the tx_status ring desc because status_fifo is full\n"); 555 } 556 557 ath11k_hal_srng_access_end(ab, status_ring); 558 559 spin_unlock_bh(&status_ring->lock); 560 561 while (ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_tail) != tx_ring->tx_status_head) { 562 struct hal_wbm_release_ring *tx_status; 563 u32 desc_id; 564 565 tx_ring->tx_status_tail = 566 ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_tail); 567 tx_status = &tx_ring->tx_status[tx_ring->tx_status_tail]; 568 ath11k_dp_tx_status_parse(ab, tx_status, &ts); 569 570 desc_id = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, 571 tx_status->buf_addr_info.info1); 572 mac_id = FIELD_GET(DP_TX_DESC_ID_MAC_ID, desc_id); 573 msdu_id = FIELD_GET(DP_TX_DESC_ID_MSDU_ID, desc_id); 574 575 if (unlikely(ts.buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW)) { 576 ath11k_dp_tx_process_htt_tx_complete(ab, 577 (void *)tx_status, 578 mac_id, msdu_id, 579 tx_ring); 580 continue; 581 } 582 583 spin_lock(&tx_ring->tx_idr_lock); 584 msdu = idr_remove(&tx_ring->txbuf_idr, msdu_id); 585 if (unlikely(!msdu)) { 586 ath11k_warn(ab, "tx completion for unknown msdu_id %d\n", 587 msdu_id); 588 spin_unlock(&tx_ring->tx_idr_lock); 589 continue; 590 } 591 592 spin_unlock(&tx_ring->tx_idr_lock); 593 594 ar = ab->pdevs[mac_id].ar; 595 596 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 597 wake_up(&ar->dp.tx_empty_waitq); 598 599 ath11k_dp_tx_complete_msdu(ar, msdu, &ts); 600 } 601 } 602 603 int ath11k_dp_tx_send_reo_cmd(struct ath11k_base *ab, struct dp_rx_tid *rx_tid, 604 enum hal_reo_cmd_type type, 605 struct ath11k_hal_reo_cmd *cmd, 606 void (*cb)(struct ath11k_dp *, void *, 607 enum hal_reo_cmd_status)) 608 { 609 struct ath11k_dp *dp = &ab->dp; 610 struct dp_reo_cmd *dp_cmd; 611 struct hal_srng *cmd_ring; 612 int cmd_num; 613 614 if (test_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags)) 615 return -ESHUTDOWN; 616 617 cmd_ring = &ab->hal.srng_list[dp->reo_cmd_ring.ring_id]; 618 cmd_num = ath11k_hal_reo_cmd_send(ab, cmd_ring, type, cmd); 619 620 /* cmd_num should start from 1, during failure return the error code */ 621 if (cmd_num < 0) 622 return cmd_num; 623 624 /* reo cmd ring descriptors has cmd_num starting from 1 */ 625 if (cmd_num == 0) 626 return -EINVAL; 627 628 if (!cb) 629 return 0; 630 631 /* Can this be optimized so that we keep the pending command list only 632 * for tid delete command to free up the resoruce on the command status 633 * indication? 634 */ 635 dp_cmd = kzalloc(sizeof(*dp_cmd), GFP_ATOMIC); 636 637 if (!dp_cmd) 638 return -ENOMEM; 639 640 memcpy(&dp_cmd->data, rx_tid, sizeof(struct dp_rx_tid)); 641 dp_cmd->cmd_num = cmd_num; 642 dp_cmd->handler = cb; 643 644 spin_lock_bh(&dp->reo_cmd_lock); 645 list_add_tail(&dp_cmd->list, &dp->reo_cmd_list); 646 spin_unlock_bh(&dp->reo_cmd_lock); 647 648 return 0; 649 } 650 651 static int 652 ath11k_dp_tx_get_ring_id_type(struct ath11k_base *ab, 653 int mac_id, u32 ring_id, 654 enum hal_ring_type ring_type, 655 enum htt_srng_ring_type *htt_ring_type, 656 enum htt_srng_ring_id *htt_ring_id) 657 { 658 int lmac_ring_id_offset = 0; 659 int ret = 0; 660 661 switch (ring_type) { 662 case HAL_RXDMA_BUF: 663 lmac_ring_id_offset = mac_id * HAL_SRNG_RINGS_PER_LMAC; 664 665 /* for QCA6390, host fills rx buffer to fw and fw fills to 666 * rxbuf ring for each rxdma 667 */ 668 if (!ab->hw_params.rx_mac_buf_ring) { 669 if (!(ring_id == (HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_BUF + 670 lmac_ring_id_offset) || 671 ring_id == (HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_BUF + 672 lmac_ring_id_offset))) { 673 ret = -EINVAL; 674 } 675 *htt_ring_id = HTT_RXDMA_HOST_BUF_RING; 676 *htt_ring_type = HTT_SW_TO_HW_RING; 677 } else { 678 if (ring_id == HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_BUF) { 679 *htt_ring_id = HTT_HOST1_TO_FW_RXBUF_RING; 680 *htt_ring_type = HTT_SW_TO_SW_RING; 681 } else { 682 *htt_ring_id = HTT_RXDMA_HOST_BUF_RING; 683 *htt_ring_type = HTT_SW_TO_HW_RING; 684 } 685 } 686 break; 687 case HAL_RXDMA_DST: 688 *htt_ring_id = HTT_RXDMA_NON_MONITOR_DEST_RING; 689 *htt_ring_type = HTT_HW_TO_SW_RING; 690 break; 691 case HAL_RXDMA_MONITOR_BUF: 692 *htt_ring_id = HTT_RXDMA_MONITOR_BUF_RING; 693 *htt_ring_type = HTT_SW_TO_HW_RING; 694 break; 695 case HAL_RXDMA_MONITOR_STATUS: 696 *htt_ring_id = HTT_RXDMA_MONITOR_STATUS_RING; 697 *htt_ring_type = HTT_SW_TO_HW_RING; 698 break; 699 case HAL_RXDMA_MONITOR_DST: 700 *htt_ring_id = HTT_RXDMA_MONITOR_DEST_RING; 701 *htt_ring_type = HTT_HW_TO_SW_RING; 702 break; 703 case HAL_RXDMA_MONITOR_DESC: 704 *htt_ring_id = HTT_RXDMA_MONITOR_DESC_RING; 705 *htt_ring_type = HTT_SW_TO_HW_RING; 706 break; 707 default: 708 ath11k_warn(ab, "Unsupported ring type in DP :%d\n", ring_type); 709 ret = -EINVAL; 710 } 711 return ret; 712 } 713 714 int ath11k_dp_tx_htt_srng_setup(struct ath11k_base *ab, u32 ring_id, 715 int mac_id, enum hal_ring_type ring_type) 716 { 717 struct htt_srng_setup_cmd *cmd; 718 struct hal_srng *srng = &ab->hal.srng_list[ring_id]; 719 struct hal_srng_params params; 720 struct sk_buff *skb; 721 u32 ring_entry_sz; 722 int len = sizeof(*cmd); 723 dma_addr_t hp_addr, tp_addr; 724 enum htt_srng_ring_type htt_ring_type; 725 enum htt_srng_ring_id htt_ring_id; 726 int ret; 727 728 skb = ath11k_htc_alloc_skb(ab, len); 729 if (!skb) 730 return -ENOMEM; 731 732 memset(¶ms, 0, sizeof(params)); 733 ath11k_hal_srng_get_params(ab, srng, ¶ms); 734 735 hp_addr = ath11k_hal_srng_get_hp_addr(ab, srng); 736 tp_addr = ath11k_hal_srng_get_tp_addr(ab, srng); 737 738 ret = ath11k_dp_tx_get_ring_id_type(ab, mac_id, ring_id, 739 ring_type, &htt_ring_type, 740 &htt_ring_id); 741 if (ret) 742 goto err_free; 743 744 skb_put(skb, len); 745 cmd = (struct htt_srng_setup_cmd *)skb->data; 746 cmd->info0 = FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE, 747 HTT_H2T_MSG_TYPE_SRING_SETUP); 748 if (htt_ring_type == HTT_SW_TO_HW_RING || 749 htt_ring_type == HTT_HW_TO_SW_RING) 750 cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID, 751 DP_SW2HW_MACID(mac_id)); 752 else 753 cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID, 754 mac_id); 755 cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE, 756 htt_ring_type); 757 cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_RING_ID, htt_ring_id); 758 759 cmd->ring_base_addr_lo = params.ring_base_paddr & 760 HAL_ADDR_LSB_REG_MASK; 761 762 cmd->ring_base_addr_hi = (u64)params.ring_base_paddr >> 763 HAL_ADDR_MSB_REG_SHIFT; 764 765 ret = ath11k_hal_srng_get_entrysize(ab, ring_type); 766 if (ret < 0) 767 goto err_free; 768 769 ring_entry_sz = ret; 770 771 ring_entry_sz >>= 2; 772 cmd->info1 = FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE, 773 ring_entry_sz); 774 cmd->info1 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE, 775 params.num_entries * ring_entry_sz); 776 cmd->info1 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP, 777 !!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP)); 778 cmd->info1 |= FIELD_PREP( 779 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP, 780 !!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP)); 781 cmd->info1 |= FIELD_PREP( 782 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP, 783 !!(params.flags & HAL_SRNG_FLAGS_RING_PTR_SWAP)); 784 if (htt_ring_type == HTT_SW_TO_HW_RING) 785 cmd->info1 |= HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS; 786 787 cmd->ring_head_off32_remote_addr_lo = hp_addr & HAL_ADDR_LSB_REG_MASK; 788 cmd->ring_head_off32_remote_addr_hi = (u64)hp_addr >> 789 HAL_ADDR_MSB_REG_SHIFT; 790 791 cmd->ring_tail_off32_remote_addr_lo = tp_addr & HAL_ADDR_LSB_REG_MASK; 792 cmd->ring_tail_off32_remote_addr_hi = (u64)tp_addr >> 793 HAL_ADDR_MSB_REG_SHIFT; 794 795 cmd->ring_msi_addr_lo = lower_32_bits(params.msi_addr); 796 cmd->ring_msi_addr_hi = upper_32_bits(params.msi_addr); 797 cmd->msi_data = params.msi_data; 798 799 cmd->intr_info = FIELD_PREP( 800 HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH, 801 params.intr_batch_cntr_thres_entries * ring_entry_sz); 802 cmd->intr_info |= FIELD_PREP( 803 HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH, 804 params.intr_timer_thres_us >> 3); 805 806 cmd->info2 = 0; 807 if (params.flags & HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN) { 808 cmd->info2 = FIELD_PREP( 809 HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH, 810 params.low_threshold); 811 } 812 813 ath11k_dbg(ab, ATH11k_DBG_HAL, 814 "%s msi_addr_lo:0x%x, msi_addr_hi:0x%x, msi_data:0x%x\n", 815 __func__, cmd->ring_msi_addr_lo, cmd->ring_msi_addr_hi, 816 cmd->msi_data); 817 818 ath11k_dbg(ab, ATH11k_DBG_HAL, 819 "ring_id:%d, ring_type:%d, intr_info:0x%x, flags:0x%x\n", 820 ring_id, ring_type, cmd->intr_info, cmd->info2); 821 822 ret = ath11k_htc_send(&ab->htc, ab->dp.eid, skb); 823 if (ret) 824 goto err_free; 825 826 return 0; 827 828 err_free: 829 dev_kfree_skb_any(skb); 830 831 return ret; 832 } 833 834 #define HTT_TARGET_VERSION_TIMEOUT_HZ (3 * HZ) 835 836 int ath11k_dp_tx_htt_h2t_ver_req_msg(struct ath11k_base *ab) 837 { 838 struct ath11k_dp *dp = &ab->dp; 839 struct sk_buff *skb; 840 struct htt_ver_req_cmd *cmd; 841 int len = sizeof(*cmd); 842 int ret; 843 844 init_completion(&dp->htt_tgt_version_received); 845 846 skb = ath11k_htc_alloc_skb(ab, len); 847 if (!skb) 848 return -ENOMEM; 849 850 skb_put(skb, len); 851 cmd = (struct htt_ver_req_cmd *)skb->data; 852 cmd->ver_reg_info = FIELD_PREP(HTT_VER_REQ_INFO_MSG_ID, 853 HTT_H2T_MSG_TYPE_VERSION_REQ); 854 855 ret = ath11k_htc_send(&ab->htc, dp->eid, skb); 856 if (ret) { 857 dev_kfree_skb_any(skb); 858 return ret; 859 } 860 861 ret = wait_for_completion_timeout(&dp->htt_tgt_version_received, 862 HTT_TARGET_VERSION_TIMEOUT_HZ); 863 if (ret == 0) { 864 ath11k_warn(ab, "htt target version request timed out\n"); 865 return -ETIMEDOUT; 866 } 867 868 if (dp->htt_tgt_ver_major != HTT_TARGET_VERSION_MAJOR) { 869 ath11k_err(ab, "unsupported htt major version %d supported version is %d\n", 870 dp->htt_tgt_ver_major, HTT_TARGET_VERSION_MAJOR); 871 return -ENOTSUPP; 872 } 873 874 return 0; 875 } 876 877 int ath11k_dp_tx_htt_h2t_ppdu_stats_req(struct ath11k *ar, u32 mask) 878 { 879 struct ath11k_base *ab = ar->ab; 880 struct ath11k_dp *dp = &ab->dp; 881 struct sk_buff *skb; 882 struct htt_ppdu_stats_cfg_cmd *cmd; 883 int len = sizeof(*cmd); 884 u8 pdev_mask; 885 int ret; 886 int i; 887 888 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 889 skb = ath11k_htc_alloc_skb(ab, len); 890 if (!skb) 891 return -ENOMEM; 892 893 skb_put(skb, len); 894 cmd = (struct htt_ppdu_stats_cfg_cmd *)skb->data; 895 cmd->msg = FIELD_PREP(HTT_PPDU_STATS_CFG_MSG_TYPE, 896 HTT_H2T_MSG_TYPE_PPDU_STATS_CFG); 897 898 pdev_mask = 1 << (ar->pdev_idx + i); 899 cmd->msg |= FIELD_PREP(HTT_PPDU_STATS_CFG_PDEV_ID, pdev_mask); 900 cmd->msg |= FIELD_PREP(HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK, mask); 901 902 ret = ath11k_htc_send(&ab->htc, dp->eid, skb); 903 if (ret) { 904 dev_kfree_skb_any(skb); 905 return ret; 906 } 907 } 908 909 return 0; 910 } 911 912 int ath11k_dp_tx_htt_rx_filter_setup(struct ath11k_base *ab, u32 ring_id, 913 int mac_id, enum hal_ring_type ring_type, 914 int rx_buf_size, 915 struct htt_rx_ring_tlv_filter *tlv_filter) 916 { 917 struct htt_rx_ring_selection_cfg_cmd *cmd; 918 struct hal_srng *srng = &ab->hal.srng_list[ring_id]; 919 struct hal_srng_params params; 920 struct sk_buff *skb; 921 int len = sizeof(*cmd); 922 enum htt_srng_ring_type htt_ring_type; 923 enum htt_srng_ring_id htt_ring_id; 924 int ret; 925 926 skb = ath11k_htc_alloc_skb(ab, len); 927 if (!skb) 928 return -ENOMEM; 929 930 memset(¶ms, 0, sizeof(params)); 931 ath11k_hal_srng_get_params(ab, srng, ¶ms); 932 933 ret = ath11k_dp_tx_get_ring_id_type(ab, mac_id, ring_id, 934 ring_type, &htt_ring_type, 935 &htt_ring_id); 936 if (ret) 937 goto err_free; 938 939 skb_put(skb, len); 940 cmd = (struct htt_rx_ring_selection_cfg_cmd *)skb->data; 941 cmd->info0 = FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE, 942 HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG); 943 if (htt_ring_type == HTT_SW_TO_HW_RING || 944 htt_ring_type == HTT_HW_TO_SW_RING) 945 cmd->info0 |= 946 FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID, 947 DP_SW2HW_MACID(mac_id)); 948 else 949 cmd->info0 |= 950 FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID, 951 mac_id); 952 cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID, 953 htt_ring_id); 954 cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS, 955 !!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP)); 956 cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS, 957 !!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP)); 958 959 cmd->info1 = FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE, 960 rx_buf_size); 961 cmd->pkt_type_en_flags0 = tlv_filter->pkt_filter_flags0; 962 cmd->pkt_type_en_flags1 = tlv_filter->pkt_filter_flags1; 963 cmd->pkt_type_en_flags2 = tlv_filter->pkt_filter_flags2; 964 cmd->pkt_type_en_flags3 = tlv_filter->pkt_filter_flags3; 965 cmd->rx_filter_tlv = tlv_filter->rx_filter; 966 967 ret = ath11k_htc_send(&ab->htc, ab->dp.eid, skb); 968 if (ret) 969 goto err_free; 970 971 return 0; 972 973 err_free: 974 dev_kfree_skb_any(skb); 975 976 return ret; 977 } 978 979 int 980 ath11k_dp_tx_htt_h2t_ext_stats_req(struct ath11k *ar, u8 type, 981 struct htt_ext_stats_cfg_params *cfg_params, 982 u64 cookie) 983 { 984 struct ath11k_base *ab = ar->ab; 985 struct ath11k_dp *dp = &ab->dp; 986 struct sk_buff *skb; 987 struct htt_ext_stats_cfg_cmd *cmd; 988 int len = sizeof(*cmd); 989 int ret; 990 991 skb = ath11k_htc_alloc_skb(ab, len); 992 if (!skb) 993 return -ENOMEM; 994 995 skb_put(skb, len); 996 997 cmd = (struct htt_ext_stats_cfg_cmd *)skb->data; 998 memset(cmd, 0, sizeof(*cmd)); 999 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_EXT_STATS_CFG; 1000 1001 cmd->hdr.pdev_mask = 1 << ar->pdev->pdev_id; 1002 1003 cmd->hdr.stats_type = type; 1004 cmd->cfg_param0 = cfg_params->cfg0; 1005 cmd->cfg_param1 = cfg_params->cfg1; 1006 cmd->cfg_param2 = cfg_params->cfg2; 1007 cmd->cfg_param3 = cfg_params->cfg3; 1008 cmd->cookie_lsb = lower_32_bits(cookie); 1009 cmd->cookie_msb = upper_32_bits(cookie); 1010 1011 ret = ath11k_htc_send(&ab->htc, dp->eid, skb); 1012 if (ret) { 1013 ath11k_warn(ab, "failed to send htt type stats request: %d", 1014 ret); 1015 dev_kfree_skb_any(skb); 1016 return ret; 1017 } 1018 1019 return 0; 1020 } 1021 1022 int ath11k_dp_tx_htt_monitor_mode_ring_config(struct ath11k *ar, bool reset) 1023 { 1024 struct ath11k_pdev_dp *dp = &ar->dp; 1025 struct ath11k_base *ab = ar->ab; 1026 struct htt_rx_ring_tlv_filter tlv_filter = {0}; 1027 int ret = 0, ring_id = 0, i; 1028 1029 ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id; 1030 1031 if (!reset) { 1032 tlv_filter.rx_filter = HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING; 1033 tlv_filter.pkt_filter_flags0 = 1034 HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 | 1035 HTT_RX_MON_MO_MGMT_FILTER_FLAGS0; 1036 tlv_filter.pkt_filter_flags1 = 1037 HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 | 1038 HTT_RX_MON_MO_MGMT_FILTER_FLAGS1; 1039 tlv_filter.pkt_filter_flags2 = 1040 HTT_RX_MON_FP_CTRL_FILTER_FLASG2 | 1041 HTT_RX_MON_MO_CTRL_FILTER_FLASG2; 1042 tlv_filter.pkt_filter_flags3 = 1043 HTT_RX_MON_FP_CTRL_FILTER_FLASG3 | 1044 HTT_RX_MON_MO_CTRL_FILTER_FLASG3 | 1045 HTT_RX_MON_FP_DATA_FILTER_FLASG3 | 1046 HTT_RX_MON_MO_DATA_FILTER_FLASG3; 1047 } 1048 1049 if (ab->hw_params.rxdma1_enable) { 1050 ret = ath11k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id, dp->mac_id, 1051 HAL_RXDMA_MONITOR_BUF, 1052 DP_RXDMA_REFILL_RING_SIZE, 1053 &tlv_filter); 1054 } else if (!reset) { 1055 /* set in monitor mode only */ 1056 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 1057 ring_id = dp->rx_mac_buf_ring[i].ring_id; 1058 ret = ath11k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id, 1059 dp->mac_id + i, 1060 HAL_RXDMA_BUF, 1061 1024, 1062 &tlv_filter); 1063 } 1064 } 1065 1066 if (ret) 1067 return ret; 1068 1069 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 1070 ring_id = dp->rx_mon_status_refill_ring[i].refill_buf_ring.ring_id; 1071 if (!reset) { 1072 tlv_filter.rx_filter = 1073 HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING; 1074 } else { 1075 tlv_filter = ath11k_mac_mon_status_filter_default; 1076 1077 if (ath11k_debugfs_is_extd_rx_stats_enabled(ar)) 1078 tlv_filter.rx_filter = ath11k_debugfs_rx_filter(ar); 1079 } 1080 1081 ret = ath11k_dp_tx_htt_rx_filter_setup(ab, ring_id, 1082 dp->mac_id + i, 1083 HAL_RXDMA_MONITOR_STATUS, 1084 DP_RXDMA_REFILL_RING_SIZE, 1085 &tlv_filter); 1086 } 1087 1088 if (!ar->ab->hw_params.rxdma1_enable) 1089 mod_timer(&ar->ab->mon_reap_timer, jiffies + 1090 msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL)); 1091 1092 return ret; 1093 } 1094