1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/ieee80211.h> 7 #include <linux/kernel.h> 8 #include <linux/skbuff.h> 9 #include <crypto/hash.h> 10 #include "core.h" 11 #include "debug.h" 12 #include "debugfs_htt_stats.h" 13 #include "debugfs_sta.h" 14 #include "hal_desc.h" 15 #include "hw.h" 16 #include "dp_rx.h" 17 #include "hal_rx.h" 18 #include "dp_tx.h" 19 #include "peer.h" 20 21 #define ATH11K_DP_RX_FRAGMENT_TIMEOUT_MS (2 * HZ) 22 23 static inline 24 u8 *ath11k_dp_rx_h_80211_hdr(struct ath11k_base *ab, struct hal_rx_desc *desc) 25 { 26 return ab->hw_params.hw_ops->rx_desc_get_hdr_status(desc); 27 } 28 29 static inline 30 enum hal_encrypt_type ath11k_dp_rx_h_mpdu_start_enctype(struct ath11k_base *ab, 31 struct hal_rx_desc *desc) 32 { 33 if (!ab->hw_params.hw_ops->rx_desc_encrypt_valid(desc)) 34 return HAL_ENCRYPT_TYPE_OPEN; 35 36 return ab->hw_params.hw_ops->rx_desc_get_encrypt_type(desc); 37 } 38 39 static inline u8 ath11k_dp_rx_h_msdu_start_decap_type(struct ath11k_base *ab, 40 struct hal_rx_desc *desc) 41 { 42 return ab->hw_params.hw_ops->rx_desc_get_decap_type(desc); 43 } 44 45 static inline 46 bool ath11k_dp_rx_h_msdu_start_ldpc_support(struct ath11k_base *ab, 47 struct hal_rx_desc *desc) 48 { 49 return ab->hw_params.hw_ops->rx_desc_get_ldpc_support(desc); 50 } 51 52 static inline 53 u8 ath11k_dp_rx_h_msdu_start_mesh_ctl_present(struct ath11k_base *ab, 54 struct hal_rx_desc *desc) 55 { 56 return ab->hw_params.hw_ops->rx_desc_get_mesh_ctl(desc); 57 } 58 59 static inline 60 bool ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(struct ath11k_base *ab, 61 struct hal_rx_desc *desc) 62 { 63 return ab->hw_params.hw_ops->rx_desc_get_mpdu_seq_ctl_vld(desc); 64 } 65 66 static inline bool ath11k_dp_rx_h_mpdu_start_fc_valid(struct ath11k_base *ab, 67 struct hal_rx_desc *desc) 68 { 69 return ab->hw_params.hw_ops->rx_desc_get_mpdu_fc_valid(desc); 70 } 71 72 static inline bool ath11k_dp_rx_h_mpdu_start_more_frags(struct ath11k_base *ab, 73 struct sk_buff *skb) 74 { 75 struct ieee80211_hdr *hdr; 76 77 hdr = (struct ieee80211_hdr *)(skb->data + ab->hw_params.hal_desc_sz); 78 return ieee80211_has_morefrags(hdr->frame_control); 79 } 80 81 static inline u16 ath11k_dp_rx_h_mpdu_start_frag_no(struct ath11k_base *ab, 82 struct sk_buff *skb) 83 { 84 struct ieee80211_hdr *hdr; 85 86 hdr = (struct ieee80211_hdr *)(skb->data + ab->hw_params.hal_desc_sz); 87 return le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG; 88 } 89 90 static inline u16 ath11k_dp_rx_h_mpdu_start_seq_no(struct ath11k_base *ab, 91 struct hal_rx_desc *desc) 92 { 93 return ab->hw_params.hw_ops->rx_desc_get_mpdu_start_seq_no(desc); 94 } 95 96 static inline void *ath11k_dp_rx_get_attention(struct ath11k_base *ab, 97 struct hal_rx_desc *desc) 98 { 99 return ab->hw_params.hw_ops->rx_desc_get_attention(desc); 100 } 101 102 static inline bool ath11k_dp_rx_h_attn_msdu_done(struct rx_attention *attn) 103 { 104 return !!FIELD_GET(RX_ATTENTION_INFO2_MSDU_DONE, 105 __le32_to_cpu(attn->info2)); 106 } 107 108 static inline bool ath11k_dp_rx_h_attn_l4_cksum_fail(struct rx_attention *attn) 109 { 110 return !!FIELD_GET(RX_ATTENTION_INFO1_TCP_UDP_CKSUM_FAIL, 111 __le32_to_cpu(attn->info1)); 112 } 113 114 static inline bool ath11k_dp_rx_h_attn_ip_cksum_fail(struct rx_attention *attn) 115 { 116 return !!FIELD_GET(RX_ATTENTION_INFO1_IP_CKSUM_FAIL, 117 __le32_to_cpu(attn->info1)); 118 } 119 120 static inline bool ath11k_dp_rx_h_attn_is_decrypted(struct rx_attention *attn) 121 { 122 return (FIELD_GET(RX_ATTENTION_INFO2_DCRYPT_STATUS_CODE, 123 __le32_to_cpu(attn->info2)) == 124 RX_DESC_DECRYPT_STATUS_CODE_OK); 125 } 126 127 static u32 ath11k_dp_rx_h_attn_mpdu_err(struct rx_attention *attn) 128 { 129 u32 info = __le32_to_cpu(attn->info1); 130 u32 errmap = 0; 131 132 if (info & RX_ATTENTION_INFO1_FCS_ERR) 133 errmap |= DP_RX_MPDU_ERR_FCS; 134 135 if (info & RX_ATTENTION_INFO1_DECRYPT_ERR) 136 errmap |= DP_RX_MPDU_ERR_DECRYPT; 137 138 if (info & RX_ATTENTION_INFO1_TKIP_MIC_ERR) 139 errmap |= DP_RX_MPDU_ERR_TKIP_MIC; 140 141 if (info & RX_ATTENTION_INFO1_A_MSDU_ERROR) 142 errmap |= DP_RX_MPDU_ERR_AMSDU_ERR; 143 144 if (info & RX_ATTENTION_INFO1_OVERFLOW_ERR) 145 errmap |= DP_RX_MPDU_ERR_OVERFLOW; 146 147 if (info & RX_ATTENTION_INFO1_MSDU_LEN_ERR) 148 errmap |= DP_RX_MPDU_ERR_MSDU_LEN; 149 150 if (info & RX_ATTENTION_INFO1_MPDU_LEN_ERR) 151 errmap |= DP_RX_MPDU_ERR_MPDU_LEN; 152 153 return errmap; 154 } 155 156 static bool ath11k_dp_rx_h_attn_msdu_len_err(struct ath11k_base *ab, 157 struct hal_rx_desc *desc) 158 { 159 struct rx_attention *rx_attention; 160 u32 errmap; 161 162 rx_attention = ath11k_dp_rx_get_attention(ab, desc); 163 errmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention); 164 165 return errmap & DP_RX_MPDU_ERR_MSDU_LEN; 166 } 167 168 static inline u16 ath11k_dp_rx_h_msdu_start_msdu_len(struct ath11k_base *ab, 169 struct hal_rx_desc *desc) 170 { 171 return ab->hw_params.hw_ops->rx_desc_get_msdu_len(desc); 172 } 173 174 static inline u8 ath11k_dp_rx_h_msdu_start_sgi(struct ath11k_base *ab, 175 struct hal_rx_desc *desc) 176 { 177 return ab->hw_params.hw_ops->rx_desc_get_msdu_sgi(desc); 178 } 179 180 static inline u8 ath11k_dp_rx_h_msdu_start_rate_mcs(struct ath11k_base *ab, 181 struct hal_rx_desc *desc) 182 { 183 return ab->hw_params.hw_ops->rx_desc_get_msdu_rate_mcs(desc); 184 } 185 186 static inline u8 ath11k_dp_rx_h_msdu_start_rx_bw(struct ath11k_base *ab, 187 struct hal_rx_desc *desc) 188 { 189 return ab->hw_params.hw_ops->rx_desc_get_msdu_rx_bw(desc); 190 } 191 192 static inline u32 ath11k_dp_rx_h_msdu_start_freq(struct ath11k_base *ab, 193 struct hal_rx_desc *desc) 194 { 195 return ab->hw_params.hw_ops->rx_desc_get_msdu_freq(desc); 196 } 197 198 static inline u8 ath11k_dp_rx_h_msdu_start_pkt_type(struct ath11k_base *ab, 199 struct hal_rx_desc *desc) 200 { 201 return ab->hw_params.hw_ops->rx_desc_get_msdu_pkt_type(desc); 202 } 203 204 static inline u8 ath11k_dp_rx_h_msdu_start_nss(struct ath11k_base *ab, 205 struct hal_rx_desc *desc) 206 { 207 return hweight8(ab->hw_params.hw_ops->rx_desc_get_msdu_nss(desc)); 208 } 209 210 static inline u8 ath11k_dp_rx_h_mpdu_start_tid(struct ath11k_base *ab, 211 struct hal_rx_desc *desc) 212 { 213 return ab->hw_params.hw_ops->rx_desc_get_mpdu_tid(desc); 214 } 215 216 static inline u16 ath11k_dp_rx_h_mpdu_start_peer_id(struct ath11k_base *ab, 217 struct hal_rx_desc *desc) 218 { 219 return ab->hw_params.hw_ops->rx_desc_get_mpdu_peer_id(desc); 220 } 221 222 static inline u8 ath11k_dp_rx_h_msdu_end_l3pad(struct ath11k_base *ab, 223 struct hal_rx_desc *desc) 224 { 225 return ab->hw_params.hw_ops->rx_desc_get_l3_pad_bytes(desc); 226 } 227 228 static inline bool ath11k_dp_rx_h_msdu_end_first_msdu(struct ath11k_base *ab, 229 struct hal_rx_desc *desc) 230 { 231 return ab->hw_params.hw_ops->rx_desc_get_first_msdu(desc); 232 } 233 234 static bool ath11k_dp_rx_h_msdu_end_last_msdu(struct ath11k_base *ab, 235 struct hal_rx_desc *desc) 236 { 237 return ab->hw_params.hw_ops->rx_desc_get_last_msdu(desc); 238 } 239 240 static void ath11k_dp_rx_desc_end_tlv_copy(struct ath11k_base *ab, 241 struct hal_rx_desc *fdesc, 242 struct hal_rx_desc *ldesc) 243 { 244 ab->hw_params.hw_ops->rx_desc_copy_attn_end_tlv(fdesc, ldesc); 245 } 246 247 static inline u32 ath11k_dp_rxdesc_get_mpdulen_err(struct rx_attention *attn) 248 { 249 return FIELD_GET(RX_ATTENTION_INFO1_MPDU_LEN_ERR, 250 __le32_to_cpu(attn->info1)); 251 } 252 253 static inline u8 *ath11k_dp_rxdesc_get_80211hdr(struct ath11k_base *ab, 254 struct hal_rx_desc *rx_desc) 255 { 256 u8 *rx_pkt_hdr; 257 258 rx_pkt_hdr = ab->hw_params.hw_ops->rx_desc_get_msdu_payload(rx_desc); 259 260 return rx_pkt_hdr; 261 } 262 263 static inline bool ath11k_dp_rxdesc_mpdu_valid(struct ath11k_base *ab, 264 struct hal_rx_desc *rx_desc) 265 { 266 u32 tlv_tag; 267 268 tlv_tag = ab->hw_params.hw_ops->rx_desc_get_mpdu_start_tag(rx_desc); 269 270 return tlv_tag == HAL_RX_MPDU_START; 271 } 272 273 static inline u32 ath11k_dp_rxdesc_get_ppduid(struct ath11k_base *ab, 274 struct hal_rx_desc *rx_desc) 275 { 276 return ab->hw_params.hw_ops->rx_desc_get_mpdu_ppdu_id(rx_desc); 277 } 278 279 static inline void ath11k_dp_rxdesc_set_msdu_len(struct ath11k_base *ab, 280 struct hal_rx_desc *desc, 281 u16 len) 282 { 283 ab->hw_params.hw_ops->rx_desc_set_msdu_len(desc, len); 284 } 285 286 static bool ath11k_dp_rx_h_attn_is_mcbc(struct ath11k_base *ab, 287 struct hal_rx_desc *desc) 288 { 289 struct rx_attention *attn = ath11k_dp_rx_get_attention(ab, desc); 290 291 return ath11k_dp_rx_h_msdu_end_first_msdu(ab, desc) && 292 (!!FIELD_GET(RX_ATTENTION_INFO1_MCAST_BCAST, 293 __le32_to_cpu(attn->info1))); 294 } 295 296 static bool ath11k_dp_rxdesc_mac_addr2_valid(struct ath11k_base *ab, 297 struct hal_rx_desc *desc) 298 { 299 return ab->hw_params.hw_ops->rx_desc_mac_addr2_valid(desc); 300 } 301 302 static u8 *ath11k_dp_rxdesc_mpdu_start_addr2(struct ath11k_base *ab, 303 struct hal_rx_desc *desc) 304 { 305 return ab->hw_params.hw_ops->rx_desc_mpdu_start_addr2(desc); 306 } 307 308 static void ath11k_dp_service_mon_ring(struct timer_list *t) 309 { 310 struct ath11k_base *ab = from_timer(ab, t, mon_reap_timer); 311 int i; 312 313 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) 314 ath11k_dp_rx_process_mon_rings(ab, i, NULL, DP_MON_SERVICE_BUDGET); 315 316 mod_timer(&ab->mon_reap_timer, jiffies + 317 msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL)); 318 } 319 320 static int ath11k_dp_purge_mon_ring(struct ath11k_base *ab) 321 { 322 int i, reaped = 0; 323 unsigned long timeout = jiffies + msecs_to_jiffies(DP_MON_PURGE_TIMEOUT_MS); 324 325 do { 326 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) 327 reaped += ath11k_dp_rx_process_mon_rings(ab, i, 328 NULL, 329 DP_MON_SERVICE_BUDGET); 330 331 /* nothing more to reap */ 332 if (reaped < DP_MON_SERVICE_BUDGET) 333 return 0; 334 335 } while (time_before(jiffies, timeout)); 336 337 ath11k_warn(ab, "dp mon ring purge timeout"); 338 339 return -ETIMEDOUT; 340 } 341 342 /* Returns number of Rx buffers replenished */ 343 int ath11k_dp_rxbufs_replenish(struct ath11k_base *ab, int mac_id, 344 struct dp_rxdma_ring *rx_ring, 345 int req_entries, 346 enum hal_rx_buf_return_buf_manager mgr) 347 { 348 struct hal_srng *srng; 349 u32 *desc; 350 struct sk_buff *skb; 351 int num_free; 352 int num_remain; 353 int buf_id; 354 u32 cookie; 355 dma_addr_t paddr; 356 357 req_entries = min(req_entries, rx_ring->bufs_max); 358 359 srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id]; 360 361 spin_lock_bh(&srng->lock); 362 363 ath11k_hal_srng_access_begin(ab, srng); 364 365 num_free = ath11k_hal_srng_src_num_free(ab, srng, true); 366 if (!req_entries && (num_free > (rx_ring->bufs_max * 3) / 4)) 367 req_entries = num_free; 368 369 req_entries = min(num_free, req_entries); 370 num_remain = req_entries; 371 372 while (num_remain > 0) { 373 skb = dev_alloc_skb(DP_RX_BUFFER_SIZE + 374 DP_RX_BUFFER_ALIGN_SIZE); 375 if (!skb) 376 break; 377 378 if (!IS_ALIGNED((unsigned long)skb->data, 379 DP_RX_BUFFER_ALIGN_SIZE)) { 380 skb_pull(skb, 381 PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) - 382 skb->data); 383 } 384 385 paddr = dma_map_single(ab->dev, skb->data, 386 skb->len + skb_tailroom(skb), 387 DMA_FROM_DEVICE); 388 if (dma_mapping_error(ab->dev, paddr)) 389 goto fail_free_skb; 390 391 spin_lock_bh(&rx_ring->idr_lock); 392 buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 1, 393 (rx_ring->bufs_max * 3) + 1, GFP_ATOMIC); 394 spin_unlock_bh(&rx_ring->idr_lock); 395 if (buf_id <= 0) 396 goto fail_dma_unmap; 397 398 desc = ath11k_hal_srng_src_get_next_entry(ab, srng); 399 if (!desc) 400 goto fail_idr_remove; 401 402 ATH11K_SKB_RXCB(skb)->paddr = paddr; 403 404 cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) | 405 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id); 406 407 num_remain--; 408 409 ath11k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr); 410 } 411 412 ath11k_hal_srng_access_end(ab, srng); 413 414 spin_unlock_bh(&srng->lock); 415 416 return req_entries - num_remain; 417 418 fail_idr_remove: 419 spin_lock_bh(&rx_ring->idr_lock); 420 idr_remove(&rx_ring->bufs_idr, buf_id); 421 spin_unlock_bh(&rx_ring->idr_lock); 422 fail_dma_unmap: 423 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb), 424 DMA_FROM_DEVICE); 425 fail_free_skb: 426 dev_kfree_skb_any(skb); 427 428 ath11k_hal_srng_access_end(ab, srng); 429 430 spin_unlock_bh(&srng->lock); 431 432 return req_entries - num_remain; 433 } 434 435 static int ath11k_dp_rxdma_buf_ring_free(struct ath11k *ar, 436 struct dp_rxdma_ring *rx_ring) 437 { 438 struct sk_buff *skb; 439 int buf_id; 440 441 spin_lock_bh(&rx_ring->idr_lock); 442 idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) { 443 idr_remove(&rx_ring->bufs_idr, buf_id); 444 /* TODO: Understand where internal driver does this dma_unmap 445 * of rxdma_buffer. 446 */ 447 dma_unmap_single(ar->ab->dev, ATH11K_SKB_RXCB(skb)->paddr, 448 skb->len + skb_tailroom(skb), DMA_FROM_DEVICE); 449 dev_kfree_skb_any(skb); 450 } 451 452 idr_destroy(&rx_ring->bufs_idr); 453 spin_unlock_bh(&rx_ring->idr_lock); 454 455 return 0; 456 } 457 458 static int ath11k_dp_rxdma_pdev_buf_free(struct ath11k *ar) 459 { 460 struct ath11k_pdev_dp *dp = &ar->dp; 461 struct ath11k_base *ab = ar->ab; 462 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring; 463 int i; 464 465 ath11k_dp_rxdma_buf_ring_free(ar, rx_ring); 466 467 rx_ring = &dp->rxdma_mon_buf_ring; 468 ath11k_dp_rxdma_buf_ring_free(ar, rx_ring); 469 470 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 471 rx_ring = &dp->rx_mon_status_refill_ring[i]; 472 ath11k_dp_rxdma_buf_ring_free(ar, rx_ring); 473 } 474 475 return 0; 476 } 477 478 static int ath11k_dp_rxdma_ring_buf_setup(struct ath11k *ar, 479 struct dp_rxdma_ring *rx_ring, 480 u32 ringtype) 481 { 482 struct ath11k_pdev_dp *dp = &ar->dp; 483 int num_entries; 484 485 num_entries = rx_ring->refill_buf_ring.size / 486 ath11k_hal_srng_get_entrysize(ar->ab, ringtype); 487 488 rx_ring->bufs_max = num_entries; 489 ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id, rx_ring, num_entries, 490 ar->ab->hw_params.hal_params->rx_buf_rbm); 491 return 0; 492 } 493 494 static int ath11k_dp_rxdma_pdev_buf_setup(struct ath11k *ar) 495 { 496 struct ath11k_pdev_dp *dp = &ar->dp; 497 struct ath11k_base *ab = ar->ab; 498 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring; 499 int i; 500 501 ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_BUF); 502 503 if (ar->ab->hw_params.rxdma1_enable) { 504 rx_ring = &dp->rxdma_mon_buf_ring; 505 ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_MONITOR_BUF); 506 } 507 508 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 509 rx_ring = &dp->rx_mon_status_refill_ring[i]; 510 ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_MONITOR_STATUS); 511 } 512 513 return 0; 514 } 515 516 static void ath11k_dp_rx_pdev_srng_free(struct ath11k *ar) 517 { 518 struct ath11k_pdev_dp *dp = &ar->dp; 519 struct ath11k_base *ab = ar->ab; 520 int i; 521 522 ath11k_dp_srng_cleanup(ab, &dp->rx_refill_buf_ring.refill_buf_ring); 523 524 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 525 if (ab->hw_params.rx_mac_buf_ring) 526 ath11k_dp_srng_cleanup(ab, &dp->rx_mac_buf_ring[i]); 527 528 ath11k_dp_srng_cleanup(ab, &dp->rxdma_err_dst_ring[i]); 529 ath11k_dp_srng_cleanup(ab, 530 &dp->rx_mon_status_refill_ring[i].refill_buf_ring); 531 } 532 533 ath11k_dp_srng_cleanup(ab, &dp->rxdma_mon_buf_ring.refill_buf_ring); 534 } 535 536 void ath11k_dp_pdev_reo_cleanup(struct ath11k_base *ab) 537 { 538 struct ath11k_dp *dp = &ab->dp; 539 int i; 540 541 for (i = 0; i < DP_REO_DST_RING_MAX; i++) 542 ath11k_dp_srng_cleanup(ab, &dp->reo_dst_ring[i]); 543 } 544 545 int ath11k_dp_pdev_reo_setup(struct ath11k_base *ab) 546 { 547 struct ath11k_dp *dp = &ab->dp; 548 int ret; 549 int i; 550 551 for (i = 0; i < DP_REO_DST_RING_MAX; i++) { 552 ret = ath11k_dp_srng_setup(ab, &dp->reo_dst_ring[i], 553 HAL_REO_DST, i, 0, 554 DP_REO_DST_RING_SIZE); 555 if (ret) { 556 ath11k_warn(ab, "failed to setup reo_dst_ring\n"); 557 goto err_reo_cleanup; 558 } 559 } 560 561 return 0; 562 563 err_reo_cleanup: 564 ath11k_dp_pdev_reo_cleanup(ab); 565 566 return ret; 567 } 568 569 static int ath11k_dp_rx_pdev_srng_alloc(struct ath11k *ar) 570 { 571 struct ath11k_pdev_dp *dp = &ar->dp; 572 struct ath11k_base *ab = ar->ab; 573 struct dp_srng *srng = NULL; 574 int i; 575 int ret; 576 577 ret = ath11k_dp_srng_setup(ar->ab, 578 &dp->rx_refill_buf_ring.refill_buf_ring, 579 HAL_RXDMA_BUF, 0, 580 dp->mac_id, DP_RXDMA_BUF_RING_SIZE); 581 if (ret) { 582 ath11k_warn(ar->ab, "failed to setup rx_refill_buf_ring\n"); 583 return ret; 584 } 585 586 if (ar->ab->hw_params.rx_mac_buf_ring) { 587 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 588 ret = ath11k_dp_srng_setup(ar->ab, 589 &dp->rx_mac_buf_ring[i], 590 HAL_RXDMA_BUF, 1, 591 dp->mac_id + i, 1024); 592 if (ret) { 593 ath11k_warn(ar->ab, "failed to setup rx_mac_buf_ring %d\n", 594 i); 595 return ret; 596 } 597 } 598 } 599 600 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 601 ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_err_dst_ring[i], 602 HAL_RXDMA_DST, 0, dp->mac_id + i, 603 DP_RXDMA_ERR_DST_RING_SIZE); 604 if (ret) { 605 ath11k_warn(ar->ab, "failed to setup rxdma_err_dst_ring %d\n", i); 606 return ret; 607 } 608 } 609 610 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 611 srng = &dp->rx_mon_status_refill_ring[i].refill_buf_ring; 612 ret = ath11k_dp_srng_setup(ar->ab, 613 srng, 614 HAL_RXDMA_MONITOR_STATUS, 0, dp->mac_id + i, 615 DP_RXDMA_MON_STATUS_RING_SIZE); 616 if (ret) { 617 ath11k_warn(ar->ab, 618 "failed to setup rx_mon_status_refill_ring %d\n", i); 619 return ret; 620 } 621 } 622 623 /* if rxdma1_enable is false, then it doesn't need 624 * to setup rxdam_mon_buf_ring, rxdma_mon_dst_ring 625 * and rxdma_mon_desc_ring. 626 * init reap timer for QCA6390. 627 */ 628 if (!ar->ab->hw_params.rxdma1_enable) { 629 //init mon status buffer reap timer 630 timer_setup(&ar->ab->mon_reap_timer, 631 ath11k_dp_service_mon_ring, 0); 632 return 0; 633 } 634 635 ret = ath11k_dp_srng_setup(ar->ab, 636 &dp->rxdma_mon_buf_ring.refill_buf_ring, 637 HAL_RXDMA_MONITOR_BUF, 0, dp->mac_id, 638 DP_RXDMA_MONITOR_BUF_RING_SIZE); 639 if (ret) { 640 ath11k_warn(ar->ab, 641 "failed to setup HAL_RXDMA_MONITOR_BUF\n"); 642 return ret; 643 } 644 645 ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_mon_dst_ring, 646 HAL_RXDMA_MONITOR_DST, 0, dp->mac_id, 647 DP_RXDMA_MONITOR_DST_RING_SIZE); 648 if (ret) { 649 ath11k_warn(ar->ab, 650 "failed to setup HAL_RXDMA_MONITOR_DST\n"); 651 return ret; 652 } 653 654 ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_mon_desc_ring, 655 HAL_RXDMA_MONITOR_DESC, 0, dp->mac_id, 656 DP_RXDMA_MONITOR_DESC_RING_SIZE); 657 if (ret) { 658 ath11k_warn(ar->ab, 659 "failed to setup HAL_RXDMA_MONITOR_DESC\n"); 660 return ret; 661 } 662 663 return 0; 664 } 665 666 void ath11k_dp_reo_cmd_list_cleanup(struct ath11k_base *ab) 667 { 668 struct ath11k_dp *dp = &ab->dp; 669 struct dp_reo_cmd *cmd, *tmp; 670 struct dp_reo_cache_flush_elem *cmd_cache, *tmp_cache; 671 struct dp_rx_tid *rx_tid; 672 673 spin_lock_bh(&dp->reo_cmd_lock); 674 list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) { 675 list_del(&cmd->list); 676 rx_tid = &cmd->data; 677 if (rx_tid->vaddr) { 678 dma_unmap_single(ab->dev, rx_tid->paddr, 679 rx_tid->size, DMA_BIDIRECTIONAL); 680 kfree(rx_tid->vaddr); 681 rx_tid->vaddr = NULL; 682 } 683 kfree(cmd); 684 } 685 686 list_for_each_entry_safe(cmd_cache, tmp_cache, 687 &dp->reo_cmd_cache_flush_list, list) { 688 list_del(&cmd_cache->list); 689 dp->reo_cmd_cache_flush_count--; 690 rx_tid = &cmd_cache->data; 691 if (rx_tid->vaddr) { 692 dma_unmap_single(ab->dev, rx_tid->paddr, 693 rx_tid->size, DMA_BIDIRECTIONAL); 694 kfree(rx_tid->vaddr); 695 rx_tid->vaddr = NULL; 696 } 697 kfree(cmd_cache); 698 } 699 spin_unlock_bh(&dp->reo_cmd_lock); 700 } 701 702 static void ath11k_dp_reo_cmd_free(struct ath11k_dp *dp, void *ctx, 703 enum hal_reo_cmd_status status) 704 { 705 struct dp_rx_tid *rx_tid = ctx; 706 707 if (status != HAL_REO_CMD_SUCCESS) 708 ath11k_warn(dp->ab, "failed to flush rx tid hw desc, tid %d status %d\n", 709 rx_tid->tid, status); 710 if (rx_tid->vaddr) { 711 dma_unmap_single(dp->ab->dev, rx_tid->paddr, rx_tid->size, 712 DMA_BIDIRECTIONAL); 713 kfree(rx_tid->vaddr); 714 rx_tid->vaddr = NULL; 715 } 716 } 717 718 static void ath11k_dp_reo_cache_flush(struct ath11k_base *ab, 719 struct dp_rx_tid *rx_tid) 720 { 721 struct ath11k_hal_reo_cmd cmd = {0}; 722 unsigned long tot_desc_sz, desc_sz; 723 int ret; 724 725 tot_desc_sz = rx_tid->size; 726 desc_sz = ath11k_hal_reo_qdesc_size(0, HAL_DESC_REO_NON_QOS_TID); 727 728 while (tot_desc_sz > desc_sz) { 729 tot_desc_sz -= desc_sz; 730 cmd.addr_lo = lower_32_bits(rx_tid->paddr + tot_desc_sz); 731 cmd.addr_hi = upper_32_bits(rx_tid->paddr); 732 ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid, 733 HAL_REO_CMD_FLUSH_CACHE, &cmd, 734 NULL); 735 if (ret) 736 ath11k_warn(ab, 737 "failed to send HAL_REO_CMD_FLUSH_CACHE, tid %d (%d)\n", 738 rx_tid->tid, ret); 739 } 740 741 memset(&cmd, 0, sizeof(cmd)); 742 cmd.addr_lo = lower_32_bits(rx_tid->paddr); 743 cmd.addr_hi = upper_32_bits(rx_tid->paddr); 744 cmd.flag |= HAL_REO_CMD_FLG_NEED_STATUS; 745 ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid, 746 HAL_REO_CMD_FLUSH_CACHE, 747 &cmd, ath11k_dp_reo_cmd_free); 748 if (ret) { 749 ath11k_err(ab, "failed to send HAL_REO_CMD_FLUSH_CACHE cmd, tid %d (%d)\n", 750 rx_tid->tid, ret); 751 dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size, 752 DMA_BIDIRECTIONAL); 753 kfree(rx_tid->vaddr); 754 rx_tid->vaddr = NULL; 755 } 756 } 757 758 static void ath11k_dp_rx_tid_del_func(struct ath11k_dp *dp, void *ctx, 759 enum hal_reo_cmd_status status) 760 { 761 struct ath11k_base *ab = dp->ab; 762 struct dp_rx_tid *rx_tid = ctx; 763 struct dp_reo_cache_flush_elem *elem, *tmp; 764 765 if (status == HAL_REO_CMD_DRAIN) { 766 goto free_desc; 767 } else if (status != HAL_REO_CMD_SUCCESS) { 768 /* Shouldn't happen! Cleanup in case of other failure? */ 769 ath11k_warn(ab, "failed to delete rx tid %d hw descriptor %d\n", 770 rx_tid->tid, status); 771 return; 772 } 773 774 elem = kzalloc(sizeof(*elem), GFP_ATOMIC); 775 if (!elem) 776 goto free_desc; 777 778 elem->ts = jiffies; 779 memcpy(&elem->data, rx_tid, sizeof(*rx_tid)); 780 781 spin_lock_bh(&dp->reo_cmd_lock); 782 list_add_tail(&elem->list, &dp->reo_cmd_cache_flush_list); 783 dp->reo_cmd_cache_flush_count++; 784 785 /* Flush and invalidate aged REO desc from HW cache */ 786 list_for_each_entry_safe(elem, tmp, &dp->reo_cmd_cache_flush_list, 787 list) { 788 if (dp->reo_cmd_cache_flush_count > DP_REO_DESC_FREE_THRESHOLD || 789 time_after(jiffies, elem->ts + 790 msecs_to_jiffies(DP_REO_DESC_FREE_TIMEOUT_MS))) { 791 list_del(&elem->list); 792 dp->reo_cmd_cache_flush_count--; 793 spin_unlock_bh(&dp->reo_cmd_lock); 794 795 ath11k_dp_reo_cache_flush(ab, &elem->data); 796 kfree(elem); 797 spin_lock_bh(&dp->reo_cmd_lock); 798 } 799 } 800 spin_unlock_bh(&dp->reo_cmd_lock); 801 802 return; 803 free_desc: 804 dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size, 805 DMA_BIDIRECTIONAL); 806 kfree(rx_tid->vaddr); 807 rx_tid->vaddr = NULL; 808 } 809 810 void ath11k_peer_rx_tid_delete(struct ath11k *ar, 811 struct ath11k_peer *peer, u8 tid) 812 { 813 struct ath11k_hal_reo_cmd cmd = {0}; 814 struct dp_rx_tid *rx_tid = &peer->rx_tid[tid]; 815 int ret; 816 817 if (!rx_tid->active) 818 return; 819 820 rx_tid->active = false; 821 822 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS; 823 cmd.addr_lo = lower_32_bits(rx_tid->paddr); 824 cmd.addr_hi = upper_32_bits(rx_tid->paddr); 825 cmd.upd0 |= HAL_REO_CMD_UPD0_VLD; 826 ret = ath11k_dp_tx_send_reo_cmd(ar->ab, rx_tid, 827 HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd, 828 ath11k_dp_rx_tid_del_func); 829 if (ret) { 830 if (ret != -ESHUTDOWN) 831 ath11k_err(ar->ab, "failed to send HAL_REO_CMD_UPDATE_RX_QUEUE cmd, tid %d (%d)\n", 832 tid, ret); 833 dma_unmap_single(ar->ab->dev, rx_tid->paddr, rx_tid->size, 834 DMA_BIDIRECTIONAL); 835 kfree(rx_tid->vaddr); 836 rx_tid->vaddr = NULL; 837 } 838 839 rx_tid->paddr = 0; 840 rx_tid->size = 0; 841 } 842 843 static int ath11k_dp_rx_link_desc_return(struct ath11k_base *ab, 844 u32 *link_desc, 845 enum hal_wbm_rel_bm_act action) 846 { 847 struct ath11k_dp *dp = &ab->dp; 848 struct hal_srng *srng; 849 u32 *desc; 850 int ret = 0; 851 852 srng = &ab->hal.srng_list[dp->wbm_desc_rel_ring.ring_id]; 853 854 spin_lock_bh(&srng->lock); 855 856 ath11k_hal_srng_access_begin(ab, srng); 857 858 desc = ath11k_hal_srng_src_get_next_entry(ab, srng); 859 if (!desc) { 860 ret = -ENOBUFS; 861 goto exit; 862 } 863 864 ath11k_hal_rx_msdu_link_desc_set(ab, (void *)desc, (void *)link_desc, 865 action); 866 867 exit: 868 ath11k_hal_srng_access_end(ab, srng); 869 870 spin_unlock_bh(&srng->lock); 871 872 return ret; 873 } 874 875 static void ath11k_dp_rx_frags_cleanup(struct dp_rx_tid *rx_tid, bool rel_link_desc) 876 { 877 struct ath11k_base *ab = rx_tid->ab; 878 879 lockdep_assert_held(&ab->base_lock); 880 881 if (rx_tid->dst_ring_desc) { 882 if (rel_link_desc) 883 ath11k_dp_rx_link_desc_return(ab, (u32 *)rx_tid->dst_ring_desc, 884 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 885 kfree(rx_tid->dst_ring_desc); 886 rx_tid->dst_ring_desc = NULL; 887 } 888 889 rx_tid->cur_sn = 0; 890 rx_tid->last_frag_no = 0; 891 rx_tid->rx_frag_bitmap = 0; 892 __skb_queue_purge(&rx_tid->rx_frags); 893 } 894 895 void ath11k_peer_frags_flush(struct ath11k *ar, struct ath11k_peer *peer) 896 { 897 struct dp_rx_tid *rx_tid; 898 int i; 899 900 lockdep_assert_held(&ar->ab->base_lock); 901 902 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) { 903 rx_tid = &peer->rx_tid[i]; 904 905 spin_unlock_bh(&ar->ab->base_lock); 906 del_timer_sync(&rx_tid->frag_timer); 907 spin_lock_bh(&ar->ab->base_lock); 908 909 ath11k_dp_rx_frags_cleanup(rx_tid, true); 910 } 911 } 912 913 void ath11k_peer_rx_tid_cleanup(struct ath11k *ar, struct ath11k_peer *peer) 914 { 915 struct dp_rx_tid *rx_tid; 916 int i; 917 918 lockdep_assert_held(&ar->ab->base_lock); 919 920 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) { 921 rx_tid = &peer->rx_tid[i]; 922 923 ath11k_peer_rx_tid_delete(ar, peer, i); 924 ath11k_dp_rx_frags_cleanup(rx_tid, true); 925 926 spin_unlock_bh(&ar->ab->base_lock); 927 del_timer_sync(&rx_tid->frag_timer); 928 spin_lock_bh(&ar->ab->base_lock); 929 } 930 } 931 932 static int ath11k_peer_rx_tid_reo_update(struct ath11k *ar, 933 struct ath11k_peer *peer, 934 struct dp_rx_tid *rx_tid, 935 u32 ba_win_sz, u16 ssn, 936 bool update_ssn) 937 { 938 struct ath11k_hal_reo_cmd cmd = {0}; 939 int ret; 940 941 cmd.addr_lo = lower_32_bits(rx_tid->paddr); 942 cmd.addr_hi = upper_32_bits(rx_tid->paddr); 943 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS; 944 cmd.upd0 = HAL_REO_CMD_UPD0_BA_WINDOW_SIZE; 945 cmd.ba_window_size = ba_win_sz; 946 947 if (update_ssn) { 948 cmd.upd0 |= HAL_REO_CMD_UPD0_SSN; 949 cmd.upd2 = FIELD_PREP(HAL_REO_CMD_UPD2_SSN, ssn); 950 } 951 952 ret = ath11k_dp_tx_send_reo_cmd(ar->ab, rx_tid, 953 HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd, 954 NULL); 955 if (ret) { 956 ath11k_warn(ar->ab, "failed to update rx tid queue, tid %d (%d)\n", 957 rx_tid->tid, ret); 958 return ret; 959 } 960 961 rx_tid->ba_win_sz = ba_win_sz; 962 963 return 0; 964 } 965 966 static void ath11k_dp_rx_tid_mem_free(struct ath11k_base *ab, 967 const u8 *peer_mac, int vdev_id, u8 tid) 968 { 969 struct ath11k_peer *peer; 970 struct dp_rx_tid *rx_tid; 971 972 spin_lock_bh(&ab->base_lock); 973 974 peer = ath11k_peer_find(ab, vdev_id, peer_mac); 975 if (!peer) { 976 ath11k_warn(ab, "failed to find the peer to free up rx tid mem\n"); 977 goto unlock_exit; 978 } 979 980 rx_tid = &peer->rx_tid[tid]; 981 if (!rx_tid->active) 982 goto unlock_exit; 983 984 dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size, 985 DMA_BIDIRECTIONAL); 986 kfree(rx_tid->vaddr); 987 rx_tid->vaddr = NULL; 988 989 rx_tid->active = false; 990 991 unlock_exit: 992 spin_unlock_bh(&ab->base_lock); 993 } 994 995 int ath11k_peer_rx_tid_setup(struct ath11k *ar, const u8 *peer_mac, int vdev_id, 996 u8 tid, u32 ba_win_sz, u16 ssn, 997 enum hal_pn_type pn_type) 998 { 999 struct ath11k_base *ab = ar->ab; 1000 struct ath11k_peer *peer; 1001 struct dp_rx_tid *rx_tid; 1002 u32 hw_desc_sz; 1003 u32 *addr_aligned; 1004 void *vaddr; 1005 dma_addr_t paddr; 1006 int ret; 1007 1008 spin_lock_bh(&ab->base_lock); 1009 1010 peer = ath11k_peer_find(ab, vdev_id, peer_mac); 1011 if (!peer) { 1012 ath11k_warn(ab, "failed to find the peer %pM to set up rx tid\n", 1013 peer_mac); 1014 spin_unlock_bh(&ab->base_lock); 1015 return -ENOENT; 1016 } 1017 1018 rx_tid = &peer->rx_tid[tid]; 1019 /* Update the tid queue if it is already setup */ 1020 if (rx_tid->active) { 1021 paddr = rx_tid->paddr; 1022 ret = ath11k_peer_rx_tid_reo_update(ar, peer, rx_tid, 1023 ba_win_sz, ssn, true); 1024 spin_unlock_bh(&ab->base_lock); 1025 if (ret) { 1026 ath11k_warn(ab, "failed to update reo for peer %pM rx tid %d\n: %d", 1027 peer_mac, tid, ret); 1028 return ret; 1029 } 1030 1031 ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, 1032 peer_mac, paddr, 1033 tid, 1, ba_win_sz); 1034 if (ret) 1035 ath11k_warn(ab, "failed to send wmi rx reorder queue for peer %pM tid %d: %d\n", 1036 peer_mac, tid, ret); 1037 return ret; 1038 } 1039 1040 rx_tid->tid = tid; 1041 1042 rx_tid->ba_win_sz = ba_win_sz; 1043 1044 /* TODO: Optimize the memory allocation for qos tid based on 1045 * the actual BA window size in REO tid update path. 1046 */ 1047 if (tid == HAL_DESC_REO_NON_QOS_TID) 1048 hw_desc_sz = ath11k_hal_reo_qdesc_size(ba_win_sz, tid); 1049 else 1050 hw_desc_sz = ath11k_hal_reo_qdesc_size(DP_BA_WIN_SZ_MAX, tid); 1051 1052 vaddr = kzalloc(hw_desc_sz + HAL_LINK_DESC_ALIGN - 1, GFP_ATOMIC); 1053 if (!vaddr) { 1054 spin_unlock_bh(&ab->base_lock); 1055 return -ENOMEM; 1056 } 1057 1058 addr_aligned = PTR_ALIGN(vaddr, HAL_LINK_DESC_ALIGN); 1059 1060 ath11k_hal_reo_qdesc_setup(addr_aligned, tid, ba_win_sz, 1061 ssn, pn_type); 1062 1063 paddr = dma_map_single(ab->dev, addr_aligned, hw_desc_sz, 1064 DMA_BIDIRECTIONAL); 1065 1066 ret = dma_mapping_error(ab->dev, paddr); 1067 if (ret) { 1068 spin_unlock_bh(&ab->base_lock); 1069 ath11k_warn(ab, "failed to setup dma map for peer %pM rx tid %d: %d\n", 1070 peer_mac, tid, ret); 1071 goto err_mem_free; 1072 } 1073 1074 rx_tid->vaddr = vaddr; 1075 rx_tid->paddr = paddr; 1076 rx_tid->size = hw_desc_sz; 1077 rx_tid->active = true; 1078 1079 spin_unlock_bh(&ab->base_lock); 1080 1081 ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, peer_mac, 1082 paddr, tid, 1, ba_win_sz); 1083 if (ret) { 1084 ath11k_warn(ar->ab, "failed to setup rx reorder queue for peer %pM tid %d: %d\n", 1085 peer_mac, tid, ret); 1086 ath11k_dp_rx_tid_mem_free(ab, peer_mac, vdev_id, tid); 1087 } 1088 1089 return ret; 1090 1091 err_mem_free: 1092 kfree(rx_tid->vaddr); 1093 rx_tid->vaddr = NULL; 1094 1095 return ret; 1096 } 1097 1098 int ath11k_dp_rx_ampdu_start(struct ath11k *ar, 1099 struct ieee80211_ampdu_params *params) 1100 { 1101 struct ath11k_base *ab = ar->ab; 1102 struct ath11k_sta *arsta = ath11k_sta_to_arsta(params->sta); 1103 int vdev_id = arsta->arvif->vdev_id; 1104 int ret; 1105 1106 ret = ath11k_peer_rx_tid_setup(ar, params->sta->addr, vdev_id, 1107 params->tid, params->buf_size, 1108 params->ssn, arsta->pn_type); 1109 if (ret) 1110 ath11k_warn(ab, "failed to setup rx tid %d\n", ret); 1111 1112 return ret; 1113 } 1114 1115 int ath11k_dp_rx_ampdu_stop(struct ath11k *ar, 1116 struct ieee80211_ampdu_params *params) 1117 { 1118 struct ath11k_base *ab = ar->ab; 1119 struct ath11k_peer *peer; 1120 struct ath11k_sta *arsta = ath11k_sta_to_arsta(params->sta); 1121 int vdev_id = arsta->arvif->vdev_id; 1122 dma_addr_t paddr; 1123 bool active; 1124 int ret; 1125 1126 spin_lock_bh(&ab->base_lock); 1127 1128 peer = ath11k_peer_find(ab, vdev_id, params->sta->addr); 1129 if (!peer) { 1130 ath11k_warn(ab, "failed to find the peer to stop rx aggregation\n"); 1131 spin_unlock_bh(&ab->base_lock); 1132 return -ENOENT; 1133 } 1134 1135 paddr = peer->rx_tid[params->tid].paddr; 1136 active = peer->rx_tid[params->tid].active; 1137 1138 if (!active) { 1139 spin_unlock_bh(&ab->base_lock); 1140 return 0; 1141 } 1142 1143 ret = ath11k_peer_rx_tid_reo_update(ar, peer, peer->rx_tid, 1, 0, false); 1144 spin_unlock_bh(&ab->base_lock); 1145 if (ret) { 1146 ath11k_warn(ab, "failed to update reo for rx tid %d: %d\n", 1147 params->tid, ret); 1148 return ret; 1149 } 1150 1151 ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, 1152 params->sta->addr, paddr, 1153 params->tid, 1, 1); 1154 if (ret) 1155 ath11k_warn(ab, "failed to send wmi to delete rx tid %d\n", 1156 ret); 1157 1158 return ret; 1159 } 1160 1161 int ath11k_dp_peer_rx_pn_replay_config(struct ath11k_vif *arvif, 1162 const u8 *peer_addr, 1163 enum set_key_cmd key_cmd, 1164 struct ieee80211_key_conf *key) 1165 { 1166 struct ath11k *ar = arvif->ar; 1167 struct ath11k_base *ab = ar->ab; 1168 struct ath11k_hal_reo_cmd cmd = {0}; 1169 struct ath11k_peer *peer; 1170 struct dp_rx_tid *rx_tid; 1171 u8 tid; 1172 int ret = 0; 1173 1174 /* NOTE: Enable PN/TSC replay check offload only for unicast frames. 1175 * We use mac80211 PN/TSC replay check functionality for bcast/mcast 1176 * for now. 1177 */ 1178 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) 1179 return 0; 1180 1181 cmd.flag |= HAL_REO_CMD_FLG_NEED_STATUS; 1182 cmd.upd0 |= HAL_REO_CMD_UPD0_PN | 1183 HAL_REO_CMD_UPD0_PN_SIZE | 1184 HAL_REO_CMD_UPD0_PN_VALID | 1185 HAL_REO_CMD_UPD0_PN_CHECK | 1186 HAL_REO_CMD_UPD0_SVLD; 1187 1188 switch (key->cipher) { 1189 case WLAN_CIPHER_SUITE_TKIP: 1190 case WLAN_CIPHER_SUITE_CCMP: 1191 case WLAN_CIPHER_SUITE_CCMP_256: 1192 case WLAN_CIPHER_SUITE_GCMP: 1193 case WLAN_CIPHER_SUITE_GCMP_256: 1194 if (key_cmd == SET_KEY) { 1195 cmd.upd1 |= HAL_REO_CMD_UPD1_PN_CHECK; 1196 cmd.pn_size = 48; 1197 } 1198 break; 1199 default: 1200 break; 1201 } 1202 1203 spin_lock_bh(&ab->base_lock); 1204 1205 peer = ath11k_peer_find(ab, arvif->vdev_id, peer_addr); 1206 if (!peer) { 1207 ath11k_warn(ab, "failed to find the peer to configure pn replay detection\n"); 1208 spin_unlock_bh(&ab->base_lock); 1209 return -ENOENT; 1210 } 1211 1212 for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) { 1213 rx_tid = &peer->rx_tid[tid]; 1214 if (!rx_tid->active) 1215 continue; 1216 cmd.addr_lo = lower_32_bits(rx_tid->paddr); 1217 cmd.addr_hi = upper_32_bits(rx_tid->paddr); 1218 ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid, 1219 HAL_REO_CMD_UPDATE_RX_QUEUE, 1220 &cmd, NULL); 1221 if (ret) { 1222 ath11k_warn(ab, "failed to configure rx tid %d queue for pn replay detection %d\n", 1223 tid, ret); 1224 break; 1225 } 1226 } 1227 1228 spin_unlock_bh(&ab->base_lock); 1229 1230 return ret; 1231 } 1232 1233 static inline int ath11k_get_ppdu_user_index(struct htt_ppdu_stats *ppdu_stats, 1234 u16 peer_id) 1235 { 1236 int i; 1237 1238 for (i = 0; i < HTT_PPDU_STATS_MAX_USERS - 1; i++) { 1239 if (ppdu_stats->user_stats[i].is_valid_peer_id) { 1240 if (peer_id == ppdu_stats->user_stats[i].peer_id) 1241 return i; 1242 } else { 1243 return i; 1244 } 1245 } 1246 1247 return -EINVAL; 1248 } 1249 1250 static int ath11k_htt_tlv_ppdu_stats_parse(struct ath11k_base *ab, 1251 u16 tag, u16 len, const void *ptr, 1252 void *data) 1253 { 1254 struct htt_ppdu_stats_info *ppdu_info; 1255 struct htt_ppdu_user_stats *user_stats; 1256 int cur_user; 1257 u16 peer_id; 1258 1259 ppdu_info = data; 1260 1261 switch (tag) { 1262 case HTT_PPDU_STATS_TAG_COMMON: 1263 if (len < sizeof(struct htt_ppdu_stats_common)) { 1264 ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1265 len, tag); 1266 return -EINVAL; 1267 } 1268 memcpy((void *)&ppdu_info->ppdu_stats.common, ptr, 1269 sizeof(struct htt_ppdu_stats_common)); 1270 break; 1271 case HTT_PPDU_STATS_TAG_USR_RATE: 1272 if (len < sizeof(struct htt_ppdu_stats_user_rate)) { 1273 ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1274 len, tag); 1275 return -EINVAL; 1276 } 1277 1278 peer_id = ((struct htt_ppdu_stats_user_rate *)ptr)->sw_peer_id; 1279 cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats, 1280 peer_id); 1281 if (cur_user < 0) 1282 return -EINVAL; 1283 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user]; 1284 user_stats->peer_id = peer_id; 1285 user_stats->is_valid_peer_id = true; 1286 memcpy((void *)&user_stats->rate, ptr, 1287 sizeof(struct htt_ppdu_stats_user_rate)); 1288 user_stats->tlv_flags |= BIT(tag); 1289 break; 1290 case HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON: 1291 if (len < sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)) { 1292 ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1293 len, tag); 1294 return -EINVAL; 1295 } 1296 1297 peer_id = ((struct htt_ppdu_stats_usr_cmpltn_cmn *)ptr)->sw_peer_id; 1298 cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats, 1299 peer_id); 1300 if (cur_user < 0) 1301 return -EINVAL; 1302 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user]; 1303 user_stats->peer_id = peer_id; 1304 user_stats->is_valid_peer_id = true; 1305 memcpy((void *)&user_stats->cmpltn_cmn, ptr, 1306 sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)); 1307 user_stats->tlv_flags |= BIT(tag); 1308 break; 1309 case HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS: 1310 if (len < 1311 sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)) { 1312 ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1313 len, tag); 1314 return -EINVAL; 1315 } 1316 1317 peer_id = 1318 ((struct htt_ppdu_stats_usr_cmpltn_ack_ba_status *)ptr)->sw_peer_id; 1319 cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats, 1320 peer_id); 1321 if (cur_user < 0) 1322 return -EINVAL; 1323 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user]; 1324 user_stats->peer_id = peer_id; 1325 user_stats->is_valid_peer_id = true; 1326 memcpy((void *)&user_stats->ack_ba, ptr, 1327 sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)); 1328 user_stats->tlv_flags |= BIT(tag); 1329 break; 1330 } 1331 return 0; 1332 } 1333 1334 int ath11k_dp_htt_tlv_iter(struct ath11k_base *ab, const void *ptr, size_t len, 1335 int (*iter)(struct ath11k_base *ar, u16 tag, u16 len, 1336 const void *ptr, void *data), 1337 void *data) 1338 { 1339 const struct htt_tlv *tlv; 1340 const void *begin = ptr; 1341 u16 tlv_tag, tlv_len; 1342 int ret = -EINVAL; 1343 1344 while (len > 0) { 1345 if (len < sizeof(*tlv)) { 1346 ath11k_err(ab, "htt tlv parse failure at byte %zd (%zu bytes left, %zu expected)\n", 1347 ptr - begin, len, sizeof(*tlv)); 1348 return -EINVAL; 1349 } 1350 tlv = (struct htt_tlv *)ptr; 1351 tlv_tag = FIELD_GET(HTT_TLV_TAG, tlv->header); 1352 tlv_len = FIELD_GET(HTT_TLV_LEN, tlv->header); 1353 ptr += sizeof(*tlv); 1354 len -= sizeof(*tlv); 1355 1356 if (tlv_len > len) { 1357 ath11k_err(ab, "htt tlv parse failure of tag %u at byte %zd (%zu bytes left, %u expected)\n", 1358 tlv_tag, ptr - begin, len, tlv_len); 1359 return -EINVAL; 1360 } 1361 ret = iter(ab, tlv_tag, tlv_len, ptr, data); 1362 if (ret == -ENOMEM) 1363 return ret; 1364 1365 ptr += tlv_len; 1366 len -= tlv_len; 1367 } 1368 return 0; 1369 } 1370 1371 static void 1372 ath11k_update_per_peer_tx_stats(struct ath11k *ar, 1373 struct htt_ppdu_stats *ppdu_stats, u8 user) 1374 { 1375 struct ath11k_base *ab = ar->ab; 1376 struct ath11k_peer *peer; 1377 struct ieee80211_sta *sta; 1378 struct ath11k_sta *arsta; 1379 struct htt_ppdu_stats_user_rate *user_rate; 1380 struct ath11k_per_peer_tx_stats *peer_stats = &ar->peer_tx_stats; 1381 struct htt_ppdu_user_stats *usr_stats = &ppdu_stats->user_stats[user]; 1382 struct htt_ppdu_stats_common *common = &ppdu_stats->common; 1383 int ret; 1384 u8 flags, mcs, nss, bw, sgi, dcm, rate_idx = 0; 1385 u32 succ_bytes = 0; 1386 u16 rate = 0, succ_pkts = 0; 1387 u32 tx_duration = 0; 1388 u8 tid = HTT_PPDU_STATS_NON_QOS_TID; 1389 bool is_ampdu = false; 1390 1391 if (!(usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_RATE))) 1392 return; 1393 1394 if (usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON)) 1395 is_ampdu = 1396 HTT_USR_CMPLTN_IS_AMPDU(usr_stats->cmpltn_cmn.flags); 1397 1398 if (usr_stats->tlv_flags & 1399 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS)) { 1400 succ_bytes = usr_stats->ack_ba.success_bytes; 1401 succ_pkts = FIELD_GET(HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M, 1402 usr_stats->ack_ba.info); 1403 tid = FIELD_GET(HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM, 1404 usr_stats->ack_ba.info); 1405 } 1406 1407 if (common->fes_duration_us) 1408 tx_duration = common->fes_duration_us; 1409 1410 user_rate = &usr_stats->rate; 1411 flags = HTT_USR_RATE_PREAMBLE(user_rate->rate_flags); 1412 bw = HTT_USR_RATE_BW(user_rate->rate_flags) - 2; 1413 nss = HTT_USR_RATE_NSS(user_rate->rate_flags) + 1; 1414 mcs = HTT_USR_RATE_MCS(user_rate->rate_flags); 1415 sgi = HTT_USR_RATE_GI(user_rate->rate_flags); 1416 dcm = HTT_USR_RATE_DCM(user_rate->rate_flags); 1417 1418 /* Note: If host configured fixed rates and in some other special 1419 * cases, the broadcast/management frames are sent in different rates. 1420 * Firmware rate's control to be skipped for this? 1421 */ 1422 1423 if (flags == WMI_RATE_PREAMBLE_HE && mcs > ATH11K_HE_MCS_MAX) { 1424 ath11k_warn(ab, "Invalid HE mcs %d peer stats", mcs); 1425 return; 1426 } 1427 1428 if (flags == WMI_RATE_PREAMBLE_VHT && mcs > ATH11K_VHT_MCS_MAX) { 1429 ath11k_warn(ab, "Invalid VHT mcs %d peer stats", mcs); 1430 return; 1431 } 1432 1433 if (flags == WMI_RATE_PREAMBLE_HT && (mcs > ATH11K_HT_MCS_MAX || nss < 1)) { 1434 ath11k_warn(ab, "Invalid HT mcs %d nss %d peer stats", 1435 mcs, nss); 1436 return; 1437 } 1438 1439 if (flags == WMI_RATE_PREAMBLE_CCK || flags == WMI_RATE_PREAMBLE_OFDM) { 1440 ret = ath11k_mac_hw_ratecode_to_legacy_rate(mcs, 1441 flags, 1442 &rate_idx, 1443 &rate); 1444 if (ret < 0) 1445 return; 1446 } 1447 1448 rcu_read_lock(); 1449 spin_lock_bh(&ab->base_lock); 1450 peer = ath11k_peer_find_by_id(ab, usr_stats->peer_id); 1451 1452 if (!peer || !peer->sta) { 1453 spin_unlock_bh(&ab->base_lock); 1454 rcu_read_unlock(); 1455 return; 1456 } 1457 1458 sta = peer->sta; 1459 arsta = ath11k_sta_to_arsta(sta); 1460 1461 memset(&arsta->txrate, 0, sizeof(arsta->txrate)); 1462 1463 switch (flags) { 1464 case WMI_RATE_PREAMBLE_OFDM: 1465 arsta->txrate.legacy = rate; 1466 break; 1467 case WMI_RATE_PREAMBLE_CCK: 1468 arsta->txrate.legacy = rate; 1469 break; 1470 case WMI_RATE_PREAMBLE_HT: 1471 arsta->txrate.mcs = mcs + 8 * (nss - 1); 1472 arsta->txrate.flags = RATE_INFO_FLAGS_MCS; 1473 if (sgi) 1474 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 1475 break; 1476 case WMI_RATE_PREAMBLE_VHT: 1477 arsta->txrate.mcs = mcs; 1478 arsta->txrate.flags = RATE_INFO_FLAGS_VHT_MCS; 1479 if (sgi) 1480 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 1481 break; 1482 case WMI_RATE_PREAMBLE_HE: 1483 arsta->txrate.mcs = mcs; 1484 arsta->txrate.flags = RATE_INFO_FLAGS_HE_MCS; 1485 arsta->txrate.he_dcm = dcm; 1486 arsta->txrate.he_gi = ath11k_mac_he_gi_to_nl80211_he_gi(sgi); 1487 arsta->txrate.he_ru_alloc = ath11k_mac_phy_he_ru_to_nl80211_he_ru_alloc 1488 ((user_rate->ru_end - 1489 user_rate->ru_start) + 1); 1490 break; 1491 } 1492 1493 arsta->txrate.nss = nss; 1494 1495 arsta->txrate.bw = ath11k_mac_bw_to_mac80211_bw(bw); 1496 arsta->tx_duration += tx_duration; 1497 memcpy(&arsta->last_txrate, &arsta->txrate, sizeof(struct rate_info)); 1498 1499 /* PPDU stats reported for mgmt packet doesn't have valid tx bytes. 1500 * So skip peer stats update for mgmt packets. 1501 */ 1502 if (tid < HTT_PPDU_STATS_NON_QOS_TID) { 1503 memset(peer_stats, 0, sizeof(*peer_stats)); 1504 peer_stats->succ_pkts = succ_pkts; 1505 peer_stats->succ_bytes = succ_bytes; 1506 peer_stats->is_ampdu = is_ampdu; 1507 peer_stats->duration = tx_duration; 1508 peer_stats->ba_fails = 1509 HTT_USR_CMPLTN_LONG_RETRY(usr_stats->cmpltn_cmn.flags) + 1510 HTT_USR_CMPLTN_SHORT_RETRY(usr_stats->cmpltn_cmn.flags); 1511 1512 if (ath11k_debugfs_is_extd_tx_stats_enabled(ar)) 1513 ath11k_debugfs_sta_add_tx_stats(arsta, peer_stats, rate_idx); 1514 } 1515 1516 spin_unlock_bh(&ab->base_lock); 1517 rcu_read_unlock(); 1518 } 1519 1520 static void ath11k_htt_update_ppdu_stats(struct ath11k *ar, 1521 struct htt_ppdu_stats *ppdu_stats) 1522 { 1523 u8 user; 1524 1525 for (user = 0; user < HTT_PPDU_STATS_MAX_USERS - 1; user++) 1526 ath11k_update_per_peer_tx_stats(ar, ppdu_stats, user); 1527 } 1528 1529 static 1530 struct htt_ppdu_stats_info *ath11k_dp_htt_get_ppdu_desc(struct ath11k *ar, 1531 u32 ppdu_id) 1532 { 1533 struct htt_ppdu_stats_info *ppdu_info; 1534 1535 lockdep_assert_held(&ar->data_lock); 1536 1537 if (!list_empty(&ar->ppdu_stats_info)) { 1538 list_for_each_entry(ppdu_info, &ar->ppdu_stats_info, list) { 1539 if (ppdu_info->ppdu_id == ppdu_id) 1540 return ppdu_info; 1541 } 1542 1543 if (ar->ppdu_stat_list_depth > HTT_PPDU_DESC_MAX_DEPTH) { 1544 ppdu_info = list_first_entry(&ar->ppdu_stats_info, 1545 typeof(*ppdu_info), list); 1546 list_del(&ppdu_info->list); 1547 ar->ppdu_stat_list_depth--; 1548 ath11k_htt_update_ppdu_stats(ar, &ppdu_info->ppdu_stats); 1549 kfree(ppdu_info); 1550 } 1551 } 1552 1553 ppdu_info = kzalloc(sizeof(*ppdu_info), GFP_ATOMIC); 1554 if (!ppdu_info) 1555 return NULL; 1556 1557 list_add_tail(&ppdu_info->list, &ar->ppdu_stats_info); 1558 ar->ppdu_stat_list_depth++; 1559 1560 return ppdu_info; 1561 } 1562 1563 static int ath11k_htt_pull_ppdu_stats(struct ath11k_base *ab, 1564 struct sk_buff *skb) 1565 { 1566 struct ath11k_htt_ppdu_stats_msg *msg; 1567 struct htt_ppdu_stats_info *ppdu_info; 1568 struct ath11k *ar; 1569 int ret; 1570 u8 pdev_id; 1571 u32 ppdu_id, len; 1572 1573 msg = (struct ath11k_htt_ppdu_stats_msg *)skb->data; 1574 len = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE, msg->info); 1575 pdev_id = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PDEV_ID, msg->info); 1576 ppdu_id = msg->ppdu_id; 1577 1578 rcu_read_lock(); 1579 ar = ath11k_mac_get_ar_by_pdev_id(ab, pdev_id); 1580 if (!ar) { 1581 ret = -EINVAL; 1582 goto out; 1583 } 1584 1585 if (ath11k_debugfs_is_pktlog_lite_mode_enabled(ar)) 1586 trace_ath11k_htt_ppdu_stats(ar, skb->data, len); 1587 1588 spin_lock_bh(&ar->data_lock); 1589 ppdu_info = ath11k_dp_htt_get_ppdu_desc(ar, ppdu_id); 1590 if (!ppdu_info) { 1591 ret = -EINVAL; 1592 goto out_unlock_data; 1593 } 1594 1595 ppdu_info->ppdu_id = ppdu_id; 1596 ret = ath11k_dp_htt_tlv_iter(ab, msg->data, len, 1597 ath11k_htt_tlv_ppdu_stats_parse, 1598 (void *)ppdu_info); 1599 if (ret) { 1600 ath11k_warn(ab, "Failed to parse tlv %d\n", ret); 1601 goto out_unlock_data; 1602 } 1603 1604 out_unlock_data: 1605 spin_unlock_bh(&ar->data_lock); 1606 1607 out: 1608 rcu_read_unlock(); 1609 1610 return ret; 1611 } 1612 1613 static void ath11k_htt_pktlog(struct ath11k_base *ab, struct sk_buff *skb) 1614 { 1615 struct htt_pktlog_msg *data = (struct htt_pktlog_msg *)skb->data; 1616 struct ath_pktlog_hdr *hdr = (struct ath_pktlog_hdr *)data; 1617 struct ath11k *ar; 1618 u8 pdev_id; 1619 1620 pdev_id = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PDEV_ID, data->hdr); 1621 1622 rcu_read_lock(); 1623 1624 ar = ath11k_mac_get_ar_by_pdev_id(ab, pdev_id); 1625 if (!ar) { 1626 ath11k_warn(ab, "invalid pdev id %d on htt pktlog\n", pdev_id); 1627 goto out; 1628 } 1629 1630 trace_ath11k_htt_pktlog(ar, data->payload, hdr->size, 1631 ar->ab->pktlog_defs_checksum); 1632 1633 out: 1634 rcu_read_unlock(); 1635 } 1636 1637 static void ath11k_htt_backpressure_event_handler(struct ath11k_base *ab, 1638 struct sk_buff *skb) 1639 { 1640 u32 *data = (u32 *)skb->data; 1641 u8 pdev_id, ring_type, ring_id, pdev_idx; 1642 u16 hp, tp; 1643 u32 backpressure_time; 1644 struct ath11k_bp_stats *bp_stats; 1645 1646 pdev_id = FIELD_GET(HTT_BACKPRESSURE_EVENT_PDEV_ID_M, *data); 1647 ring_type = FIELD_GET(HTT_BACKPRESSURE_EVENT_RING_TYPE_M, *data); 1648 ring_id = FIELD_GET(HTT_BACKPRESSURE_EVENT_RING_ID_M, *data); 1649 ++data; 1650 1651 hp = FIELD_GET(HTT_BACKPRESSURE_EVENT_HP_M, *data); 1652 tp = FIELD_GET(HTT_BACKPRESSURE_EVENT_TP_M, *data); 1653 ++data; 1654 1655 backpressure_time = *data; 1656 1657 ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "backpressure event, pdev %d, ring type %d,ring id %d, hp %d tp %d, backpressure time %d\n", 1658 pdev_id, ring_type, ring_id, hp, tp, backpressure_time); 1659 1660 if (ring_type == HTT_BACKPRESSURE_UMAC_RING_TYPE) { 1661 if (ring_id >= HTT_SW_UMAC_RING_IDX_MAX) 1662 return; 1663 1664 bp_stats = &ab->soc_stats.bp_stats.umac_ring_bp_stats[ring_id]; 1665 } else if (ring_type == HTT_BACKPRESSURE_LMAC_RING_TYPE) { 1666 pdev_idx = DP_HW2SW_MACID(pdev_id); 1667 1668 if (ring_id >= HTT_SW_LMAC_RING_IDX_MAX || pdev_idx >= MAX_RADIOS) 1669 return; 1670 1671 bp_stats = &ab->soc_stats.bp_stats.lmac_ring_bp_stats[ring_id][pdev_idx]; 1672 } else { 1673 ath11k_warn(ab, "unknown ring type received in htt bp event %d\n", 1674 ring_type); 1675 return; 1676 } 1677 1678 spin_lock_bh(&ab->base_lock); 1679 bp_stats->hp = hp; 1680 bp_stats->tp = tp; 1681 bp_stats->count++; 1682 bp_stats->jiffies = jiffies; 1683 spin_unlock_bh(&ab->base_lock); 1684 } 1685 1686 void ath11k_dp_htt_htc_t2h_msg_handler(struct ath11k_base *ab, 1687 struct sk_buff *skb) 1688 { 1689 struct ath11k_dp *dp = &ab->dp; 1690 struct htt_resp_msg *resp = (struct htt_resp_msg *)skb->data; 1691 enum htt_t2h_msg_type type = FIELD_GET(HTT_T2H_MSG_TYPE, *(u32 *)resp); 1692 u16 peer_id; 1693 u8 vdev_id; 1694 u8 mac_addr[ETH_ALEN]; 1695 u16 peer_mac_h16; 1696 u16 ast_hash; 1697 u16 hw_peer_id; 1698 1699 ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "dp_htt rx msg type :0x%0x\n", type); 1700 1701 switch (type) { 1702 case HTT_T2H_MSG_TYPE_VERSION_CONF: 1703 dp->htt_tgt_ver_major = FIELD_GET(HTT_T2H_VERSION_CONF_MAJOR, 1704 resp->version_msg.version); 1705 dp->htt_tgt_ver_minor = FIELD_GET(HTT_T2H_VERSION_CONF_MINOR, 1706 resp->version_msg.version); 1707 complete(&dp->htt_tgt_version_received); 1708 break; 1709 case HTT_T2H_MSG_TYPE_PEER_MAP: 1710 vdev_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_VDEV_ID, 1711 resp->peer_map_ev.info); 1712 peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_PEER_ID, 1713 resp->peer_map_ev.info); 1714 peer_mac_h16 = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16, 1715 resp->peer_map_ev.info1); 1716 ath11k_dp_get_mac_addr(resp->peer_map_ev.mac_addr_l32, 1717 peer_mac_h16, mac_addr); 1718 ath11k_peer_map_event(ab, vdev_id, peer_id, mac_addr, 0, 0); 1719 break; 1720 case HTT_T2H_MSG_TYPE_PEER_MAP2: 1721 vdev_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_VDEV_ID, 1722 resp->peer_map_ev.info); 1723 peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_PEER_ID, 1724 resp->peer_map_ev.info); 1725 peer_mac_h16 = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16, 1726 resp->peer_map_ev.info1); 1727 ath11k_dp_get_mac_addr(resp->peer_map_ev.mac_addr_l32, 1728 peer_mac_h16, mac_addr); 1729 ast_hash = FIELD_GET(HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL, 1730 resp->peer_map_ev.info2); 1731 hw_peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID, 1732 resp->peer_map_ev.info1); 1733 ath11k_peer_map_event(ab, vdev_id, peer_id, mac_addr, ast_hash, 1734 hw_peer_id); 1735 break; 1736 case HTT_T2H_MSG_TYPE_PEER_UNMAP: 1737 case HTT_T2H_MSG_TYPE_PEER_UNMAP2: 1738 peer_id = FIELD_GET(HTT_T2H_PEER_UNMAP_INFO_PEER_ID, 1739 resp->peer_unmap_ev.info); 1740 ath11k_peer_unmap_event(ab, peer_id); 1741 break; 1742 case HTT_T2H_MSG_TYPE_PPDU_STATS_IND: 1743 ath11k_htt_pull_ppdu_stats(ab, skb); 1744 break; 1745 case HTT_T2H_MSG_TYPE_EXT_STATS_CONF: 1746 ath11k_debugfs_htt_ext_stats_handler(ab, skb); 1747 break; 1748 case HTT_T2H_MSG_TYPE_PKTLOG: 1749 ath11k_htt_pktlog(ab, skb); 1750 break; 1751 case HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND: 1752 ath11k_htt_backpressure_event_handler(ab, skb); 1753 break; 1754 default: 1755 ath11k_warn(ab, "htt event %d not handled\n", type); 1756 break; 1757 } 1758 1759 dev_kfree_skb_any(skb); 1760 } 1761 1762 static int ath11k_dp_rx_msdu_coalesce(struct ath11k *ar, 1763 struct sk_buff_head *msdu_list, 1764 struct sk_buff *first, struct sk_buff *last, 1765 u8 l3pad_bytes, int msdu_len) 1766 { 1767 struct ath11k_base *ab = ar->ab; 1768 struct sk_buff *skb; 1769 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(first); 1770 int buf_first_hdr_len, buf_first_len; 1771 struct hal_rx_desc *ldesc; 1772 int space_extra, rem_len, buf_len; 1773 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz; 1774 1775 /* As the msdu is spread across multiple rx buffers, 1776 * find the offset to the start of msdu for computing 1777 * the length of the msdu in the first buffer. 1778 */ 1779 buf_first_hdr_len = hal_rx_desc_sz + l3pad_bytes; 1780 buf_first_len = DP_RX_BUFFER_SIZE - buf_first_hdr_len; 1781 1782 if (WARN_ON_ONCE(msdu_len <= buf_first_len)) { 1783 skb_put(first, buf_first_hdr_len + msdu_len); 1784 skb_pull(first, buf_first_hdr_len); 1785 return 0; 1786 } 1787 1788 ldesc = (struct hal_rx_desc *)last->data; 1789 rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ab, ldesc); 1790 rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ab, ldesc); 1791 1792 /* MSDU spans over multiple buffers because the length of the MSDU 1793 * exceeds DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. So assume the data 1794 * in the first buf is of length DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. 1795 */ 1796 skb_put(first, DP_RX_BUFFER_SIZE); 1797 skb_pull(first, buf_first_hdr_len); 1798 1799 /* When an MSDU spread over multiple buffers attention, MSDU_END and 1800 * MPDU_END tlvs are valid only in the last buffer. Copy those tlvs. 1801 */ 1802 ath11k_dp_rx_desc_end_tlv_copy(ab, rxcb->rx_desc, ldesc); 1803 1804 space_extra = msdu_len - (buf_first_len + skb_tailroom(first)); 1805 if (space_extra > 0 && 1806 (pskb_expand_head(first, 0, space_extra, GFP_ATOMIC) < 0)) { 1807 /* Free up all buffers of the MSDU */ 1808 while ((skb = __skb_dequeue(msdu_list)) != NULL) { 1809 rxcb = ATH11K_SKB_RXCB(skb); 1810 if (!rxcb->is_continuation) { 1811 dev_kfree_skb_any(skb); 1812 break; 1813 } 1814 dev_kfree_skb_any(skb); 1815 } 1816 return -ENOMEM; 1817 } 1818 1819 rem_len = msdu_len - buf_first_len; 1820 while ((skb = __skb_dequeue(msdu_list)) != NULL && rem_len > 0) { 1821 rxcb = ATH11K_SKB_RXCB(skb); 1822 if (rxcb->is_continuation) 1823 buf_len = DP_RX_BUFFER_SIZE - hal_rx_desc_sz; 1824 else 1825 buf_len = rem_len; 1826 1827 if (buf_len > (DP_RX_BUFFER_SIZE - hal_rx_desc_sz)) { 1828 WARN_ON_ONCE(1); 1829 dev_kfree_skb_any(skb); 1830 return -EINVAL; 1831 } 1832 1833 skb_put(skb, buf_len + hal_rx_desc_sz); 1834 skb_pull(skb, hal_rx_desc_sz); 1835 skb_copy_from_linear_data(skb, skb_put(first, buf_len), 1836 buf_len); 1837 dev_kfree_skb_any(skb); 1838 1839 rem_len -= buf_len; 1840 if (!rxcb->is_continuation) 1841 break; 1842 } 1843 1844 return 0; 1845 } 1846 1847 static struct sk_buff *ath11k_dp_rx_get_msdu_last_buf(struct sk_buff_head *msdu_list, 1848 struct sk_buff *first) 1849 { 1850 struct sk_buff *skb; 1851 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(first); 1852 1853 if (!rxcb->is_continuation) 1854 return first; 1855 1856 skb_queue_walk(msdu_list, skb) { 1857 rxcb = ATH11K_SKB_RXCB(skb); 1858 if (!rxcb->is_continuation) 1859 return skb; 1860 } 1861 1862 return NULL; 1863 } 1864 1865 static void ath11k_dp_rx_h_csum_offload(struct ath11k *ar, struct sk_buff *msdu) 1866 { 1867 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 1868 struct rx_attention *rx_attention; 1869 bool ip_csum_fail, l4_csum_fail; 1870 1871 rx_attention = ath11k_dp_rx_get_attention(ar->ab, rxcb->rx_desc); 1872 ip_csum_fail = ath11k_dp_rx_h_attn_ip_cksum_fail(rx_attention); 1873 l4_csum_fail = ath11k_dp_rx_h_attn_l4_cksum_fail(rx_attention); 1874 1875 msdu->ip_summed = (ip_csum_fail || l4_csum_fail) ? 1876 CHECKSUM_NONE : CHECKSUM_UNNECESSARY; 1877 } 1878 1879 static int ath11k_dp_rx_crypto_mic_len(struct ath11k *ar, 1880 enum hal_encrypt_type enctype) 1881 { 1882 switch (enctype) { 1883 case HAL_ENCRYPT_TYPE_OPEN: 1884 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC: 1885 case HAL_ENCRYPT_TYPE_TKIP_MIC: 1886 return 0; 1887 case HAL_ENCRYPT_TYPE_CCMP_128: 1888 return IEEE80211_CCMP_MIC_LEN; 1889 case HAL_ENCRYPT_TYPE_CCMP_256: 1890 return IEEE80211_CCMP_256_MIC_LEN; 1891 case HAL_ENCRYPT_TYPE_GCMP_128: 1892 case HAL_ENCRYPT_TYPE_AES_GCMP_256: 1893 return IEEE80211_GCMP_MIC_LEN; 1894 case HAL_ENCRYPT_TYPE_WEP_40: 1895 case HAL_ENCRYPT_TYPE_WEP_104: 1896 case HAL_ENCRYPT_TYPE_WEP_128: 1897 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4: 1898 case HAL_ENCRYPT_TYPE_WAPI: 1899 break; 1900 } 1901 1902 ath11k_warn(ar->ab, "unsupported encryption type %d for mic len\n", enctype); 1903 return 0; 1904 } 1905 1906 static int ath11k_dp_rx_crypto_param_len(struct ath11k *ar, 1907 enum hal_encrypt_type enctype) 1908 { 1909 switch (enctype) { 1910 case HAL_ENCRYPT_TYPE_OPEN: 1911 return 0; 1912 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC: 1913 case HAL_ENCRYPT_TYPE_TKIP_MIC: 1914 return IEEE80211_TKIP_IV_LEN; 1915 case HAL_ENCRYPT_TYPE_CCMP_128: 1916 return IEEE80211_CCMP_HDR_LEN; 1917 case HAL_ENCRYPT_TYPE_CCMP_256: 1918 return IEEE80211_CCMP_256_HDR_LEN; 1919 case HAL_ENCRYPT_TYPE_GCMP_128: 1920 case HAL_ENCRYPT_TYPE_AES_GCMP_256: 1921 return IEEE80211_GCMP_HDR_LEN; 1922 case HAL_ENCRYPT_TYPE_WEP_40: 1923 case HAL_ENCRYPT_TYPE_WEP_104: 1924 case HAL_ENCRYPT_TYPE_WEP_128: 1925 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4: 1926 case HAL_ENCRYPT_TYPE_WAPI: 1927 break; 1928 } 1929 1930 ath11k_warn(ar->ab, "unsupported encryption type %d\n", enctype); 1931 return 0; 1932 } 1933 1934 static int ath11k_dp_rx_crypto_icv_len(struct ath11k *ar, 1935 enum hal_encrypt_type enctype) 1936 { 1937 switch (enctype) { 1938 case HAL_ENCRYPT_TYPE_OPEN: 1939 case HAL_ENCRYPT_TYPE_CCMP_128: 1940 case HAL_ENCRYPT_TYPE_CCMP_256: 1941 case HAL_ENCRYPT_TYPE_GCMP_128: 1942 case HAL_ENCRYPT_TYPE_AES_GCMP_256: 1943 return 0; 1944 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC: 1945 case HAL_ENCRYPT_TYPE_TKIP_MIC: 1946 return IEEE80211_TKIP_ICV_LEN; 1947 case HAL_ENCRYPT_TYPE_WEP_40: 1948 case HAL_ENCRYPT_TYPE_WEP_104: 1949 case HAL_ENCRYPT_TYPE_WEP_128: 1950 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4: 1951 case HAL_ENCRYPT_TYPE_WAPI: 1952 break; 1953 } 1954 1955 ath11k_warn(ar->ab, "unsupported encryption type %d\n", enctype); 1956 return 0; 1957 } 1958 1959 static void ath11k_dp_rx_h_undecap_nwifi(struct ath11k *ar, 1960 struct sk_buff *msdu, 1961 u8 *first_hdr, 1962 enum hal_encrypt_type enctype, 1963 struct ieee80211_rx_status *status) 1964 { 1965 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 1966 u8 decap_hdr[DP_MAX_NWIFI_HDR_LEN]; 1967 struct ieee80211_hdr *hdr; 1968 size_t hdr_len; 1969 u8 da[ETH_ALEN]; 1970 u8 sa[ETH_ALEN]; 1971 u16 qos_ctl = 0; 1972 u8 *qos; 1973 1974 /* copy SA & DA and pull decapped header */ 1975 hdr = (struct ieee80211_hdr *)msdu->data; 1976 hdr_len = ieee80211_hdrlen(hdr->frame_control); 1977 ether_addr_copy(da, ieee80211_get_DA(hdr)); 1978 ether_addr_copy(sa, ieee80211_get_SA(hdr)); 1979 skb_pull(msdu, ieee80211_hdrlen(hdr->frame_control)); 1980 1981 if (rxcb->is_first_msdu) { 1982 /* original 802.11 header is valid for the first msdu 1983 * hence we can reuse the same header 1984 */ 1985 hdr = (struct ieee80211_hdr *)first_hdr; 1986 hdr_len = ieee80211_hdrlen(hdr->frame_control); 1987 1988 /* Each A-MSDU subframe will be reported as a separate MSDU, 1989 * so strip the A-MSDU bit from QoS Ctl. 1990 */ 1991 if (ieee80211_is_data_qos(hdr->frame_control)) { 1992 qos = ieee80211_get_qos_ctl(hdr); 1993 qos[0] &= ~IEEE80211_QOS_CTL_A_MSDU_PRESENT; 1994 } 1995 } else { 1996 /* Rebuild qos header if this is a middle/last msdu */ 1997 hdr->frame_control |= __cpu_to_le16(IEEE80211_STYPE_QOS_DATA); 1998 1999 /* Reset the order bit as the HT_Control header is stripped */ 2000 hdr->frame_control &= ~(__cpu_to_le16(IEEE80211_FCTL_ORDER)); 2001 2002 qos_ctl = rxcb->tid; 2003 2004 if (ath11k_dp_rx_h_msdu_start_mesh_ctl_present(ar->ab, rxcb->rx_desc)) 2005 qos_ctl |= IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT; 2006 2007 /* TODO Add other QoS ctl fields when required */ 2008 2009 /* copy decap header before overwriting for reuse below */ 2010 memcpy(decap_hdr, (uint8_t *)hdr, hdr_len); 2011 } 2012 2013 if (!(status->flag & RX_FLAG_IV_STRIPPED)) { 2014 memcpy(skb_push(msdu, 2015 ath11k_dp_rx_crypto_param_len(ar, enctype)), 2016 (void *)hdr + hdr_len, 2017 ath11k_dp_rx_crypto_param_len(ar, enctype)); 2018 } 2019 2020 if (!rxcb->is_first_msdu) { 2021 memcpy(skb_push(msdu, 2022 IEEE80211_QOS_CTL_LEN), &qos_ctl, 2023 IEEE80211_QOS_CTL_LEN); 2024 memcpy(skb_push(msdu, hdr_len), decap_hdr, hdr_len); 2025 return; 2026 } 2027 2028 memcpy(skb_push(msdu, hdr_len), hdr, hdr_len); 2029 2030 /* original 802.11 header has a different DA and in 2031 * case of 4addr it may also have different SA 2032 */ 2033 hdr = (struct ieee80211_hdr *)msdu->data; 2034 ether_addr_copy(ieee80211_get_DA(hdr), da); 2035 ether_addr_copy(ieee80211_get_SA(hdr), sa); 2036 } 2037 2038 static void ath11k_dp_rx_h_undecap_raw(struct ath11k *ar, struct sk_buff *msdu, 2039 enum hal_encrypt_type enctype, 2040 struct ieee80211_rx_status *status, 2041 bool decrypted) 2042 { 2043 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 2044 struct ieee80211_hdr *hdr; 2045 size_t hdr_len; 2046 size_t crypto_len; 2047 2048 if (!rxcb->is_first_msdu || 2049 !(rxcb->is_first_msdu && rxcb->is_last_msdu)) { 2050 WARN_ON_ONCE(1); 2051 return; 2052 } 2053 2054 skb_trim(msdu, msdu->len - FCS_LEN); 2055 2056 if (!decrypted) 2057 return; 2058 2059 hdr = (void *)msdu->data; 2060 2061 /* Tail */ 2062 if (status->flag & RX_FLAG_IV_STRIPPED) { 2063 skb_trim(msdu, msdu->len - 2064 ath11k_dp_rx_crypto_mic_len(ar, enctype)); 2065 2066 skb_trim(msdu, msdu->len - 2067 ath11k_dp_rx_crypto_icv_len(ar, enctype)); 2068 } else { 2069 /* MIC */ 2070 if (status->flag & RX_FLAG_MIC_STRIPPED) 2071 skb_trim(msdu, msdu->len - 2072 ath11k_dp_rx_crypto_mic_len(ar, enctype)); 2073 2074 /* ICV */ 2075 if (status->flag & RX_FLAG_ICV_STRIPPED) 2076 skb_trim(msdu, msdu->len - 2077 ath11k_dp_rx_crypto_icv_len(ar, enctype)); 2078 } 2079 2080 /* MMIC */ 2081 if ((status->flag & RX_FLAG_MMIC_STRIPPED) && 2082 !ieee80211_has_morefrags(hdr->frame_control) && 2083 enctype == HAL_ENCRYPT_TYPE_TKIP_MIC) 2084 skb_trim(msdu, msdu->len - IEEE80211_CCMP_MIC_LEN); 2085 2086 /* Head */ 2087 if (status->flag & RX_FLAG_IV_STRIPPED) { 2088 hdr_len = ieee80211_hdrlen(hdr->frame_control); 2089 crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype); 2090 2091 memmove((void *)msdu->data + crypto_len, 2092 (void *)msdu->data, hdr_len); 2093 skb_pull(msdu, crypto_len); 2094 } 2095 } 2096 2097 static void *ath11k_dp_rx_h_find_rfc1042(struct ath11k *ar, 2098 struct sk_buff *msdu, 2099 enum hal_encrypt_type enctype) 2100 { 2101 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 2102 struct ieee80211_hdr *hdr; 2103 size_t hdr_len, crypto_len; 2104 void *rfc1042; 2105 bool is_amsdu; 2106 2107 is_amsdu = !(rxcb->is_first_msdu && rxcb->is_last_msdu); 2108 hdr = (struct ieee80211_hdr *)ath11k_dp_rx_h_80211_hdr(ar->ab, rxcb->rx_desc); 2109 rfc1042 = hdr; 2110 2111 if (rxcb->is_first_msdu) { 2112 hdr_len = ieee80211_hdrlen(hdr->frame_control); 2113 crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype); 2114 2115 rfc1042 += hdr_len + crypto_len; 2116 } 2117 2118 if (is_amsdu) 2119 rfc1042 += sizeof(struct ath11k_dp_amsdu_subframe_hdr); 2120 2121 return rfc1042; 2122 } 2123 2124 static void ath11k_dp_rx_h_undecap_eth(struct ath11k *ar, 2125 struct sk_buff *msdu, 2126 u8 *first_hdr, 2127 enum hal_encrypt_type enctype, 2128 struct ieee80211_rx_status *status) 2129 { 2130 struct ieee80211_hdr *hdr; 2131 struct ethhdr *eth; 2132 size_t hdr_len; 2133 u8 da[ETH_ALEN]; 2134 u8 sa[ETH_ALEN]; 2135 void *rfc1042; 2136 2137 rfc1042 = ath11k_dp_rx_h_find_rfc1042(ar, msdu, enctype); 2138 if (WARN_ON_ONCE(!rfc1042)) 2139 return; 2140 2141 /* pull decapped header and copy SA & DA */ 2142 eth = (struct ethhdr *)msdu->data; 2143 ether_addr_copy(da, eth->h_dest); 2144 ether_addr_copy(sa, eth->h_source); 2145 skb_pull(msdu, sizeof(struct ethhdr)); 2146 2147 /* push rfc1042/llc/snap */ 2148 memcpy(skb_push(msdu, sizeof(struct ath11k_dp_rfc1042_hdr)), rfc1042, 2149 sizeof(struct ath11k_dp_rfc1042_hdr)); 2150 2151 /* push original 802.11 header */ 2152 hdr = (struct ieee80211_hdr *)first_hdr; 2153 hdr_len = ieee80211_hdrlen(hdr->frame_control); 2154 2155 if (!(status->flag & RX_FLAG_IV_STRIPPED)) { 2156 memcpy(skb_push(msdu, 2157 ath11k_dp_rx_crypto_param_len(ar, enctype)), 2158 (void *)hdr + hdr_len, 2159 ath11k_dp_rx_crypto_param_len(ar, enctype)); 2160 } 2161 2162 memcpy(skb_push(msdu, hdr_len), hdr, hdr_len); 2163 2164 /* original 802.11 header has a different DA and in 2165 * case of 4addr it may also have different SA 2166 */ 2167 hdr = (struct ieee80211_hdr *)msdu->data; 2168 ether_addr_copy(ieee80211_get_DA(hdr), da); 2169 ether_addr_copy(ieee80211_get_SA(hdr), sa); 2170 } 2171 2172 static void ath11k_dp_rx_h_undecap(struct ath11k *ar, struct sk_buff *msdu, 2173 struct hal_rx_desc *rx_desc, 2174 enum hal_encrypt_type enctype, 2175 struct ieee80211_rx_status *status, 2176 bool decrypted) 2177 { 2178 u8 *first_hdr; 2179 u8 decap; 2180 struct ethhdr *ehdr; 2181 2182 first_hdr = ath11k_dp_rx_h_80211_hdr(ar->ab, rx_desc); 2183 decap = ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rx_desc); 2184 2185 switch (decap) { 2186 case DP_RX_DECAP_TYPE_NATIVE_WIFI: 2187 ath11k_dp_rx_h_undecap_nwifi(ar, msdu, first_hdr, 2188 enctype, status); 2189 break; 2190 case DP_RX_DECAP_TYPE_RAW: 2191 ath11k_dp_rx_h_undecap_raw(ar, msdu, enctype, status, 2192 decrypted); 2193 break; 2194 case DP_RX_DECAP_TYPE_ETHERNET2_DIX: 2195 ehdr = (struct ethhdr *)msdu->data; 2196 2197 /* mac80211 allows fast path only for authorized STA */ 2198 if (ehdr->h_proto == cpu_to_be16(ETH_P_PAE)) { 2199 ATH11K_SKB_RXCB(msdu)->is_eapol = true; 2200 ath11k_dp_rx_h_undecap_eth(ar, msdu, first_hdr, 2201 enctype, status); 2202 break; 2203 } 2204 2205 /* PN for mcast packets will be validated in mac80211; 2206 * remove eth header and add 802.11 header. 2207 */ 2208 if (ATH11K_SKB_RXCB(msdu)->is_mcbc && decrypted) 2209 ath11k_dp_rx_h_undecap_eth(ar, msdu, first_hdr, 2210 enctype, status); 2211 break; 2212 case DP_RX_DECAP_TYPE_8023: 2213 /* TODO: Handle undecap for these formats */ 2214 break; 2215 } 2216 } 2217 2218 static struct ath11k_peer * 2219 ath11k_dp_rx_h_find_peer(struct ath11k_base *ab, struct sk_buff *msdu) 2220 { 2221 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 2222 struct hal_rx_desc *rx_desc = rxcb->rx_desc; 2223 struct ath11k_peer *peer = NULL; 2224 2225 lockdep_assert_held(&ab->base_lock); 2226 2227 if (rxcb->peer_id) 2228 peer = ath11k_peer_find_by_id(ab, rxcb->peer_id); 2229 2230 if (peer) 2231 return peer; 2232 2233 if (!rx_desc || !(ath11k_dp_rxdesc_mac_addr2_valid(ab, rx_desc))) 2234 return NULL; 2235 2236 peer = ath11k_peer_find_by_addr(ab, 2237 ath11k_dp_rxdesc_mpdu_start_addr2(ab, rx_desc)); 2238 return peer; 2239 } 2240 2241 static void ath11k_dp_rx_h_mpdu(struct ath11k *ar, 2242 struct sk_buff *msdu, 2243 struct hal_rx_desc *rx_desc, 2244 struct ieee80211_rx_status *rx_status) 2245 { 2246 bool fill_crypto_hdr; 2247 enum hal_encrypt_type enctype; 2248 bool is_decrypted = false; 2249 struct ath11k_skb_rxcb *rxcb; 2250 struct ieee80211_hdr *hdr; 2251 struct ath11k_peer *peer; 2252 struct rx_attention *rx_attention; 2253 u32 err_bitmap; 2254 2255 /* PN for multicast packets will be checked in mac80211 */ 2256 rxcb = ATH11K_SKB_RXCB(msdu); 2257 fill_crypto_hdr = ath11k_dp_rx_h_attn_is_mcbc(ar->ab, rx_desc); 2258 rxcb->is_mcbc = fill_crypto_hdr; 2259 2260 if (rxcb->is_mcbc) { 2261 rxcb->peer_id = ath11k_dp_rx_h_mpdu_start_peer_id(ar->ab, rx_desc); 2262 rxcb->seq_no = ath11k_dp_rx_h_mpdu_start_seq_no(ar->ab, rx_desc); 2263 } 2264 2265 spin_lock_bh(&ar->ab->base_lock); 2266 peer = ath11k_dp_rx_h_find_peer(ar->ab, msdu); 2267 if (peer) { 2268 if (rxcb->is_mcbc) 2269 enctype = peer->sec_type_grp; 2270 else 2271 enctype = peer->sec_type; 2272 } else { 2273 enctype = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc); 2274 } 2275 spin_unlock_bh(&ar->ab->base_lock); 2276 2277 rx_attention = ath11k_dp_rx_get_attention(ar->ab, rx_desc); 2278 err_bitmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention); 2279 if (enctype != HAL_ENCRYPT_TYPE_OPEN && !err_bitmap) 2280 is_decrypted = ath11k_dp_rx_h_attn_is_decrypted(rx_attention); 2281 2282 /* Clear per-MPDU flags while leaving per-PPDU flags intact */ 2283 rx_status->flag &= ~(RX_FLAG_FAILED_FCS_CRC | 2284 RX_FLAG_MMIC_ERROR | 2285 RX_FLAG_DECRYPTED | 2286 RX_FLAG_IV_STRIPPED | 2287 RX_FLAG_MMIC_STRIPPED); 2288 2289 if (err_bitmap & DP_RX_MPDU_ERR_FCS) 2290 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 2291 if (err_bitmap & DP_RX_MPDU_ERR_TKIP_MIC) 2292 rx_status->flag |= RX_FLAG_MMIC_ERROR; 2293 2294 if (is_decrypted) { 2295 rx_status->flag |= RX_FLAG_DECRYPTED | RX_FLAG_MMIC_STRIPPED; 2296 2297 if (fill_crypto_hdr) 2298 rx_status->flag |= RX_FLAG_MIC_STRIPPED | 2299 RX_FLAG_ICV_STRIPPED; 2300 else 2301 rx_status->flag |= RX_FLAG_IV_STRIPPED | 2302 RX_FLAG_PN_VALIDATED; 2303 } 2304 2305 ath11k_dp_rx_h_csum_offload(ar, msdu); 2306 ath11k_dp_rx_h_undecap(ar, msdu, rx_desc, 2307 enctype, rx_status, is_decrypted); 2308 2309 if (!is_decrypted || fill_crypto_hdr) 2310 return; 2311 2312 if (ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rx_desc) != 2313 DP_RX_DECAP_TYPE_ETHERNET2_DIX) { 2314 hdr = (void *)msdu->data; 2315 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_PROTECTED); 2316 } 2317 } 2318 2319 static void ath11k_dp_rx_h_rate(struct ath11k *ar, struct hal_rx_desc *rx_desc, 2320 struct ieee80211_rx_status *rx_status) 2321 { 2322 struct ieee80211_supported_band *sband; 2323 enum rx_msdu_start_pkt_type pkt_type; 2324 u8 bw; 2325 u8 rate_mcs, nss; 2326 u8 sgi; 2327 bool is_cck, is_ldpc; 2328 2329 pkt_type = ath11k_dp_rx_h_msdu_start_pkt_type(ar->ab, rx_desc); 2330 bw = ath11k_dp_rx_h_msdu_start_rx_bw(ar->ab, rx_desc); 2331 rate_mcs = ath11k_dp_rx_h_msdu_start_rate_mcs(ar->ab, rx_desc); 2332 nss = ath11k_dp_rx_h_msdu_start_nss(ar->ab, rx_desc); 2333 sgi = ath11k_dp_rx_h_msdu_start_sgi(ar->ab, rx_desc); 2334 2335 switch (pkt_type) { 2336 case RX_MSDU_START_PKT_TYPE_11A: 2337 case RX_MSDU_START_PKT_TYPE_11B: 2338 is_cck = (pkt_type == RX_MSDU_START_PKT_TYPE_11B); 2339 sband = &ar->mac.sbands[rx_status->band]; 2340 rx_status->rate_idx = ath11k_mac_hw_rate_to_idx(sband, rate_mcs, 2341 is_cck); 2342 break; 2343 case RX_MSDU_START_PKT_TYPE_11N: 2344 rx_status->encoding = RX_ENC_HT; 2345 if (rate_mcs > ATH11K_HT_MCS_MAX) { 2346 ath11k_warn(ar->ab, 2347 "Received with invalid mcs in HT mode %d\n", 2348 rate_mcs); 2349 break; 2350 } 2351 rx_status->rate_idx = rate_mcs + (8 * (nss - 1)); 2352 if (sgi) 2353 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 2354 rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw); 2355 break; 2356 case RX_MSDU_START_PKT_TYPE_11AC: 2357 rx_status->encoding = RX_ENC_VHT; 2358 rx_status->rate_idx = rate_mcs; 2359 if (rate_mcs > ATH11K_VHT_MCS_MAX) { 2360 ath11k_warn(ar->ab, 2361 "Received with invalid mcs in VHT mode %d\n", 2362 rate_mcs); 2363 break; 2364 } 2365 rx_status->nss = nss; 2366 if (sgi) 2367 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 2368 rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw); 2369 is_ldpc = ath11k_dp_rx_h_msdu_start_ldpc_support(ar->ab, rx_desc); 2370 if (is_ldpc) 2371 rx_status->enc_flags |= RX_ENC_FLAG_LDPC; 2372 break; 2373 case RX_MSDU_START_PKT_TYPE_11AX: 2374 rx_status->rate_idx = rate_mcs; 2375 if (rate_mcs > ATH11K_HE_MCS_MAX) { 2376 ath11k_warn(ar->ab, 2377 "Received with invalid mcs in HE mode %d\n", 2378 rate_mcs); 2379 break; 2380 } 2381 rx_status->encoding = RX_ENC_HE; 2382 rx_status->nss = nss; 2383 rx_status->he_gi = ath11k_mac_he_gi_to_nl80211_he_gi(sgi); 2384 rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw); 2385 break; 2386 } 2387 } 2388 2389 static void ath11k_dp_rx_h_ppdu(struct ath11k *ar, struct hal_rx_desc *rx_desc, 2390 struct ieee80211_rx_status *rx_status) 2391 { 2392 u8 channel_num; 2393 u32 center_freq, meta_data; 2394 struct ieee80211_channel *channel; 2395 2396 rx_status->freq = 0; 2397 rx_status->rate_idx = 0; 2398 rx_status->nss = 0; 2399 rx_status->encoding = RX_ENC_LEGACY; 2400 rx_status->bw = RATE_INFO_BW_20; 2401 2402 rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL; 2403 2404 meta_data = ath11k_dp_rx_h_msdu_start_freq(ar->ab, rx_desc); 2405 channel_num = meta_data; 2406 center_freq = meta_data >> 16; 2407 2408 if (center_freq >= ATH11K_MIN_6G_FREQ && 2409 center_freq <= ATH11K_MAX_6G_FREQ) { 2410 rx_status->band = NL80211_BAND_6GHZ; 2411 rx_status->freq = center_freq; 2412 } else if (channel_num >= 1 && channel_num <= 14) { 2413 rx_status->band = NL80211_BAND_2GHZ; 2414 } else if (channel_num >= 36 && channel_num <= 177) { 2415 rx_status->band = NL80211_BAND_5GHZ; 2416 } else { 2417 spin_lock_bh(&ar->data_lock); 2418 channel = ar->rx_channel; 2419 if (channel) { 2420 rx_status->band = channel->band; 2421 channel_num = 2422 ieee80211_frequency_to_channel(channel->center_freq); 2423 } 2424 spin_unlock_bh(&ar->data_lock); 2425 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "rx_desc: ", 2426 rx_desc, sizeof(struct hal_rx_desc)); 2427 } 2428 2429 if (rx_status->band != NL80211_BAND_6GHZ) 2430 rx_status->freq = ieee80211_channel_to_frequency(channel_num, 2431 rx_status->band); 2432 2433 ath11k_dp_rx_h_rate(ar, rx_desc, rx_status); 2434 } 2435 2436 static void ath11k_dp_rx_deliver_msdu(struct ath11k *ar, struct napi_struct *napi, 2437 struct sk_buff *msdu, 2438 struct ieee80211_rx_status *status) 2439 { 2440 static const struct ieee80211_radiotap_he known = { 2441 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN | 2442 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN), 2443 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN), 2444 }; 2445 struct ieee80211_rx_status *rx_status; 2446 struct ieee80211_radiotap_he *he = NULL; 2447 struct ieee80211_sta *pubsta = NULL; 2448 struct ath11k_peer *peer; 2449 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 2450 u8 decap = DP_RX_DECAP_TYPE_RAW; 2451 bool is_mcbc = rxcb->is_mcbc; 2452 bool is_eapol = rxcb->is_eapol; 2453 2454 if (status->encoding == RX_ENC_HE && 2455 !(status->flag & RX_FLAG_RADIOTAP_HE) && 2456 !(status->flag & RX_FLAG_SKIP_MONITOR)) { 2457 he = skb_push(msdu, sizeof(known)); 2458 memcpy(he, &known, sizeof(known)); 2459 status->flag |= RX_FLAG_RADIOTAP_HE; 2460 } 2461 2462 if (!(status->flag & RX_FLAG_ONLY_MONITOR)) 2463 decap = ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rxcb->rx_desc); 2464 2465 spin_lock_bh(&ar->ab->base_lock); 2466 peer = ath11k_dp_rx_h_find_peer(ar->ab, msdu); 2467 if (peer && peer->sta) 2468 pubsta = peer->sta; 2469 spin_unlock_bh(&ar->ab->base_lock); 2470 2471 ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 2472 "rx skb %p len %u peer %pM %d %s sn %u %s%s%s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n", 2473 msdu, 2474 msdu->len, 2475 peer ? peer->addr : NULL, 2476 rxcb->tid, 2477 is_mcbc ? "mcast" : "ucast", 2478 rxcb->seq_no, 2479 (status->encoding == RX_ENC_LEGACY) ? "legacy" : "", 2480 (status->encoding == RX_ENC_HT) ? "ht" : "", 2481 (status->encoding == RX_ENC_VHT) ? "vht" : "", 2482 (status->encoding == RX_ENC_HE) ? "he" : "", 2483 (status->bw == RATE_INFO_BW_40) ? "40" : "", 2484 (status->bw == RATE_INFO_BW_80) ? "80" : "", 2485 (status->bw == RATE_INFO_BW_160) ? "160" : "", 2486 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? "sgi " : "", 2487 status->rate_idx, 2488 status->nss, 2489 status->freq, 2490 status->band, status->flag, 2491 !!(status->flag & RX_FLAG_FAILED_FCS_CRC), 2492 !!(status->flag & RX_FLAG_MMIC_ERROR), 2493 !!(status->flag & RX_FLAG_AMSDU_MORE)); 2494 2495 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DP_RX, NULL, "dp rx msdu: ", 2496 msdu->data, msdu->len); 2497 2498 rx_status = IEEE80211_SKB_RXCB(msdu); 2499 *rx_status = *status; 2500 2501 /* TODO: trace rx packet */ 2502 2503 /* PN for multicast packets are not validate in HW, 2504 * so skip 802.3 rx path 2505 * Also, fast_rx expects the STA to be authorized, hence 2506 * eapol packets are sent in slow path. 2507 */ 2508 if (decap == DP_RX_DECAP_TYPE_ETHERNET2_DIX && !is_eapol && 2509 !(is_mcbc && rx_status->flag & RX_FLAG_DECRYPTED)) 2510 rx_status->flag |= RX_FLAG_8023; 2511 2512 ieee80211_rx_napi(ar->hw, pubsta, msdu, napi); 2513 } 2514 2515 static int ath11k_dp_rx_process_msdu(struct ath11k *ar, 2516 struct sk_buff *msdu, 2517 struct sk_buff_head *msdu_list, 2518 struct ieee80211_rx_status *rx_status) 2519 { 2520 struct ath11k_base *ab = ar->ab; 2521 struct hal_rx_desc *rx_desc, *lrx_desc; 2522 struct rx_attention *rx_attention; 2523 struct ath11k_skb_rxcb *rxcb; 2524 struct sk_buff *last_buf; 2525 u8 l3_pad_bytes; 2526 u8 *hdr_status; 2527 u16 msdu_len; 2528 int ret; 2529 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz; 2530 2531 last_buf = ath11k_dp_rx_get_msdu_last_buf(msdu_list, msdu); 2532 if (!last_buf) { 2533 ath11k_warn(ab, 2534 "No valid Rx buffer to access Atten/MSDU_END/MPDU_END tlvs\n"); 2535 ret = -EIO; 2536 goto free_out; 2537 } 2538 2539 rx_desc = (struct hal_rx_desc *)msdu->data; 2540 if (ath11k_dp_rx_h_attn_msdu_len_err(ab, rx_desc)) { 2541 ath11k_warn(ar->ab, "msdu len not valid\n"); 2542 ret = -EIO; 2543 goto free_out; 2544 } 2545 2546 lrx_desc = (struct hal_rx_desc *)last_buf->data; 2547 rx_attention = ath11k_dp_rx_get_attention(ab, lrx_desc); 2548 if (!ath11k_dp_rx_h_attn_msdu_done(rx_attention)) { 2549 ath11k_warn(ab, "msdu_done bit in attention is not set\n"); 2550 ret = -EIO; 2551 goto free_out; 2552 } 2553 2554 rxcb = ATH11K_SKB_RXCB(msdu); 2555 rxcb->rx_desc = rx_desc; 2556 msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ab, rx_desc); 2557 l3_pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ab, lrx_desc); 2558 2559 if (rxcb->is_frag) { 2560 skb_pull(msdu, hal_rx_desc_sz); 2561 } else if (!rxcb->is_continuation) { 2562 if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) { 2563 hdr_status = ath11k_dp_rx_h_80211_hdr(ab, rx_desc); 2564 ret = -EINVAL; 2565 ath11k_warn(ab, "invalid msdu len %u\n", msdu_len); 2566 ath11k_dbg_dump(ab, ATH11K_DBG_DATA, NULL, "", hdr_status, 2567 sizeof(struct ieee80211_hdr)); 2568 ath11k_dbg_dump(ab, ATH11K_DBG_DATA, NULL, "", rx_desc, 2569 sizeof(struct hal_rx_desc)); 2570 goto free_out; 2571 } 2572 skb_put(msdu, hal_rx_desc_sz + l3_pad_bytes + msdu_len); 2573 skb_pull(msdu, hal_rx_desc_sz + l3_pad_bytes); 2574 } else { 2575 ret = ath11k_dp_rx_msdu_coalesce(ar, msdu_list, 2576 msdu, last_buf, 2577 l3_pad_bytes, msdu_len); 2578 if (ret) { 2579 ath11k_warn(ab, 2580 "failed to coalesce msdu rx buffer%d\n", ret); 2581 goto free_out; 2582 } 2583 } 2584 2585 ath11k_dp_rx_h_ppdu(ar, rx_desc, rx_status); 2586 ath11k_dp_rx_h_mpdu(ar, msdu, rx_desc, rx_status); 2587 2588 rx_status->flag |= RX_FLAG_SKIP_MONITOR | RX_FLAG_DUP_VALIDATED; 2589 2590 return 0; 2591 2592 free_out: 2593 return ret; 2594 } 2595 2596 static void ath11k_dp_rx_process_received_packets(struct ath11k_base *ab, 2597 struct napi_struct *napi, 2598 struct sk_buff_head *msdu_list, 2599 int mac_id) 2600 { 2601 struct sk_buff *msdu; 2602 struct ath11k *ar; 2603 struct ieee80211_rx_status rx_status = {0}; 2604 int ret; 2605 2606 if (skb_queue_empty(msdu_list)) 2607 return; 2608 2609 if (unlikely(!rcu_access_pointer(ab->pdevs_active[mac_id]))) { 2610 __skb_queue_purge(msdu_list); 2611 return; 2612 } 2613 2614 ar = ab->pdevs[mac_id].ar; 2615 if (unlikely(test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags))) { 2616 __skb_queue_purge(msdu_list); 2617 return; 2618 } 2619 2620 while ((msdu = __skb_dequeue(msdu_list))) { 2621 ret = ath11k_dp_rx_process_msdu(ar, msdu, msdu_list, &rx_status); 2622 if (unlikely(ret)) { 2623 ath11k_dbg(ab, ATH11K_DBG_DATA, 2624 "Unable to process msdu %d", ret); 2625 dev_kfree_skb_any(msdu); 2626 continue; 2627 } 2628 2629 ath11k_dp_rx_deliver_msdu(ar, napi, msdu, &rx_status); 2630 } 2631 } 2632 2633 int ath11k_dp_process_rx(struct ath11k_base *ab, int ring_id, 2634 struct napi_struct *napi, int budget) 2635 { 2636 struct ath11k_dp *dp = &ab->dp; 2637 struct dp_rxdma_ring *rx_ring; 2638 int num_buffs_reaped[MAX_RADIOS] = {0}; 2639 struct sk_buff_head msdu_list[MAX_RADIOS]; 2640 struct ath11k_skb_rxcb *rxcb; 2641 int total_msdu_reaped = 0; 2642 struct hal_srng *srng; 2643 struct sk_buff *msdu; 2644 bool done = false; 2645 int buf_id, mac_id; 2646 struct ath11k *ar; 2647 struct hal_reo_dest_ring *desc; 2648 enum hal_reo_dest_ring_push_reason push_reason; 2649 u32 cookie; 2650 int i; 2651 2652 for (i = 0; i < MAX_RADIOS; i++) 2653 __skb_queue_head_init(&msdu_list[i]); 2654 2655 srng = &ab->hal.srng_list[dp->reo_dst_ring[ring_id].ring_id]; 2656 2657 spin_lock_bh(&srng->lock); 2658 2659 try_again: 2660 ath11k_hal_srng_access_begin(ab, srng); 2661 2662 while (likely(desc = 2663 (struct hal_reo_dest_ring *)ath11k_hal_srng_dst_get_next_entry(ab, 2664 srng))) { 2665 cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, 2666 desc->buf_addr_info.info1); 2667 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, 2668 cookie); 2669 mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, cookie); 2670 2671 if (unlikely(buf_id == 0)) 2672 continue; 2673 2674 ar = ab->pdevs[mac_id].ar; 2675 rx_ring = &ar->dp.rx_refill_buf_ring; 2676 spin_lock_bh(&rx_ring->idr_lock); 2677 msdu = idr_find(&rx_ring->bufs_idr, buf_id); 2678 if (unlikely(!msdu)) { 2679 ath11k_warn(ab, "frame rx with invalid buf_id %d\n", 2680 buf_id); 2681 spin_unlock_bh(&rx_ring->idr_lock); 2682 continue; 2683 } 2684 2685 idr_remove(&rx_ring->bufs_idr, buf_id); 2686 spin_unlock_bh(&rx_ring->idr_lock); 2687 2688 rxcb = ATH11K_SKB_RXCB(msdu); 2689 dma_unmap_single(ab->dev, rxcb->paddr, 2690 msdu->len + skb_tailroom(msdu), 2691 DMA_FROM_DEVICE); 2692 2693 num_buffs_reaped[mac_id]++; 2694 2695 push_reason = FIELD_GET(HAL_REO_DEST_RING_INFO0_PUSH_REASON, 2696 desc->info0); 2697 if (unlikely(push_reason != 2698 HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION)) { 2699 dev_kfree_skb_any(msdu); 2700 ab->soc_stats.hal_reo_error[dp->reo_dst_ring[ring_id].ring_id]++; 2701 continue; 2702 } 2703 2704 rxcb->is_first_msdu = !!(desc->rx_msdu_info.info0 & 2705 RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU); 2706 rxcb->is_last_msdu = !!(desc->rx_msdu_info.info0 & 2707 RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU); 2708 rxcb->is_continuation = !!(desc->rx_msdu_info.info0 & 2709 RX_MSDU_DESC_INFO0_MSDU_CONTINUATION); 2710 rxcb->peer_id = FIELD_GET(RX_MPDU_DESC_META_DATA_PEER_ID, 2711 desc->rx_mpdu_info.meta_data); 2712 rxcb->seq_no = FIELD_GET(RX_MPDU_DESC_INFO0_SEQ_NUM, 2713 desc->rx_mpdu_info.info0); 2714 rxcb->tid = FIELD_GET(HAL_REO_DEST_RING_INFO0_RX_QUEUE_NUM, 2715 desc->info0); 2716 2717 rxcb->mac_id = mac_id; 2718 __skb_queue_tail(&msdu_list[mac_id], msdu); 2719 2720 if (rxcb->is_continuation) { 2721 done = false; 2722 } else { 2723 total_msdu_reaped++; 2724 done = true; 2725 } 2726 2727 if (total_msdu_reaped >= budget) 2728 break; 2729 } 2730 2731 /* Hw might have updated the head pointer after we cached it. 2732 * In this case, even though there are entries in the ring we'll 2733 * get rx_desc NULL. Give the read another try with updated cached 2734 * head pointer so that we can reap complete MPDU in the current 2735 * rx processing. 2736 */ 2737 if (unlikely(!done && ath11k_hal_srng_dst_num_free(ab, srng, true))) { 2738 ath11k_hal_srng_access_end(ab, srng); 2739 goto try_again; 2740 } 2741 2742 ath11k_hal_srng_access_end(ab, srng); 2743 2744 spin_unlock_bh(&srng->lock); 2745 2746 if (unlikely(!total_msdu_reaped)) 2747 goto exit; 2748 2749 for (i = 0; i < ab->num_radios; i++) { 2750 if (!num_buffs_reaped[i]) 2751 continue; 2752 2753 ath11k_dp_rx_process_received_packets(ab, napi, &msdu_list[i], i); 2754 2755 ar = ab->pdevs[i].ar; 2756 rx_ring = &ar->dp.rx_refill_buf_ring; 2757 2758 ath11k_dp_rxbufs_replenish(ab, i, rx_ring, num_buffs_reaped[i], 2759 ab->hw_params.hal_params->rx_buf_rbm); 2760 } 2761 exit: 2762 return total_msdu_reaped; 2763 } 2764 2765 static void ath11k_dp_rx_update_peer_stats(struct ath11k_sta *arsta, 2766 struct hal_rx_mon_ppdu_info *ppdu_info) 2767 { 2768 struct ath11k_rx_peer_stats *rx_stats = arsta->rx_stats; 2769 u32 num_msdu; 2770 int i; 2771 2772 if (!rx_stats) 2773 return; 2774 2775 arsta->rssi_comb = ppdu_info->rssi_comb; 2776 ewma_avg_rssi_add(&arsta->avg_rssi, ppdu_info->rssi_comb); 2777 2778 num_msdu = ppdu_info->tcp_msdu_count + ppdu_info->tcp_ack_msdu_count + 2779 ppdu_info->udp_msdu_count + ppdu_info->other_msdu_count; 2780 2781 rx_stats->num_msdu += num_msdu; 2782 rx_stats->tcp_msdu_count += ppdu_info->tcp_msdu_count + 2783 ppdu_info->tcp_ack_msdu_count; 2784 rx_stats->udp_msdu_count += ppdu_info->udp_msdu_count; 2785 rx_stats->other_msdu_count += ppdu_info->other_msdu_count; 2786 2787 if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11A || 2788 ppdu_info->preamble_type == HAL_RX_PREAMBLE_11B) { 2789 ppdu_info->nss = 1; 2790 ppdu_info->mcs = HAL_RX_MAX_MCS; 2791 ppdu_info->tid = IEEE80211_NUM_TIDS; 2792 } 2793 2794 if (ppdu_info->nss > 0 && ppdu_info->nss <= HAL_RX_MAX_NSS) 2795 rx_stats->nss_count[ppdu_info->nss - 1] += num_msdu; 2796 2797 if (ppdu_info->mcs <= HAL_RX_MAX_MCS) 2798 rx_stats->mcs_count[ppdu_info->mcs] += num_msdu; 2799 2800 if (ppdu_info->gi < HAL_RX_GI_MAX) 2801 rx_stats->gi_count[ppdu_info->gi] += num_msdu; 2802 2803 if (ppdu_info->bw < HAL_RX_BW_MAX) 2804 rx_stats->bw_count[ppdu_info->bw] += num_msdu; 2805 2806 if (ppdu_info->ldpc < HAL_RX_SU_MU_CODING_MAX) 2807 rx_stats->coding_count[ppdu_info->ldpc] += num_msdu; 2808 2809 if (ppdu_info->tid <= IEEE80211_NUM_TIDS) 2810 rx_stats->tid_count[ppdu_info->tid] += num_msdu; 2811 2812 if (ppdu_info->preamble_type < HAL_RX_PREAMBLE_MAX) 2813 rx_stats->pream_cnt[ppdu_info->preamble_type] += num_msdu; 2814 2815 if (ppdu_info->reception_type < HAL_RX_RECEPTION_TYPE_MAX) 2816 rx_stats->reception_type[ppdu_info->reception_type] += num_msdu; 2817 2818 if (ppdu_info->is_stbc) 2819 rx_stats->stbc_count += num_msdu; 2820 2821 if (ppdu_info->beamformed) 2822 rx_stats->beamformed_count += num_msdu; 2823 2824 if (ppdu_info->num_mpdu_fcs_ok > 1) 2825 rx_stats->ampdu_msdu_count += num_msdu; 2826 else 2827 rx_stats->non_ampdu_msdu_count += num_msdu; 2828 2829 rx_stats->num_mpdu_fcs_ok += ppdu_info->num_mpdu_fcs_ok; 2830 rx_stats->num_mpdu_fcs_err += ppdu_info->num_mpdu_fcs_err; 2831 rx_stats->dcm_count += ppdu_info->dcm; 2832 rx_stats->ru_alloc_cnt[ppdu_info->ru_alloc] += num_msdu; 2833 2834 arsta->rssi_comb = ppdu_info->rssi_comb; 2835 2836 BUILD_BUG_ON(ARRAY_SIZE(arsta->chain_signal) > 2837 ARRAY_SIZE(ppdu_info->rssi_chain_pri20)); 2838 2839 for (i = 0; i < ARRAY_SIZE(arsta->chain_signal); i++) 2840 arsta->chain_signal[i] = ppdu_info->rssi_chain_pri20[i]; 2841 2842 rx_stats->rx_duration += ppdu_info->rx_duration; 2843 arsta->rx_duration = rx_stats->rx_duration; 2844 } 2845 2846 static struct sk_buff *ath11k_dp_rx_alloc_mon_status_buf(struct ath11k_base *ab, 2847 struct dp_rxdma_ring *rx_ring, 2848 int *buf_id) 2849 { 2850 struct sk_buff *skb; 2851 dma_addr_t paddr; 2852 2853 skb = dev_alloc_skb(DP_RX_BUFFER_SIZE + 2854 DP_RX_BUFFER_ALIGN_SIZE); 2855 2856 if (!skb) 2857 goto fail_alloc_skb; 2858 2859 if (!IS_ALIGNED((unsigned long)skb->data, 2860 DP_RX_BUFFER_ALIGN_SIZE)) { 2861 skb_pull(skb, PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) - 2862 skb->data); 2863 } 2864 2865 paddr = dma_map_single(ab->dev, skb->data, 2866 skb->len + skb_tailroom(skb), 2867 DMA_FROM_DEVICE); 2868 if (unlikely(dma_mapping_error(ab->dev, paddr))) 2869 goto fail_free_skb; 2870 2871 spin_lock_bh(&rx_ring->idr_lock); 2872 *buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 0, 2873 rx_ring->bufs_max, GFP_ATOMIC); 2874 spin_unlock_bh(&rx_ring->idr_lock); 2875 if (*buf_id < 0) 2876 goto fail_dma_unmap; 2877 2878 ATH11K_SKB_RXCB(skb)->paddr = paddr; 2879 return skb; 2880 2881 fail_dma_unmap: 2882 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb), 2883 DMA_FROM_DEVICE); 2884 fail_free_skb: 2885 dev_kfree_skb_any(skb); 2886 fail_alloc_skb: 2887 return NULL; 2888 } 2889 2890 int ath11k_dp_rx_mon_status_bufs_replenish(struct ath11k_base *ab, int mac_id, 2891 struct dp_rxdma_ring *rx_ring, 2892 int req_entries, 2893 enum hal_rx_buf_return_buf_manager mgr) 2894 { 2895 struct hal_srng *srng; 2896 u32 *desc; 2897 struct sk_buff *skb; 2898 int num_free; 2899 int num_remain; 2900 int buf_id; 2901 u32 cookie; 2902 dma_addr_t paddr; 2903 2904 req_entries = min(req_entries, rx_ring->bufs_max); 2905 2906 srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id]; 2907 2908 spin_lock_bh(&srng->lock); 2909 2910 ath11k_hal_srng_access_begin(ab, srng); 2911 2912 num_free = ath11k_hal_srng_src_num_free(ab, srng, true); 2913 2914 req_entries = min(num_free, req_entries); 2915 num_remain = req_entries; 2916 2917 while (num_remain > 0) { 2918 skb = ath11k_dp_rx_alloc_mon_status_buf(ab, rx_ring, 2919 &buf_id); 2920 if (!skb) 2921 break; 2922 paddr = ATH11K_SKB_RXCB(skb)->paddr; 2923 2924 desc = ath11k_hal_srng_src_get_next_entry(ab, srng); 2925 if (!desc) 2926 goto fail_desc_get; 2927 2928 cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) | 2929 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id); 2930 2931 num_remain--; 2932 2933 ath11k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr); 2934 } 2935 2936 ath11k_hal_srng_access_end(ab, srng); 2937 2938 spin_unlock_bh(&srng->lock); 2939 2940 return req_entries - num_remain; 2941 2942 fail_desc_get: 2943 spin_lock_bh(&rx_ring->idr_lock); 2944 idr_remove(&rx_ring->bufs_idr, buf_id); 2945 spin_unlock_bh(&rx_ring->idr_lock); 2946 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb), 2947 DMA_FROM_DEVICE); 2948 dev_kfree_skb_any(skb); 2949 ath11k_hal_srng_access_end(ab, srng); 2950 spin_unlock_bh(&srng->lock); 2951 2952 return req_entries - num_remain; 2953 } 2954 2955 #define ATH11K_DP_RX_FULL_MON_PPDU_ID_WRAP 32535 2956 2957 static void 2958 ath11k_dp_rx_mon_update_status_buf_state(struct ath11k_mon_data *pmon, 2959 struct hal_tlv_hdr *tlv) 2960 { 2961 struct hal_rx_ppdu_start *ppdu_start; 2962 u16 ppdu_id_diff, ppdu_id, tlv_len; 2963 u8 *ptr; 2964 2965 /* PPDU id is part of second tlv, move ptr to second tlv */ 2966 tlv_len = FIELD_GET(HAL_TLV_HDR_LEN, tlv->tl); 2967 ptr = (u8 *)tlv; 2968 ptr += sizeof(*tlv) + tlv_len; 2969 tlv = (struct hal_tlv_hdr *)ptr; 2970 2971 if (FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl) != HAL_RX_PPDU_START) 2972 return; 2973 2974 ptr += sizeof(*tlv); 2975 ppdu_start = (struct hal_rx_ppdu_start *)ptr; 2976 ppdu_id = FIELD_GET(HAL_RX_PPDU_START_INFO0_PPDU_ID, 2977 __le32_to_cpu(ppdu_start->info0)); 2978 2979 if (pmon->sw_mon_entries.ppdu_id < ppdu_id) { 2980 pmon->buf_state = DP_MON_STATUS_LEAD; 2981 ppdu_id_diff = ppdu_id - pmon->sw_mon_entries.ppdu_id; 2982 if (ppdu_id_diff > ATH11K_DP_RX_FULL_MON_PPDU_ID_WRAP) 2983 pmon->buf_state = DP_MON_STATUS_LAG; 2984 } else if (pmon->sw_mon_entries.ppdu_id > ppdu_id) { 2985 pmon->buf_state = DP_MON_STATUS_LAG; 2986 ppdu_id_diff = pmon->sw_mon_entries.ppdu_id - ppdu_id; 2987 if (ppdu_id_diff > ATH11K_DP_RX_FULL_MON_PPDU_ID_WRAP) 2988 pmon->buf_state = DP_MON_STATUS_LEAD; 2989 } 2990 } 2991 2992 static int ath11k_dp_rx_reap_mon_status_ring(struct ath11k_base *ab, int mac_id, 2993 int *budget, struct sk_buff_head *skb_list) 2994 { 2995 struct ath11k *ar; 2996 const struct ath11k_hw_hal_params *hal_params; 2997 struct ath11k_pdev_dp *dp; 2998 struct dp_rxdma_ring *rx_ring; 2999 struct ath11k_mon_data *pmon; 3000 struct hal_srng *srng; 3001 void *rx_mon_status_desc; 3002 struct sk_buff *skb; 3003 struct ath11k_skb_rxcb *rxcb; 3004 struct hal_tlv_hdr *tlv; 3005 u32 cookie; 3006 int buf_id, srng_id; 3007 dma_addr_t paddr; 3008 u8 rbm; 3009 int num_buffs_reaped = 0; 3010 3011 ar = ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar; 3012 dp = &ar->dp; 3013 pmon = &dp->mon_data; 3014 srng_id = ath11k_hw_mac_id_to_srng_id(&ab->hw_params, mac_id); 3015 rx_ring = &dp->rx_mon_status_refill_ring[srng_id]; 3016 3017 srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id]; 3018 3019 spin_lock_bh(&srng->lock); 3020 3021 ath11k_hal_srng_access_begin(ab, srng); 3022 while (*budget) { 3023 *budget -= 1; 3024 rx_mon_status_desc = 3025 ath11k_hal_srng_src_peek(ab, srng); 3026 if (!rx_mon_status_desc) { 3027 pmon->buf_state = DP_MON_STATUS_REPLINISH; 3028 break; 3029 } 3030 3031 ath11k_hal_rx_buf_addr_info_get(rx_mon_status_desc, &paddr, 3032 &cookie, &rbm); 3033 if (paddr) { 3034 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, cookie); 3035 3036 spin_lock_bh(&rx_ring->idr_lock); 3037 skb = idr_find(&rx_ring->bufs_idr, buf_id); 3038 spin_unlock_bh(&rx_ring->idr_lock); 3039 3040 if (!skb) { 3041 ath11k_warn(ab, "rx monitor status with invalid buf_id %d\n", 3042 buf_id); 3043 pmon->buf_state = DP_MON_STATUS_REPLINISH; 3044 goto move_next; 3045 } 3046 3047 rxcb = ATH11K_SKB_RXCB(skb); 3048 3049 dma_sync_single_for_cpu(ab->dev, rxcb->paddr, 3050 skb->len + skb_tailroom(skb), 3051 DMA_FROM_DEVICE); 3052 3053 tlv = (struct hal_tlv_hdr *)skb->data; 3054 if (FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl) != 3055 HAL_RX_STATUS_BUFFER_DONE) { 3056 ath11k_warn(ab, "mon status DONE not set %lx, buf_id %d\n", 3057 FIELD_GET(HAL_TLV_HDR_TAG, 3058 tlv->tl), buf_id); 3059 /* If done status is missing, hold onto status 3060 * ring until status is done for this status 3061 * ring buffer. 3062 * Keep HP in mon_status_ring unchanged, 3063 * and break from here. 3064 * Check status for same buffer for next time 3065 */ 3066 pmon->buf_state = DP_MON_STATUS_NO_DMA; 3067 break; 3068 } 3069 3070 spin_lock_bh(&rx_ring->idr_lock); 3071 idr_remove(&rx_ring->bufs_idr, buf_id); 3072 spin_unlock_bh(&rx_ring->idr_lock); 3073 if (ab->hw_params.full_monitor_mode) { 3074 ath11k_dp_rx_mon_update_status_buf_state(pmon, tlv); 3075 if (paddr == pmon->mon_status_paddr) 3076 pmon->buf_state = DP_MON_STATUS_MATCH; 3077 } 3078 3079 dma_unmap_single(ab->dev, rxcb->paddr, 3080 skb->len + skb_tailroom(skb), 3081 DMA_FROM_DEVICE); 3082 3083 __skb_queue_tail(skb_list, skb); 3084 } else { 3085 pmon->buf_state = DP_MON_STATUS_REPLINISH; 3086 } 3087 move_next: 3088 skb = ath11k_dp_rx_alloc_mon_status_buf(ab, rx_ring, 3089 &buf_id); 3090 3091 if (!skb) { 3092 hal_params = ab->hw_params.hal_params; 3093 ath11k_hal_rx_buf_addr_info_set(rx_mon_status_desc, 0, 0, 3094 hal_params->rx_buf_rbm); 3095 num_buffs_reaped++; 3096 break; 3097 } 3098 rxcb = ATH11K_SKB_RXCB(skb); 3099 3100 cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) | 3101 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id); 3102 3103 ath11k_hal_rx_buf_addr_info_set(rx_mon_status_desc, rxcb->paddr, 3104 cookie, 3105 ab->hw_params.hal_params->rx_buf_rbm); 3106 ath11k_hal_srng_src_get_next_entry(ab, srng); 3107 num_buffs_reaped++; 3108 } 3109 ath11k_hal_srng_access_end(ab, srng); 3110 spin_unlock_bh(&srng->lock); 3111 3112 return num_buffs_reaped; 3113 } 3114 3115 static void ath11k_dp_rx_frag_timer(struct timer_list *timer) 3116 { 3117 struct dp_rx_tid *rx_tid = from_timer(rx_tid, timer, frag_timer); 3118 3119 spin_lock_bh(&rx_tid->ab->base_lock); 3120 if (rx_tid->last_frag_no && 3121 rx_tid->rx_frag_bitmap == GENMASK(rx_tid->last_frag_no, 0)) { 3122 spin_unlock_bh(&rx_tid->ab->base_lock); 3123 return; 3124 } 3125 ath11k_dp_rx_frags_cleanup(rx_tid, true); 3126 spin_unlock_bh(&rx_tid->ab->base_lock); 3127 } 3128 3129 int ath11k_peer_rx_frag_setup(struct ath11k *ar, const u8 *peer_mac, int vdev_id) 3130 { 3131 struct ath11k_base *ab = ar->ab; 3132 struct crypto_shash *tfm; 3133 struct ath11k_peer *peer; 3134 struct dp_rx_tid *rx_tid; 3135 int i; 3136 3137 tfm = crypto_alloc_shash("michael_mic", 0, 0); 3138 if (IS_ERR(tfm)) { 3139 ath11k_warn(ab, "failed to allocate michael_mic shash: %ld\n", 3140 PTR_ERR(tfm)); 3141 return PTR_ERR(tfm); 3142 } 3143 3144 spin_lock_bh(&ab->base_lock); 3145 3146 peer = ath11k_peer_find(ab, vdev_id, peer_mac); 3147 if (!peer) { 3148 ath11k_warn(ab, "failed to find the peer to set up fragment info\n"); 3149 spin_unlock_bh(&ab->base_lock); 3150 crypto_free_shash(tfm); 3151 return -ENOENT; 3152 } 3153 3154 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) { 3155 rx_tid = &peer->rx_tid[i]; 3156 rx_tid->ab = ab; 3157 timer_setup(&rx_tid->frag_timer, ath11k_dp_rx_frag_timer, 0); 3158 skb_queue_head_init(&rx_tid->rx_frags); 3159 } 3160 3161 peer->tfm_mmic = tfm; 3162 peer->dp_setup_done = true; 3163 spin_unlock_bh(&ab->base_lock); 3164 3165 return 0; 3166 } 3167 3168 static int ath11k_dp_rx_h_michael_mic(struct crypto_shash *tfm, u8 *key, 3169 struct ieee80211_hdr *hdr, u8 *data, 3170 size_t data_len, u8 *mic) 3171 { 3172 SHASH_DESC_ON_STACK(desc, tfm); 3173 u8 mic_hdr[16] = {0}; 3174 u8 tid = 0; 3175 int ret; 3176 3177 if (!tfm) 3178 return -EINVAL; 3179 3180 desc->tfm = tfm; 3181 3182 ret = crypto_shash_setkey(tfm, key, 8); 3183 if (ret) 3184 goto out; 3185 3186 ret = crypto_shash_init(desc); 3187 if (ret) 3188 goto out; 3189 3190 /* TKIP MIC header */ 3191 memcpy(mic_hdr, ieee80211_get_DA(hdr), ETH_ALEN); 3192 memcpy(mic_hdr + ETH_ALEN, ieee80211_get_SA(hdr), ETH_ALEN); 3193 if (ieee80211_is_data_qos(hdr->frame_control)) 3194 tid = ieee80211_get_tid(hdr); 3195 mic_hdr[12] = tid; 3196 3197 ret = crypto_shash_update(desc, mic_hdr, 16); 3198 if (ret) 3199 goto out; 3200 ret = crypto_shash_update(desc, data, data_len); 3201 if (ret) 3202 goto out; 3203 ret = crypto_shash_final(desc, mic); 3204 out: 3205 shash_desc_zero(desc); 3206 return ret; 3207 } 3208 3209 static int ath11k_dp_rx_h_verify_tkip_mic(struct ath11k *ar, struct ath11k_peer *peer, 3210 struct sk_buff *msdu) 3211 { 3212 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)msdu->data; 3213 struct ieee80211_rx_status *rxs = IEEE80211_SKB_RXCB(msdu); 3214 struct ieee80211_key_conf *key_conf; 3215 struct ieee80211_hdr *hdr; 3216 u8 mic[IEEE80211_CCMP_MIC_LEN]; 3217 int head_len, tail_len, ret; 3218 size_t data_len; 3219 u32 hdr_len, hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz; 3220 u8 *key, *data; 3221 u8 key_idx; 3222 3223 if (ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc) != 3224 HAL_ENCRYPT_TYPE_TKIP_MIC) 3225 return 0; 3226 3227 hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz); 3228 hdr_len = ieee80211_hdrlen(hdr->frame_control); 3229 head_len = hdr_len + hal_rx_desc_sz + IEEE80211_TKIP_IV_LEN; 3230 tail_len = IEEE80211_CCMP_MIC_LEN + IEEE80211_TKIP_ICV_LEN + FCS_LEN; 3231 3232 if (!is_multicast_ether_addr(hdr->addr1)) 3233 key_idx = peer->ucast_keyidx; 3234 else 3235 key_idx = peer->mcast_keyidx; 3236 3237 key_conf = peer->keys[key_idx]; 3238 3239 data = msdu->data + head_len; 3240 data_len = msdu->len - head_len - tail_len; 3241 key = &key_conf->key[NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY]; 3242 3243 ret = ath11k_dp_rx_h_michael_mic(peer->tfm_mmic, key, hdr, data, data_len, mic); 3244 if (ret || memcmp(mic, data + data_len, IEEE80211_CCMP_MIC_LEN)) 3245 goto mic_fail; 3246 3247 return 0; 3248 3249 mic_fail: 3250 (ATH11K_SKB_RXCB(msdu))->is_first_msdu = true; 3251 (ATH11K_SKB_RXCB(msdu))->is_last_msdu = true; 3252 3253 rxs->flag |= RX_FLAG_MMIC_ERROR | RX_FLAG_MMIC_STRIPPED | 3254 RX_FLAG_IV_STRIPPED | RX_FLAG_DECRYPTED; 3255 skb_pull(msdu, hal_rx_desc_sz); 3256 3257 ath11k_dp_rx_h_ppdu(ar, rx_desc, rxs); 3258 ath11k_dp_rx_h_undecap(ar, msdu, rx_desc, 3259 HAL_ENCRYPT_TYPE_TKIP_MIC, rxs, true); 3260 ieee80211_rx(ar->hw, msdu); 3261 return -EINVAL; 3262 } 3263 3264 static void ath11k_dp_rx_h_undecap_frag(struct ath11k *ar, struct sk_buff *msdu, 3265 enum hal_encrypt_type enctype, u32 flags) 3266 { 3267 struct ieee80211_hdr *hdr; 3268 size_t hdr_len; 3269 size_t crypto_len; 3270 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz; 3271 3272 if (!flags) 3273 return; 3274 3275 hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz); 3276 3277 if (flags & RX_FLAG_MIC_STRIPPED) 3278 skb_trim(msdu, msdu->len - 3279 ath11k_dp_rx_crypto_mic_len(ar, enctype)); 3280 3281 if (flags & RX_FLAG_ICV_STRIPPED) 3282 skb_trim(msdu, msdu->len - 3283 ath11k_dp_rx_crypto_icv_len(ar, enctype)); 3284 3285 if (flags & RX_FLAG_IV_STRIPPED) { 3286 hdr_len = ieee80211_hdrlen(hdr->frame_control); 3287 crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype); 3288 3289 memmove((void *)msdu->data + hal_rx_desc_sz + crypto_len, 3290 (void *)msdu->data + hal_rx_desc_sz, hdr_len); 3291 skb_pull(msdu, crypto_len); 3292 } 3293 } 3294 3295 static int ath11k_dp_rx_h_defrag(struct ath11k *ar, 3296 struct ath11k_peer *peer, 3297 struct dp_rx_tid *rx_tid, 3298 struct sk_buff **defrag_skb) 3299 { 3300 struct hal_rx_desc *rx_desc; 3301 struct sk_buff *skb, *first_frag, *last_frag; 3302 struct ieee80211_hdr *hdr; 3303 struct rx_attention *rx_attention; 3304 enum hal_encrypt_type enctype; 3305 bool is_decrypted = false; 3306 int msdu_len = 0; 3307 int extra_space; 3308 u32 flags, hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz; 3309 3310 first_frag = skb_peek(&rx_tid->rx_frags); 3311 last_frag = skb_peek_tail(&rx_tid->rx_frags); 3312 3313 skb_queue_walk(&rx_tid->rx_frags, skb) { 3314 flags = 0; 3315 rx_desc = (struct hal_rx_desc *)skb->data; 3316 hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz); 3317 3318 enctype = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc); 3319 if (enctype != HAL_ENCRYPT_TYPE_OPEN) { 3320 rx_attention = ath11k_dp_rx_get_attention(ar->ab, rx_desc); 3321 is_decrypted = ath11k_dp_rx_h_attn_is_decrypted(rx_attention); 3322 } 3323 3324 if (is_decrypted) { 3325 if (skb != first_frag) 3326 flags |= RX_FLAG_IV_STRIPPED; 3327 if (skb != last_frag) 3328 flags |= RX_FLAG_ICV_STRIPPED | 3329 RX_FLAG_MIC_STRIPPED; 3330 } 3331 3332 /* RX fragments are always raw packets */ 3333 if (skb != last_frag) 3334 skb_trim(skb, skb->len - FCS_LEN); 3335 ath11k_dp_rx_h_undecap_frag(ar, skb, enctype, flags); 3336 3337 if (skb != first_frag) 3338 skb_pull(skb, hal_rx_desc_sz + 3339 ieee80211_hdrlen(hdr->frame_control)); 3340 msdu_len += skb->len; 3341 } 3342 3343 extra_space = msdu_len - (DP_RX_BUFFER_SIZE + skb_tailroom(first_frag)); 3344 if (extra_space > 0 && 3345 (pskb_expand_head(first_frag, 0, extra_space, GFP_ATOMIC) < 0)) 3346 return -ENOMEM; 3347 3348 __skb_unlink(first_frag, &rx_tid->rx_frags); 3349 while ((skb = __skb_dequeue(&rx_tid->rx_frags))) { 3350 skb_put_data(first_frag, skb->data, skb->len); 3351 dev_kfree_skb_any(skb); 3352 } 3353 3354 hdr = (struct ieee80211_hdr *)(first_frag->data + hal_rx_desc_sz); 3355 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_MOREFRAGS); 3356 ATH11K_SKB_RXCB(first_frag)->is_frag = 1; 3357 3358 if (ath11k_dp_rx_h_verify_tkip_mic(ar, peer, first_frag)) 3359 first_frag = NULL; 3360 3361 *defrag_skb = first_frag; 3362 return 0; 3363 } 3364 3365 static int ath11k_dp_rx_h_defrag_reo_reinject(struct ath11k *ar, struct dp_rx_tid *rx_tid, 3366 struct sk_buff *defrag_skb) 3367 { 3368 struct ath11k_base *ab = ar->ab; 3369 struct ath11k_pdev_dp *dp = &ar->dp; 3370 struct dp_rxdma_ring *rx_refill_ring = &dp->rx_refill_buf_ring; 3371 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)defrag_skb->data; 3372 struct hal_reo_entrance_ring *reo_ent_ring; 3373 struct hal_reo_dest_ring *reo_dest_ring; 3374 struct dp_link_desc_bank *link_desc_banks; 3375 struct hal_rx_msdu_link *msdu_link; 3376 struct hal_rx_msdu_details *msdu0; 3377 struct hal_srng *srng; 3378 dma_addr_t paddr; 3379 u32 desc_bank, msdu_info, mpdu_info; 3380 u32 dst_idx, cookie, hal_rx_desc_sz; 3381 int ret, buf_id; 3382 3383 hal_rx_desc_sz = ab->hw_params.hal_desc_sz; 3384 link_desc_banks = ab->dp.link_desc_banks; 3385 reo_dest_ring = rx_tid->dst_ring_desc; 3386 3387 ath11k_hal_rx_reo_ent_paddr_get(ab, reo_dest_ring, &paddr, &desc_bank); 3388 msdu_link = (struct hal_rx_msdu_link *)(link_desc_banks[desc_bank].vaddr + 3389 (paddr - link_desc_banks[desc_bank].paddr)); 3390 msdu0 = &msdu_link->msdu_link[0]; 3391 dst_idx = FIELD_GET(RX_MSDU_DESC_INFO0_REO_DEST_IND, msdu0->rx_msdu_info.info0); 3392 memset(msdu0, 0, sizeof(*msdu0)); 3393 3394 msdu_info = FIELD_PREP(RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU, 1) | 3395 FIELD_PREP(RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU, 1) | 3396 FIELD_PREP(RX_MSDU_DESC_INFO0_MSDU_CONTINUATION, 0) | 3397 FIELD_PREP(RX_MSDU_DESC_INFO0_MSDU_LENGTH, 3398 defrag_skb->len - hal_rx_desc_sz) | 3399 FIELD_PREP(RX_MSDU_DESC_INFO0_REO_DEST_IND, dst_idx) | 3400 FIELD_PREP(RX_MSDU_DESC_INFO0_VALID_SA, 1) | 3401 FIELD_PREP(RX_MSDU_DESC_INFO0_VALID_DA, 1); 3402 msdu0->rx_msdu_info.info0 = msdu_info; 3403 3404 /* change msdu len in hal rx desc */ 3405 ath11k_dp_rxdesc_set_msdu_len(ab, rx_desc, defrag_skb->len - hal_rx_desc_sz); 3406 3407 paddr = dma_map_single(ab->dev, defrag_skb->data, 3408 defrag_skb->len + skb_tailroom(defrag_skb), 3409 DMA_TO_DEVICE); 3410 if (dma_mapping_error(ab->dev, paddr)) 3411 return -ENOMEM; 3412 3413 spin_lock_bh(&rx_refill_ring->idr_lock); 3414 buf_id = idr_alloc(&rx_refill_ring->bufs_idr, defrag_skb, 0, 3415 rx_refill_ring->bufs_max * 3, GFP_ATOMIC); 3416 spin_unlock_bh(&rx_refill_ring->idr_lock); 3417 if (buf_id < 0) { 3418 ret = -ENOMEM; 3419 goto err_unmap_dma; 3420 } 3421 3422 ATH11K_SKB_RXCB(defrag_skb)->paddr = paddr; 3423 cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, dp->mac_id) | 3424 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id); 3425 3426 ath11k_hal_rx_buf_addr_info_set(msdu0, paddr, cookie, 3427 ab->hw_params.hal_params->rx_buf_rbm); 3428 3429 /* Fill mpdu details into reo entrance ring */ 3430 srng = &ab->hal.srng_list[ab->dp.reo_reinject_ring.ring_id]; 3431 3432 spin_lock_bh(&srng->lock); 3433 ath11k_hal_srng_access_begin(ab, srng); 3434 3435 reo_ent_ring = (struct hal_reo_entrance_ring *) 3436 ath11k_hal_srng_src_get_next_entry(ab, srng); 3437 if (!reo_ent_ring) { 3438 ath11k_hal_srng_access_end(ab, srng); 3439 spin_unlock_bh(&srng->lock); 3440 ret = -ENOSPC; 3441 goto err_free_idr; 3442 } 3443 memset(reo_ent_ring, 0, sizeof(*reo_ent_ring)); 3444 3445 ath11k_hal_rx_reo_ent_paddr_get(ab, reo_dest_ring, &paddr, &desc_bank); 3446 ath11k_hal_rx_buf_addr_info_set(reo_ent_ring, paddr, desc_bank, 3447 HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST); 3448 3449 mpdu_info = FIELD_PREP(RX_MPDU_DESC_INFO0_MSDU_COUNT, 1) | 3450 FIELD_PREP(RX_MPDU_DESC_INFO0_SEQ_NUM, rx_tid->cur_sn) | 3451 FIELD_PREP(RX_MPDU_DESC_INFO0_FRAG_FLAG, 0) | 3452 FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_SA, 1) | 3453 FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_DA, 1) | 3454 FIELD_PREP(RX_MPDU_DESC_INFO0_RAW_MPDU, 1) | 3455 FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_PN, 1); 3456 3457 reo_ent_ring->rx_mpdu_info.info0 = mpdu_info; 3458 reo_ent_ring->rx_mpdu_info.meta_data = reo_dest_ring->rx_mpdu_info.meta_data; 3459 reo_ent_ring->queue_addr_lo = reo_dest_ring->queue_addr_lo; 3460 reo_ent_ring->info0 = FIELD_PREP(HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI, 3461 FIELD_GET(HAL_REO_DEST_RING_INFO0_QUEUE_ADDR_HI, 3462 reo_dest_ring->info0)) | 3463 FIELD_PREP(HAL_REO_ENTR_RING_INFO0_DEST_IND, dst_idx); 3464 ath11k_hal_srng_access_end(ab, srng); 3465 spin_unlock_bh(&srng->lock); 3466 3467 return 0; 3468 3469 err_free_idr: 3470 spin_lock_bh(&rx_refill_ring->idr_lock); 3471 idr_remove(&rx_refill_ring->bufs_idr, buf_id); 3472 spin_unlock_bh(&rx_refill_ring->idr_lock); 3473 err_unmap_dma: 3474 dma_unmap_single(ab->dev, paddr, defrag_skb->len + skb_tailroom(defrag_skb), 3475 DMA_TO_DEVICE); 3476 return ret; 3477 } 3478 3479 static int ath11k_dp_rx_h_cmp_frags(struct ath11k *ar, 3480 struct sk_buff *a, struct sk_buff *b) 3481 { 3482 int frag1, frag2; 3483 3484 frag1 = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, a); 3485 frag2 = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, b); 3486 3487 return frag1 - frag2; 3488 } 3489 3490 static void ath11k_dp_rx_h_sort_frags(struct ath11k *ar, 3491 struct sk_buff_head *frag_list, 3492 struct sk_buff *cur_frag) 3493 { 3494 struct sk_buff *skb; 3495 int cmp; 3496 3497 skb_queue_walk(frag_list, skb) { 3498 cmp = ath11k_dp_rx_h_cmp_frags(ar, skb, cur_frag); 3499 if (cmp < 0) 3500 continue; 3501 __skb_queue_before(frag_list, skb, cur_frag); 3502 return; 3503 } 3504 __skb_queue_tail(frag_list, cur_frag); 3505 } 3506 3507 static u64 ath11k_dp_rx_h_get_pn(struct ath11k *ar, struct sk_buff *skb) 3508 { 3509 struct ieee80211_hdr *hdr; 3510 u64 pn = 0; 3511 u8 *ehdr; 3512 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz; 3513 3514 hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz); 3515 ehdr = skb->data + hal_rx_desc_sz + ieee80211_hdrlen(hdr->frame_control); 3516 3517 pn = ehdr[0]; 3518 pn |= (u64)ehdr[1] << 8; 3519 pn |= (u64)ehdr[4] << 16; 3520 pn |= (u64)ehdr[5] << 24; 3521 pn |= (u64)ehdr[6] << 32; 3522 pn |= (u64)ehdr[7] << 40; 3523 3524 return pn; 3525 } 3526 3527 static bool 3528 ath11k_dp_rx_h_defrag_validate_incr_pn(struct ath11k *ar, struct dp_rx_tid *rx_tid) 3529 { 3530 enum hal_encrypt_type encrypt_type; 3531 struct sk_buff *first_frag, *skb; 3532 struct hal_rx_desc *desc; 3533 u64 last_pn; 3534 u64 cur_pn; 3535 3536 first_frag = skb_peek(&rx_tid->rx_frags); 3537 desc = (struct hal_rx_desc *)first_frag->data; 3538 3539 encrypt_type = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, desc); 3540 if (encrypt_type != HAL_ENCRYPT_TYPE_CCMP_128 && 3541 encrypt_type != HAL_ENCRYPT_TYPE_CCMP_256 && 3542 encrypt_type != HAL_ENCRYPT_TYPE_GCMP_128 && 3543 encrypt_type != HAL_ENCRYPT_TYPE_AES_GCMP_256) 3544 return true; 3545 3546 last_pn = ath11k_dp_rx_h_get_pn(ar, first_frag); 3547 skb_queue_walk(&rx_tid->rx_frags, skb) { 3548 if (skb == first_frag) 3549 continue; 3550 3551 cur_pn = ath11k_dp_rx_h_get_pn(ar, skb); 3552 if (cur_pn != last_pn + 1) 3553 return false; 3554 last_pn = cur_pn; 3555 } 3556 return true; 3557 } 3558 3559 static int ath11k_dp_rx_frag_h_mpdu(struct ath11k *ar, 3560 struct sk_buff *msdu, 3561 u32 *ring_desc) 3562 { 3563 struct ath11k_base *ab = ar->ab; 3564 struct hal_rx_desc *rx_desc; 3565 struct ath11k_peer *peer; 3566 struct dp_rx_tid *rx_tid; 3567 struct sk_buff *defrag_skb = NULL; 3568 u32 peer_id; 3569 u16 seqno, frag_no; 3570 u8 tid; 3571 int ret = 0; 3572 bool more_frags; 3573 bool is_mcbc; 3574 3575 rx_desc = (struct hal_rx_desc *)msdu->data; 3576 peer_id = ath11k_dp_rx_h_mpdu_start_peer_id(ar->ab, rx_desc); 3577 tid = ath11k_dp_rx_h_mpdu_start_tid(ar->ab, rx_desc); 3578 seqno = ath11k_dp_rx_h_mpdu_start_seq_no(ar->ab, rx_desc); 3579 frag_no = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, msdu); 3580 more_frags = ath11k_dp_rx_h_mpdu_start_more_frags(ar->ab, msdu); 3581 is_mcbc = ath11k_dp_rx_h_attn_is_mcbc(ar->ab, rx_desc); 3582 3583 /* Multicast/Broadcast fragments are not expected */ 3584 if (is_mcbc) 3585 return -EINVAL; 3586 3587 if (!ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(ar->ab, rx_desc) || 3588 !ath11k_dp_rx_h_mpdu_start_fc_valid(ar->ab, rx_desc) || 3589 tid > IEEE80211_NUM_TIDS) 3590 return -EINVAL; 3591 3592 /* received unfragmented packet in reo 3593 * exception ring, this shouldn't happen 3594 * as these packets typically come from 3595 * reo2sw srngs. 3596 */ 3597 if (WARN_ON_ONCE(!frag_no && !more_frags)) 3598 return -EINVAL; 3599 3600 spin_lock_bh(&ab->base_lock); 3601 peer = ath11k_peer_find_by_id(ab, peer_id); 3602 if (!peer) { 3603 ath11k_warn(ab, "failed to find the peer to de-fragment received fragment peer_id %d\n", 3604 peer_id); 3605 ret = -ENOENT; 3606 goto out_unlock; 3607 } 3608 if (!peer->dp_setup_done) { 3609 ath11k_warn(ab, "The peer %pM [%d] has uninitialized datapath\n", 3610 peer->addr, peer_id); 3611 ret = -ENOENT; 3612 goto out_unlock; 3613 } 3614 3615 rx_tid = &peer->rx_tid[tid]; 3616 3617 if ((!skb_queue_empty(&rx_tid->rx_frags) && seqno != rx_tid->cur_sn) || 3618 skb_queue_empty(&rx_tid->rx_frags)) { 3619 /* Flush stored fragments and start a new sequence */ 3620 ath11k_dp_rx_frags_cleanup(rx_tid, true); 3621 rx_tid->cur_sn = seqno; 3622 } 3623 3624 if (rx_tid->rx_frag_bitmap & BIT(frag_no)) { 3625 /* Fragment already present */ 3626 ret = -EINVAL; 3627 goto out_unlock; 3628 } 3629 3630 if (!rx_tid->rx_frag_bitmap || (frag_no > __fls(rx_tid->rx_frag_bitmap))) 3631 __skb_queue_tail(&rx_tid->rx_frags, msdu); 3632 else 3633 ath11k_dp_rx_h_sort_frags(ar, &rx_tid->rx_frags, msdu); 3634 3635 rx_tid->rx_frag_bitmap |= BIT(frag_no); 3636 if (!more_frags) 3637 rx_tid->last_frag_no = frag_no; 3638 3639 if (frag_no == 0) { 3640 rx_tid->dst_ring_desc = kmemdup(ring_desc, 3641 sizeof(*rx_tid->dst_ring_desc), 3642 GFP_ATOMIC); 3643 if (!rx_tid->dst_ring_desc) { 3644 ret = -ENOMEM; 3645 goto out_unlock; 3646 } 3647 } else { 3648 ath11k_dp_rx_link_desc_return(ab, ring_desc, 3649 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 3650 } 3651 3652 if (!rx_tid->last_frag_no || 3653 rx_tid->rx_frag_bitmap != GENMASK(rx_tid->last_frag_no, 0)) { 3654 mod_timer(&rx_tid->frag_timer, jiffies + 3655 ATH11K_DP_RX_FRAGMENT_TIMEOUT_MS); 3656 goto out_unlock; 3657 } 3658 3659 spin_unlock_bh(&ab->base_lock); 3660 del_timer_sync(&rx_tid->frag_timer); 3661 spin_lock_bh(&ab->base_lock); 3662 3663 peer = ath11k_peer_find_by_id(ab, peer_id); 3664 if (!peer) 3665 goto err_frags_cleanup; 3666 3667 if (!ath11k_dp_rx_h_defrag_validate_incr_pn(ar, rx_tid)) 3668 goto err_frags_cleanup; 3669 3670 if (ath11k_dp_rx_h_defrag(ar, peer, rx_tid, &defrag_skb)) 3671 goto err_frags_cleanup; 3672 3673 if (!defrag_skb) 3674 goto err_frags_cleanup; 3675 3676 if (ath11k_dp_rx_h_defrag_reo_reinject(ar, rx_tid, defrag_skb)) 3677 goto err_frags_cleanup; 3678 3679 ath11k_dp_rx_frags_cleanup(rx_tid, false); 3680 goto out_unlock; 3681 3682 err_frags_cleanup: 3683 dev_kfree_skb_any(defrag_skb); 3684 ath11k_dp_rx_frags_cleanup(rx_tid, true); 3685 out_unlock: 3686 spin_unlock_bh(&ab->base_lock); 3687 return ret; 3688 } 3689 3690 static int 3691 ath11k_dp_process_rx_err_buf(struct ath11k *ar, u32 *ring_desc, int buf_id, bool drop) 3692 { 3693 struct ath11k_pdev_dp *dp = &ar->dp; 3694 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring; 3695 struct sk_buff *msdu; 3696 struct ath11k_skb_rxcb *rxcb; 3697 struct hal_rx_desc *rx_desc; 3698 u8 *hdr_status; 3699 u16 msdu_len; 3700 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz; 3701 3702 spin_lock_bh(&rx_ring->idr_lock); 3703 msdu = idr_find(&rx_ring->bufs_idr, buf_id); 3704 if (!msdu) { 3705 ath11k_warn(ar->ab, "rx err buf with invalid buf_id %d\n", 3706 buf_id); 3707 spin_unlock_bh(&rx_ring->idr_lock); 3708 return -EINVAL; 3709 } 3710 3711 idr_remove(&rx_ring->bufs_idr, buf_id); 3712 spin_unlock_bh(&rx_ring->idr_lock); 3713 3714 rxcb = ATH11K_SKB_RXCB(msdu); 3715 dma_unmap_single(ar->ab->dev, rxcb->paddr, 3716 msdu->len + skb_tailroom(msdu), 3717 DMA_FROM_DEVICE); 3718 3719 if (drop) { 3720 dev_kfree_skb_any(msdu); 3721 return 0; 3722 } 3723 3724 rcu_read_lock(); 3725 if (!rcu_dereference(ar->ab->pdevs_active[ar->pdev_idx])) { 3726 dev_kfree_skb_any(msdu); 3727 goto exit; 3728 } 3729 3730 if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) { 3731 dev_kfree_skb_any(msdu); 3732 goto exit; 3733 } 3734 3735 rx_desc = (struct hal_rx_desc *)msdu->data; 3736 msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, rx_desc); 3737 if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) { 3738 hdr_status = ath11k_dp_rx_h_80211_hdr(ar->ab, rx_desc); 3739 ath11k_warn(ar->ab, "invalid msdu leng %u", msdu_len); 3740 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", hdr_status, 3741 sizeof(struct ieee80211_hdr)); 3742 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", rx_desc, 3743 sizeof(struct hal_rx_desc)); 3744 dev_kfree_skb_any(msdu); 3745 goto exit; 3746 } 3747 3748 skb_put(msdu, hal_rx_desc_sz + msdu_len); 3749 3750 if (ath11k_dp_rx_frag_h_mpdu(ar, msdu, ring_desc)) { 3751 dev_kfree_skb_any(msdu); 3752 ath11k_dp_rx_link_desc_return(ar->ab, ring_desc, 3753 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 3754 } 3755 exit: 3756 rcu_read_unlock(); 3757 return 0; 3758 } 3759 3760 int ath11k_dp_process_rx_err(struct ath11k_base *ab, struct napi_struct *napi, 3761 int budget) 3762 { 3763 u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC]; 3764 struct dp_link_desc_bank *link_desc_banks; 3765 enum hal_rx_buf_return_buf_manager rbm; 3766 int tot_n_bufs_reaped, quota, ret, i; 3767 int n_bufs_reaped[MAX_RADIOS] = {0}; 3768 struct dp_rxdma_ring *rx_ring; 3769 struct dp_srng *reo_except; 3770 u32 desc_bank, num_msdus; 3771 struct hal_srng *srng; 3772 struct ath11k_dp *dp; 3773 void *link_desc_va; 3774 int buf_id, mac_id; 3775 struct ath11k *ar; 3776 dma_addr_t paddr; 3777 u32 *desc; 3778 bool is_frag; 3779 u8 drop = 0; 3780 3781 tot_n_bufs_reaped = 0; 3782 quota = budget; 3783 3784 dp = &ab->dp; 3785 reo_except = &dp->reo_except_ring; 3786 link_desc_banks = dp->link_desc_banks; 3787 3788 srng = &ab->hal.srng_list[reo_except->ring_id]; 3789 3790 spin_lock_bh(&srng->lock); 3791 3792 ath11k_hal_srng_access_begin(ab, srng); 3793 3794 while (budget && 3795 (desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) { 3796 struct hal_reo_dest_ring *reo_desc = (struct hal_reo_dest_ring *)desc; 3797 3798 ab->soc_stats.err_ring_pkts++; 3799 ret = ath11k_hal_desc_reo_parse_err(ab, desc, &paddr, 3800 &desc_bank); 3801 if (ret) { 3802 ath11k_warn(ab, "failed to parse error reo desc %d\n", 3803 ret); 3804 continue; 3805 } 3806 link_desc_va = link_desc_banks[desc_bank].vaddr + 3807 (paddr - link_desc_banks[desc_bank].paddr); 3808 ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus, msdu_cookies, 3809 &rbm); 3810 if (rbm != HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST && 3811 rbm != HAL_RX_BUF_RBM_SW3_BM) { 3812 ab->soc_stats.invalid_rbm++; 3813 ath11k_warn(ab, "invalid return buffer manager %d\n", rbm); 3814 ath11k_dp_rx_link_desc_return(ab, desc, 3815 HAL_WBM_REL_BM_ACT_REL_MSDU); 3816 continue; 3817 } 3818 3819 is_frag = !!(reo_desc->rx_mpdu_info.info0 & RX_MPDU_DESC_INFO0_FRAG_FLAG); 3820 3821 /* Process only rx fragments with one msdu per link desc below, and drop 3822 * msdu's indicated due to error reasons. 3823 */ 3824 if (!is_frag || num_msdus > 1) { 3825 drop = 1; 3826 /* Return the link desc back to wbm idle list */ 3827 ath11k_dp_rx_link_desc_return(ab, desc, 3828 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 3829 } 3830 3831 for (i = 0; i < num_msdus; i++) { 3832 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, 3833 msdu_cookies[i]); 3834 3835 mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, 3836 msdu_cookies[i]); 3837 3838 ar = ab->pdevs[mac_id].ar; 3839 3840 if (!ath11k_dp_process_rx_err_buf(ar, desc, buf_id, drop)) { 3841 n_bufs_reaped[mac_id]++; 3842 tot_n_bufs_reaped++; 3843 } 3844 } 3845 3846 if (tot_n_bufs_reaped >= quota) { 3847 tot_n_bufs_reaped = quota; 3848 goto exit; 3849 } 3850 3851 budget = quota - tot_n_bufs_reaped; 3852 } 3853 3854 exit: 3855 ath11k_hal_srng_access_end(ab, srng); 3856 3857 spin_unlock_bh(&srng->lock); 3858 3859 for (i = 0; i < ab->num_radios; i++) { 3860 if (!n_bufs_reaped[i]) 3861 continue; 3862 3863 ar = ab->pdevs[i].ar; 3864 rx_ring = &ar->dp.rx_refill_buf_ring; 3865 3866 ath11k_dp_rxbufs_replenish(ab, i, rx_ring, n_bufs_reaped[i], 3867 ab->hw_params.hal_params->rx_buf_rbm); 3868 } 3869 3870 return tot_n_bufs_reaped; 3871 } 3872 3873 static void ath11k_dp_rx_null_q_desc_sg_drop(struct ath11k *ar, 3874 int msdu_len, 3875 struct sk_buff_head *msdu_list) 3876 { 3877 struct sk_buff *skb, *tmp; 3878 struct ath11k_skb_rxcb *rxcb; 3879 int n_buffs; 3880 3881 n_buffs = DIV_ROUND_UP(msdu_len, 3882 (DP_RX_BUFFER_SIZE - ar->ab->hw_params.hal_desc_sz)); 3883 3884 skb_queue_walk_safe(msdu_list, skb, tmp) { 3885 rxcb = ATH11K_SKB_RXCB(skb); 3886 if (rxcb->err_rel_src == HAL_WBM_REL_SRC_MODULE_REO && 3887 rxcb->err_code == HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO) { 3888 if (!n_buffs) 3889 break; 3890 __skb_unlink(skb, msdu_list); 3891 dev_kfree_skb_any(skb); 3892 n_buffs--; 3893 } 3894 } 3895 } 3896 3897 static int ath11k_dp_rx_h_null_q_desc(struct ath11k *ar, struct sk_buff *msdu, 3898 struct ieee80211_rx_status *status, 3899 struct sk_buff_head *msdu_list) 3900 { 3901 u16 msdu_len; 3902 struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data; 3903 struct rx_attention *rx_attention; 3904 u8 l3pad_bytes; 3905 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 3906 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz; 3907 3908 msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, desc); 3909 3910 if (!rxcb->is_frag && ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE)) { 3911 /* First buffer will be freed by the caller, so deduct it's length */ 3912 msdu_len = msdu_len - (DP_RX_BUFFER_SIZE - hal_rx_desc_sz); 3913 ath11k_dp_rx_null_q_desc_sg_drop(ar, msdu_len, msdu_list); 3914 return -EINVAL; 3915 } 3916 3917 rx_attention = ath11k_dp_rx_get_attention(ar->ab, desc); 3918 if (!ath11k_dp_rx_h_attn_msdu_done(rx_attention)) { 3919 ath11k_warn(ar->ab, 3920 "msdu_done bit not set in null_q_des processing\n"); 3921 __skb_queue_purge(msdu_list); 3922 return -EIO; 3923 } 3924 3925 /* Handle NULL queue descriptor violations arising out a missing 3926 * REO queue for a given peer or a given TID. This typically 3927 * may happen if a packet is received on a QOS enabled TID before the 3928 * ADDBA negotiation for that TID, when the TID queue is setup. Or 3929 * it may also happen for MC/BC frames if they are not routed to the 3930 * non-QOS TID queue, in the absence of any other default TID queue. 3931 * This error can show up both in a REO destination or WBM release ring. 3932 */ 3933 3934 rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ar->ab, desc); 3935 rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ar->ab, desc); 3936 3937 if (rxcb->is_frag) { 3938 skb_pull(msdu, hal_rx_desc_sz); 3939 } else { 3940 l3pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, desc); 3941 3942 if ((hal_rx_desc_sz + l3pad_bytes + msdu_len) > DP_RX_BUFFER_SIZE) 3943 return -EINVAL; 3944 3945 skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len); 3946 skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes); 3947 } 3948 ath11k_dp_rx_h_ppdu(ar, desc, status); 3949 3950 ath11k_dp_rx_h_mpdu(ar, msdu, desc, status); 3951 3952 rxcb->tid = ath11k_dp_rx_h_mpdu_start_tid(ar->ab, desc); 3953 3954 /* Please note that caller will having the access to msdu and completing 3955 * rx with mac80211. Need not worry about cleaning up amsdu_list. 3956 */ 3957 3958 return 0; 3959 } 3960 3961 static bool ath11k_dp_rx_h_reo_err(struct ath11k *ar, struct sk_buff *msdu, 3962 struct ieee80211_rx_status *status, 3963 struct sk_buff_head *msdu_list) 3964 { 3965 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 3966 bool drop = false; 3967 3968 ar->ab->soc_stats.reo_error[rxcb->err_code]++; 3969 3970 switch (rxcb->err_code) { 3971 case HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO: 3972 if (ath11k_dp_rx_h_null_q_desc(ar, msdu, status, msdu_list)) 3973 drop = true; 3974 break; 3975 case HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED: 3976 /* TODO: Do not drop PN failed packets in the driver; 3977 * instead, it is good to drop such packets in mac80211 3978 * after incrementing the replay counters. 3979 */ 3980 fallthrough; 3981 default: 3982 /* TODO: Review other errors and process them to mac80211 3983 * as appropriate. 3984 */ 3985 drop = true; 3986 break; 3987 } 3988 3989 return drop; 3990 } 3991 3992 static void ath11k_dp_rx_h_tkip_mic_err(struct ath11k *ar, struct sk_buff *msdu, 3993 struct ieee80211_rx_status *status) 3994 { 3995 u16 msdu_len; 3996 struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data; 3997 u8 l3pad_bytes; 3998 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 3999 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz; 4000 4001 rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ar->ab, desc); 4002 rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ar->ab, desc); 4003 4004 l3pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, desc); 4005 msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, desc); 4006 skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len); 4007 skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes); 4008 4009 ath11k_dp_rx_h_ppdu(ar, desc, status); 4010 4011 status->flag |= (RX_FLAG_MMIC_STRIPPED | RX_FLAG_MMIC_ERROR | 4012 RX_FLAG_DECRYPTED); 4013 4014 ath11k_dp_rx_h_undecap(ar, msdu, desc, 4015 HAL_ENCRYPT_TYPE_TKIP_MIC, status, false); 4016 } 4017 4018 static bool ath11k_dp_rx_h_rxdma_err(struct ath11k *ar, struct sk_buff *msdu, 4019 struct ieee80211_rx_status *status) 4020 { 4021 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 4022 bool drop = false; 4023 4024 ar->ab->soc_stats.rxdma_error[rxcb->err_code]++; 4025 4026 switch (rxcb->err_code) { 4027 case HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR: 4028 ath11k_dp_rx_h_tkip_mic_err(ar, msdu, status); 4029 break; 4030 default: 4031 /* TODO: Review other rxdma error code to check if anything is 4032 * worth reporting to mac80211 4033 */ 4034 drop = true; 4035 break; 4036 } 4037 4038 return drop; 4039 } 4040 4041 static void ath11k_dp_rx_wbm_err(struct ath11k *ar, 4042 struct napi_struct *napi, 4043 struct sk_buff *msdu, 4044 struct sk_buff_head *msdu_list) 4045 { 4046 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 4047 struct ieee80211_rx_status rxs = {0}; 4048 bool drop = true; 4049 4050 switch (rxcb->err_rel_src) { 4051 case HAL_WBM_REL_SRC_MODULE_REO: 4052 drop = ath11k_dp_rx_h_reo_err(ar, msdu, &rxs, msdu_list); 4053 break; 4054 case HAL_WBM_REL_SRC_MODULE_RXDMA: 4055 drop = ath11k_dp_rx_h_rxdma_err(ar, msdu, &rxs); 4056 break; 4057 default: 4058 /* msdu will get freed */ 4059 break; 4060 } 4061 4062 if (drop) { 4063 dev_kfree_skb_any(msdu); 4064 return; 4065 } 4066 4067 ath11k_dp_rx_deliver_msdu(ar, napi, msdu, &rxs); 4068 } 4069 4070 int ath11k_dp_rx_process_wbm_err(struct ath11k_base *ab, 4071 struct napi_struct *napi, int budget) 4072 { 4073 struct ath11k *ar; 4074 struct ath11k_dp *dp = &ab->dp; 4075 struct dp_rxdma_ring *rx_ring; 4076 struct hal_rx_wbm_rel_info err_info; 4077 struct hal_srng *srng; 4078 struct sk_buff *msdu; 4079 struct sk_buff_head msdu_list[MAX_RADIOS]; 4080 struct ath11k_skb_rxcb *rxcb; 4081 u32 *rx_desc; 4082 int buf_id, mac_id; 4083 int num_buffs_reaped[MAX_RADIOS] = {0}; 4084 int total_num_buffs_reaped = 0; 4085 int ret, i; 4086 4087 for (i = 0; i < ab->num_radios; i++) 4088 __skb_queue_head_init(&msdu_list[i]); 4089 4090 srng = &ab->hal.srng_list[dp->rx_rel_ring.ring_id]; 4091 4092 spin_lock_bh(&srng->lock); 4093 4094 ath11k_hal_srng_access_begin(ab, srng); 4095 4096 while (budget) { 4097 rx_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng); 4098 if (!rx_desc) 4099 break; 4100 4101 ret = ath11k_hal_wbm_desc_parse_err(ab, rx_desc, &err_info); 4102 if (ret) { 4103 ath11k_warn(ab, 4104 "failed to parse rx error in wbm_rel ring desc %d\n", 4105 ret); 4106 continue; 4107 } 4108 4109 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, err_info.cookie); 4110 mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, err_info.cookie); 4111 4112 ar = ab->pdevs[mac_id].ar; 4113 rx_ring = &ar->dp.rx_refill_buf_ring; 4114 4115 spin_lock_bh(&rx_ring->idr_lock); 4116 msdu = idr_find(&rx_ring->bufs_idr, buf_id); 4117 if (!msdu) { 4118 ath11k_warn(ab, "frame rx with invalid buf_id %d pdev %d\n", 4119 buf_id, mac_id); 4120 spin_unlock_bh(&rx_ring->idr_lock); 4121 continue; 4122 } 4123 4124 idr_remove(&rx_ring->bufs_idr, buf_id); 4125 spin_unlock_bh(&rx_ring->idr_lock); 4126 4127 rxcb = ATH11K_SKB_RXCB(msdu); 4128 dma_unmap_single(ab->dev, rxcb->paddr, 4129 msdu->len + skb_tailroom(msdu), 4130 DMA_FROM_DEVICE); 4131 4132 num_buffs_reaped[mac_id]++; 4133 total_num_buffs_reaped++; 4134 budget--; 4135 4136 if (err_info.push_reason != 4137 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) { 4138 dev_kfree_skb_any(msdu); 4139 continue; 4140 } 4141 4142 rxcb->err_rel_src = err_info.err_rel_src; 4143 rxcb->err_code = err_info.err_code; 4144 rxcb->rx_desc = (struct hal_rx_desc *)msdu->data; 4145 __skb_queue_tail(&msdu_list[mac_id], msdu); 4146 } 4147 4148 ath11k_hal_srng_access_end(ab, srng); 4149 4150 spin_unlock_bh(&srng->lock); 4151 4152 if (!total_num_buffs_reaped) 4153 goto done; 4154 4155 for (i = 0; i < ab->num_radios; i++) { 4156 if (!num_buffs_reaped[i]) 4157 continue; 4158 4159 ar = ab->pdevs[i].ar; 4160 rx_ring = &ar->dp.rx_refill_buf_ring; 4161 4162 ath11k_dp_rxbufs_replenish(ab, i, rx_ring, num_buffs_reaped[i], 4163 ab->hw_params.hal_params->rx_buf_rbm); 4164 } 4165 4166 rcu_read_lock(); 4167 for (i = 0; i < ab->num_radios; i++) { 4168 if (!rcu_dereference(ab->pdevs_active[i])) { 4169 __skb_queue_purge(&msdu_list[i]); 4170 continue; 4171 } 4172 4173 ar = ab->pdevs[i].ar; 4174 4175 if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) { 4176 __skb_queue_purge(&msdu_list[i]); 4177 continue; 4178 } 4179 4180 while ((msdu = __skb_dequeue(&msdu_list[i])) != NULL) 4181 ath11k_dp_rx_wbm_err(ar, napi, msdu, &msdu_list[i]); 4182 } 4183 rcu_read_unlock(); 4184 done: 4185 return total_num_buffs_reaped; 4186 } 4187 4188 int ath11k_dp_process_rxdma_err(struct ath11k_base *ab, int mac_id, int budget) 4189 { 4190 struct ath11k *ar; 4191 struct dp_srng *err_ring; 4192 struct dp_rxdma_ring *rx_ring; 4193 struct dp_link_desc_bank *link_desc_banks = ab->dp.link_desc_banks; 4194 struct hal_srng *srng; 4195 u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC]; 4196 enum hal_rx_buf_return_buf_manager rbm; 4197 enum hal_reo_entr_rxdma_ecode rxdma_err_code; 4198 struct ath11k_skb_rxcb *rxcb; 4199 struct sk_buff *skb; 4200 struct hal_reo_entrance_ring *entr_ring; 4201 void *desc; 4202 int num_buf_freed = 0; 4203 int quota = budget; 4204 dma_addr_t paddr; 4205 u32 desc_bank; 4206 void *link_desc_va; 4207 int num_msdus; 4208 int i; 4209 int buf_id; 4210 4211 ar = ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar; 4212 err_ring = &ar->dp.rxdma_err_dst_ring[ath11k_hw_mac_id_to_srng_id(&ab->hw_params, 4213 mac_id)]; 4214 rx_ring = &ar->dp.rx_refill_buf_ring; 4215 4216 srng = &ab->hal.srng_list[err_ring->ring_id]; 4217 4218 spin_lock_bh(&srng->lock); 4219 4220 ath11k_hal_srng_access_begin(ab, srng); 4221 4222 while (quota-- && 4223 (desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) { 4224 ath11k_hal_rx_reo_ent_paddr_get(ab, desc, &paddr, &desc_bank); 4225 4226 entr_ring = (struct hal_reo_entrance_ring *)desc; 4227 rxdma_err_code = 4228 FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE, 4229 entr_ring->info1); 4230 ab->soc_stats.rxdma_error[rxdma_err_code]++; 4231 4232 link_desc_va = link_desc_banks[desc_bank].vaddr + 4233 (paddr - link_desc_banks[desc_bank].paddr); 4234 ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus, 4235 msdu_cookies, &rbm); 4236 4237 for (i = 0; i < num_msdus; i++) { 4238 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, 4239 msdu_cookies[i]); 4240 4241 spin_lock_bh(&rx_ring->idr_lock); 4242 skb = idr_find(&rx_ring->bufs_idr, buf_id); 4243 if (!skb) { 4244 ath11k_warn(ab, "rxdma error with invalid buf_id %d\n", 4245 buf_id); 4246 spin_unlock_bh(&rx_ring->idr_lock); 4247 continue; 4248 } 4249 4250 idr_remove(&rx_ring->bufs_idr, buf_id); 4251 spin_unlock_bh(&rx_ring->idr_lock); 4252 4253 rxcb = ATH11K_SKB_RXCB(skb); 4254 dma_unmap_single(ab->dev, rxcb->paddr, 4255 skb->len + skb_tailroom(skb), 4256 DMA_FROM_DEVICE); 4257 dev_kfree_skb_any(skb); 4258 4259 num_buf_freed++; 4260 } 4261 4262 ath11k_dp_rx_link_desc_return(ab, desc, 4263 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 4264 } 4265 4266 ath11k_hal_srng_access_end(ab, srng); 4267 4268 spin_unlock_bh(&srng->lock); 4269 4270 if (num_buf_freed) 4271 ath11k_dp_rxbufs_replenish(ab, mac_id, rx_ring, num_buf_freed, 4272 ab->hw_params.hal_params->rx_buf_rbm); 4273 4274 return budget - quota; 4275 } 4276 4277 void ath11k_dp_process_reo_status(struct ath11k_base *ab) 4278 { 4279 struct ath11k_dp *dp = &ab->dp; 4280 struct hal_srng *srng; 4281 struct dp_reo_cmd *cmd, *tmp; 4282 bool found = false; 4283 u32 *reo_desc; 4284 u16 tag; 4285 struct hal_reo_status reo_status; 4286 4287 srng = &ab->hal.srng_list[dp->reo_status_ring.ring_id]; 4288 4289 memset(&reo_status, 0, sizeof(reo_status)); 4290 4291 spin_lock_bh(&srng->lock); 4292 4293 ath11k_hal_srng_access_begin(ab, srng); 4294 4295 while ((reo_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) { 4296 tag = FIELD_GET(HAL_SRNG_TLV_HDR_TAG, *reo_desc); 4297 4298 switch (tag) { 4299 case HAL_REO_GET_QUEUE_STATS_STATUS: 4300 ath11k_hal_reo_status_queue_stats(ab, reo_desc, 4301 &reo_status); 4302 break; 4303 case HAL_REO_FLUSH_QUEUE_STATUS: 4304 ath11k_hal_reo_flush_queue_status(ab, reo_desc, 4305 &reo_status); 4306 break; 4307 case HAL_REO_FLUSH_CACHE_STATUS: 4308 ath11k_hal_reo_flush_cache_status(ab, reo_desc, 4309 &reo_status); 4310 break; 4311 case HAL_REO_UNBLOCK_CACHE_STATUS: 4312 ath11k_hal_reo_unblk_cache_status(ab, reo_desc, 4313 &reo_status); 4314 break; 4315 case HAL_REO_FLUSH_TIMEOUT_LIST_STATUS: 4316 ath11k_hal_reo_flush_timeout_list_status(ab, reo_desc, 4317 &reo_status); 4318 break; 4319 case HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS: 4320 ath11k_hal_reo_desc_thresh_reached_status(ab, reo_desc, 4321 &reo_status); 4322 break; 4323 case HAL_REO_UPDATE_RX_REO_QUEUE_STATUS: 4324 ath11k_hal_reo_update_rx_reo_queue_status(ab, reo_desc, 4325 &reo_status); 4326 break; 4327 default: 4328 ath11k_warn(ab, "Unknown reo status type %d\n", tag); 4329 continue; 4330 } 4331 4332 spin_lock_bh(&dp->reo_cmd_lock); 4333 list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) { 4334 if (reo_status.uniform_hdr.cmd_num == cmd->cmd_num) { 4335 found = true; 4336 list_del(&cmd->list); 4337 break; 4338 } 4339 } 4340 spin_unlock_bh(&dp->reo_cmd_lock); 4341 4342 if (found) { 4343 cmd->handler(dp, (void *)&cmd->data, 4344 reo_status.uniform_hdr.cmd_status); 4345 kfree(cmd); 4346 } 4347 4348 found = false; 4349 } 4350 4351 ath11k_hal_srng_access_end(ab, srng); 4352 4353 spin_unlock_bh(&srng->lock); 4354 } 4355 4356 void ath11k_dp_rx_pdev_free(struct ath11k_base *ab, int mac_id) 4357 { 4358 struct ath11k *ar = ab->pdevs[mac_id].ar; 4359 4360 ath11k_dp_rx_pdev_srng_free(ar); 4361 ath11k_dp_rxdma_pdev_buf_free(ar); 4362 } 4363 4364 int ath11k_dp_rx_pdev_alloc(struct ath11k_base *ab, int mac_id) 4365 { 4366 struct ath11k *ar = ab->pdevs[mac_id].ar; 4367 struct ath11k_pdev_dp *dp = &ar->dp; 4368 u32 ring_id; 4369 int i; 4370 int ret; 4371 4372 ret = ath11k_dp_rx_pdev_srng_alloc(ar); 4373 if (ret) { 4374 ath11k_warn(ab, "failed to setup rx srngs\n"); 4375 return ret; 4376 } 4377 4378 ret = ath11k_dp_rxdma_pdev_buf_setup(ar); 4379 if (ret) { 4380 ath11k_warn(ab, "failed to setup rxdma ring\n"); 4381 return ret; 4382 } 4383 4384 ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id; 4385 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, mac_id, HAL_RXDMA_BUF); 4386 if (ret) { 4387 ath11k_warn(ab, "failed to configure rx_refill_buf_ring %d\n", 4388 ret); 4389 return ret; 4390 } 4391 4392 if (ab->hw_params.rx_mac_buf_ring) { 4393 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 4394 ring_id = dp->rx_mac_buf_ring[i].ring_id; 4395 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, 4396 mac_id + i, HAL_RXDMA_BUF); 4397 if (ret) { 4398 ath11k_warn(ab, "failed to configure rx_mac_buf_ring%d %d\n", 4399 i, ret); 4400 return ret; 4401 } 4402 } 4403 } 4404 4405 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 4406 ring_id = dp->rxdma_err_dst_ring[i].ring_id; 4407 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, 4408 mac_id + i, HAL_RXDMA_DST); 4409 if (ret) { 4410 ath11k_warn(ab, "failed to configure rxdma_err_dest_ring%d %d\n", 4411 i, ret); 4412 return ret; 4413 } 4414 } 4415 4416 if (!ab->hw_params.rxdma1_enable) 4417 goto config_refill_ring; 4418 4419 ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id; 4420 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, 4421 mac_id, HAL_RXDMA_MONITOR_BUF); 4422 if (ret) { 4423 ath11k_warn(ab, "failed to configure rxdma_mon_buf_ring %d\n", 4424 ret); 4425 return ret; 4426 } 4427 ret = ath11k_dp_tx_htt_srng_setup(ab, 4428 dp->rxdma_mon_dst_ring.ring_id, 4429 mac_id, HAL_RXDMA_MONITOR_DST); 4430 if (ret) { 4431 ath11k_warn(ab, "failed to configure rxdma_mon_dst_ring %d\n", 4432 ret); 4433 return ret; 4434 } 4435 ret = ath11k_dp_tx_htt_srng_setup(ab, 4436 dp->rxdma_mon_desc_ring.ring_id, 4437 mac_id, HAL_RXDMA_MONITOR_DESC); 4438 if (ret) { 4439 ath11k_warn(ab, "failed to configure rxdma_mon_dst_ring %d\n", 4440 ret); 4441 return ret; 4442 } 4443 4444 config_refill_ring: 4445 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 4446 ring_id = dp->rx_mon_status_refill_ring[i].refill_buf_ring.ring_id; 4447 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, mac_id + i, 4448 HAL_RXDMA_MONITOR_STATUS); 4449 if (ret) { 4450 ath11k_warn(ab, 4451 "failed to configure mon_status_refill_ring%d %d\n", 4452 i, ret); 4453 return ret; 4454 } 4455 } 4456 4457 return 0; 4458 } 4459 4460 static void ath11k_dp_mon_set_frag_len(u32 *total_len, u32 *frag_len) 4461 { 4462 if (*total_len >= (DP_RX_BUFFER_SIZE - sizeof(struct hal_rx_desc))) { 4463 *frag_len = DP_RX_BUFFER_SIZE - sizeof(struct hal_rx_desc); 4464 *total_len -= *frag_len; 4465 } else { 4466 *frag_len = *total_len; 4467 *total_len = 0; 4468 } 4469 } 4470 4471 static 4472 int ath11k_dp_rx_monitor_link_desc_return(struct ath11k *ar, 4473 void *p_last_buf_addr_info, 4474 u8 mac_id) 4475 { 4476 struct ath11k_pdev_dp *dp = &ar->dp; 4477 struct dp_srng *dp_srng; 4478 void *hal_srng; 4479 void *src_srng_desc; 4480 int ret = 0; 4481 4482 if (ar->ab->hw_params.rxdma1_enable) { 4483 dp_srng = &dp->rxdma_mon_desc_ring; 4484 hal_srng = &ar->ab->hal.srng_list[dp_srng->ring_id]; 4485 } else { 4486 dp_srng = &ar->ab->dp.wbm_desc_rel_ring; 4487 hal_srng = &ar->ab->hal.srng_list[dp_srng->ring_id]; 4488 } 4489 4490 ath11k_hal_srng_access_begin(ar->ab, hal_srng); 4491 4492 src_srng_desc = ath11k_hal_srng_src_get_next_entry(ar->ab, hal_srng); 4493 4494 if (src_srng_desc) { 4495 struct ath11k_buffer_addr *src_desc = src_srng_desc; 4496 4497 *src_desc = *((struct ath11k_buffer_addr *)p_last_buf_addr_info); 4498 } else { 4499 ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 4500 "Monitor Link Desc Ring %d Full", mac_id); 4501 ret = -ENOMEM; 4502 } 4503 4504 ath11k_hal_srng_access_end(ar->ab, hal_srng); 4505 return ret; 4506 } 4507 4508 static 4509 void ath11k_dp_rx_mon_next_link_desc_get(void *rx_msdu_link_desc, 4510 dma_addr_t *paddr, u32 *sw_cookie, 4511 u8 *rbm, 4512 void **pp_buf_addr_info) 4513 { 4514 struct hal_rx_msdu_link *msdu_link = rx_msdu_link_desc; 4515 struct ath11k_buffer_addr *buf_addr_info; 4516 4517 buf_addr_info = (struct ath11k_buffer_addr *)&msdu_link->buf_addr_info; 4518 4519 ath11k_hal_rx_buf_addr_info_get(buf_addr_info, paddr, sw_cookie, rbm); 4520 4521 *pp_buf_addr_info = (void *)buf_addr_info; 4522 } 4523 4524 static int ath11k_dp_pkt_set_pktlen(struct sk_buff *skb, u32 len) 4525 { 4526 if (skb->len > len) { 4527 skb_trim(skb, len); 4528 } else { 4529 if (skb_tailroom(skb) < len - skb->len) { 4530 if ((pskb_expand_head(skb, 0, 4531 len - skb->len - skb_tailroom(skb), 4532 GFP_ATOMIC))) { 4533 dev_kfree_skb_any(skb); 4534 return -ENOMEM; 4535 } 4536 } 4537 skb_put(skb, (len - skb->len)); 4538 } 4539 return 0; 4540 } 4541 4542 static void ath11k_hal_rx_msdu_list_get(struct ath11k *ar, 4543 void *msdu_link_desc, 4544 struct hal_rx_msdu_list *msdu_list, 4545 u16 *num_msdus) 4546 { 4547 struct hal_rx_msdu_details *msdu_details = NULL; 4548 struct rx_msdu_desc *msdu_desc_info = NULL; 4549 struct hal_rx_msdu_link *msdu_link = NULL; 4550 int i; 4551 u32 last = FIELD_PREP(RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU, 1); 4552 u32 first = FIELD_PREP(RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU, 1); 4553 u8 tmp = 0; 4554 4555 msdu_link = msdu_link_desc; 4556 msdu_details = &msdu_link->msdu_link[0]; 4557 4558 for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) { 4559 if (FIELD_GET(BUFFER_ADDR_INFO0_ADDR, 4560 msdu_details[i].buf_addr_info.info0) == 0) { 4561 msdu_desc_info = &msdu_details[i - 1].rx_msdu_info; 4562 msdu_desc_info->info0 |= last; 4563 ; 4564 break; 4565 } 4566 msdu_desc_info = &msdu_details[i].rx_msdu_info; 4567 4568 if (!i) 4569 msdu_desc_info->info0 |= first; 4570 else if (i == (HAL_RX_NUM_MSDU_DESC - 1)) 4571 msdu_desc_info->info0 |= last; 4572 msdu_list->msdu_info[i].msdu_flags = msdu_desc_info->info0; 4573 msdu_list->msdu_info[i].msdu_len = 4574 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info->info0); 4575 msdu_list->sw_cookie[i] = 4576 FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, 4577 msdu_details[i].buf_addr_info.info1); 4578 tmp = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR, 4579 msdu_details[i].buf_addr_info.info1); 4580 msdu_list->rbm[i] = tmp; 4581 } 4582 *num_msdus = i; 4583 } 4584 4585 static u32 ath11k_dp_rx_mon_comp_ppduid(u32 msdu_ppdu_id, u32 *ppdu_id, 4586 u32 *rx_bufs_used) 4587 { 4588 u32 ret = 0; 4589 4590 if ((*ppdu_id < msdu_ppdu_id) && 4591 ((msdu_ppdu_id - *ppdu_id) < DP_NOT_PPDU_ID_WRAP_AROUND)) { 4592 *ppdu_id = msdu_ppdu_id; 4593 ret = msdu_ppdu_id; 4594 } else if ((*ppdu_id > msdu_ppdu_id) && 4595 ((*ppdu_id - msdu_ppdu_id) > DP_NOT_PPDU_ID_WRAP_AROUND)) { 4596 /* mon_dst is behind than mon_status 4597 * skip dst_ring and free it 4598 */ 4599 *rx_bufs_used += 1; 4600 *ppdu_id = msdu_ppdu_id; 4601 ret = msdu_ppdu_id; 4602 } 4603 return ret; 4604 } 4605 4606 static void ath11k_dp_mon_get_buf_len(struct hal_rx_msdu_desc_info *info, 4607 bool *is_frag, u32 *total_len, 4608 u32 *frag_len, u32 *msdu_cnt) 4609 { 4610 if (info->msdu_flags & RX_MSDU_DESC_INFO0_MSDU_CONTINUATION) { 4611 if (!*is_frag) { 4612 *total_len = info->msdu_len; 4613 *is_frag = true; 4614 } 4615 ath11k_dp_mon_set_frag_len(total_len, 4616 frag_len); 4617 } else { 4618 if (*is_frag) { 4619 ath11k_dp_mon_set_frag_len(total_len, 4620 frag_len); 4621 } else { 4622 *frag_len = info->msdu_len; 4623 } 4624 *is_frag = false; 4625 *msdu_cnt -= 1; 4626 } 4627 } 4628 4629 static u32 4630 ath11k_dp_rx_mon_mpdu_pop(struct ath11k *ar, int mac_id, 4631 void *ring_entry, struct sk_buff **head_msdu, 4632 struct sk_buff **tail_msdu, u32 *npackets, 4633 u32 *ppdu_id) 4634 { 4635 struct ath11k_pdev_dp *dp = &ar->dp; 4636 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data; 4637 struct dp_rxdma_ring *rx_ring = &dp->rxdma_mon_buf_ring; 4638 struct sk_buff *msdu = NULL, *last = NULL; 4639 struct hal_rx_msdu_list msdu_list; 4640 void *p_buf_addr_info, *p_last_buf_addr_info; 4641 struct hal_rx_desc *rx_desc; 4642 void *rx_msdu_link_desc; 4643 dma_addr_t paddr; 4644 u16 num_msdus = 0; 4645 u32 rx_buf_size, rx_pkt_offset, sw_cookie; 4646 u32 rx_bufs_used = 0, i = 0; 4647 u32 msdu_ppdu_id = 0, msdu_cnt = 0; 4648 u32 total_len = 0, frag_len = 0; 4649 bool is_frag, is_first_msdu; 4650 bool drop_mpdu = false; 4651 struct ath11k_skb_rxcb *rxcb; 4652 struct hal_reo_entrance_ring *ent_desc = ring_entry; 4653 int buf_id; 4654 u32 rx_link_buf_info[2]; 4655 u8 rbm; 4656 4657 if (!ar->ab->hw_params.rxdma1_enable) 4658 rx_ring = &dp->rx_refill_buf_ring; 4659 4660 ath11k_hal_rx_reo_ent_buf_paddr_get(ring_entry, &paddr, 4661 &sw_cookie, 4662 &p_last_buf_addr_info, &rbm, 4663 &msdu_cnt); 4664 4665 if (FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_PUSH_REASON, 4666 ent_desc->info1) == 4667 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) { 4668 u8 rxdma_err = 4669 FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE, 4670 ent_desc->info1); 4671 if (rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR || 4672 rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR || 4673 rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR) { 4674 drop_mpdu = true; 4675 pmon->rx_mon_stats.dest_mpdu_drop++; 4676 } 4677 } 4678 4679 is_frag = false; 4680 is_first_msdu = true; 4681 4682 do { 4683 if (pmon->mon_last_linkdesc_paddr == paddr) { 4684 pmon->rx_mon_stats.dup_mon_linkdesc_cnt++; 4685 return rx_bufs_used; 4686 } 4687 4688 if (ar->ab->hw_params.rxdma1_enable) 4689 rx_msdu_link_desc = 4690 (void *)pmon->link_desc_banks[sw_cookie].vaddr + 4691 (paddr - pmon->link_desc_banks[sw_cookie].paddr); 4692 else 4693 rx_msdu_link_desc = 4694 (void *)ar->ab->dp.link_desc_banks[sw_cookie].vaddr + 4695 (paddr - ar->ab->dp.link_desc_banks[sw_cookie].paddr); 4696 4697 ath11k_hal_rx_msdu_list_get(ar, rx_msdu_link_desc, &msdu_list, 4698 &num_msdus); 4699 4700 for (i = 0; i < num_msdus; i++) { 4701 u32 l2_hdr_offset; 4702 4703 if (pmon->mon_last_buf_cookie == msdu_list.sw_cookie[i]) { 4704 ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 4705 "i %d last_cookie %d is same\n", 4706 i, pmon->mon_last_buf_cookie); 4707 drop_mpdu = true; 4708 pmon->rx_mon_stats.dup_mon_buf_cnt++; 4709 continue; 4710 } 4711 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, 4712 msdu_list.sw_cookie[i]); 4713 4714 spin_lock_bh(&rx_ring->idr_lock); 4715 msdu = idr_find(&rx_ring->bufs_idr, buf_id); 4716 spin_unlock_bh(&rx_ring->idr_lock); 4717 if (!msdu) { 4718 ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 4719 "msdu_pop: invalid buf_id %d\n", buf_id); 4720 break; 4721 } 4722 rxcb = ATH11K_SKB_RXCB(msdu); 4723 if (!rxcb->unmapped) { 4724 dma_unmap_single(ar->ab->dev, rxcb->paddr, 4725 msdu->len + 4726 skb_tailroom(msdu), 4727 DMA_FROM_DEVICE); 4728 rxcb->unmapped = 1; 4729 } 4730 if (drop_mpdu) { 4731 ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 4732 "i %d drop msdu %p *ppdu_id %x\n", 4733 i, msdu, *ppdu_id); 4734 dev_kfree_skb_any(msdu); 4735 msdu = NULL; 4736 goto next_msdu; 4737 } 4738 4739 rx_desc = (struct hal_rx_desc *)msdu->data; 4740 4741 rx_pkt_offset = sizeof(struct hal_rx_desc); 4742 l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, rx_desc); 4743 4744 if (is_first_msdu) { 4745 if (!ath11k_dp_rxdesc_mpdu_valid(ar->ab, rx_desc)) { 4746 drop_mpdu = true; 4747 dev_kfree_skb_any(msdu); 4748 msdu = NULL; 4749 pmon->mon_last_linkdesc_paddr = paddr; 4750 goto next_msdu; 4751 } 4752 4753 msdu_ppdu_id = 4754 ath11k_dp_rxdesc_get_ppduid(ar->ab, rx_desc); 4755 4756 if (ath11k_dp_rx_mon_comp_ppduid(msdu_ppdu_id, 4757 ppdu_id, 4758 &rx_bufs_used)) { 4759 if (rx_bufs_used) { 4760 drop_mpdu = true; 4761 dev_kfree_skb_any(msdu); 4762 msdu = NULL; 4763 goto next_msdu; 4764 } 4765 return rx_bufs_used; 4766 } 4767 pmon->mon_last_linkdesc_paddr = paddr; 4768 is_first_msdu = false; 4769 } 4770 ath11k_dp_mon_get_buf_len(&msdu_list.msdu_info[i], 4771 &is_frag, &total_len, 4772 &frag_len, &msdu_cnt); 4773 rx_buf_size = rx_pkt_offset + l2_hdr_offset + frag_len; 4774 4775 ath11k_dp_pkt_set_pktlen(msdu, rx_buf_size); 4776 4777 if (!(*head_msdu)) 4778 *head_msdu = msdu; 4779 else if (last) 4780 last->next = msdu; 4781 4782 last = msdu; 4783 next_msdu: 4784 pmon->mon_last_buf_cookie = msdu_list.sw_cookie[i]; 4785 rx_bufs_used++; 4786 spin_lock_bh(&rx_ring->idr_lock); 4787 idr_remove(&rx_ring->bufs_idr, buf_id); 4788 spin_unlock_bh(&rx_ring->idr_lock); 4789 } 4790 4791 ath11k_hal_rx_buf_addr_info_set(rx_link_buf_info, paddr, sw_cookie, rbm); 4792 4793 ath11k_dp_rx_mon_next_link_desc_get(rx_msdu_link_desc, &paddr, 4794 &sw_cookie, &rbm, 4795 &p_buf_addr_info); 4796 4797 if (ar->ab->hw_params.rxdma1_enable) { 4798 if (ath11k_dp_rx_monitor_link_desc_return(ar, 4799 p_last_buf_addr_info, 4800 dp->mac_id)) 4801 ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 4802 "dp_rx_monitor_link_desc_return failed"); 4803 } else { 4804 ath11k_dp_rx_link_desc_return(ar->ab, rx_link_buf_info, 4805 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 4806 } 4807 4808 p_last_buf_addr_info = p_buf_addr_info; 4809 4810 } while (paddr && msdu_cnt); 4811 4812 if (last) 4813 last->next = NULL; 4814 4815 *tail_msdu = msdu; 4816 4817 if (msdu_cnt == 0) 4818 *npackets = 1; 4819 4820 return rx_bufs_used; 4821 } 4822 4823 static void ath11k_dp_rx_msdus_set_payload(struct ath11k *ar, struct sk_buff *msdu) 4824 { 4825 u32 rx_pkt_offset, l2_hdr_offset; 4826 4827 rx_pkt_offset = ar->ab->hw_params.hal_desc_sz; 4828 l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, 4829 (struct hal_rx_desc *)msdu->data); 4830 skb_pull(msdu, rx_pkt_offset + l2_hdr_offset); 4831 } 4832 4833 static struct sk_buff * 4834 ath11k_dp_rx_mon_merg_msdus(struct ath11k *ar, 4835 u32 mac_id, struct sk_buff *head_msdu, 4836 struct sk_buff *last_msdu, 4837 struct ieee80211_rx_status *rxs, bool *fcs_err) 4838 { 4839 struct ath11k_base *ab = ar->ab; 4840 struct sk_buff *msdu, *prev_buf; 4841 struct hal_rx_desc *rx_desc; 4842 char *hdr_desc; 4843 u8 *dest, decap_format; 4844 struct ieee80211_hdr_3addr *wh; 4845 struct rx_attention *rx_attention; 4846 u32 err_bitmap; 4847 4848 if (!head_msdu) 4849 goto err_merge_fail; 4850 4851 rx_desc = (struct hal_rx_desc *)head_msdu->data; 4852 rx_attention = ath11k_dp_rx_get_attention(ab, rx_desc); 4853 err_bitmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention); 4854 4855 if (err_bitmap & DP_RX_MPDU_ERR_FCS) 4856 *fcs_err = true; 4857 4858 if (ath11k_dp_rxdesc_get_mpdulen_err(rx_attention)) 4859 return NULL; 4860 4861 decap_format = ath11k_dp_rx_h_msdu_start_decap_type(ab, rx_desc); 4862 4863 ath11k_dp_rx_h_ppdu(ar, rx_desc, rxs); 4864 4865 if (decap_format == DP_RX_DECAP_TYPE_RAW) { 4866 ath11k_dp_rx_msdus_set_payload(ar, head_msdu); 4867 4868 prev_buf = head_msdu; 4869 msdu = head_msdu->next; 4870 4871 while (msdu) { 4872 ath11k_dp_rx_msdus_set_payload(ar, msdu); 4873 4874 prev_buf = msdu; 4875 msdu = msdu->next; 4876 } 4877 4878 prev_buf->next = NULL; 4879 4880 skb_trim(prev_buf, prev_buf->len - HAL_RX_FCS_LEN); 4881 } else if (decap_format == DP_RX_DECAP_TYPE_NATIVE_WIFI) { 4882 u8 qos_pkt = 0; 4883 4884 rx_desc = (struct hal_rx_desc *)head_msdu->data; 4885 hdr_desc = ath11k_dp_rxdesc_get_80211hdr(ab, rx_desc); 4886 4887 /* Base size */ 4888 wh = (struct ieee80211_hdr_3addr *)hdr_desc; 4889 4890 if (ieee80211_is_data_qos(wh->frame_control)) 4891 qos_pkt = 1; 4892 4893 msdu = head_msdu; 4894 4895 while (msdu) { 4896 ath11k_dp_rx_msdus_set_payload(ar, msdu); 4897 if (qos_pkt) { 4898 dest = skb_push(msdu, sizeof(__le16)); 4899 if (!dest) 4900 goto err_merge_fail; 4901 memcpy(dest, hdr_desc, sizeof(struct ieee80211_qos_hdr)); 4902 } 4903 prev_buf = msdu; 4904 msdu = msdu->next; 4905 } 4906 dest = skb_put(prev_buf, HAL_RX_FCS_LEN); 4907 if (!dest) 4908 goto err_merge_fail; 4909 4910 ath11k_dbg(ab, ATH11K_DBG_DATA, 4911 "mpdu_buf %p mpdu_buf->len %u", 4912 prev_buf, prev_buf->len); 4913 } else { 4914 ath11k_dbg(ab, ATH11K_DBG_DATA, 4915 "decap format %d is not supported!\n", 4916 decap_format); 4917 goto err_merge_fail; 4918 } 4919 4920 return head_msdu; 4921 4922 err_merge_fail: 4923 return NULL; 4924 } 4925 4926 static void 4927 ath11k_dp_rx_update_radiotap_he(struct hal_rx_mon_ppdu_info *rx_status, 4928 u8 *rtap_buf) 4929 { 4930 u32 rtap_len = 0; 4931 4932 put_unaligned_le16(rx_status->he_data1, &rtap_buf[rtap_len]); 4933 rtap_len += 2; 4934 4935 put_unaligned_le16(rx_status->he_data2, &rtap_buf[rtap_len]); 4936 rtap_len += 2; 4937 4938 put_unaligned_le16(rx_status->he_data3, &rtap_buf[rtap_len]); 4939 rtap_len += 2; 4940 4941 put_unaligned_le16(rx_status->he_data4, &rtap_buf[rtap_len]); 4942 rtap_len += 2; 4943 4944 put_unaligned_le16(rx_status->he_data5, &rtap_buf[rtap_len]); 4945 rtap_len += 2; 4946 4947 put_unaligned_le16(rx_status->he_data6, &rtap_buf[rtap_len]); 4948 } 4949 4950 static void 4951 ath11k_dp_rx_update_radiotap_he_mu(struct hal_rx_mon_ppdu_info *rx_status, 4952 u8 *rtap_buf) 4953 { 4954 u32 rtap_len = 0; 4955 4956 put_unaligned_le16(rx_status->he_flags1, &rtap_buf[rtap_len]); 4957 rtap_len += 2; 4958 4959 put_unaligned_le16(rx_status->he_flags2, &rtap_buf[rtap_len]); 4960 rtap_len += 2; 4961 4962 rtap_buf[rtap_len] = rx_status->he_RU[0]; 4963 rtap_len += 1; 4964 4965 rtap_buf[rtap_len] = rx_status->he_RU[1]; 4966 rtap_len += 1; 4967 4968 rtap_buf[rtap_len] = rx_status->he_RU[2]; 4969 rtap_len += 1; 4970 4971 rtap_buf[rtap_len] = rx_status->he_RU[3]; 4972 } 4973 4974 static void ath11k_update_radiotap(struct ath11k *ar, 4975 struct hal_rx_mon_ppdu_info *ppduinfo, 4976 struct sk_buff *mon_skb, 4977 struct ieee80211_rx_status *rxs) 4978 { 4979 struct ieee80211_supported_band *sband; 4980 u8 *ptr = NULL; 4981 4982 rxs->flag |= RX_FLAG_MACTIME_START; 4983 rxs->signal = ppduinfo->rssi_comb + ATH11K_DEFAULT_NOISE_FLOOR; 4984 4985 if (ppduinfo->nss) 4986 rxs->nss = ppduinfo->nss; 4987 4988 if (ppduinfo->he_mu_flags) { 4989 rxs->flag |= RX_FLAG_RADIOTAP_HE_MU; 4990 rxs->encoding = RX_ENC_HE; 4991 ptr = skb_push(mon_skb, sizeof(struct ieee80211_radiotap_he_mu)); 4992 ath11k_dp_rx_update_radiotap_he_mu(ppduinfo, ptr); 4993 } else if (ppduinfo->he_flags) { 4994 rxs->flag |= RX_FLAG_RADIOTAP_HE; 4995 rxs->encoding = RX_ENC_HE; 4996 ptr = skb_push(mon_skb, sizeof(struct ieee80211_radiotap_he)); 4997 ath11k_dp_rx_update_radiotap_he(ppduinfo, ptr); 4998 rxs->rate_idx = ppduinfo->rate; 4999 } else if (ppduinfo->vht_flags) { 5000 rxs->encoding = RX_ENC_VHT; 5001 rxs->rate_idx = ppduinfo->rate; 5002 } else if (ppduinfo->ht_flags) { 5003 rxs->encoding = RX_ENC_HT; 5004 rxs->rate_idx = ppduinfo->rate; 5005 } else { 5006 rxs->encoding = RX_ENC_LEGACY; 5007 sband = &ar->mac.sbands[rxs->band]; 5008 rxs->rate_idx = ath11k_mac_hw_rate_to_idx(sband, ppduinfo->rate, 5009 ppduinfo->cck_flag); 5010 } 5011 5012 rxs->mactime = ppduinfo->tsft; 5013 } 5014 5015 static int ath11k_dp_rx_mon_deliver(struct ath11k *ar, u32 mac_id, 5016 struct sk_buff *head_msdu, 5017 struct hal_rx_mon_ppdu_info *ppduinfo, 5018 struct sk_buff *tail_msdu, 5019 struct napi_struct *napi) 5020 { 5021 struct ath11k_pdev_dp *dp = &ar->dp; 5022 struct sk_buff *mon_skb, *skb_next, *header; 5023 struct ieee80211_rx_status *rxs = &dp->rx_status; 5024 bool fcs_err = false; 5025 5026 mon_skb = ath11k_dp_rx_mon_merg_msdus(ar, mac_id, head_msdu, 5027 tail_msdu, rxs, &fcs_err); 5028 5029 if (!mon_skb) 5030 goto mon_deliver_fail; 5031 5032 header = mon_skb; 5033 5034 rxs->flag = 0; 5035 5036 if (fcs_err) 5037 rxs->flag = RX_FLAG_FAILED_FCS_CRC; 5038 5039 do { 5040 skb_next = mon_skb->next; 5041 if (!skb_next) 5042 rxs->flag &= ~RX_FLAG_AMSDU_MORE; 5043 else 5044 rxs->flag |= RX_FLAG_AMSDU_MORE; 5045 5046 if (mon_skb == header) { 5047 header = NULL; 5048 rxs->flag &= ~RX_FLAG_ALLOW_SAME_PN; 5049 } else { 5050 rxs->flag |= RX_FLAG_ALLOW_SAME_PN; 5051 } 5052 rxs->flag |= RX_FLAG_ONLY_MONITOR; 5053 ath11k_update_radiotap(ar, ppduinfo, mon_skb, rxs); 5054 5055 ath11k_dp_rx_deliver_msdu(ar, napi, mon_skb, rxs); 5056 mon_skb = skb_next; 5057 } while (mon_skb); 5058 rxs->flag = 0; 5059 5060 return 0; 5061 5062 mon_deliver_fail: 5063 mon_skb = head_msdu; 5064 while (mon_skb) { 5065 skb_next = mon_skb->next; 5066 dev_kfree_skb_any(mon_skb); 5067 mon_skb = skb_next; 5068 } 5069 return -EINVAL; 5070 } 5071 5072 /* The destination ring processing is stuck if the destination is not 5073 * moving while status ring moves 16 PPDU. The destination ring processing 5074 * skips this destination ring PPDU as a workaround. 5075 */ 5076 #define MON_DEST_RING_STUCK_MAX_CNT 16 5077 5078 static void ath11k_dp_rx_mon_dest_process(struct ath11k *ar, int mac_id, 5079 u32 quota, struct napi_struct *napi) 5080 { 5081 struct ath11k_pdev_dp *dp = &ar->dp; 5082 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data; 5083 const struct ath11k_hw_hal_params *hal_params; 5084 void *ring_entry; 5085 void *mon_dst_srng; 5086 u32 ppdu_id; 5087 u32 rx_bufs_used; 5088 u32 ring_id; 5089 struct ath11k_pdev_mon_stats *rx_mon_stats; 5090 u32 npackets = 0; 5091 u32 mpdu_rx_bufs_used; 5092 5093 if (ar->ab->hw_params.rxdma1_enable) 5094 ring_id = dp->rxdma_mon_dst_ring.ring_id; 5095 else 5096 ring_id = dp->rxdma_err_dst_ring[mac_id].ring_id; 5097 5098 mon_dst_srng = &ar->ab->hal.srng_list[ring_id]; 5099 5100 spin_lock_bh(&pmon->mon_lock); 5101 5102 ath11k_hal_srng_access_begin(ar->ab, mon_dst_srng); 5103 5104 ppdu_id = pmon->mon_ppdu_info.ppdu_id; 5105 rx_bufs_used = 0; 5106 rx_mon_stats = &pmon->rx_mon_stats; 5107 5108 while ((ring_entry = ath11k_hal_srng_dst_peek(ar->ab, mon_dst_srng))) { 5109 struct sk_buff *head_msdu, *tail_msdu; 5110 5111 head_msdu = NULL; 5112 tail_msdu = NULL; 5113 5114 mpdu_rx_bufs_used = ath11k_dp_rx_mon_mpdu_pop(ar, mac_id, ring_entry, 5115 &head_msdu, 5116 &tail_msdu, 5117 &npackets, &ppdu_id); 5118 5119 rx_bufs_used += mpdu_rx_bufs_used; 5120 5121 if (mpdu_rx_bufs_used) { 5122 dp->mon_dest_ring_stuck_cnt = 0; 5123 } else { 5124 dp->mon_dest_ring_stuck_cnt++; 5125 rx_mon_stats->dest_mon_not_reaped++; 5126 } 5127 5128 if (dp->mon_dest_ring_stuck_cnt > MON_DEST_RING_STUCK_MAX_CNT) { 5129 rx_mon_stats->dest_mon_stuck++; 5130 ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 5131 "status ring ppdu_id=%d dest ring ppdu_id=%d mon_dest_ring_stuck_cnt=%d dest_mon_not_reaped=%u dest_mon_stuck=%u\n", 5132 pmon->mon_ppdu_info.ppdu_id, ppdu_id, 5133 dp->mon_dest_ring_stuck_cnt, 5134 rx_mon_stats->dest_mon_not_reaped, 5135 rx_mon_stats->dest_mon_stuck); 5136 pmon->mon_ppdu_info.ppdu_id = ppdu_id; 5137 continue; 5138 } 5139 5140 if (ppdu_id != pmon->mon_ppdu_info.ppdu_id) { 5141 pmon->mon_ppdu_status = DP_PPDU_STATUS_START; 5142 ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 5143 "dest_rx: new ppdu_id %x != status ppdu_id %x dest_mon_not_reaped = %u dest_mon_stuck = %u\n", 5144 ppdu_id, pmon->mon_ppdu_info.ppdu_id, 5145 rx_mon_stats->dest_mon_not_reaped, 5146 rx_mon_stats->dest_mon_stuck); 5147 break; 5148 } 5149 if (head_msdu && tail_msdu) { 5150 ath11k_dp_rx_mon_deliver(ar, dp->mac_id, head_msdu, 5151 &pmon->mon_ppdu_info, 5152 tail_msdu, napi); 5153 rx_mon_stats->dest_mpdu_done++; 5154 } 5155 5156 ring_entry = ath11k_hal_srng_dst_get_next_entry(ar->ab, 5157 mon_dst_srng); 5158 } 5159 ath11k_hal_srng_access_end(ar->ab, mon_dst_srng); 5160 5161 spin_unlock_bh(&pmon->mon_lock); 5162 5163 if (rx_bufs_used) { 5164 rx_mon_stats->dest_ppdu_done++; 5165 hal_params = ar->ab->hw_params.hal_params; 5166 5167 if (ar->ab->hw_params.rxdma1_enable) 5168 ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id, 5169 &dp->rxdma_mon_buf_ring, 5170 rx_bufs_used, 5171 hal_params->rx_buf_rbm); 5172 else 5173 ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id, 5174 &dp->rx_refill_buf_ring, 5175 rx_bufs_used, 5176 hal_params->rx_buf_rbm); 5177 } 5178 } 5179 5180 int ath11k_dp_rx_process_mon_status(struct ath11k_base *ab, int mac_id, 5181 struct napi_struct *napi, int budget) 5182 { 5183 struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id); 5184 enum hal_rx_mon_status hal_status; 5185 struct sk_buff *skb; 5186 struct sk_buff_head skb_list; 5187 struct ath11k_peer *peer; 5188 struct ath11k_sta *arsta; 5189 int num_buffs_reaped = 0; 5190 u32 rx_buf_sz; 5191 u16 log_type; 5192 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&ar->dp.mon_data; 5193 struct ath11k_pdev_mon_stats *rx_mon_stats = &pmon->rx_mon_stats; 5194 struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info; 5195 5196 __skb_queue_head_init(&skb_list); 5197 5198 num_buffs_reaped = ath11k_dp_rx_reap_mon_status_ring(ab, mac_id, &budget, 5199 &skb_list); 5200 if (!num_buffs_reaped) 5201 goto exit; 5202 5203 memset(ppdu_info, 0, sizeof(*ppdu_info)); 5204 ppdu_info->peer_id = HAL_INVALID_PEERID; 5205 5206 while ((skb = __skb_dequeue(&skb_list))) { 5207 if (ath11k_debugfs_is_pktlog_lite_mode_enabled(ar)) { 5208 log_type = ATH11K_PKTLOG_TYPE_LITE_RX; 5209 rx_buf_sz = DP_RX_BUFFER_SIZE_LITE; 5210 } else if (ath11k_debugfs_is_pktlog_rx_stats_enabled(ar)) { 5211 log_type = ATH11K_PKTLOG_TYPE_RX_STATBUF; 5212 rx_buf_sz = DP_RX_BUFFER_SIZE; 5213 } else { 5214 log_type = ATH11K_PKTLOG_TYPE_INVALID; 5215 rx_buf_sz = 0; 5216 } 5217 5218 if (log_type != ATH11K_PKTLOG_TYPE_INVALID) 5219 trace_ath11k_htt_rxdesc(ar, skb->data, log_type, rx_buf_sz); 5220 5221 memset(ppdu_info, 0, sizeof(*ppdu_info)); 5222 ppdu_info->peer_id = HAL_INVALID_PEERID; 5223 hal_status = ath11k_hal_rx_parse_mon_status(ab, ppdu_info, skb); 5224 5225 if (test_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags) && 5226 pmon->mon_ppdu_status == DP_PPDU_STATUS_START && 5227 hal_status == HAL_TLV_STATUS_PPDU_DONE) { 5228 rx_mon_stats->status_ppdu_done++; 5229 pmon->mon_ppdu_status = DP_PPDU_STATUS_DONE; 5230 ath11k_dp_rx_mon_dest_process(ar, mac_id, budget, napi); 5231 pmon->mon_ppdu_status = DP_PPDU_STATUS_START; 5232 } 5233 5234 if (ppdu_info->peer_id == HAL_INVALID_PEERID || 5235 hal_status != HAL_RX_MON_STATUS_PPDU_DONE) { 5236 dev_kfree_skb_any(skb); 5237 continue; 5238 } 5239 5240 rcu_read_lock(); 5241 spin_lock_bh(&ab->base_lock); 5242 peer = ath11k_peer_find_by_id(ab, ppdu_info->peer_id); 5243 5244 if (!peer || !peer->sta) { 5245 ath11k_dbg(ab, ATH11K_DBG_DATA, 5246 "failed to find the peer with peer_id %d\n", 5247 ppdu_info->peer_id); 5248 goto next_skb; 5249 } 5250 5251 arsta = ath11k_sta_to_arsta(peer->sta); 5252 ath11k_dp_rx_update_peer_stats(arsta, ppdu_info); 5253 5254 if (ath11k_debugfs_is_pktlog_peer_valid(ar, peer->addr)) 5255 trace_ath11k_htt_rxdesc(ar, skb->data, log_type, rx_buf_sz); 5256 5257 next_skb: 5258 spin_unlock_bh(&ab->base_lock); 5259 rcu_read_unlock(); 5260 5261 dev_kfree_skb_any(skb); 5262 memset(ppdu_info, 0, sizeof(*ppdu_info)); 5263 ppdu_info->peer_id = HAL_INVALID_PEERID; 5264 } 5265 exit: 5266 return num_buffs_reaped; 5267 } 5268 5269 static u32 5270 ath11k_dp_rx_full_mon_mpdu_pop(struct ath11k *ar, 5271 void *ring_entry, struct sk_buff **head_msdu, 5272 struct sk_buff **tail_msdu, 5273 struct hal_sw_mon_ring_entries *sw_mon_entries) 5274 { 5275 struct ath11k_pdev_dp *dp = &ar->dp; 5276 struct ath11k_mon_data *pmon = &dp->mon_data; 5277 struct dp_rxdma_ring *rx_ring = &dp->rxdma_mon_buf_ring; 5278 struct sk_buff *msdu = NULL, *last = NULL; 5279 struct hal_sw_monitor_ring *sw_desc = ring_entry; 5280 struct hal_rx_msdu_list msdu_list; 5281 struct hal_rx_desc *rx_desc; 5282 struct ath11k_skb_rxcb *rxcb; 5283 void *rx_msdu_link_desc; 5284 void *p_buf_addr_info, *p_last_buf_addr_info; 5285 int buf_id, i = 0; 5286 u32 rx_buf_size, rx_pkt_offset, l2_hdr_offset; 5287 u32 rx_bufs_used = 0, msdu_cnt = 0; 5288 u32 total_len = 0, frag_len = 0, sw_cookie; 5289 u16 num_msdus = 0; 5290 u8 rxdma_err, rbm; 5291 bool is_frag, is_first_msdu; 5292 bool drop_mpdu = false; 5293 5294 ath11k_hal_rx_sw_mon_ring_buf_paddr_get(ring_entry, sw_mon_entries); 5295 5296 sw_cookie = sw_mon_entries->mon_dst_sw_cookie; 5297 sw_mon_entries->end_of_ppdu = false; 5298 sw_mon_entries->drop_ppdu = false; 5299 p_last_buf_addr_info = sw_mon_entries->dst_buf_addr_info; 5300 msdu_cnt = sw_mon_entries->msdu_cnt; 5301 5302 sw_mon_entries->end_of_ppdu = 5303 FIELD_GET(HAL_SW_MON_RING_INFO0_END_OF_PPDU, sw_desc->info0); 5304 if (sw_mon_entries->end_of_ppdu) 5305 return rx_bufs_used; 5306 5307 if (FIELD_GET(HAL_SW_MON_RING_INFO0_RXDMA_PUSH_REASON, 5308 sw_desc->info0) == 5309 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) { 5310 rxdma_err = 5311 FIELD_GET(HAL_SW_MON_RING_INFO0_RXDMA_ERROR_CODE, 5312 sw_desc->info0); 5313 if (rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR || 5314 rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR || 5315 rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR) { 5316 pmon->rx_mon_stats.dest_mpdu_drop++; 5317 drop_mpdu = true; 5318 } 5319 } 5320 5321 is_frag = false; 5322 is_first_msdu = true; 5323 5324 do { 5325 rx_msdu_link_desc = 5326 (u8 *)pmon->link_desc_banks[sw_cookie].vaddr + 5327 (sw_mon_entries->mon_dst_paddr - 5328 pmon->link_desc_banks[sw_cookie].paddr); 5329 5330 ath11k_hal_rx_msdu_list_get(ar, rx_msdu_link_desc, &msdu_list, 5331 &num_msdus); 5332 5333 for (i = 0; i < num_msdus; i++) { 5334 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, 5335 msdu_list.sw_cookie[i]); 5336 5337 spin_lock_bh(&rx_ring->idr_lock); 5338 msdu = idr_find(&rx_ring->bufs_idr, buf_id); 5339 if (!msdu) { 5340 ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 5341 "full mon msdu_pop: invalid buf_id %d\n", 5342 buf_id); 5343 spin_unlock_bh(&rx_ring->idr_lock); 5344 break; 5345 } 5346 idr_remove(&rx_ring->bufs_idr, buf_id); 5347 spin_unlock_bh(&rx_ring->idr_lock); 5348 5349 rxcb = ATH11K_SKB_RXCB(msdu); 5350 if (!rxcb->unmapped) { 5351 dma_unmap_single(ar->ab->dev, rxcb->paddr, 5352 msdu->len + 5353 skb_tailroom(msdu), 5354 DMA_FROM_DEVICE); 5355 rxcb->unmapped = 1; 5356 } 5357 if (drop_mpdu) { 5358 ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 5359 "full mon: i %d drop msdu %p *ppdu_id %x\n", 5360 i, msdu, sw_mon_entries->ppdu_id); 5361 dev_kfree_skb_any(msdu); 5362 msdu_cnt--; 5363 goto next_msdu; 5364 } 5365 5366 rx_desc = (struct hal_rx_desc *)msdu->data; 5367 5368 rx_pkt_offset = sizeof(struct hal_rx_desc); 5369 l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, rx_desc); 5370 5371 if (is_first_msdu) { 5372 if (!ath11k_dp_rxdesc_mpdu_valid(ar->ab, rx_desc)) { 5373 drop_mpdu = true; 5374 dev_kfree_skb_any(msdu); 5375 msdu = NULL; 5376 goto next_msdu; 5377 } 5378 is_first_msdu = false; 5379 } 5380 5381 ath11k_dp_mon_get_buf_len(&msdu_list.msdu_info[i], 5382 &is_frag, &total_len, 5383 &frag_len, &msdu_cnt); 5384 5385 rx_buf_size = rx_pkt_offset + l2_hdr_offset + frag_len; 5386 5387 ath11k_dp_pkt_set_pktlen(msdu, rx_buf_size); 5388 5389 if (!(*head_msdu)) 5390 *head_msdu = msdu; 5391 else if (last) 5392 last->next = msdu; 5393 5394 last = msdu; 5395 next_msdu: 5396 rx_bufs_used++; 5397 } 5398 5399 ath11k_dp_rx_mon_next_link_desc_get(rx_msdu_link_desc, 5400 &sw_mon_entries->mon_dst_paddr, 5401 &sw_mon_entries->mon_dst_sw_cookie, 5402 &rbm, 5403 &p_buf_addr_info); 5404 5405 if (ath11k_dp_rx_monitor_link_desc_return(ar, 5406 p_last_buf_addr_info, 5407 dp->mac_id)) 5408 ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 5409 "full mon: dp_rx_monitor_link_desc_return failed\n"); 5410 5411 p_last_buf_addr_info = p_buf_addr_info; 5412 5413 } while (sw_mon_entries->mon_dst_paddr && msdu_cnt); 5414 5415 if (last) 5416 last->next = NULL; 5417 5418 *tail_msdu = msdu; 5419 5420 return rx_bufs_used; 5421 } 5422 5423 static int ath11k_dp_rx_full_mon_prepare_mpdu(struct ath11k_dp *dp, 5424 struct dp_full_mon_mpdu *mon_mpdu, 5425 struct sk_buff *head, 5426 struct sk_buff *tail) 5427 { 5428 mon_mpdu = kzalloc(sizeof(*mon_mpdu), GFP_ATOMIC); 5429 if (!mon_mpdu) 5430 return -ENOMEM; 5431 5432 list_add_tail(&mon_mpdu->list, &dp->dp_full_mon_mpdu_list); 5433 mon_mpdu->head = head; 5434 mon_mpdu->tail = tail; 5435 5436 return 0; 5437 } 5438 5439 static void ath11k_dp_rx_full_mon_drop_ppdu(struct ath11k_dp *dp, 5440 struct dp_full_mon_mpdu *mon_mpdu) 5441 { 5442 struct dp_full_mon_mpdu *tmp; 5443 struct sk_buff *tmp_msdu, *skb_next; 5444 5445 if (list_empty(&dp->dp_full_mon_mpdu_list)) 5446 return; 5447 5448 list_for_each_entry_safe(mon_mpdu, tmp, &dp->dp_full_mon_mpdu_list, list) { 5449 list_del(&mon_mpdu->list); 5450 5451 tmp_msdu = mon_mpdu->head; 5452 while (tmp_msdu) { 5453 skb_next = tmp_msdu->next; 5454 dev_kfree_skb_any(tmp_msdu); 5455 tmp_msdu = skb_next; 5456 } 5457 5458 kfree(mon_mpdu); 5459 } 5460 } 5461 5462 static int ath11k_dp_rx_full_mon_deliver_ppdu(struct ath11k *ar, 5463 int mac_id, 5464 struct ath11k_mon_data *pmon, 5465 struct napi_struct *napi) 5466 { 5467 struct ath11k_pdev_mon_stats *rx_mon_stats; 5468 struct dp_full_mon_mpdu *tmp; 5469 struct dp_full_mon_mpdu *mon_mpdu = pmon->mon_mpdu; 5470 struct sk_buff *head_msdu, *tail_msdu; 5471 struct ath11k_base *ab = ar->ab; 5472 struct ath11k_dp *dp = &ab->dp; 5473 int ret; 5474 5475 rx_mon_stats = &pmon->rx_mon_stats; 5476 5477 list_for_each_entry_safe(mon_mpdu, tmp, &dp->dp_full_mon_mpdu_list, list) { 5478 list_del(&mon_mpdu->list); 5479 head_msdu = mon_mpdu->head; 5480 tail_msdu = mon_mpdu->tail; 5481 if (head_msdu && tail_msdu) { 5482 ret = ath11k_dp_rx_mon_deliver(ar, mac_id, head_msdu, 5483 &pmon->mon_ppdu_info, 5484 tail_msdu, napi); 5485 rx_mon_stats->dest_mpdu_done++; 5486 ath11k_dbg(ar->ab, ATH11K_DBG_DATA, "full mon: deliver ppdu\n"); 5487 } 5488 kfree(mon_mpdu); 5489 } 5490 5491 return ret; 5492 } 5493 5494 static int 5495 ath11k_dp_rx_process_full_mon_status_ring(struct ath11k_base *ab, int mac_id, 5496 struct napi_struct *napi, int budget) 5497 { 5498 struct ath11k *ar = ab->pdevs[mac_id].ar; 5499 struct ath11k_pdev_dp *dp = &ar->dp; 5500 struct ath11k_mon_data *pmon = &dp->mon_data; 5501 struct hal_sw_mon_ring_entries *sw_mon_entries; 5502 int quota = 0, work = 0, count; 5503 5504 sw_mon_entries = &pmon->sw_mon_entries; 5505 5506 while (pmon->hold_mon_dst_ring) { 5507 quota = ath11k_dp_rx_process_mon_status(ab, mac_id, 5508 napi, 1); 5509 if (pmon->buf_state == DP_MON_STATUS_MATCH) { 5510 count = sw_mon_entries->status_buf_count; 5511 if (count > 1) { 5512 quota += ath11k_dp_rx_process_mon_status(ab, mac_id, 5513 napi, count); 5514 } 5515 5516 ath11k_dp_rx_full_mon_deliver_ppdu(ar, dp->mac_id, 5517 pmon, napi); 5518 pmon->hold_mon_dst_ring = false; 5519 } else if (!pmon->mon_status_paddr || 5520 pmon->buf_state == DP_MON_STATUS_LEAD) { 5521 sw_mon_entries->drop_ppdu = true; 5522 pmon->hold_mon_dst_ring = false; 5523 } 5524 5525 if (!quota) 5526 break; 5527 5528 work += quota; 5529 } 5530 5531 if (sw_mon_entries->drop_ppdu) 5532 ath11k_dp_rx_full_mon_drop_ppdu(&ab->dp, pmon->mon_mpdu); 5533 5534 return work; 5535 } 5536 5537 static int ath11k_dp_full_mon_process_rx(struct ath11k_base *ab, int mac_id, 5538 struct napi_struct *napi, int budget) 5539 { 5540 struct ath11k *ar = ab->pdevs[mac_id].ar; 5541 struct ath11k_pdev_dp *dp = &ar->dp; 5542 struct ath11k_mon_data *pmon = &dp->mon_data; 5543 struct hal_sw_mon_ring_entries *sw_mon_entries; 5544 struct ath11k_pdev_mon_stats *rx_mon_stats; 5545 struct sk_buff *head_msdu, *tail_msdu; 5546 void *mon_dst_srng = &ar->ab->hal.srng_list[dp->rxdma_mon_dst_ring.ring_id]; 5547 void *ring_entry; 5548 u32 rx_bufs_used = 0, mpdu_rx_bufs_used; 5549 int quota = 0, ret; 5550 bool break_dst_ring = false; 5551 5552 spin_lock_bh(&pmon->mon_lock); 5553 5554 sw_mon_entries = &pmon->sw_mon_entries; 5555 rx_mon_stats = &pmon->rx_mon_stats; 5556 5557 if (pmon->hold_mon_dst_ring) { 5558 spin_unlock_bh(&pmon->mon_lock); 5559 goto reap_status_ring; 5560 } 5561 5562 ath11k_hal_srng_access_begin(ar->ab, mon_dst_srng); 5563 while ((ring_entry = ath11k_hal_srng_dst_peek(ar->ab, mon_dst_srng))) { 5564 head_msdu = NULL; 5565 tail_msdu = NULL; 5566 5567 mpdu_rx_bufs_used = ath11k_dp_rx_full_mon_mpdu_pop(ar, ring_entry, 5568 &head_msdu, 5569 &tail_msdu, 5570 sw_mon_entries); 5571 rx_bufs_used += mpdu_rx_bufs_used; 5572 5573 if (!sw_mon_entries->end_of_ppdu) { 5574 if (head_msdu) { 5575 ret = ath11k_dp_rx_full_mon_prepare_mpdu(&ab->dp, 5576 pmon->mon_mpdu, 5577 head_msdu, 5578 tail_msdu); 5579 if (ret) 5580 break_dst_ring = true; 5581 } 5582 5583 goto next_entry; 5584 } else { 5585 if (!sw_mon_entries->ppdu_id && 5586 !sw_mon_entries->mon_status_paddr) { 5587 break_dst_ring = true; 5588 goto next_entry; 5589 } 5590 } 5591 5592 rx_mon_stats->dest_ppdu_done++; 5593 pmon->mon_ppdu_status = DP_PPDU_STATUS_START; 5594 pmon->buf_state = DP_MON_STATUS_LAG; 5595 pmon->mon_status_paddr = sw_mon_entries->mon_status_paddr; 5596 pmon->hold_mon_dst_ring = true; 5597 next_entry: 5598 ring_entry = ath11k_hal_srng_dst_get_next_entry(ar->ab, 5599 mon_dst_srng); 5600 if (break_dst_ring) 5601 break; 5602 } 5603 5604 ath11k_hal_srng_access_end(ar->ab, mon_dst_srng); 5605 spin_unlock_bh(&pmon->mon_lock); 5606 5607 if (rx_bufs_used) { 5608 ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id, 5609 &dp->rxdma_mon_buf_ring, 5610 rx_bufs_used, 5611 HAL_RX_BUF_RBM_SW3_BM); 5612 } 5613 5614 reap_status_ring: 5615 quota = ath11k_dp_rx_process_full_mon_status_ring(ab, mac_id, 5616 napi, budget); 5617 5618 return quota; 5619 } 5620 5621 int ath11k_dp_rx_process_mon_rings(struct ath11k_base *ab, int mac_id, 5622 struct napi_struct *napi, int budget) 5623 { 5624 struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id); 5625 int ret = 0; 5626 5627 if (test_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags) && 5628 ab->hw_params.full_monitor_mode) 5629 ret = ath11k_dp_full_mon_process_rx(ab, mac_id, napi, budget); 5630 else 5631 ret = ath11k_dp_rx_process_mon_status(ab, mac_id, napi, budget); 5632 5633 return ret; 5634 } 5635 5636 static int ath11k_dp_rx_pdev_mon_status_attach(struct ath11k *ar) 5637 { 5638 struct ath11k_pdev_dp *dp = &ar->dp; 5639 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data; 5640 5641 skb_queue_head_init(&pmon->rx_status_q); 5642 5643 pmon->mon_ppdu_status = DP_PPDU_STATUS_START; 5644 5645 memset(&pmon->rx_mon_stats, 0, 5646 sizeof(pmon->rx_mon_stats)); 5647 return 0; 5648 } 5649 5650 int ath11k_dp_rx_pdev_mon_attach(struct ath11k *ar) 5651 { 5652 struct ath11k_pdev_dp *dp = &ar->dp; 5653 struct ath11k_mon_data *pmon = &dp->mon_data; 5654 struct hal_srng *mon_desc_srng = NULL; 5655 struct dp_srng *dp_srng; 5656 int ret = 0; 5657 u32 n_link_desc = 0; 5658 5659 ret = ath11k_dp_rx_pdev_mon_status_attach(ar); 5660 if (ret) { 5661 ath11k_warn(ar->ab, "pdev_mon_status_attach() failed"); 5662 return ret; 5663 } 5664 5665 /* if rxdma1_enable is false, no need to setup 5666 * rxdma_mon_desc_ring. 5667 */ 5668 if (!ar->ab->hw_params.rxdma1_enable) 5669 return 0; 5670 5671 dp_srng = &dp->rxdma_mon_desc_ring; 5672 n_link_desc = dp_srng->size / 5673 ath11k_hal_srng_get_entrysize(ar->ab, HAL_RXDMA_MONITOR_DESC); 5674 mon_desc_srng = 5675 &ar->ab->hal.srng_list[dp->rxdma_mon_desc_ring.ring_id]; 5676 5677 ret = ath11k_dp_link_desc_setup(ar->ab, pmon->link_desc_banks, 5678 HAL_RXDMA_MONITOR_DESC, mon_desc_srng, 5679 n_link_desc); 5680 if (ret) { 5681 ath11k_warn(ar->ab, "mon_link_desc_pool_setup() failed"); 5682 return ret; 5683 } 5684 pmon->mon_last_linkdesc_paddr = 0; 5685 pmon->mon_last_buf_cookie = DP_RX_DESC_COOKIE_MAX + 1; 5686 spin_lock_init(&pmon->mon_lock); 5687 5688 return 0; 5689 } 5690 5691 static int ath11k_dp_mon_link_free(struct ath11k *ar) 5692 { 5693 struct ath11k_pdev_dp *dp = &ar->dp; 5694 struct ath11k_mon_data *pmon = &dp->mon_data; 5695 5696 ath11k_dp_link_desc_cleanup(ar->ab, pmon->link_desc_banks, 5697 HAL_RXDMA_MONITOR_DESC, 5698 &dp->rxdma_mon_desc_ring); 5699 return 0; 5700 } 5701 5702 int ath11k_dp_rx_pdev_mon_detach(struct ath11k *ar) 5703 { 5704 ath11k_dp_mon_link_free(ar); 5705 return 0; 5706 } 5707 5708 int ath11k_dp_rx_pktlog_start(struct ath11k_base *ab) 5709 { 5710 /* start reap timer */ 5711 mod_timer(&ab->mon_reap_timer, 5712 jiffies + msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL)); 5713 5714 return 0; 5715 } 5716 5717 int ath11k_dp_rx_pktlog_stop(struct ath11k_base *ab, bool stop_timer) 5718 { 5719 int ret; 5720 5721 if (stop_timer) 5722 del_timer_sync(&ab->mon_reap_timer); 5723 5724 /* reap all the monitor related rings */ 5725 ret = ath11k_dp_purge_mon_ring(ab); 5726 if (ret) { 5727 ath11k_warn(ab, "failed to purge dp mon ring: %d\n", ret); 5728 return ret; 5729 } 5730 5731 return 0; 5732 } 5733