1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/ieee80211.h> 7 #include <linux/kernel.h> 8 #include <linux/skbuff.h> 9 #include <crypto/hash.h> 10 #include "core.h" 11 #include "debug.h" 12 #include "hal_desc.h" 13 #include "hw.h" 14 #include "dp_rx.h" 15 #include "hal_rx.h" 16 #include "dp_tx.h" 17 #include "peer.h" 18 19 #define ATH11K_DP_RX_FRAGMENT_TIMEOUT_MS (2 * HZ) 20 21 static u8 *ath11k_dp_rx_h_80211_hdr(struct hal_rx_desc *desc) 22 { 23 return desc->hdr_status; 24 } 25 26 static enum hal_encrypt_type ath11k_dp_rx_h_mpdu_start_enctype(struct hal_rx_desc *desc) 27 { 28 if (!(__le32_to_cpu(desc->mpdu_start.info1) & 29 RX_MPDU_START_INFO1_ENCRYPT_INFO_VALID)) 30 return HAL_ENCRYPT_TYPE_OPEN; 31 32 return FIELD_GET(RX_MPDU_START_INFO2_ENC_TYPE, 33 __le32_to_cpu(desc->mpdu_start.info2)); 34 } 35 36 static u8 ath11k_dp_rx_h_msdu_start_decap_type(struct hal_rx_desc *desc) 37 { 38 return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT, 39 __le32_to_cpu(desc->msdu_start.info2)); 40 } 41 42 static u8 ath11k_dp_rx_h_msdu_start_mesh_ctl_present(struct hal_rx_desc *desc) 43 { 44 return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT, 45 __le32_to_cpu(desc->msdu_start.info2)); 46 } 47 48 static bool ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(struct hal_rx_desc *desc) 49 { 50 return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_CTRL_VALID, 51 __le32_to_cpu(desc->mpdu_start.info1)); 52 } 53 54 static bool ath11k_dp_rx_h_mpdu_start_fc_valid(struct hal_rx_desc *desc) 55 { 56 return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_FCTRL_VALID, 57 __le32_to_cpu(desc->mpdu_start.info1)); 58 } 59 60 static bool ath11k_dp_rx_h_mpdu_start_more_frags(struct sk_buff *skb) 61 { 62 struct ieee80211_hdr *hdr; 63 64 hdr = (struct ieee80211_hdr *)(skb->data + HAL_RX_DESC_SIZE); 65 return ieee80211_has_morefrags(hdr->frame_control); 66 } 67 68 static u16 ath11k_dp_rx_h_mpdu_start_frag_no(struct sk_buff *skb) 69 { 70 struct ieee80211_hdr *hdr; 71 72 hdr = (struct ieee80211_hdr *)(skb->data + HAL_RX_DESC_SIZE); 73 return le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG; 74 } 75 76 static u16 ath11k_dp_rx_h_mpdu_start_seq_no(struct hal_rx_desc *desc) 77 { 78 return FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_NUM, 79 __le32_to_cpu(desc->mpdu_start.info1)); 80 } 81 82 static bool ath11k_dp_rx_h_attn_msdu_done(struct hal_rx_desc *desc) 83 { 84 return !!FIELD_GET(RX_ATTENTION_INFO2_MSDU_DONE, 85 __le32_to_cpu(desc->attention.info2)); 86 } 87 88 static bool ath11k_dp_rx_h_attn_l4_cksum_fail(struct hal_rx_desc *desc) 89 { 90 return !!FIELD_GET(RX_ATTENTION_INFO1_TCP_UDP_CKSUM_FAIL, 91 __le32_to_cpu(desc->attention.info1)); 92 } 93 94 static bool ath11k_dp_rx_h_attn_ip_cksum_fail(struct hal_rx_desc *desc) 95 { 96 return !!FIELD_GET(RX_ATTENTION_INFO1_IP_CKSUM_FAIL, 97 __le32_to_cpu(desc->attention.info1)); 98 } 99 100 static bool ath11k_dp_rx_h_attn_is_decrypted(struct hal_rx_desc *desc) 101 { 102 return (FIELD_GET(RX_ATTENTION_INFO2_DCRYPT_STATUS_CODE, 103 __le32_to_cpu(desc->attention.info2)) == 104 RX_DESC_DECRYPT_STATUS_CODE_OK); 105 } 106 107 static u32 ath11k_dp_rx_h_attn_mpdu_err(struct hal_rx_desc *desc) 108 { 109 u32 info = __le32_to_cpu(desc->attention.info1); 110 u32 errmap = 0; 111 112 if (info & RX_ATTENTION_INFO1_FCS_ERR) 113 errmap |= DP_RX_MPDU_ERR_FCS; 114 115 if (info & RX_ATTENTION_INFO1_DECRYPT_ERR) 116 errmap |= DP_RX_MPDU_ERR_DECRYPT; 117 118 if (info & RX_ATTENTION_INFO1_TKIP_MIC_ERR) 119 errmap |= DP_RX_MPDU_ERR_TKIP_MIC; 120 121 if (info & RX_ATTENTION_INFO1_A_MSDU_ERROR) 122 errmap |= DP_RX_MPDU_ERR_AMSDU_ERR; 123 124 if (info & RX_ATTENTION_INFO1_OVERFLOW_ERR) 125 errmap |= DP_RX_MPDU_ERR_OVERFLOW; 126 127 if (info & RX_ATTENTION_INFO1_MSDU_LEN_ERR) 128 errmap |= DP_RX_MPDU_ERR_MSDU_LEN; 129 130 if (info & RX_ATTENTION_INFO1_MPDU_LEN_ERR) 131 errmap |= DP_RX_MPDU_ERR_MPDU_LEN; 132 133 return errmap; 134 } 135 136 static u16 ath11k_dp_rx_h_msdu_start_msdu_len(struct hal_rx_desc *desc) 137 { 138 return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH, 139 __le32_to_cpu(desc->msdu_start.info1)); 140 } 141 142 static u8 ath11k_dp_rx_h_msdu_start_sgi(struct hal_rx_desc *desc) 143 { 144 return FIELD_GET(RX_MSDU_START_INFO3_SGI, 145 __le32_to_cpu(desc->msdu_start.info3)); 146 } 147 148 static u8 ath11k_dp_rx_h_msdu_start_rate_mcs(struct hal_rx_desc *desc) 149 { 150 return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS, 151 __le32_to_cpu(desc->msdu_start.info3)); 152 } 153 154 static u8 ath11k_dp_rx_h_msdu_start_rx_bw(struct hal_rx_desc *desc) 155 { 156 return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW, 157 __le32_to_cpu(desc->msdu_start.info3)); 158 } 159 160 static u32 ath11k_dp_rx_h_msdu_start_freq(struct hal_rx_desc *desc) 161 { 162 return __le32_to_cpu(desc->msdu_start.phy_meta_data); 163 } 164 165 static u8 ath11k_dp_rx_h_msdu_start_pkt_type(struct hal_rx_desc *desc) 166 { 167 return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE, 168 __le32_to_cpu(desc->msdu_start.info3)); 169 } 170 171 static u8 ath11k_dp_rx_h_msdu_start_nss(struct hal_rx_desc *desc) 172 { 173 u8 mimo_ss_bitmap = FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP, 174 __le32_to_cpu(desc->msdu_start.info3)); 175 176 return hweight8(mimo_ss_bitmap); 177 } 178 179 static u8 ath11k_dp_rx_h_mpdu_start_tid(struct hal_rx_desc *desc) 180 { 181 return FIELD_GET(RX_MPDU_START_INFO2_TID, 182 __le32_to_cpu(desc->mpdu_start.info2)); 183 } 184 185 static u16 ath11k_dp_rx_h_mpdu_start_peer_id(struct hal_rx_desc *desc) 186 { 187 return __le16_to_cpu(desc->mpdu_start.sw_peer_id); 188 } 189 190 static u8 ath11k_dp_rx_h_msdu_end_l3pad(struct hal_rx_desc *desc) 191 { 192 return FIELD_GET(RX_MSDU_END_INFO2_L3_HDR_PADDING, 193 __le32_to_cpu(desc->msdu_end.info2)); 194 } 195 196 static bool ath11k_dp_rx_h_msdu_end_first_msdu(struct hal_rx_desc *desc) 197 { 198 return !!FIELD_GET(RX_MSDU_END_INFO2_FIRST_MSDU, 199 __le32_to_cpu(desc->msdu_end.info2)); 200 } 201 202 static bool ath11k_dp_rx_h_msdu_end_last_msdu(struct hal_rx_desc *desc) 203 { 204 return !!FIELD_GET(RX_MSDU_END_INFO2_LAST_MSDU, 205 __le32_to_cpu(desc->msdu_end.info2)); 206 } 207 208 static void ath11k_dp_rx_desc_end_tlv_copy(struct hal_rx_desc *fdesc, 209 struct hal_rx_desc *ldesc) 210 { 211 memcpy((u8 *)&fdesc->msdu_end, (u8 *)&ldesc->msdu_end, 212 sizeof(struct rx_msdu_end)); 213 memcpy((u8 *)&fdesc->attention, (u8 *)&ldesc->attention, 214 sizeof(struct rx_attention)); 215 memcpy((u8 *)&fdesc->mpdu_end, (u8 *)&ldesc->mpdu_end, 216 sizeof(struct rx_mpdu_end)); 217 } 218 219 static u32 ath11k_dp_rxdesc_get_mpdulen_err(struct hal_rx_desc *rx_desc) 220 { 221 struct rx_attention *rx_attn; 222 223 rx_attn = &rx_desc->attention; 224 225 return FIELD_GET(RX_ATTENTION_INFO1_MPDU_LEN_ERR, 226 __le32_to_cpu(rx_attn->info1)); 227 } 228 229 static u32 ath11k_dp_rxdesc_get_decap_format(struct hal_rx_desc *rx_desc) 230 { 231 struct rx_msdu_start *rx_msdu_start; 232 233 rx_msdu_start = &rx_desc->msdu_start; 234 235 return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT, 236 __le32_to_cpu(rx_msdu_start->info2)); 237 } 238 239 static u8 *ath11k_dp_rxdesc_get_80211hdr(struct hal_rx_desc *rx_desc) 240 { 241 u8 *rx_pkt_hdr; 242 243 rx_pkt_hdr = &rx_desc->msdu_payload[0]; 244 245 return rx_pkt_hdr; 246 } 247 248 static bool ath11k_dp_rxdesc_mpdu_valid(struct hal_rx_desc *rx_desc) 249 { 250 u32 tlv_tag; 251 252 tlv_tag = FIELD_GET(HAL_TLV_HDR_TAG, 253 __le32_to_cpu(rx_desc->mpdu_start_tag)); 254 255 return tlv_tag == HAL_RX_MPDU_START; 256 } 257 258 static u32 ath11k_dp_rxdesc_get_ppduid(struct hal_rx_desc *rx_desc) 259 { 260 return __le16_to_cpu(rx_desc->mpdu_start.phy_ppdu_id); 261 } 262 263 /* Returns number of Rx buffers replenished */ 264 int ath11k_dp_rxbufs_replenish(struct ath11k_base *ab, int mac_id, 265 struct dp_rxdma_ring *rx_ring, 266 int req_entries, 267 enum hal_rx_buf_return_buf_manager mgr, 268 gfp_t gfp) 269 { 270 struct hal_srng *srng; 271 u32 *desc; 272 struct sk_buff *skb; 273 int num_free; 274 int num_remain; 275 int buf_id; 276 u32 cookie; 277 dma_addr_t paddr; 278 279 req_entries = min(req_entries, rx_ring->bufs_max); 280 281 srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id]; 282 283 spin_lock_bh(&srng->lock); 284 285 ath11k_hal_srng_access_begin(ab, srng); 286 287 num_free = ath11k_hal_srng_src_num_free(ab, srng, true); 288 if (!req_entries && (num_free > (rx_ring->bufs_max * 3) / 4)) 289 req_entries = num_free; 290 291 req_entries = min(num_free, req_entries); 292 num_remain = req_entries; 293 294 while (num_remain > 0) { 295 skb = dev_alloc_skb(DP_RX_BUFFER_SIZE + 296 DP_RX_BUFFER_ALIGN_SIZE); 297 if (!skb) 298 break; 299 300 if (!IS_ALIGNED((unsigned long)skb->data, 301 DP_RX_BUFFER_ALIGN_SIZE)) { 302 skb_pull(skb, 303 PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) - 304 skb->data); 305 } 306 307 paddr = dma_map_single(ab->dev, skb->data, 308 skb->len + skb_tailroom(skb), 309 DMA_FROM_DEVICE); 310 if (dma_mapping_error(ab->dev, paddr)) 311 goto fail_free_skb; 312 313 spin_lock_bh(&rx_ring->idr_lock); 314 buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 0, 315 rx_ring->bufs_max * 3, gfp); 316 spin_unlock_bh(&rx_ring->idr_lock); 317 if (buf_id < 0) 318 goto fail_dma_unmap; 319 320 desc = ath11k_hal_srng_src_get_next_entry(ab, srng); 321 if (!desc) 322 goto fail_idr_remove; 323 324 ATH11K_SKB_RXCB(skb)->paddr = paddr; 325 326 cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) | 327 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id); 328 329 num_remain--; 330 331 ath11k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr); 332 } 333 334 ath11k_hal_srng_access_end(ab, srng); 335 336 spin_unlock_bh(&srng->lock); 337 338 return req_entries - num_remain; 339 340 fail_idr_remove: 341 spin_lock_bh(&rx_ring->idr_lock); 342 idr_remove(&rx_ring->bufs_idr, buf_id); 343 spin_unlock_bh(&rx_ring->idr_lock); 344 fail_dma_unmap: 345 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb), 346 DMA_FROM_DEVICE); 347 fail_free_skb: 348 dev_kfree_skb_any(skb); 349 350 ath11k_hal_srng_access_end(ab, srng); 351 352 spin_unlock_bh(&srng->lock); 353 354 return req_entries - num_remain; 355 } 356 357 static int ath11k_dp_rxdma_buf_ring_free(struct ath11k *ar, 358 struct dp_rxdma_ring *rx_ring) 359 { 360 struct ath11k_pdev_dp *dp = &ar->dp; 361 struct sk_buff *skb; 362 int buf_id; 363 364 spin_lock_bh(&rx_ring->idr_lock); 365 idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) { 366 idr_remove(&rx_ring->bufs_idr, buf_id); 367 /* TODO: Understand where internal driver does this dma_unmap of 368 * of rxdma_buffer. 369 */ 370 dma_unmap_single(ar->ab->dev, ATH11K_SKB_RXCB(skb)->paddr, 371 skb->len + skb_tailroom(skb), DMA_FROM_DEVICE); 372 dev_kfree_skb_any(skb); 373 } 374 375 idr_destroy(&rx_ring->bufs_idr); 376 spin_unlock_bh(&rx_ring->idr_lock); 377 378 rx_ring = &dp->rx_mon_status_refill_ring; 379 380 spin_lock_bh(&rx_ring->idr_lock); 381 idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) { 382 idr_remove(&rx_ring->bufs_idr, buf_id); 383 /* XXX: Understand where internal driver does this dma_unmap of 384 * of rxdma_buffer. 385 */ 386 dma_unmap_single(ar->ab->dev, ATH11K_SKB_RXCB(skb)->paddr, 387 skb->len + skb_tailroom(skb), DMA_BIDIRECTIONAL); 388 dev_kfree_skb_any(skb); 389 } 390 391 idr_destroy(&rx_ring->bufs_idr); 392 spin_unlock_bh(&rx_ring->idr_lock); 393 return 0; 394 } 395 396 static int ath11k_dp_rxdma_pdev_buf_free(struct ath11k *ar) 397 { 398 struct ath11k_pdev_dp *dp = &ar->dp; 399 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring; 400 401 ath11k_dp_rxdma_buf_ring_free(ar, rx_ring); 402 403 rx_ring = &dp->rxdma_mon_buf_ring; 404 ath11k_dp_rxdma_buf_ring_free(ar, rx_ring); 405 406 rx_ring = &dp->rx_mon_status_refill_ring; 407 ath11k_dp_rxdma_buf_ring_free(ar, rx_ring); 408 return 0; 409 } 410 411 static int ath11k_dp_rxdma_ring_buf_setup(struct ath11k *ar, 412 struct dp_rxdma_ring *rx_ring, 413 u32 ringtype) 414 { 415 struct ath11k_pdev_dp *dp = &ar->dp; 416 int num_entries; 417 418 num_entries = rx_ring->refill_buf_ring.size / 419 ath11k_hal_srng_get_entrysize(ringtype); 420 421 rx_ring->bufs_max = num_entries; 422 ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id, rx_ring, num_entries, 423 HAL_RX_BUF_RBM_SW3_BM, GFP_KERNEL); 424 return 0; 425 } 426 427 static int ath11k_dp_rxdma_pdev_buf_setup(struct ath11k *ar) 428 { 429 struct ath11k_pdev_dp *dp = &ar->dp; 430 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring; 431 432 ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_BUF); 433 434 rx_ring = &dp->rxdma_mon_buf_ring; 435 ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_MONITOR_BUF); 436 437 rx_ring = &dp->rx_mon_status_refill_ring; 438 ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_MONITOR_STATUS); 439 440 return 0; 441 } 442 443 static void ath11k_dp_rx_pdev_srng_free(struct ath11k *ar) 444 { 445 struct ath11k_pdev_dp *dp = &ar->dp; 446 447 ath11k_dp_srng_cleanup(ar->ab, &dp->rx_refill_buf_ring.refill_buf_ring); 448 ath11k_dp_srng_cleanup(ar->ab, &dp->rxdma_err_dst_ring); 449 ath11k_dp_srng_cleanup(ar->ab, &dp->rx_mon_status_refill_ring.refill_buf_ring); 450 ath11k_dp_srng_cleanup(ar->ab, &dp->rxdma_mon_buf_ring.refill_buf_ring); 451 } 452 453 void ath11k_dp_pdev_reo_cleanup(struct ath11k_base *ab) 454 { 455 struct ath11k_dp *dp = &ab->dp; 456 int i; 457 458 for (i = 0; i < DP_REO_DST_RING_MAX; i++) 459 ath11k_dp_srng_cleanup(ab, &dp->reo_dst_ring[i]); 460 } 461 462 int ath11k_dp_pdev_reo_setup(struct ath11k_base *ab) 463 { 464 struct ath11k_dp *dp = &ab->dp; 465 int ret; 466 int i; 467 468 for (i = 0; i < DP_REO_DST_RING_MAX; i++) { 469 ret = ath11k_dp_srng_setup(ab, &dp->reo_dst_ring[i], 470 HAL_REO_DST, i, 0, 471 DP_REO_DST_RING_SIZE); 472 if (ret) { 473 ath11k_warn(ab, "failed to setup reo_dst_ring\n"); 474 goto err_reo_cleanup; 475 } 476 } 477 478 return 0; 479 480 err_reo_cleanup: 481 ath11k_dp_pdev_reo_cleanup(ab); 482 483 return ret; 484 } 485 486 static int ath11k_dp_rx_pdev_srng_alloc(struct ath11k *ar) 487 { 488 struct ath11k_pdev_dp *dp = &ar->dp; 489 struct dp_srng *srng = NULL; 490 int ret; 491 492 ret = ath11k_dp_srng_setup(ar->ab, 493 &dp->rx_refill_buf_ring.refill_buf_ring, 494 HAL_RXDMA_BUF, 0, 495 dp->mac_id, DP_RXDMA_BUF_RING_SIZE); 496 if (ret) { 497 ath11k_warn(ar->ab, "failed to setup rx_refill_buf_ring\n"); 498 return ret; 499 } 500 501 ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_err_dst_ring, 502 HAL_RXDMA_DST, 0, dp->mac_id, 503 DP_RXDMA_ERR_DST_RING_SIZE); 504 if (ret) { 505 ath11k_warn(ar->ab, "failed to setup rxdma_err_dst_ring\n"); 506 return ret; 507 } 508 509 srng = &dp->rx_mon_status_refill_ring.refill_buf_ring; 510 ret = ath11k_dp_srng_setup(ar->ab, 511 srng, 512 HAL_RXDMA_MONITOR_STATUS, 0, dp->mac_id, 513 DP_RXDMA_MON_STATUS_RING_SIZE); 514 if (ret) { 515 ath11k_warn(ar->ab, 516 "failed to setup rx_mon_status_refill_ring\n"); 517 return ret; 518 } 519 ret = ath11k_dp_srng_setup(ar->ab, 520 &dp->rxdma_mon_buf_ring.refill_buf_ring, 521 HAL_RXDMA_MONITOR_BUF, 0, dp->mac_id, 522 DP_RXDMA_MONITOR_BUF_RING_SIZE); 523 if (ret) { 524 ath11k_warn(ar->ab, 525 "failed to setup HAL_RXDMA_MONITOR_BUF\n"); 526 return ret; 527 } 528 529 ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_mon_dst_ring, 530 HAL_RXDMA_MONITOR_DST, 0, dp->mac_id, 531 DP_RXDMA_MONITOR_DST_RING_SIZE); 532 if (ret) { 533 ath11k_warn(ar->ab, 534 "failed to setup HAL_RXDMA_MONITOR_DST\n"); 535 return ret; 536 } 537 538 ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_mon_desc_ring, 539 HAL_RXDMA_MONITOR_DESC, 0, dp->mac_id, 540 DP_RXDMA_MONITOR_DESC_RING_SIZE); 541 if (ret) { 542 ath11k_warn(ar->ab, 543 "failed to setup HAL_RXDMA_MONITOR_DESC\n"); 544 return ret; 545 } 546 547 return 0; 548 } 549 550 void ath11k_dp_reo_cmd_list_cleanup(struct ath11k_base *ab) 551 { 552 struct ath11k_dp *dp = &ab->dp; 553 struct dp_reo_cmd *cmd, *tmp; 554 struct dp_reo_cache_flush_elem *cmd_cache, *tmp_cache; 555 556 spin_lock_bh(&dp->reo_cmd_lock); 557 list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) { 558 list_del(&cmd->list); 559 dma_unmap_single(ab->dev, cmd->data.paddr, 560 cmd->data.size, DMA_BIDIRECTIONAL); 561 kfree(cmd->data.vaddr); 562 kfree(cmd); 563 } 564 565 list_for_each_entry_safe(cmd_cache, tmp_cache, 566 &dp->reo_cmd_cache_flush_list, list) { 567 list_del(&cmd_cache->list); 568 dp->reo_cmd_cache_flush_count--; 569 dma_unmap_single(ab->dev, cmd_cache->data.paddr, 570 cmd_cache->data.size, DMA_BIDIRECTIONAL); 571 kfree(cmd_cache->data.vaddr); 572 kfree(cmd_cache); 573 } 574 spin_unlock_bh(&dp->reo_cmd_lock); 575 } 576 577 static void ath11k_dp_reo_cmd_free(struct ath11k_dp *dp, void *ctx, 578 enum hal_reo_cmd_status status) 579 { 580 struct dp_rx_tid *rx_tid = ctx; 581 582 if (status != HAL_REO_CMD_SUCCESS) 583 ath11k_warn(dp->ab, "failed to flush rx tid hw desc, tid %d status %d\n", 584 rx_tid->tid, status); 585 586 dma_unmap_single(dp->ab->dev, rx_tid->paddr, rx_tid->size, 587 DMA_BIDIRECTIONAL); 588 kfree(rx_tid->vaddr); 589 } 590 591 static void ath11k_dp_reo_cache_flush(struct ath11k_base *ab, 592 struct dp_rx_tid *rx_tid) 593 { 594 struct ath11k_hal_reo_cmd cmd = {0}; 595 unsigned long tot_desc_sz, desc_sz; 596 int ret; 597 598 tot_desc_sz = rx_tid->size; 599 desc_sz = ath11k_hal_reo_qdesc_size(0, HAL_DESC_REO_NON_QOS_TID); 600 601 while (tot_desc_sz > desc_sz) { 602 tot_desc_sz -= desc_sz; 603 cmd.addr_lo = lower_32_bits(rx_tid->paddr + tot_desc_sz); 604 cmd.addr_hi = upper_32_bits(rx_tid->paddr); 605 ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid, 606 HAL_REO_CMD_FLUSH_CACHE, &cmd, 607 NULL); 608 if (ret) 609 ath11k_warn(ab, 610 "failed to send HAL_REO_CMD_FLUSH_CACHE, tid %d (%d)\n", 611 rx_tid->tid, ret); 612 } 613 614 memset(&cmd, 0, sizeof(cmd)); 615 cmd.addr_lo = lower_32_bits(rx_tid->paddr); 616 cmd.addr_hi = upper_32_bits(rx_tid->paddr); 617 cmd.flag |= HAL_REO_CMD_FLG_NEED_STATUS; 618 ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid, 619 HAL_REO_CMD_FLUSH_CACHE, 620 &cmd, ath11k_dp_reo_cmd_free); 621 if (ret) { 622 ath11k_err(ab, "failed to send HAL_REO_CMD_FLUSH_CACHE cmd, tid %d (%d)\n", 623 rx_tid->tid, ret); 624 dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size, 625 DMA_BIDIRECTIONAL); 626 kfree(rx_tid->vaddr); 627 } 628 } 629 630 static void ath11k_dp_rx_tid_del_func(struct ath11k_dp *dp, void *ctx, 631 enum hal_reo_cmd_status status) 632 { 633 struct ath11k_base *ab = dp->ab; 634 struct dp_rx_tid *rx_tid = ctx; 635 struct dp_reo_cache_flush_elem *elem, *tmp; 636 637 if (status == HAL_REO_CMD_DRAIN) { 638 goto free_desc; 639 } else if (status != HAL_REO_CMD_SUCCESS) { 640 /* Shouldn't happen! Cleanup in case of other failure? */ 641 ath11k_warn(ab, "failed to delete rx tid %d hw descriptor %d\n", 642 rx_tid->tid, status); 643 return; 644 } 645 646 elem = kzalloc(sizeof(*elem), GFP_ATOMIC); 647 if (!elem) 648 goto free_desc; 649 650 elem->ts = jiffies; 651 memcpy(&elem->data, rx_tid, sizeof(*rx_tid)); 652 653 spin_lock_bh(&dp->reo_cmd_lock); 654 list_add_tail(&elem->list, &dp->reo_cmd_cache_flush_list); 655 dp->reo_cmd_cache_flush_count++; 656 spin_unlock_bh(&dp->reo_cmd_lock); 657 658 /* Flush and invalidate aged REO desc from HW cache */ 659 spin_lock_bh(&dp->reo_cmd_lock); 660 list_for_each_entry_safe(elem, tmp, &dp->reo_cmd_cache_flush_list, 661 list) { 662 if (dp->reo_cmd_cache_flush_count > DP_REO_DESC_FREE_THRESHOLD || 663 time_after(jiffies, elem->ts + 664 msecs_to_jiffies(DP_REO_DESC_FREE_TIMEOUT_MS))) { 665 list_del(&elem->list); 666 dp->reo_cmd_cache_flush_count--; 667 spin_unlock_bh(&dp->reo_cmd_lock); 668 669 ath11k_dp_reo_cache_flush(ab, &elem->data); 670 kfree(elem); 671 spin_lock_bh(&dp->reo_cmd_lock); 672 } 673 } 674 spin_unlock_bh(&dp->reo_cmd_lock); 675 676 return; 677 free_desc: 678 dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size, 679 DMA_BIDIRECTIONAL); 680 kfree(rx_tid->vaddr); 681 } 682 683 void ath11k_peer_rx_tid_delete(struct ath11k *ar, 684 struct ath11k_peer *peer, u8 tid) 685 { 686 struct ath11k_hal_reo_cmd cmd = {0}; 687 struct dp_rx_tid *rx_tid = &peer->rx_tid[tid]; 688 int ret; 689 690 if (!rx_tid->active) 691 return; 692 693 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS; 694 cmd.addr_lo = lower_32_bits(rx_tid->paddr); 695 cmd.addr_hi = upper_32_bits(rx_tid->paddr); 696 cmd.upd0 |= HAL_REO_CMD_UPD0_VLD; 697 ret = ath11k_dp_tx_send_reo_cmd(ar->ab, rx_tid, 698 HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd, 699 ath11k_dp_rx_tid_del_func); 700 if (ret) { 701 ath11k_err(ar->ab, "failed to send HAL_REO_CMD_UPDATE_RX_QUEUE cmd, tid %d (%d)\n", 702 tid, ret); 703 dma_unmap_single(ar->ab->dev, rx_tid->paddr, rx_tid->size, 704 DMA_BIDIRECTIONAL); 705 kfree(rx_tid->vaddr); 706 } 707 708 rx_tid->active = false; 709 } 710 711 static int ath11k_dp_rx_link_desc_return(struct ath11k_base *ab, 712 u32 *link_desc, 713 enum hal_wbm_rel_bm_act action) 714 { 715 struct ath11k_dp *dp = &ab->dp; 716 struct hal_srng *srng; 717 u32 *desc; 718 int ret = 0; 719 720 srng = &ab->hal.srng_list[dp->wbm_desc_rel_ring.ring_id]; 721 722 spin_lock_bh(&srng->lock); 723 724 ath11k_hal_srng_access_begin(ab, srng); 725 726 desc = ath11k_hal_srng_src_get_next_entry(ab, srng); 727 if (!desc) { 728 ret = -ENOBUFS; 729 goto exit; 730 } 731 732 ath11k_hal_rx_msdu_link_desc_set(ab, (void *)desc, (void *)link_desc, 733 action); 734 735 exit: 736 ath11k_hal_srng_access_end(ab, srng); 737 738 spin_unlock_bh(&srng->lock); 739 740 return ret; 741 } 742 743 static void ath11k_dp_rx_frags_cleanup(struct dp_rx_tid *rx_tid, bool rel_link_desc) 744 { 745 struct ath11k_base *ab = rx_tid->ab; 746 747 lockdep_assert_held(&ab->base_lock); 748 749 if (rx_tid->dst_ring_desc) { 750 if (rel_link_desc) 751 ath11k_dp_rx_link_desc_return(ab, (u32 *)rx_tid->dst_ring_desc, 752 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 753 kfree(rx_tid->dst_ring_desc); 754 rx_tid->dst_ring_desc = NULL; 755 } 756 757 rx_tid->cur_sn = 0; 758 rx_tid->last_frag_no = 0; 759 rx_tid->rx_frag_bitmap = 0; 760 __skb_queue_purge(&rx_tid->rx_frags); 761 } 762 763 void ath11k_peer_rx_tid_cleanup(struct ath11k *ar, struct ath11k_peer *peer) 764 { 765 struct dp_rx_tid *rx_tid; 766 int i; 767 768 lockdep_assert_held(&ar->ab->base_lock); 769 770 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) { 771 rx_tid = &peer->rx_tid[i]; 772 773 ath11k_peer_rx_tid_delete(ar, peer, i); 774 ath11k_dp_rx_frags_cleanup(rx_tid, true); 775 776 spin_unlock_bh(&ar->ab->base_lock); 777 del_timer_sync(&rx_tid->frag_timer); 778 spin_lock_bh(&ar->ab->base_lock); 779 } 780 } 781 782 static int ath11k_peer_rx_tid_reo_update(struct ath11k *ar, 783 struct ath11k_peer *peer, 784 struct dp_rx_tid *rx_tid, 785 u32 ba_win_sz, u16 ssn, 786 bool update_ssn) 787 { 788 struct ath11k_hal_reo_cmd cmd = {0}; 789 int ret; 790 791 cmd.addr_lo = lower_32_bits(rx_tid->paddr); 792 cmd.addr_hi = upper_32_bits(rx_tid->paddr); 793 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS; 794 cmd.upd0 = HAL_REO_CMD_UPD0_BA_WINDOW_SIZE; 795 cmd.ba_window_size = ba_win_sz; 796 797 if (update_ssn) { 798 cmd.upd0 |= HAL_REO_CMD_UPD0_SSN; 799 cmd.upd2 = FIELD_PREP(HAL_REO_CMD_UPD2_SSN, ssn); 800 } 801 802 ret = ath11k_dp_tx_send_reo_cmd(ar->ab, rx_tid, 803 HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd, 804 NULL); 805 if (ret) { 806 ath11k_warn(ar->ab, "failed to update rx tid queue, tid %d (%d)\n", 807 rx_tid->tid, ret); 808 return ret; 809 } 810 811 rx_tid->ba_win_sz = ba_win_sz; 812 813 return 0; 814 } 815 816 static void ath11k_dp_rx_tid_mem_free(struct ath11k_base *ab, 817 const u8 *peer_mac, int vdev_id, u8 tid) 818 { 819 struct ath11k_peer *peer; 820 struct dp_rx_tid *rx_tid; 821 822 spin_lock_bh(&ab->base_lock); 823 824 peer = ath11k_peer_find(ab, vdev_id, peer_mac); 825 if (!peer) { 826 ath11k_warn(ab, "failed to find the peer to free up rx tid mem\n"); 827 goto unlock_exit; 828 } 829 830 rx_tid = &peer->rx_tid[tid]; 831 if (!rx_tid->active) 832 goto unlock_exit; 833 834 dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size, 835 DMA_BIDIRECTIONAL); 836 kfree(rx_tid->vaddr); 837 838 rx_tid->active = false; 839 840 unlock_exit: 841 spin_unlock_bh(&ab->base_lock); 842 } 843 844 int ath11k_peer_rx_tid_setup(struct ath11k *ar, const u8 *peer_mac, int vdev_id, 845 u8 tid, u32 ba_win_sz, u16 ssn, 846 enum hal_pn_type pn_type) 847 { 848 struct ath11k_base *ab = ar->ab; 849 struct ath11k_peer *peer; 850 struct dp_rx_tid *rx_tid; 851 u32 hw_desc_sz; 852 u32 *addr_aligned; 853 void *vaddr; 854 dma_addr_t paddr; 855 int ret; 856 857 spin_lock_bh(&ab->base_lock); 858 859 peer = ath11k_peer_find(ab, vdev_id, peer_mac); 860 if (!peer) { 861 ath11k_warn(ab, "failed to find the peer to set up rx tid\n"); 862 spin_unlock_bh(&ab->base_lock); 863 return -ENOENT; 864 } 865 866 rx_tid = &peer->rx_tid[tid]; 867 /* Update the tid queue if it is already setup */ 868 if (rx_tid->active) { 869 paddr = rx_tid->paddr; 870 ret = ath11k_peer_rx_tid_reo_update(ar, peer, rx_tid, 871 ba_win_sz, ssn, true); 872 spin_unlock_bh(&ab->base_lock); 873 if (ret) { 874 ath11k_warn(ab, "failed to update reo for rx tid %d\n", tid); 875 return ret; 876 } 877 878 ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, 879 peer_mac, paddr, 880 tid, 1, ba_win_sz); 881 if (ret) 882 ath11k_warn(ab, "failed to send wmi command to update rx reorder queue, tid :%d (%d)\n", 883 tid, ret); 884 return ret; 885 } 886 887 rx_tid->tid = tid; 888 889 rx_tid->ba_win_sz = ba_win_sz; 890 891 /* TODO: Optimize the memory allocation for qos tid based on the 892 * the actual BA window size in REO tid update path. 893 */ 894 if (tid == HAL_DESC_REO_NON_QOS_TID) 895 hw_desc_sz = ath11k_hal_reo_qdesc_size(ba_win_sz, tid); 896 else 897 hw_desc_sz = ath11k_hal_reo_qdesc_size(DP_BA_WIN_SZ_MAX, tid); 898 899 vaddr = kzalloc(hw_desc_sz + HAL_LINK_DESC_ALIGN - 1, GFP_ATOMIC); 900 if (!vaddr) { 901 spin_unlock_bh(&ab->base_lock); 902 return -ENOMEM; 903 } 904 905 addr_aligned = PTR_ALIGN(vaddr, HAL_LINK_DESC_ALIGN); 906 907 ath11k_hal_reo_qdesc_setup(addr_aligned, tid, ba_win_sz, 908 ssn, pn_type); 909 910 paddr = dma_map_single(ab->dev, addr_aligned, hw_desc_sz, 911 DMA_BIDIRECTIONAL); 912 913 ret = dma_mapping_error(ab->dev, paddr); 914 if (ret) { 915 spin_unlock_bh(&ab->base_lock); 916 goto err_mem_free; 917 } 918 919 rx_tid->vaddr = vaddr; 920 rx_tid->paddr = paddr; 921 rx_tid->size = hw_desc_sz; 922 rx_tid->active = true; 923 924 spin_unlock_bh(&ab->base_lock); 925 926 ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, peer_mac, 927 paddr, tid, 1, ba_win_sz); 928 if (ret) { 929 ath11k_warn(ar->ab, "failed to setup rx reorder queue, tid :%d (%d)\n", 930 tid, ret); 931 ath11k_dp_rx_tid_mem_free(ab, peer_mac, vdev_id, tid); 932 } 933 934 return ret; 935 936 err_mem_free: 937 kfree(vaddr); 938 939 return ret; 940 } 941 942 int ath11k_dp_rx_ampdu_start(struct ath11k *ar, 943 struct ieee80211_ampdu_params *params) 944 { 945 struct ath11k_base *ab = ar->ab; 946 struct ath11k_sta *arsta = (void *)params->sta->drv_priv; 947 int vdev_id = arsta->arvif->vdev_id; 948 int ret; 949 950 ret = ath11k_peer_rx_tid_setup(ar, params->sta->addr, vdev_id, 951 params->tid, params->buf_size, 952 params->ssn, arsta->pn_type); 953 if (ret) 954 ath11k_warn(ab, "failed to setup rx tid %d\n", ret); 955 956 return ret; 957 } 958 959 int ath11k_dp_rx_ampdu_stop(struct ath11k *ar, 960 struct ieee80211_ampdu_params *params) 961 { 962 struct ath11k_base *ab = ar->ab; 963 struct ath11k_peer *peer; 964 struct ath11k_sta *arsta = (void *)params->sta->drv_priv; 965 int vdev_id = arsta->arvif->vdev_id; 966 dma_addr_t paddr; 967 bool active; 968 int ret; 969 970 spin_lock_bh(&ab->base_lock); 971 972 peer = ath11k_peer_find(ab, vdev_id, params->sta->addr); 973 if (!peer) { 974 ath11k_warn(ab, "failed to find the peer to stop rx aggregation\n"); 975 spin_unlock_bh(&ab->base_lock); 976 return -ENOENT; 977 } 978 979 paddr = peer->rx_tid[params->tid].paddr; 980 active = peer->rx_tid[params->tid].active; 981 982 if (!active) { 983 spin_unlock_bh(&ab->base_lock); 984 return 0; 985 } 986 987 ret = ath11k_peer_rx_tid_reo_update(ar, peer, peer->rx_tid, 1, 0, false); 988 spin_unlock_bh(&ab->base_lock); 989 if (ret) { 990 ath11k_warn(ab, "failed to update reo for rx tid %d: %d\n", 991 params->tid, ret); 992 return ret; 993 } 994 995 ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, 996 params->sta->addr, paddr, 997 params->tid, 1, 1); 998 if (ret) 999 ath11k_warn(ab, "failed to send wmi to delete rx tid %d\n", 1000 ret); 1001 1002 return ret; 1003 } 1004 1005 int ath11k_dp_peer_rx_pn_replay_config(struct ath11k_vif *arvif, 1006 const u8 *peer_addr, 1007 enum set_key_cmd key_cmd, 1008 struct ieee80211_key_conf *key) 1009 { 1010 struct ath11k *ar = arvif->ar; 1011 struct ath11k_base *ab = ar->ab; 1012 struct ath11k_hal_reo_cmd cmd = {0}; 1013 struct ath11k_peer *peer; 1014 struct dp_rx_tid *rx_tid; 1015 u8 tid; 1016 int ret = 0; 1017 1018 /* NOTE: Enable PN/TSC replay check offload only for unicast frames. 1019 * We use mac80211 PN/TSC replay check functionality for bcast/mcast 1020 * for now. 1021 */ 1022 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) 1023 return 0; 1024 1025 cmd.flag |= HAL_REO_CMD_FLG_NEED_STATUS; 1026 cmd.upd0 |= HAL_REO_CMD_UPD0_PN | 1027 HAL_REO_CMD_UPD0_PN_SIZE | 1028 HAL_REO_CMD_UPD0_PN_VALID | 1029 HAL_REO_CMD_UPD0_PN_CHECK | 1030 HAL_REO_CMD_UPD0_SVLD; 1031 1032 switch (key->cipher) { 1033 case WLAN_CIPHER_SUITE_TKIP: 1034 case WLAN_CIPHER_SUITE_CCMP: 1035 case WLAN_CIPHER_SUITE_CCMP_256: 1036 case WLAN_CIPHER_SUITE_GCMP: 1037 case WLAN_CIPHER_SUITE_GCMP_256: 1038 if (key_cmd == SET_KEY) { 1039 cmd.upd1 |= HAL_REO_CMD_UPD1_PN_CHECK; 1040 cmd.pn_size = 48; 1041 } 1042 break; 1043 default: 1044 break; 1045 } 1046 1047 spin_lock_bh(&ab->base_lock); 1048 1049 peer = ath11k_peer_find(ab, arvif->vdev_id, peer_addr); 1050 if (!peer) { 1051 ath11k_warn(ab, "failed to find the peer to configure pn replay detection\n"); 1052 spin_unlock_bh(&ab->base_lock); 1053 return -ENOENT; 1054 } 1055 1056 for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) { 1057 rx_tid = &peer->rx_tid[tid]; 1058 if (!rx_tid->active) 1059 continue; 1060 cmd.addr_lo = lower_32_bits(rx_tid->paddr); 1061 cmd.addr_hi = upper_32_bits(rx_tid->paddr); 1062 ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid, 1063 HAL_REO_CMD_UPDATE_RX_QUEUE, 1064 &cmd, NULL); 1065 if (ret) { 1066 ath11k_warn(ab, "failed to configure rx tid %d queue for pn replay detection %d\n", 1067 tid, ret); 1068 break; 1069 } 1070 } 1071 1072 spin_unlock_bh(&ar->ab->base_lock); 1073 1074 return ret; 1075 } 1076 1077 static inline int ath11k_get_ppdu_user_index(struct htt_ppdu_stats *ppdu_stats, 1078 u16 peer_id) 1079 { 1080 int i; 1081 1082 for (i = 0; i < HTT_PPDU_STATS_MAX_USERS - 1; i++) { 1083 if (ppdu_stats->user_stats[i].is_valid_peer_id) { 1084 if (peer_id == ppdu_stats->user_stats[i].peer_id) 1085 return i; 1086 } else { 1087 return i; 1088 } 1089 } 1090 1091 return -EINVAL; 1092 } 1093 1094 static int ath11k_htt_tlv_ppdu_stats_parse(struct ath11k_base *ab, 1095 u16 tag, u16 len, const void *ptr, 1096 void *data) 1097 { 1098 struct htt_ppdu_stats_info *ppdu_info; 1099 struct htt_ppdu_user_stats *user_stats; 1100 int cur_user; 1101 u16 peer_id; 1102 1103 ppdu_info = (struct htt_ppdu_stats_info *)data; 1104 1105 switch (tag) { 1106 case HTT_PPDU_STATS_TAG_COMMON: 1107 if (len < sizeof(struct htt_ppdu_stats_common)) { 1108 ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1109 len, tag); 1110 return -EINVAL; 1111 } 1112 memcpy((void *)&ppdu_info->ppdu_stats.common, ptr, 1113 sizeof(struct htt_ppdu_stats_common)); 1114 break; 1115 case HTT_PPDU_STATS_TAG_USR_RATE: 1116 if (len < sizeof(struct htt_ppdu_stats_user_rate)) { 1117 ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1118 len, tag); 1119 return -EINVAL; 1120 } 1121 1122 peer_id = ((struct htt_ppdu_stats_user_rate *)ptr)->sw_peer_id; 1123 cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats, 1124 peer_id); 1125 if (cur_user < 0) 1126 return -EINVAL; 1127 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user]; 1128 user_stats->peer_id = peer_id; 1129 user_stats->is_valid_peer_id = true; 1130 memcpy((void *)&user_stats->rate, ptr, 1131 sizeof(struct htt_ppdu_stats_user_rate)); 1132 user_stats->tlv_flags |= BIT(tag); 1133 break; 1134 case HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON: 1135 if (len < sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)) { 1136 ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1137 len, tag); 1138 return -EINVAL; 1139 } 1140 1141 peer_id = ((struct htt_ppdu_stats_usr_cmpltn_cmn *)ptr)->sw_peer_id; 1142 cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats, 1143 peer_id); 1144 if (cur_user < 0) 1145 return -EINVAL; 1146 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user]; 1147 user_stats->peer_id = peer_id; 1148 user_stats->is_valid_peer_id = true; 1149 memcpy((void *)&user_stats->cmpltn_cmn, ptr, 1150 sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)); 1151 user_stats->tlv_flags |= BIT(tag); 1152 break; 1153 case HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS: 1154 if (len < 1155 sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)) { 1156 ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1157 len, tag); 1158 return -EINVAL; 1159 } 1160 1161 peer_id = 1162 ((struct htt_ppdu_stats_usr_cmpltn_ack_ba_status *)ptr)->sw_peer_id; 1163 cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats, 1164 peer_id); 1165 if (cur_user < 0) 1166 return -EINVAL; 1167 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user]; 1168 user_stats->peer_id = peer_id; 1169 user_stats->is_valid_peer_id = true; 1170 memcpy((void *)&user_stats->ack_ba, ptr, 1171 sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)); 1172 user_stats->tlv_flags |= BIT(tag); 1173 break; 1174 } 1175 return 0; 1176 } 1177 1178 int ath11k_dp_htt_tlv_iter(struct ath11k_base *ab, const void *ptr, size_t len, 1179 int (*iter)(struct ath11k_base *ar, u16 tag, u16 len, 1180 const void *ptr, void *data), 1181 void *data) 1182 { 1183 const struct htt_tlv *tlv; 1184 const void *begin = ptr; 1185 u16 tlv_tag, tlv_len; 1186 int ret = -EINVAL; 1187 1188 while (len > 0) { 1189 if (len < sizeof(*tlv)) { 1190 ath11k_err(ab, "htt tlv parse failure at byte %zd (%zu bytes left, %zu expected)\n", 1191 ptr - begin, len, sizeof(*tlv)); 1192 return -EINVAL; 1193 } 1194 tlv = (struct htt_tlv *)ptr; 1195 tlv_tag = FIELD_GET(HTT_TLV_TAG, tlv->header); 1196 tlv_len = FIELD_GET(HTT_TLV_LEN, tlv->header); 1197 ptr += sizeof(*tlv); 1198 len -= sizeof(*tlv); 1199 1200 if (tlv_len > len) { 1201 ath11k_err(ab, "htt tlv parse failure of tag %hhu at byte %zd (%zu bytes left, %hhu expected)\n", 1202 tlv_tag, ptr - begin, len, tlv_len); 1203 return -EINVAL; 1204 } 1205 ret = iter(ab, tlv_tag, tlv_len, ptr, data); 1206 if (ret == -ENOMEM) 1207 return ret; 1208 1209 ptr += tlv_len; 1210 len -= tlv_len; 1211 } 1212 return 0; 1213 } 1214 1215 static inline u32 ath11k_he_gi_to_nl80211_he_gi(u8 sgi) 1216 { 1217 u32 ret = 0; 1218 1219 switch (sgi) { 1220 case RX_MSDU_START_SGI_0_8_US: 1221 ret = NL80211_RATE_INFO_HE_GI_0_8; 1222 break; 1223 case RX_MSDU_START_SGI_1_6_US: 1224 ret = NL80211_RATE_INFO_HE_GI_1_6; 1225 break; 1226 case RX_MSDU_START_SGI_3_2_US: 1227 ret = NL80211_RATE_INFO_HE_GI_3_2; 1228 break; 1229 } 1230 1231 return ret; 1232 } 1233 1234 static void 1235 ath11k_update_per_peer_tx_stats(struct ath11k *ar, 1236 struct htt_ppdu_stats *ppdu_stats, u8 user) 1237 { 1238 struct ath11k_base *ab = ar->ab; 1239 struct ath11k_peer *peer; 1240 struct ieee80211_sta *sta; 1241 struct ath11k_sta *arsta; 1242 struct htt_ppdu_stats_user_rate *user_rate; 1243 struct ath11k_per_peer_tx_stats *peer_stats = &ar->peer_tx_stats; 1244 struct htt_ppdu_user_stats *usr_stats = &ppdu_stats->user_stats[user]; 1245 struct htt_ppdu_stats_common *common = &ppdu_stats->common; 1246 int ret; 1247 u8 flags, mcs, nss, bw, sgi, dcm, rate_idx = 0; 1248 u32 succ_bytes = 0; 1249 u16 rate = 0, succ_pkts = 0; 1250 u32 tx_duration = 0; 1251 u8 tid = HTT_PPDU_STATS_NON_QOS_TID; 1252 bool is_ampdu = false; 1253 1254 if (!usr_stats) 1255 return; 1256 1257 if (!(usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_RATE))) 1258 return; 1259 1260 if (usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON)) 1261 is_ampdu = 1262 HTT_USR_CMPLTN_IS_AMPDU(usr_stats->cmpltn_cmn.flags); 1263 1264 if (usr_stats->tlv_flags & 1265 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS)) { 1266 succ_bytes = usr_stats->ack_ba.success_bytes; 1267 succ_pkts = FIELD_GET(HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M, 1268 usr_stats->ack_ba.info); 1269 tid = FIELD_GET(HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM, 1270 usr_stats->ack_ba.info); 1271 } 1272 1273 if (common->fes_duration_us) 1274 tx_duration = common->fes_duration_us; 1275 1276 user_rate = &usr_stats->rate; 1277 flags = HTT_USR_RATE_PREAMBLE(user_rate->rate_flags); 1278 bw = HTT_USR_RATE_BW(user_rate->rate_flags) - 2; 1279 nss = HTT_USR_RATE_NSS(user_rate->rate_flags) + 1; 1280 mcs = HTT_USR_RATE_MCS(user_rate->rate_flags); 1281 sgi = HTT_USR_RATE_GI(user_rate->rate_flags); 1282 dcm = HTT_USR_RATE_DCM(user_rate->rate_flags); 1283 1284 /* Note: If host configured fixed rates and in some other special 1285 * cases, the broadcast/management frames are sent in different rates. 1286 * Firmware rate's control to be skipped for this? 1287 */ 1288 1289 if (flags == WMI_RATE_PREAMBLE_HE && mcs > 11) { 1290 ath11k_warn(ab, "Invalid HE mcs %hhd peer stats", mcs); 1291 return; 1292 } 1293 1294 if (flags == WMI_RATE_PREAMBLE_HE && mcs > ATH11K_HE_MCS_MAX) { 1295 ath11k_warn(ab, "Invalid HE mcs %hhd peer stats", mcs); 1296 return; 1297 } 1298 1299 if (flags == WMI_RATE_PREAMBLE_VHT && mcs > ATH11K_VHT_MCS_MAX) { 1300 ath11k_warn(ab, "Invalid VHT mcs %hhd peer stats", mcs); 1301 return; 1302 } 1303 1304 if (flags == WMI_RATE_PREAMBLE_HT && (mcs > ATH11K_HT_MCS_MAX || nss < 1)) { 1305 ath11k_warn(ab, "Invalid HT mcs %hhd nss %hhd peer stats", 1306 mcs, nss); 1307 return; 1308 } 1309 1310 if (flags == WMI_RATE_PREAMBLE_CCK || flags == WMI_RATE_PREAMBLE_OFDM) { 1311 ret = ath11k_mac_hw_ratecode_to_legacy_rate(mcs, 1312 flags, 1313 &rate_idx, 1314 &rate); 1315 if (ret < 0) 1316 return; 1317 } 1318 1319 rcu_read_lock(); 1320 spin_lock_bh(&ab->base_lock); 1321 peer = ath11k_peer_find_by_id(ab, usr_stats->peer_id); 1322 1323 if (!peer || !peer->sta) { 1324 spin_unlock_bh(&ab->base_lock); 1325 rcu_read_unlock(); 1326 return; 1327 } 1328 1329 sta = peer->sta; 1330 arsta = (struct ath11k_sta *)sta->drv_priv; 1331 1332 memset(&arsta->txrate, 0, sizeof(arsta->txrate)); 1333 1334 switch (flags) { 1335 case WMI_RATE_PREAMBLE_OFDM: 1336 arsta->txrate.legacy = rate; 1337 break; 1338 case WMI_RATE_PREAMBLE_CCK: 1339 arsta->txrate.legacy = rate; 1340 break; 1341 case WMI_RATE_PREAMBLE_HT: 1342 arsta->txrate.mcs = mcs + 8 * (nss - 1); 1343 arsta->txrate.flags = RATE_INFO_FLAGS_MCS; 1344 if (sgi) 1345 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 1346 break; 1347 case WMI_RATE_PREAMBLE_VHT: 1348 arsta->txrate.mcs = mcs; 1349 arsta->txrate.flags = RATE_INFO_FLAGS_VHT_MCS; 1350 if (sgi) 1351 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 1352 break; 1353 case WMI_RATE_PREAMBLE_HE: 1354 arsta->txrate.mcs = mcs; 1355 arsta->txrate.flags = RATE_INFO_FLAGS_HE_MCS; 1356 arsta->txrate.he_dcm = dcm; 1357 arsta->txrate.he_gi = ath11k_he_gi_to_nl80211_he_gi(sgi); 1358 arsta->txrate.he_ru_alloc = ath11k_he_ru_tones_to_nl80211_he_ru_alloc( 1359 (user_rate->ru_end - 1360 user_rate->ru_start) + 1); 1361 break; 1362 } 1363 1364 arsta->txrate.nss = nss; 1365 arsta->txrate.bw = ath11k_mac_bw_to_mac80211_bw(bw); 1366 arsta->tx_duration += tx_duration; 1367 memcpy(&arsta->last_txrate, &arsta->txrate, sizeof(struct rate_info)); 1368 1369 /* PPDU stats reported for mgmt packet doesn't have valid tx bytes. 1370 * So skip peer stats update for mgmt packets. 1371 */ 1372 if (tid < HTT_PPDU_STATS_NON_QOS_TID) { 1373 memset(peer_stats, 0, sizeof(*peer_stats)); 1374 peer_stats->succ_pkts = succ_pkts; 1375 peer_stats->succ_bytes = succ_bytes; 1376 peer_stats->is_ampdu = is_ampdu; 1377 peer_stats->duration = tx_duration; 1378 peer_stats->ba_fails = 1379 HTT_USR_CMPLTN_LONG_RETRY(usr_stats->cmpltn_cmn.flags) + 1380 HTT_USR_CMPLTN_SHORT_RETRY(usr_stats->cmpltn_cmn.flags); 1381 1382 if (ath11k_debug_is_extd_tx_stats_enabled(ar)) 1383 ath11k_accumulate_per_peer_tx_stats(arsta, 1384 peer_stats, rate_idx); 1385 } 1386 1387 spin_unlock_bh(&ab->base_lock); 1388 rcu_read_unlock(); 1389 } 1390 1391 static void ath11k_htt_update_ppdu_stats(struct ath11k *ar, 1392 struct htt_ppdu_stats *ppdu_stats) 1393 { 1394 u8 user; 1395 1396 for (user = 0; user < HTT_PPDU_STATS_MAX_USERS - 1; user++) 1397 ath11k_update_per_peer_tx_stats(ar, ppdu_stats, user); 1398 } 1399 1400 static 1401 struct htt_ppdu_stats_info *ath11k_dp_htt_get_ppdu_desc(struct ath11k *ar, 1402 u32 ppdu_id) 1403 { 1404 struct htt_ppdu_stats_info *ppdu_info; 1405 1406 spin_lock_bh(&ar->data_lock); 1407 if (!list_empty(&ar->ppdu_stats_info)) { 1408 list_for_each_entry(ppdu_info, &ar->ppdu_stats_info, list) { 1409 if (ppdu_info->ppdu_id == ppdu_id) { 1410 spin_unlock_bh(&ar->data_lock); 1411 return ppdu_info; 1412 } 1413 } 1414 1415 if (ar->ppdu_stat_list_depth > HTT_PPDU_DESC_MAX_DEPTH) { 1416 ppdu_info = list_first_entry(&ar->ppdu_stats_info, 1417 typeof(*ppdu_info), list); 1418 list_del(&ppdu_info->list); 1419 ar->ppdu_stat_list_depth--; 1420 ath11k_htt_update_ppdu_stats(ar, &ppdu_info->ppdu_stats); 1421 kfree(ppdu_info); 1422 } 1423 } 1424 spin_unlock_bh(&ar->data_lock); 1425 1426 ppdu_info = kzalloc(sizeof(*ppdu_info), GFP_KERNEL); 1427 if (!ppdu_info) 1428 return NULL; 1429 1430 spin_lock_bh(&ar->data_lock); 1431 list_add_tail(&ppdu_info->list, &ar->ppdu_stats_info); 1432 ar->ppdu_stat_list_depth++; 1433 spin_unlock_bh(&ar->data_lock); 1434 1435 return ppdu_info; 1436 } 1437 1438 static int ath11k_htt_pull_ppdu_stats(struct ath11k_base *ab, 1439 struct sk_buff *skb) 1440 { 1441 struct ath11k_htt_ppdu_stats_msg *msg; 1442 struct htt_ppdu_stats_info *ppdu_info; 1443 struct ath11k *ar; 1444 int ret; 1445 u8 pdev_id; 1446 u32 ppdu_id, len; 1447 1448 msg = (struct ath11k_htt_ppdu_stats_msg *)skb->data; 1449 len = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE, msg->info); 1450 pdev_id = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PDEV_ID, msg->info); 1451 ppdu_id = msg->ppdu_id; 1452 1453 rcu_read_lock(); 1454 ar = ath11k_mac_get_ar_by_pdev_id(ab, pdev_id); 1455 if (!ar) { 1456 ret = -EINVAL; 1457 goto exit; 1458 } 1459 1460 if (ath11k_debug_is_pktlog_lite_mode_enabled(ar)) 1461 trace_ath11k_htt_ppdu_stats(ar, skb->data, len); 1462 1463 ppdu_info = ath11k_dp_htt_get_ppdu_desc(ar, ppdu_id); 1464 if (!ppdu_info) { 1465 ret = -EINVAL; 1466 goto exit; 1467 } 1468 1469 ppdu_info->ppdu_id = ppdu_id; 1470 ret = ath11k_dp_htt_tlv_iter(ab, msg->data, len, 1471 ath11k_htt_tlv_ppdu_stats_parse, 1472 (void *)ppdu_info); 1473 if (ret) { 1474 ath11k_warn(ab, "Failed to parse tlv %d\n", ret); 1475 goto exit; 1476 } 1477 1478 exit: 1479 rcu_read_unlock(); 1480 1481 return ret; 1482 } 1483 1484 static void ath11k_htt_pktlog(struct ath11k_base *ab, struct sk_buff *skb) 1485 { 1486 struct htt_pktlog_msg *data = (struct htt_pktlog_msg *)skb->data; 1487 struct ath_pktlog_hdr *hdr = (struct ath_pktlog_hdr *)data; 1488 struct ath11k *ar; 1489 u8 pdev_id; 1490 1491 pdev_id = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PDEV_ID, data->hdr); 1492 ar = ath11k_mac_get_ar_by_pdev_id(ab, pdev_id); 1493 if (!ar) { 1494 ath11k_warn(ab, "invalid pdev id %d on htt pktlog\n", pdev_id); 1495 return; 1496 } 1497 1498 trace_ath11k_htt_pktlog(ar, data->payload, hdr->size, 1499 ar->ab->pktlog_defs_checksum); 1500 } 1501 1502 static void ath11k_htt_backpressure_event_handler(struct ath11k_base *ab, 1503 struct sk_buff *skb) 1504 { 1505 u32 *data = (u32 *)skb->data; 1506 u8 pdev_id, ring_type, ring_id; 1507 u16 hp, tp; 1508 u32 backpressure_time; 1509 1510 pdev_id = FIELD_GET(HTT_BACKPRESSURE_EVENT_PDEV_ID_M, *data); 1511 ring_type = FIELD_GET(HTT_BACKPRESSURE_EVENT_RING_TYPE_M, *data); 1512 ring_id = FIELD_GET(HTT_BACKPRESSURE_EVENT_RING_ID_M, *data); 1513 ++data; 1514 1515 hp = FIELD_GET(HTT_BACKPRESSURE_EVENT_HP_M, *data); 1516 tp = FIELD_GET(HTT_BACKPRESSURE_EVENT_TP_M, *data); 1517 ++data; 1518 1519 backpressure_time = *data; 1520 1521 ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "htt backpressure event, pdev %d, ring type %d,ring id %d, hp %d tp %d, backpressure time %d\n", 1522 pdev_id, ring_type, ring_id, hp, tp, backpressure_time); 1523 } 1524 1525 void ath11k_dp_htt_htc_t2h_msg_handler(struct ath11k_base *ab, 1526 struct sk_buff *skb) 1527 { 1528 struct ath11k_dp *dp = &ab->dp; 1529 struct htt_resp_msg *resp = (struct htt_resp_msg *)skb->data; 1530 enum htt_t2h_msg_type type = FIELD_GET(HTT_T2H_MSG_TYPE, *(u32 *)resp); 1531 u16 peer_id; 1532 u8 vdev_id; 1533 u8 mac_addr[ETH_ALEN]; 1534 u16 peer_mac_h16; 1535 u16 ast_hash; 1536 1537 ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "dp_htt rx msg type :0x%0x\n", type); 1538 1539 switch (type) { 1540 case HTT_T2H_MSG_TYPE_VERSION_CONF: 1541 dp->htt_tgt_ver_major = FIELD_GET(HTT_T2H_VERSION_CONF_MAJOR, 1542 resp->version_msg.version); 1543 dp->htt_tgt_ver_minor = FIELD_GET(HTT_T2H_VERSION_CONF_MINOR, 1544 resp->version_msg.version); 1545 complete(&dp->htt_tgt_version_received); 1546 break; 1547 case HTT_T2H_MSG_TYPE_PEER_MAP: 1548 vdev_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_VDEV_ID, 1549 resp->peer_map_ev.info); 1550 peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_PEER_ID, 1551 resp->peer_map_ev.info); 1552 peer_mac_h16 = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16, 1553 resp->peer_map_ev.info1); 1554 ath11k_dp_get_mac_addr(resp->peer_map_ev.mac_addr_l32, 1555 peer_mac_h16, mac_addr); 1556 ast_hash = FIELD_GET(HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL, 1557 resp->peer_map_ev.info2); 1558 ath11k_peer_map_event(ab, vdev_id, peer_id, mac_addr, ast_hash); 1559 break; 1560 case HTT_T2H_MSG_TYPE_PEER_UNMAP: 1561 peer_id = FIELD_GET(HTT_T2H_PEER_UNMAP_INFO_PEER_ID, 1562 resp->peer_unmap_ev.info); 1563 ath11k_peer_unmap_event(ab, peer_id); 1564 break; 1565 case HTT_T2H_MSG_TYPE_PPDU_STATS_IND: 1566 ath11k_htt_pull_ppdu_stats(ab, skb); 1567 break; 1568 case HTT_T2H_MSG_TYPE_EXT_STATS_CONF: 1569 ath11k_dbg_htt_ext_stats_handler(ab, skb); 1570 break; 1571 case HTT_T2H_MSG_TYPE_PKTLOG: 1572 ath11k_htt_pktlog(ab, skb); 1573 break; 1574 case HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND: 1575 ath11k_htt_backpressure_event_handler(ab, skb); 1576 break; 1577 default: 1578 ath11k_warn(ab, "htt event %d not handled\n", type); 1579 break; 1580 } 1581 1582 dev_kfree_skb_any(skb); 1583 } 1584 1585 static int ath11k_dp_rx_msdu_coalesce(struct ath11k *ar, 1586 struct sk_buff_head *msdu_list, 1587 struct sk_buff *first, struct sk_buff *last, 1588 u8 l3pad_bytes, int msdu_len) 1589 { 1590 struct sk_buff *skb; 1591 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(first); 1592 int buf_first_hdr_len, buf_first_len; 1593 struct hal_rx_desc *ldesc; 1594 int space_extra; 1595 int rem_len; 1596 int buf_len; 1597 1598 /* As the msdu is spread across multiple rx buffers, 1599 * find the offset to the start of msdu for computing 1600 * the length of the msdu in the first buffer. 1601 */ 1602 buf_first_hdr_len = HAL_RX_DESC_SIZE + l3pad_bytes; 1603 buf_first_len = DP_RX_BUFFER_SIZE - buf_first_hdr_len; 1604 1605 if (WARN_ON_ONCE(msdu_len <= buf_first_len)) { 1606 skb_put(first, buf_first_hdr_len + msdu_len); 1607 skb_pull(first, buf_first_hdr_len); 1608 return 0; 1609 } 1610 1611 ldesc = (struct hal_rx_desc *)last->data; 1612 rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ldesc); 1613 rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ldesc); 1614 1615 /* MSDU spans over multiple buffers because the length of the MSDU 1616 * exceeds DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. So assume the data 1617 * in the first buf is of length DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. 1618 */ 1619 skb_put(first, DP_RX_BUFFER_SIZE); 1620 skb_pull(first, buf_first_hdr_len); 1621 1622 /* When an MSDU spread over multiple buffers attention, MSDU_END and 1623 * MPDU_END tlvs are valid only in the last buffer. Copy those tlvs. 1624 */ 1625 ath11k_dp_rx_desc_end_tlv_copy(rxcb->rx_desc, ldesc); 1626 1627 space_extra = msdu_len - (buf_first_len + skb_tailroom(first)); 1628 if (space_extra > 0 && 1629 (pskb_expand_head(first, 0, space_extra, GFP_ATOMIC) < 0)) { 1630 /* Free up all buffers of the MSDU */ 1631 while ((skb = __skb_dequeue(msdu_list)) != NULL) { 1632 rxcb = ATH11K_SKB_RXCB(skb); 1633 if (!rxcb->is_continuation) { 1634 dev_kfree_skb_any(skb); 1635 break; 1636 } 1637 dev_kfree_skb_any(skb); 1638 } 1639 return -ENOMEM; 1640 } 1641 1642 rem_len = msdu_len - buf_first_len; 1643 while ((skb = __skb_dequeue(msdu_list)) != NULL && rem_len > 0) { 1644 rxcb = ATH11K_SKB_RXCB(skb); 1645 if (rxcb->is_continuation) 1646 buf_len = DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE; 1647 else 1648 buf_len = rem_len; 1649 1650 if (buf_len > (DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE)) { 1651 WARN_ON_ONCE(1); 1652 dev_kfree_skb_any(skb); 1653 return -EINVAL; 1654 } 1655 1656 skb_put(skb, buf_len + HAL_RX_DESC_SIZE); 1657 skb_pull(skb, HAL_RX_DESC_SIZE); 1658 skb_copy_from_linear_data(skb, skb_put(first, buf_len), 1659 buf_len); 1660 dev_kfree_skb_any(skb); 1661 1662 rem_len -= buf_len; 1663 if (!rxcb->is_continuation) 1664 break; 1665 } 1666 1667 return 0; 1668 } 1669 1670 static struct sk_buff *ath11k_dp_rx_get_msdu_last_buf(struct sk_buff_head *msdu_list, 1671 struct sk_buff *first) 1672 { 1673 struct sk_buff *skb; 1674 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(first); 1675 1676 if (!rxcb->is_continuation) 1677 return first; 1678 1679 skb_queue_walk(msdu_list, skb) { 1680 rxcb = ATH11K_SKB_RXCB(skb); 1681 if (!rxcb->is_continuation) 1682 return skb; 1683 } 1684 1685 return NULL; 1686 } 1687 1688 static void ath11k_dp_rx_h_csum_offload(struct sk_buff *msdu) 1689 { 1690 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 1691 bool ip_csum_fail, l4_csum_fail; 1692 1693 ip_csum_fail = ath11k_dp_rx_h_attn_ip_cksum_fail(rxcb->rx_desc); 1694 l4_csum_fail = ath11k_dp_rx_h_attn_l4_cksum_fail(rxcb->rx_desc); 1695 1696 msdu->ip_summed = (ip_csum_fail || l4_csum_fail) ? 1697 CHECKSUM_NONE : CHECKSUM_UNNECESSARY; 1698 } 1699 1700 static int ath11k_dp_rx_crypto_mic_len(struct ath11k *ar, 1701 enum hal_encrypt_type enctype) 1702 { 1703 switch (enctype) { 1704 case HAL_ENCRYPT_TYPE_OPEN: 1705 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC: 1706 case HAL_ENCRYPT_TYPE_TKIP_MIC: 1707 return 0; 1708 case HAL_ENCRYPT_TYPE_CCMP_128: 1709 return IEEE80211_CCMP_MIC_LEN; 1710 case HAL_ENCRYPT_TYPE_CCMP_256: 1711 return IEEE80211_CCMP_256_MIC_LEN; 1712 case HAL_ENCRYPT_TYPE_GCMP_128: 1713 case HAL_ENCRYPT_TYPE_AES_GCMP_256: 1714 return IEEE80211_GCMP_MIC_LEN; 1715 case HAL_ENCRYPT_TYPE_WEP_40: 1716 case HAL_ENCRYPT_TYPE_WEP_104: 1717 case HAL_ENCRYPT_TYPE_WEP_128: 1718 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4: 1719 case HAL_ENCRYPT_TYPE_WAPI: 1720 break; 1721 } 1722 1723 ath11k_warn(ar->ab, "unsupported encryption type %d for mic len\n", enctype); 1724 return 0; 1725 } 1726 1727 static int ath11k_dp_rx_crypto_param_len(struct ath11k *ar, 1728 enum hal_encrypt_type enctype) 1729 { 1730 switch (enctype) { 1731 case HAL_ENCRYPT_TYPE_OPEN: 1732 return 0; 1733 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC: 1734 case HAL_ENCRYPT_TYPE_TKIP_MIC: 1735 return IEEE80211_TKIP_IV_LEN; 1736 case HAL_ENCRYPT_TYPE_CCMP_128: 1737 return IEEE80211_CCMP_HDR_LEN; 1738 case HAL_ENCRYPT_TYPE_CCMP_256: 1739 return IEEE80211_CCMP_256_HDR_LEN; 1740 case HAL_ENCRYPT_TYPE_GCMP_128: 1741 case HAL_ENCRYPT_TYPE_AES_GCMP_256: 1742 return IEEE80211_GCMP_HDR_LEN; 1743 case HAL_ENCRYPT_TYPE_WEP_40: 1744 case HAL_ENCRYPT_TYPE_WEP_104: 1745 case HAL_ENCRYPT_TYPE_WEP_128: 1746 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4: 1747 case HAL_ENCRYPT_TYPE_WAPI: 1748 break; 1749 } 1750 1751 ath11k_warn(ar->ab, "unsupported encryption type %d\n", enctype); 1752 return 0; 1753 } 1754 1755 static int ath11k_dp_rx_crypto_icv_len(struct ath11k *ar, 1756 enum hal_encrypt_type enctype) 1757 { 1758 switch (enctype) { 1759 case HAL_ENCRYPT_TYPE_OPEN: 1760 case HAL_ENCRYPT_TYPE_CCMP_128: 1761 case HAL_ENCRYPT_TYPE_CCMP_256: 1762 case HAL_ENCRYPT_TYPE_GCMP_128: 1763 case HAL_ENCRYPT_TYPE_AES_GCMP_256: 1764 return 0; 1765 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC: 1766 case HAL_ENCRYPT_TYPE_TKIP_MIC: 1767 return IEEE80211_TKIP_ICV_LEN; 1768 case HAL_ENCRYPT_TYPE_WEP_40: 1769 case HAL_ENCRYPT_TYPE_WEP_104: 1770 case HAL_ENCRYPT_TYPE_WEP_128: 1771 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4: 1772 case HAL_ENCRYPT_TYPE_WAPI: 1773 break; 1774 } 1775 1776 ath11k_warn(ar->ab, "unsupported encryption type %d\n", enctype); 1777 return 0; 1778 } 1779 1780 static void ath11k_dp_rx_h_undecap_nwifi(struct ath11k *ar, 1781 struct sk_buff *msdu, 1782 u8 *first_hdr, 1783 enum hal_encrypt_type enctype, 1784 struct ieee80211_rx_status *status) 1785 { 1786 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 1787 u8 decap_hdr[DP_MAX_NWIFI_HDR_LEN]; 1788 struct ieee80211_hdr *hdr; 1789 size_t hdr_len; 1790 u8 da[ETH_ALEN]; 1791 u8 sa[ETH_ALEN]; 1792 u16 qos_ctl = 0; 1793 u8 *qos; 1794 1795 /* copy SA & DA and pull decapped header */ 1796 hdr = (struct ieee80211_hdr *)msdu->data; 1797 hdr_len = ieee80211_hdrlen(hdr->frame_control); 1798 ether_addr_copy(da, ieee80211_get_DA(hdr)); 1799 ether_addr_copy(sa, ieee80211_get_SA(hdr)); 1800 skb_pull(msdu, ieee80211_hdrlen(hdr->frame_control)); 1801 1802 if (rxcb->is_first_msdu) { 1803 /* original 802.11 header is valid for the first msdu 1804 * hence we can reuse the same header 1805 */ 1806 hdr = (struct ieee80211_hdr *)first_hdr; 1807 hdr_len = ieee80211_hdrlen(hdr->frame_control); 1808 1809 /* Each A-MSDU subframe will be reported as a separate MSDU, 1810 * so strip the A-MSDU bit from QoS Ctl. 1811 */ 1812 if (ieee80211_is_data_qos(hdr->frame_control)) { 1813 qos = ieee80211_get_qos_ctl(hdr); 1814 qos[0] &= ~IEEE80211_QOS_CTL_A_MSDU_PRESENT; 1815 } 1816 } else { 1817 /* Rebuild qos header if this is a middle/last msdu */ 1818 hdr->frame_control |= __cpu_to_le16(IEEE80211_STYPE_QOS_DATA); 1819 1820 /* Reset the order bit as the HT_Control header is stripped */ 1821 hdr->frame_control &= ~(__cpu_to_le16(IEEE80211_FCTL_ORDER)); 1822 1823 qos_ctl = rxcb->tid; 1824 1825 if (ath11k_dp_rx_h_msdu_start_mesh_ctl_present(rxcb->rx_desc)) 1826 qos_ctl |= IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT; 1827 1828 /* TODO Add other QoS ctl fields when required */ 1829 1830 /* copy decap header before overwriting for reuse below */ 1831 memcpy(decap_hdr, (uint8_t *)hdr, hdr_len); 1832 } 1833 1834 if (!(status->flag & RX_FLAG_IV_STRIPPED)) { 1835 memcpy(skb_push(msdu, 1836 ath11k_dp_rx_crypto_param_len(ar, enctype)), 1837 (void *)hdr + hdr_len, 1838 ath11k_dp_rx_crypto_param_len(ar, enctype)); 1839 } 1840 1841 if (!rxcb->is_first_msdu) { 1842 memcpy(skb_push(msdu, 1843 IEEE80211_QOS_CTL_LEN), &qos_ctl, 1844 IEEE80211_QOS_CTL_LEN); 1845 memcpy(skb_push(msdu, hdr_len), decap_hdr, hdr_len); 1846 return; 1847 } 1848 1849 memcpy(skb_push(msdu, hdr_len), hdr, hdr_len); 1850 1851 /* original 802.11 header has a different DA and in 1852 * case of 4addr it may also have different SA 1853 */ 1854 hdr = (struct ieee80211_hdr *)msdu->data; 1855 ether_addr_copy(ieee80211_get_DA(hdr), da); 1856 ether_addr_copy(ieee80211_get_SA(hdr), sa); 1857 } 1858 1859 static void ath11k_dp_rx_h_undecap_raw(struct ath11k *ar, struct sk_buff *msdu, 1860 enum hal_encrypt_type enctype, 1861 struct ieee80211_rx_status *status, 1862 bool decrypted) 1863 { 1864 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 1865 struct ieee80211_hdr *hdr; 1866 size_t hdr_len; 1867 size_t crypto_len; 1868 1869 if (!rxcb->is_first_msdu || 1870 !(rxcb->is_first_msdu && rxcb->is_last_msdu)) { 1871 WARN_ON_ONCE(1); 1872 return; 1873 } 1874 1875 skb_trim(msdu, msdu->len - FCS_LEN); 1876 1877 if (!decrypted) 1878 return; 1879 1880 hdr = (void *)msdu->data; 1881 1882 /* Tail */ 1883 if (status->flag & RX_FLAG_IV_STRIPPED) { 1884 skb_trim(msdu, msdu->len - 1885 ath11k_dp_rx_crypto_mic_len(ar, enctype)); 1886 1887 skb_trim(msdu, msdu->len - 1888 ath11k_dp_rx_crypto_icv_len(ar, enctype)); 1889 } else { 1890 /* MIC */ 1891 if (status->flag & RX_FLAG_MIC_STRIPPED) 1892 skb_trim(msdu, msdu->len - 1893 ath11k_dp_rx_crypto_mic_len(ar, enctype)); 1894 1895 /* ICV */ 1896 if (status->flag & RX_FLAG_ICV_STRIPPED) 1897 skb_trim(msdu, msdu->len - 1898 ath11k_dp_rx_crypto_icv_len(ar, enctype)); 1899 } 1900 1901 /* MMIC */ 1902 if ((status->flag & RX_FLAG_MMIC_STRIPPED) && 1903 !ieee80211_has_morefrags(hdr->frame_control) && 1904 enctype == HAL_ENCRYPT_TYPE_TKIP_MIC) 1905 skb_trim(msdu, msdu->len - IEEE80211_CCMP_MIC_LEN); 1906 1907 /* Head */ 1908 if (status->flag & RX_FLAG_IV_STRIPPED) { 1909 hdr_len = ieee80211_hdrlen(hdr->frame_control); 1910 crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype); 1911 1912 memmove((void *)msdu->data + crypto_len, 1913 (void *)msdu->data, hdr_len); 1914 skb_pull(msdu, crypto_len); 1915 } 1916 } 1917 1918 static void *ath11k_dp_rx_h_find_rfc1042(struct ath11k *ar, 1919 struct sk_buff *msdu, 1920 enum hal_encrypt_type enctype) 1921 { 1922 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 1923 struct ieee80211_hdr *hdr; 1924 size_t hdr_len, crypto_len; 1925 void *rfc1042; 1926 bool is_amsdu; 1927 1928 is_amsdu = !(rxcb->is_first_msdu && rxcb->is_last_msdu); 1929 hdr = (struct ieee80211_hdr *)ath11k_dp_rx_h_80211_hdr(rxcb->rx_desc); 1930 rfc1042 = hdr; 1931 1932 if (rxcb->is_first_msdu) { 1933 hdr_len = ieee80211_hdrlen(hdr->frame_control); 1934 crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype); 1935 1936 rfc1042 += hdr_len + crypto_len; 1937 } 1938 1939 if (is_amsdu) 1940 rfc1042 += sizeof(struct ath11k_dp_amsdu_subframe_hdr); 1941 1942 return rfc1042; 1943 } 1944 1945 static void ath11k_dp_rx_h_undecap_eth(struct ath11k *ar, 1946 struct sk_buff *msdu, 1947 u8 *first_hdr, 1948 enum hal_encrypt_type enctype, 1949 struct ieee80211_rx_status *status) 1950 { 1951 struct ieee80211_hdr *hdr; 1952 struct ethhdr *eth; 1953 size_t hdr_len; 1954 u8 da[ETH_ALEN]; 1955 u8 sa[ETH_ALEN]; 1956 void *rfc1042; 1957 1958 rfc1042 = ath11k_dp_rx_h_find_rfc1042(ar, msdu, enctype); 1959 if (WARN_ON_ONCE(!rfc1042)) 1960 return; 1961 1962 /* pull decapped header and copy SA & DA */ 1963 eth = (struct ethhdr *)msdu->data; 1964 ether_addr_copy(da, eth->h_dest); 1965 ether_addr_copy(sa, eth->h_source); 1966 skb_pull(msdu, sizeof(struct ethhdr)); 1967 1968 /* push rfc1042/llc/snap */ 1969 memcpy(skb_push(msdu, sizeof(struct ath11k_dp_rfc1042_hdr)), rfc1042, 1970 sizeof(struct ath11k_dp_rfc1042_hdr)); 1971 1972 /* push original 802.11 header */ 1973 hdr = (struct ieee80211_hdr *)first_hdr; 1974 hdr_len = ieee80211_hdrlen(hdr->frame_control); 1975 1976 if (!(status->flag & RX_FLAG_IV_STRIPPED)) { 1977 memcpy(skb_push(msdu, 1978 ath11k_dp_rx_crypto_param_len(ar, enctype)), 1979 (void *)hdr + hdr_len, 1980 ath11k_dp_rx_crypto_param_len(ar, enctype)); 1981 } 1982 1983 memcpy(skb_push(msdu, hdr_len), hdr, hdr_len); 1984 1985 /* original 802.11 header has a different DA and in 1986 * case of 4addr it may also have different SA 1987 */ 1988 hdr = (struct ieee80211_hdr *)msdu->data; 1989 ether_addr_copy(ieee80211_get_DA(hdr), da); 1990 ether_addr_copy(ieee80211_get_SA(hdr), sa); 1991 } 1992 1993 static void ath11k_dp_rx_h_undecap(struct ath11k *ar, struct sk_buff *msdu, 1994 struct hal_rx_desc *rx_desc, 1995 enum hal_encrypt_type enctype, 1996 struct ieee80211_rx_status *status, 1997 bool decrypted) 1998 { 1999 u8 *first_hdr; 2000 u8 decap; 2001 2002 first_hdr = ath11k_dp_rx_h_80211_hdr(rx_desc); 2003 decap = ath11k_dp_rx_h_msdu_start_decap_type(rx_desc); 2004 2005 switch (decap) { 2006 case DP_RX_DECAP_TYPE_NATIVE_WIFI: 2007 ath11k_dp_rx_h_undecap_nwifi(ar, msdu, first_hdr, 2008 enctype, status); 2009 break; 2010 case DP_RX_DECAP_TYPE_RAW: 2011 ath11k_dp_rx_h_undecap_raw(ar, msdu, enctype, status, 2012 decrypted); 2013 break; 2014 case DP_RX_DECAP_TYPE_ETHERNET2_DIX: 2015 /* TODO undecap support for middle/last msdu's of amsdu */ 2016 ath11k_dp_rx_h_undecap_eth(ar, msdu, first_hdr, 2017 enctype, status); 2018 break; 2019 case DP_RX_DECAP_TYPE_8023: 2020 /* TODO: Handle undecap for these formats */ 2021 break; 2022 } 2023 } 2024 2025 static void ath11k_dp_rx_h_mpdu(struct ath11k *ar, 2026 struct sk_buff *msdu, 2027 struct hal_rx_desc *rx_desc, 2028 struct ieee80211_rx_status *rx_status) 2029 { 2030 bool fill_crypto_hdr, mcast; 2031 enum hal_encrypt_type enctype; 2032 bool is_decrypted = false; 2033 struct ieee80211_hdr *hdr; 2034 struct ath11k_peer *peer; 2035 u32 err_bitmap; 2036 2037 hdr = (struct ieee80211_hdr *)msdu->data; 2038 2039 /* PN for multicast packets will be checked in mac80211 */ 2040 2041 mcast = is_multicast_ether_addr(hdr->addr1); 2042 fill_crypto_hdr = mcast; 2043 2044 is_decrypted = ath11k_dp_rx_h_attn_is_decrypted(rx_desc); 2045 2046 spin_lock_bh(&ar->ab->base_lock); 2047 peer = ath11k_peer_find_by_addr(ar->ab, hdr->addr2); 2048 if (peer) { 2049 if (mcast) 2050 enctype = peer->sec_type_grp; 2051 else 2052 enctype = peer->sec_type; 2053 } else { 2054 enctype = HAL_ENCRYPT_TYPE_OPEN; 2055 } 2056 spin_unlock_bh(&ar->ab->base_lock); 2057 2058 err_bitmap = ath11k_dp_rx_h_attn_mpdu_err(rx_desc); 2059 2060 /* Clear per-MPDU flags while leaving per-PPDU flags intact */ 2061 rx_status->flag &= ~(RX_FLAG_FAILED_FCS_CRC | 2062 RX_FLAG_MMIC_ERROR | 2063 RX_FLAG_DECRYPTED | 2064 RX_FLAG_IV_STRIPPED | 2065 RX_FLAG_MMIC_STRIPPED); 2066 2067 if (err_bitmap & DP_RX_MPDU_ERR_FCS) 2068 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 2069 if (err_bitmap & DP_RX_MPDU_ERR_TKIP_MIC) 2070 rx_status->flag |= RX_FLAG_MMIC_ERROR; 2071 2072 if (is_decrypted) { 2073 rx_status->flag |= RX_FLAG_DECRYPTED | RX_FLAG_MMIC_STRIPPED; 2074 2075 if (fill_crypto_hdr) 2076 rx_status->flag |= RX_FLAG_MIC_STRIPPED | 2077 RX_FLAG_ICV_STRIPPED; 2078 else 2079 rx_status->flag |= RX_FLAG_IV_STRIPPED | 2080 RX_FLAG_PN_VALIDATED; 2081 } 2082 2083 ath11k_dp_rx_h_csum_offload(msdu); 2084 ath11k_dp_rx_h_undecap(ar, msdu, rx_desc, 2085 enctype, rx_status, is_decrypted); 2086 2087 if (!is_decrypted || fill_crypto_hdr) 2088 return; 2089 2090 hdr = (void *)msdu->data; 2091 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_PROTECTED); 2092 } 2093 2094 static void ath11k_dp_rx_h_rate(struct ath11k *ar, struct hal_rx_desc *rx_desc, 2095 struct ieee80211_rx_status *rx_status) 2096 { 2097 struct ieee80211_supported_band *sband; 2098 enum rx_msdu_start_pkt_type pkt_type; 2099 u8 bw; 2100 u8 rate_mcs, nss; 2101 u8 sgi; 2102 bool is_cck; 2103 2104 pkt_type = ath11k_dp_rx_h_msdu_start_pkt_type(rx_desc); 2105 bw = ath11k_dp_rx_h_msdu_start_rx_bw(rx_desc); 2106 rate_mcs = ath11k_dp_rx_h_msdu_start_rate_mcs(rx_desc); 2107 nss = ath11k_dp_rx_h_msdu_start_nss(rx_desc); 2108 sgi = ath11k_dp_rx_h_msdu_start_sgi(rx_desc); 2109 2110 switch (pkt_type) { 2111 case RX_MSDU_START_PKT_TYPE_11A: 2112 case RX_MSDU_START_PKT_TYPE_11B: 2113 is_cck = (pkt_type == RX_MSDU_START_PKT_TYPE_11B); 2114 sband = &ar->mac.sbands[rx_status->band]; 2115 rx_status->rate_idx = ath11k_mac_hw_rate_to_idx(sband, rate_mcs, 2116 is_cck); 2117 break; 2118 case RX_MSDU_START_PKT_TYPE_11N: 2119 rx_status->encoding = RX_ENC_HT; 2120 if (rate_mcs > ATH11K_HT_MCS_MAX) { 2121 ath11k_warn(ar->ab, 2122 "Received with invalid mcs in HT mode %d\n", 2123 rate_mcs); 2124 break; 2125 } 2126 rx_status->rate_idx = rate_mcs + (8 * (nss - 1)); 2127 if (sgi) 2128 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 2129 rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw); 2130 break; 2131 case RX_MSDU_START_PKT_TYPE_11AC: 2132 rx_status->encoding = RX_ENC_VHT; 2133 rx_status->rate_idx = rate_mcs; 2134 if (rate_mcs > ATH11K_VHT_MCS_MAX) { 2135 ath11k_warn(ar->ab, 2136 "Received with invalid mcs in VHT mode %d\n", 2137 rate_mcs); 2138 break; 2139 } 2140 rx_status->nss = nss; 2141 if (sgi) 2142 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 2143 rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw); 2144 break; 2145 case RX_MSDU_START_PKT_TYPE_11AX: 2146 rx_status->rate_idx = rate_mcs; 2147 if (rate_mcs > ATH11K_HE_MCS_MAX) { 2148 ath11k_warn(ar->ab, 2149 "Received with invalid mcs in HE mode %d\n", 2150 rate_mcs); 2151 break; 2152 } 2153 rx_status->encoding = RX_ENC_HE; 2154 rx_status->nss = nss; 2155 rx_status->he_gi = ath11k_he_gi_to_nl80211_he_gi(sgi); 2156 rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw); 2157 break; 2158 } 2159 } 2160 2161 static void ath11k_dp_rx_h_ppdu(struct ath11k *ar, struct hal_rx_desc *rx_desc, 2162 struct ieee80211_rx_status *rx_status) 2163 { 2164 u8 channel_num; 2165 2166 rx_status->freq = 0; 2167 rx_status->rate_idx = 0; 2168 rx_status->nss = 0; 2169 rx_status->encoding = RX_ENC_LEGACY; 2170 rx_status->bw = RATE_INFO_BW_20; 2171 2172 rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL; 2173 2174 channel_num = ath11k_dp_rx_h_msdu_start_freq(rx_desc); 2175 2176 if (channel_num >= 1 && channel_num <= 14) { 2177 rx_status->band = NL80211_BAND_2GHZ; 2178 } else if (channel_num >= 36 && channel_num <= 173) { 2179 rx_status->band = NL80211_BAND_5GHZ; 2180 } else { 2181 spin_lock_bh(&ar->data_lock); 2182 rx_status->band = ar->rx_channel->band; 2183 channel_num = 2184 ieee80211_frequency_to_channel(ar->rx_channel->center_freq); 2185 spin_unlock_bh(&ar->data_lock); 2186 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "rx_desc: ", 2187 rx_desc, sizeof(struct hal_rx_desc)); 2188 } 2189 2190 rx_status->freq = ieee80211_channel_to_frequency(channel_num, 2191 rx_status->band); 2192 2193 ath11k_dp_rx_h_rate(ar, rx_desc, rx_status); 2194 } 2195 2196 static char *ath11k_print_get_tid(struct ieee80211_hdr *hdr, char *out, 2197 size_t size) 2198 { 2199 u8 *qc; 2200 int tid; 2201 2202 if (!ieee80211_is_data_qos(hdr->frame_control)) 2203 return ""; 2204 2205 qc = ieee80211_get_qos_ctl(hdr); 2206 tid = *qc & IEEE80211_QOS_CTL_TID_MASK; 2207 snprintf(out, size, "tid %d", tid); 2208 2209 return out; 2210 } 2211 2212 static void ath11k_dp_rx_deliver_msdu(struct ath11k *ar, struct napi_struct *napi, 2213 struct sk_buff *msdu) 2214 { 2215 static const struct ieee80211_radiotap_he known = { 2216 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN | 2217 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN), 2218 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN), 2219 }; 2220 struct ieee80211_rx_status *status; 2221 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data; 2222 struct ieee80211_radiotap_he *he = NULL; 2223 char tid[32]; 2224 2225 status = IEEE80211_SKB_RXCB(msdu); 2226 if (status->encoding == RX_ENC_HE) { 2227 he = skb_push(msdu, sizeof(known)); 2228 memcpy(he, &known, sizeof(known)); 2229 status->flag |= RX_FLAG_RADIOTAP_HE; 2230 } 2231 2232 ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 2233 "rx skb %pK len %u peer %pM %s %s sn %u %s%s%s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n", 2234 msdu, 2235 msdu->len, 2236 ieee80211_get_SA(hdr), 2237 ath11k_print_get_tid(hdr, tid, sizeof(tid)), 2238 is_multicast_ether_addr(ieee80211_get_DA(hdr)) ? 2239 "mcast" : "ucast", 2240 (__le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4, 2241 (status->encoding == RX_ENC_LEGACY) ? "legacy" : "", 2242 (status->encoding == RX_ENC_HT) ? "ht" : "", 2243 (status->encoding == RX_ENC_VHT) ? "vht" : "", 2244 (status->encoding == RX_ENC_HE) ? "he" : "", 2245 (status->bw == RATE_INFO_BW_40) ? "40" : "", 2246 (status->bw == RATE_INFO_BW_80) ? "80" : "", 2247 (status->bw == RATE_INFO_BW_160) ? "160" : "", 2248 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? "sgi " : "", 2249 status->rate_idx, 2250 status->nss, 2251 status->freq, 2252 status->band, status->flag, 2253 !!(status->flag & RX_FLAG_FAILED_FCS_CRC), 2254 !!(status->flag & RX_FLAG_MMIC_ERROR), 2255 !!(status->flag & RX_FLAG_AMSDU_MORE)); 2256 2257 /* TODO: trace rx packet */ 2258 2259 ieee80211_rx_napi(ar->hw, NULL, msdu, napi); 2260 } 2261 2262 static int ath11k_dp_rx_process_msdu(struct ath11k *ar, 2263 struct sk_buff *msdu, 2264 struct sk_buff_head *msdu_list) 2265 { 2266 struct hal_rx_desc *rx_desc, *lrx_desc; 2267 struct ieee80211_rx_status rx_status = {0}; 2268 struct ieee80211_rx_status *status; 2269 struct ath11k_skb_rxcb *rxcb; 2270 struct ieee80211_hdr *hdr; 2271 struct sk_buff *last_buf; 2272 u8 l3_pad_bytes; 2273 u8 *hdr_status; 2274 u16 msdu_len; 2275 int ret; 2276 2277 last_buf = ath11k_dp_rx_get_msdu_last_buf(msdu_list, msdu); 2278 if (!last_buf) { 2279 ath11k_warn(ar->ab, 2280 "No valid Rx buffer to access Atten/MSDU_END/MPDU_END tlvs\n"); 2281 ret = -EIO; 2282 goto free_out; 2283 } 2284 2285 rx_desc = (struct hal_rx_desc *)msdu->data; 2286 lrx_desc = (struct hal_rx_desc *)last_buf->data; 2287 if (!ath11k_dp_rx_h_attn_msdu_done(lrx_desc)) { 2288 ath11k_warn(ar->ab, "msdu_done bit in attention is not set\n"); 2289 ret = -EIO; 2290 goto free_out; 2291 } 2292 2293 rxcb = ATH11K_SKB_RXCB(msdu); 2294 rxcb->rx_desc = rx_desc; 2295 msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(rx_desc); 2296 l3_pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(lrx_desc); 2297 2298 if (rxcb->is_frag) { 2299 skb_pull(msdu, HAL_RX_DESC_SIZE); 2300 } else if (!rxcb->is_continuation) { 2301 if ((msdu_len + HAL_RX_DESC_SIZE) > DP_RX_BUFFER_SIZE) { 2302 hdr_status = ath11k_dp_rx_h_80211_hdr(rx_desc); 2303 ret = -EINVAL; 2304 ath11k_warn(ar->ab, "invalid msdu len %u\n", msdu_len); 2305 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", hdr_status, 2306 sizeof(struct ieee80211_hdr)); 2307 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", rx_desc, 2308 sizeof(struct hal_rx_desc)); 2309 goto free_out; 2310 } 2311 skb_put(msdu, HAL_RX_DESC_SIZE + l3_pad_bytes + msdu_len); 2312 skb_pull(msdu, HAL_RX_DESC_SIZE + l3_pad_bytes); 2313 } else { 2314 ret = ath11k_dp_rx_msdu_coalesce(ar, msdu_list, 2315 msdu, last_buf, 2316 l3_pad_bytes, msdu_len); 2317 if (ret) { 2318 ath11k_warn(ar->ab, 2319 "failed to coalesce msdu rx buffer%d\n", ret); 2320 goto free_out; 2321 } 2322 } 2323 2324 hdr = (struct ieee80211_hdr *)msdu->data; 2325 2326 /* Process only data frames */ 2327 if (!ieee80211_is_data(hdr->frame_control)) 2328 return -EINVAL; 2329 2330 ath11k_dp_rx_h_ppdu(ar, rx_desc, &rx_status); 2331 ath11k_dp_rx_h_mpdu(ar, msdu, rx_desc, &rx_status); 2332 2333 rx_status.flag |= RX_FLAG_SKIP_MONITOR | RX_FLAG_DUP_VALIDATED; 2334 2335 status = IEEE80211_SKB_RXCB(msdu); 2336 *status = rx_status; 2337 return 0; 2338 2339 free_out: 2340 return ret; 2341 } 2342 2343 static void ath11k_dp_rx_process_received_packets(struct ath11k_base *ab, 2344 struct napi_struct *napi, 2345 struct sk_buff_head *msdu_list, 2346 int *quota, int ring_id) 2347 { 2348 struct ath11k_skb_rxcb *rxcb; 2349 struct sk_buff *msdu; 2350 struct ath11k *ar; 2351 u8 mac_id; 2352 int ret; 2353 2354 if (skb_queue_empty(msdu_list)) 2355 return; 2356 2357 rcu_read_lock(); 2358 2359 while (*quota && (msdu = __skb_dequeue(msdu_list))) { 2360 rxcb = ATH11K_SKB_RXCB(msdu); 2361 mac_id = rxcb->mac_id; 2362 ar = ab->pdevs[mac_id].ar; 2363 if (!rcu_dereference(ab->pdevs_active[mac_id])) { 2364 dev_kfree_skb_any(msdu); 2365 continue; 2366 } 2367 2368 if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) { 2369 dev_kfree_skb_any(msdu); 2370 continue; 2371 } 2372 2373 ret = ath11k_dp_rx_process_msdu(ar, msdu, msdu_list); 2374 if (ret) { 2375 ath11k_dbg(ab, ATH11K_DBG_DATA, 2376 "Unable to process msdu %d", ret); 2377 dev_kfree_skb_any(msdu); 2378 continue; 2379 } 2380 2381 ath11k_dp_rx_deliver_msdu(ar, napi, msdu); 2382 (*quota)--; 2383 } 2384 2385 rcu_read_unlock(); 2386 } 2387 2388 int ath11k_dp_process_rx(struct ath11k_base *ab, int ring_id, 2389 struct napi_struct *napi, int budget) 2390 { 2391 struct ath11k_dp *dp = &ab->dp; 2392 struct dp_rxdma_ring *rx_ring; 2393 int num_buffs_reaped[MAX_RADIOS] = {0}; 2394 struct sk_buff_head msdu_list; 2395 struct ath11k_skb_rxcb *rxcb; 2396 int total_msdu_reaped = 0; 2397 struct hal_srng *srng; 2398 struct sk_buff *msdu; 2399 int quota = budget; 2400 bool done = false; 2401 int buf_id, mac_id; 2402 struct ath11k *ar; 2403 u32 *rx_desc; 2404 int i; 2405 2406 __skb_queue_head_init(&msdu_list); 2407 2408 srng = &ab->hal.srng_list[dp->reo_dst_ring[ring_id].ring_id]; 2409 2410 spin_lock_bh(&srng->lock); 2411 2412 ath11k_hal_srng_access_begin(ab, srng); 2413 2414 try_again: 2415 while ((rx_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) { 2416 struct hal_reo_dest_ring desc = *(struct hal_reo_dest_ring *)rx_desc; 2417 enum hal_reo_dest_ring_push_reason push_reason; 2418 u32 cookie; 2419 2420 cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, 2421 desc.buf_addr_info.info1); 2422 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, 2423 cookie); 2424 mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, cookie); 2425 2426 ar = ab->pdevs[mac_id].ar; 2427 rx_ring = &ar->dp.rx_refill_buf_ring; 2428 spin_lock_bh(&rx_ring->idr_lock); 2429 msdu = idr_find(&rx_ring->bufs_idr, buf_id); 2430 if (!msdu) { 2431 ath11k_warn(ab, "frame rx with invalid buf_id %d\n", 2432 buf_id); 2433 spin_unlock_bh(&rx_ring->idr_lock); 2434 continue; 2435 } 2436 2437 idr_remove(&rx_ring->bufs_idr, buf_id); 2438 spin_unlock_bh(&rx_ring->idr_lock); 2439 2440 rxcb = ATH11K_SKB_RXCB(msdu); 2441 dma_unmap_single(ab->dev, rxcb->paddr, 2442 msdu->len + skb_tailroom(msdu), 2443 DMA_FROM_DEVICE); 2444 2445 num_buffs_reaped[mac_id]++; 2446 total_msdu_reaped++; 2447 2448 push_reason = FIELD_GET(HAL_REO_DEST_RING_INFO0_PUSH_REASON, 2449 desc.info0); 2450 if (push_reason != 2451 HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION) { 2452 dev_kfree_skb_any(msdu); 2453 ab->soc_stats.hal_reo_error[dp->reo_dst_ring[ring_id].ring_id]++; 2454 continue; 2455 } 2456 2457 rxcb->is_first_msdu = !!(desc.rx_msdu_info.info0 & 2458 RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU); 2459 rxcb->is_last_msdu = !!(desc.rx_msdu_info.info0 & 2460 RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU); 2461 rxcb->is_continuation = !!(desc.rx_msdu_info.info0 & 2462 RX_MSDU_DESC_INFO0_MSDU_CONTINUATION); 2463 rxcb->mac_id = mac_id; 2464 rxcb->tid = FIELD_GET(HAL_REO_DEST_RING_INFO0_RX_QUEUE_NUM, 2465 desc.info0); 2466 2467 __skb_queue_tail(&msdu_list, msdu); 2468 2469 if (total_msdu_reaped >= quota && !rxcb->is_continuation) { 2470 done = true; 2471 break; 2472 } 2473 } 2474 2475 /* Hw might have updated the head pointer after we cached it. 2476 * In this case, even though there are entries in the ring we'll 2477 * get rx_desc NULL. Give the read another try with updated cached 2478 * head pointer so that we can reap complete MPDU in the current 2479 * rx processing. 2480 */ 2481 if (!done && ath11k_hal_srng_dst_num_free(ab, srng, true)) { 2482 ath11k_hal_srng_access_end(ab, srng); 2483 goto try_again; 2484 } 2485 2486 ath11k_hal_srng_access_end(ab, srng); 2487 2488 spin_unlock_bh(&srng->lock); 2489 2490 if (!total_msdu_reaped) 2491 goto exit; 2492 2493 for (i = 0; i < ab->num_radios; i++) { 2494 if (!num_buffs_reaped[i]) 2495 continue; 2496 2497 ar = ab->pdevs[i].ar; 2498 rx_ring = &ar->dp.rx_refill_buf_ring; 2499 2500 ath11k_dp_rxbufs_replenish(ab, i, rx_ring, num_buffs_reaped[i], 2501 HAL_RX_BUF_RBM_SW3_BM, GFP_ATOMIC); 2502 } 2503 2504 ath11k_dp_rx_process_received_packets(ab, napi, &msdu_list, 2505 "a, ring_id); 2506 2507 exit: 2508 return budget - quota; 2509 } 2510 2511 static void ath11k_dp_rx_update_peer_stats(struct ath11k_sta *arsta, 2512 struct hal_rx_mon_ppdu_info *ppdu_info) 2513 { 2514 struct ath11k_rx_peer_stats *rx_stats = arsta->rx_stats; 2515 u32 num_msdu; 2516 2517 if (!rx_stats) 2518 return; 2519 2520 num_msdu = ppdu_info->tcp_msdu_count + ppdu_info->tcp_ack_msdu_count + 2521 ppdu_info->udp_msdu_count + ppdu_info->other_msdu_count; 2522 2523 rx_stats->num_msdu += num_msdu; 2524 rx_stats->tcp_msdu_count += ppdu_info->tcp_msdu_count + 2525 ppdu_info->tcp_ack_msdu_count; 2526 rx_stats->udp_msdu_count += ppdu_info->udp_msdu_count; 2527 rx_stats->other_msdu_count += ppdu_info->other_msdu_count; 2528 2529 if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11A || 2530 ppdu_info->preamble_type == HAL_RX_PREAMBLE_11B) { 2531 ppdu_info->nss = 1; 2532 ppdu_info->mcs = HAL_RX_MAX_MCS; 2533 ppdu_info->tid = IEEE80211_NUM_TIDS; 2534 } 2535 2536 if (ppdu_info->nss > 0 && ppdu_info->nss <= HAL_RX_MAX_NSS) 2537 rx_stats->nss_count[ppdu_info->nss - 1] += num_msdu; 2538 2539 if (ppdu_info->mcs <= HAL_RX_MAX_MCS) 2540 rx_stats->mcs_count[ppdu_info->mcs] += num_msdu; 2541 2542 if (ppdu_info->gi < HAL_RX_GI_MAX) 2543 rx_stats->gi_count[ppdu_info->gi] += num_msdu; 2544 2545 if (ppdu_info->bw < HAL_RX_BW_MAX) 2546 rx_stats->bw_count[ppdu_info->bw] += num_msdu; 2547 2548 if (ppdu_info->ldpc < HAL_RX_SU_MU_CODING_MAX) 2549 rx_stats->coding_count[ppdu_info->ldpc] += num_msdu; 2550 2551 if (ppdu_info->tid <= IEEE80211_NUM_TIDS) 2552 rx_stats->tid_count[ppdu_info->tid] += num_msdu; 2553 2554 if (ppdu_info->preamble_type < HAL_RX_PREAMBLE_MAX) 2555 rx_stats->pream_cnt[ppdu_info->preamble_type] += num_msdu; 2556 2557 if (ppdu_info->reception_type < HAL_RX_RECEPTION_TYPE_MAX) 2558 rx_stats->reception_type[ppdu_info->reception_type] += num_msdu; 2559 2560 if (ppdu_info->is_stbc) 2561 rx_stats->stbc_count += num_msdu; 2562 2563 if (ppdu_info->beamformed) 2564 rx_stats->beamformed_count += num_msdu; 2565 2566 if (ppdu_info->num_mpdu_fcs_ok > 1) 2567 rx_stats->ampdu_msdu_count += num_msdu; 2568 else 2569 rx_stats->non_ampdu_msdu_count += num_msdu; 2570 2571 rx_stats->num_mpdu_fcs_ok += ppdu_info->num_mpdu_fcs_ok; 2572 rx_stats->num_mpdu_fcs_err += ppdu_info->num_mpdu_fcs_err; 2573 rx_stats->dcm_count += ppdu_info->dcm; 2574 rx_stats->ru_alloc_cnt[ppdu_info->ru_alloc] += num_msdu; 2575 2576 arsta->rssi_comb = ppdu_info->rssi_comb; 2577 rx_stats->rx_duration += ppdu_info->rx_duration; 2578 arsta->rx_duration = rx_stats->rx_duration; 2579 } 2580 2581 static struct sk_buff *ath11k_dp_rx_alloc_mon_status_buf(struct ath11k_base *ab, 2582 struct dp_rxdma_ring *rx_ring, 2583 int *buf_id, gfp_t gfp) 2584 { 2585 struct sk_buff *skb; 2586 dma_addr_t paddr; 2587 2588 skb = dev_alloc_skb(DP_RX_BUFFER_SIZE + 2589 DP_RX_BUFFER_ALIGN_SIZE); 2590 2591 if (!skb) 2592 goto fail_alloc_skb; 2593 2594 if (!IS_ALIGNED((unsigned long)skb->data, 2595 DP_RX_BUFFER_ALIGN_SIZE)) { 2596 skb_pull(skb, PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) - 2597 skb->data); 2598 } 2599 2600 paddr = dma_map_single(ab->dev, skb->data, 2601 skb->len + skb_tailroom(skb), 2602 DMA_BIDIRECTIONAL); 2603 if (unlikely(dma_mapping_error(ab->dev, paddr))) 2604 goto fail_free_skb; 2605 2606 spin_lock_bh(&rx_ring->idr_lock); 2607 *buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 0, 2608 rx_ring->bufs_max, gfp); 2609 spin_unlock_bh(&rx_ring->idr_lock); 2610 if (*buf_id < 0) 2611 goto fail_dma_unmap; 2612 2613 ATH11K_SKB_RXCB(skb)->paddr = paddr; 2614 return skb; 2615 2616 fail_dma_unmap: 2617 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb), 2618 DMA_BIDIRECTIONAL); 2619 fail_free_skb: 2620 dev_kfree_skb_any(skb); 2621 fail_alloc_skb: 2622 return NULL; 2623 } 2624 2625 int ath11k_dp_rx_mon_status_bufs_replenish(struct ath11k_base *ab, int mac_id, 2626 struct dp_rxdma_ring *rx_ring, 2627 int req_entries, 2628 enum hal_rx_buf_return_buf_manager mgr, 2629 gfp_t gfp) 2630 { 2631 struct hal_srng *srng; 2632 u32 *desc; 2633 struct sk_buff *skb; 2634 int num_free; 2635 int num_remain; 2636 int buf_id; 2637 u32 cookie; 2638 dma_addr_t paddr; 2639 2640 req_entries = min(req_entries, rx_ring->bufs_max); 2641 2642 srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id]; 2643 2644 spin_lock_bh(&srng->lock); 2645 2646 ath11k_hal_srng_access_begin(ab, srng); 2647 2648 num_free = ath11k_hal_srng_src_num_free(ab, srng, true); 2649 2650 req_entries = min(num_free, req_entries); 2651 num_remain = req_entries; 2652 2653 while (num_remain > 0) { 2654 skb = ath11k_dp_rx_alloc_mon_status_buf(ab, rx_ring, 2655 &buf_id, gfp); 2656 if (!skb) 2657 break; 2658 paddr = ATH11K_SKB_RXCB(skb)->paddr; 2659 2660 desc = ath11k_hal_srng_src_get_next_entry(ab, srng); 2661 if (!desc) 2662 goto fail_desc_get; 2663 2664 cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) | 2665 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id); 2666 2667 num_remain--; 2668 2669 ath11k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr); 2670 } 2671 2672 ath11k_hal_srng_access_end(ab, srng); 2673 2674 spin_unlock_bh(&srng->lock); 2675 2676 return req_entries - num_remain; 2677 2678 fail_desc_get: 2679 spin_lock_bh(&rx_ring->idr_lock); 2680 idr_remove(&rx_ring->bufs_idr, buf_id); 2681 spin_unlock_bh(&rx_ring->idr_lock); 2682 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb), 2683 DMA_BIDIRECTIONAL); 2684 dev_kfree_skb_any(skb); 2685 ath11k_hal_srng_access_end(ab, srng); 2686 spin_unlock_bh(&srng->lock); 2687 2688 return req_entries - num_remain; 2689 } 2690 2691 static int ath11k_dp_rx_reap_mon_status_ring(struct ath11k_base *ab, int mac_id, 2692 int *budget, struct sk_buff_head *skb_list) 2693 { 2694 struct ath11k *ar = ab->pdevs[mac_id].ar; 2695 struct ath11k_pdev_dp *dp = &ar->dp; 2696 struct dp_rxdma_ring *rx_ring = &dp->rx_mon_status_refill_ring; 2697 struct hal_srng *srng; 2698 void *rx_mon_status_desc; 2699 struct sk_buff *skb; 2700 struct ath11k_skb_rxcb *rxcb; 2701 struct hal_tlv_hdr *tlv; 2702 u32 cookie; 2703 int buf_id; 2704 dma_addr_t paddr; 2705 u8 rbm; 2706 int num_buffs_reaped = 0; 2707 2708 srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id]; 2709 2710 spin_lock_bh(&srng->lock); 2711 2712 ath11k_hal_srng_access_begin(ab, srng); 2713 while (*budget) { 2714 *budget -= 1; 2715 rx_mon_status_desc = 2716 ath11k_hal_srng_src_peek(ab, srng); 2717 if (!rx_mon_status_desc) 2718 break; 2719 2720 ath11k_hal_rx_buf_addr_info_get(rx_mon_status_desc, &paddr, 2721 &cookie, &rbm); 2722 if (paddr) { 2723 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, cookie); 2724 2725 spin_lock_bh(&rx_ring->idr_lock); 2726 skb = idr_find(&rx_ring->bufs_idr, buf_id); 2727 if (!skb) { 2728 ath11k_warn(ab, "rx monitor status with invalid buf_id %d\n", 2729 buf_id); 2730 spin_unlock_bh(&rx_ring->idr_lock); 2731 continue; 2732 } 2733 2734 idr_remove(&rx_ring->bufs_idr, buf_id); 2735 spin_unlock_bh(&rx_ring->idr_lock); 2736 2737 rxcb = ATH11K_SKB_RXCB(skb); 2738 2739 dma_sync_single_for_cpu(ab->dev, rxcb->paddr, 2740 skb->len + skb_tailroom(skb), 2741 DMA_FROM_DEVICE); 2742 2743 dma_unmap_single(ab->dev, rxcb->paddr, 2744 skb->len + skb_tailroom(skb), 2745 DMA_BIDIRECTIONAL); 2746 2747 tlv = (struct hal_tlv_hdr *)skb->data; 2748 if (FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl) != 2749 HAL_RX_STATUS_BUFFER_DONE) { 2750 ath11k_hal_srng_src_get_next_entry(ab, srng); 2751 continue; 2752 } 2753 2754 __skb_queue_tail(skb_list, skb); 2755 } 2756 2757 skb = ath11k_dp_rx_alloc_mon_status_buf(ab, rx_ring, 2758 &buf_id, GFP_ATOMIC); 2759 2760 if (!skb) { 2761 ath11k_hal_rx_buf_addr_info_set(rx_mon_status_desc, 0, 0, 2762 HAL_RX_BUF_RBM_SW3_BM); 2763 num_buffs_reaped++; 2764 break; 2765 } 2766 rxcb = ATH11K_SKB_RXCB(skb); 2767 2768 cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) | 2769 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id); 2770 2771 ath11k_hal_rx_buf_addr_info_set(rx_mon_status_desc, rxcb->paddr, 2772 cookie, HAL_RX_BUF_RBM_SW3_BM); 2773 ath11k_hal_srng_src_get_next_entry(ab, srng); 2774 num_buffs_reaped++; 2775 } 2776 ath11k_hal_srng_access_end(ab, srng); 2777 spin_unlock_bh(&srng->lock); 2778 2779 return num_buffs_reaped; 2780 } 2781 2782 int ath11k_dp_rx_process_mon_status(struct ath11k_base *ab, int mac_id, 2783 struct napi_struct *napi, int budget) 2784 { 2785 struct ath11k *ar = ab->pdevs[mac_id].ar; 2786 enum hal_rx_mon_status hal_status; 2787 struct sk_buff *skb; 2788 struct sk_buff_head skb_list; 2789 struct hal_rx_mon_ppdu_info ppdu_info; 2790 struct ath11k_peer *peer; 2791 struct ath11k_sta *arsta; 2792 int num_buffs_reaped = 0; 2793 2794 __skb_queue_head_init(&skb_list); 2795 2796 num_buffs_reaped = ath11k_dp_rx_reap_mon_status_ring(ab, mac_id, &budget, 2797 &skb_list); 2798 if (!num_buffs_reaped) 2799 goto exit; 2800 2801 while ((skb = __skb_dequeue(&skb_list))) { 2802 memset(&ppdu_info, 0, sizeof(ppdu_info)); 2803 ppdu_info.peer_id = HAL_INVALID_PEERID; 2804 2805 if (ath11k_debug_is_pktlog_rx_stats_enabled(ar)) 2806 trace_ath11k_htt_rxdesc(ar, skb->data, DP_RX_BUFFER_SIZE); 2807 2808 hal_status = ath11k_hal_rx_parse_mon_status(ab, &ppdu_info, skb); 2809 2810 if (ppdu_info.peer_id == HAL_INVALID_PEERID || 2811 hal_status != HAL_RX_MON_STATUS_PPDU_DONE) { 2812 dev_kfree_skb_any(skb); 2813 continue; 2814 } 2815 2816 rcu_read_lock(); 2817 spin_lock_bh(&ab->base_lock); 2818 peer = ath11k_peer_find_by_id(ab, ppdu_info.peer_id); 2819 2820 if (!peer || !peer->sta) { 2821 ath11k_dbg(ab, ATH11K_DBG_DATA, 2822 "failed to find the peer with peer_id %d\n", 2823 ppdu_info.peer_id); 2824 spin_unlock_bh(&ab->base_lock); 2825 rcu_read_unlock(); 2826 dev_kfree_skb_any(skb); 2827 continue; 2828 } 2829 2830 arsta = (struct ath11k_sta *)peer->sta->drv_priv; 2831 ath11k_dp_rx_update_peer_stats(arsta, &ppdu_info); 2832 2833 if (ath11k_debug_is_pktlog_peer_valid(ar, peer->addr)) 2834 trace_ath11k_htt_rxdesc(ar, skb->data, DP_RX_BUFFER_SIZE); 2835 2836 spin_unlock_bh(&ab->base_lock); 2837 rcu_read_unlock(); 2838 2839 dev_kfree_skb_any(skb); 2840 } 2841 exit: 2842 return num_buffs_reaped; 2843 } 2844 2845 static void ath11k_dp_rx_frag_timer(struct timer_list *timer) 2846 { 2847 struct dp_rx_tid *rx_tid = from_timer(rx_tid, timer, frag_timer); 2848 2849 spin_lock_bh(&rx_tid->ab->base_lock); 2850 if (rx_tid->last_frag_no && 2851 rx_tid->rx_frag_bitmap == GENMASK(rx_tid->last_frag_no, 0)) { 2852 spin_unlock_bh(&rx_tid->ab->base_lock); 2853 return; 2854 } 2855 ath11k_dp_rx_frags_cleanup(rx_tid, true); 2856 spin_unlock_bh(&rx_tid->ab->base_lock); 2857 } 2858 2859 int ath11k_peer_rx_frag_setup(struct ath11k *ar, const u8 *peer_mac, int vdev_id) 2860 { 2861 struct ath11k_base *ab = ar->ab; 2862 struct crypto_shash *tfm; 2863 struct ath11k_peer *peer; 2864 struct dp_rx_tid *rx_tid; 2865 int i; 2866 2867 tfm = crypto_alloc_shash("michael_mic", 0, 0); 2868 if (IS_ERR(tfm)) 2869 return PTR_ERR(tfm); 2870 2871 spin_lock_bh(&ab->base_lock); 2872 2873 peer = ath11k_peer_find(ab, vdev_id, peer_mac); 2874 if (!peer) { 2875 ath11k_warn(ab, "failed to find the peer to set up fragment info\n"); 2876 spin_unlock_bh(&ab->base_lock); 2877 return -ENOENT; 2878 } 2879 2880 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) { 2881 rx_tid = &peer->rx_tid[i]; 2882 rx_tid->ab = ab; 2883 timer_setup(&rx_tid->frag_timer, ath11k_dp_rx_frag_timer, 0); 2884 skb_queue_head_init(&rx_tid->rx_frags); 2885 } 2886 2887 peer->tfm_mmic = tfm; 2888 spin_unlock_bh(&ab->base_lock); 2889 2890 return 0; 2891 } 2892 2893 static int ath11k_dp_rx_h_michael_mic(struct crypto_shash *tfm, u8 *key, 2894 struct ieee80211_hdr *hdr, u8 *data, 2895 size_t data_len, u8 *mic) 2896 { 2897 SHASH_DESC_ON_STACK(desc, tfm); 2898 u8 mic_hdr[16] = {0}; 2899 u8 tid = 0; 2900 int ret; 2901 2902 if (!tfm) 2903 return -EINVAL; 2904 2905 desc->tfm = tfm; 2906 2907 ret = crypto_shash_setkey(tfm, key, 8); 2908 if (ret) 2909 goto out; 2910 2911 ret = crypto_shash_init(desc); 2912 if (ret) 2913 goto out; 2914 2915 /* TKIP MIC header */ 2916 memcpy(mic_hdr, ieee80211_get_DA(hdr), ETH_ALEN); 2917 memcpy(mic_hdr + ETH_ALEN, ieee80211_get_SA(hdr), ETH_ALEN); 2918 if (ieee80211_is_data_qos(hdr->frame_control)) 2919 tid = ieee80211_get_tid(hdr); 2920 mic_hdr[12] = tid; 2921 2922 ret = crypto_shash_update(desc, mic_hdr, 16); 2923 if (ret) 2924 goto out; 2925 ret = crypto_shash_update(desc, data, data_len); 2926 if (ret) 2927 goto out; 2928 ret = crypto_shash_final(desc, mic); 2929 out: 2930 shash_desc_zero(desc); 2931 return ret; 2932 } 2933 2934 static int ath11k_dp_rx_h_verify_tkip_mic(struct ath11k *ar, struct ath11k_peer *peer, 2935 struct sk_buff *msdu) 2936 { 2937 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)msdu->data; 2938 struct ieee80211_rx_status *rxs = IEEE80211_SKB_RXCB(msdu); 2939 struct ieee80211_key_conf *key_conf; 2940 struct ieee80211_hdr *hdr; 2941 u8 mic[IEEE80211_CCMP_MIC_LEN]; 2942 int head_len, tail_len, ret; 2943 size_t data_len; 2944 u32 hdr_len; 2945 u8 *key, *data; 2946 u8 key_idx; 2947 2948 if (ath11k_dp_rx_h_mpdu_start_enctype(rx_desc) != HAL_ENCRYPT_TYPE_TKIP_MIC) 2949 return 0; 2950 2951 hdr = (struct ieee80211_hdr *)(msdu->data + HAL_RX_DESC_SIZE); 2952 hdr_len = ieee80211_hdrlen(hdr->frame_control); 2953 head_len = hdr_len + HAL_RX_DESC_SIZE + IEEE80211_TKIP_IV_LEN; 2954 tail_len = IEEE80211_CCMP_MIC_LEN + IEEE80211_TKIP_ICV_LEN + FCS_LEN; 2955 2956 if (!is_multicast_ether_addr(hdr->addr1)) 2957 key_idx = peer->ucast_keyidx; 2958 else 2959 key_idx = peer->mcast_keyidx; 2960 2961 key_conf = peer->keys[key_idx]; 2962 2963 data = msdu->data + head_len; 2964 data_len = msdu->len - head_len - tail_len; 2965 key = &key_conf->key[NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY]; 2966 2967 ret = ath11k_dp_rx_h_michael_mic(peer->tfm_mmic, key, hdr, data, data_len, mic); 2968 if (ret || memcmp(mic, data + data_len, IEEE80211_CCMP_MIC_LEN)) 2969 goto mic_fail; 2970 2971 return 0; 2972 2973 mic_fail: 2974 (ATH11K_SKB_RXCB(msdu))->is_first_msdu = true; 2975 (ATH11K_SKB_RXCB(msdu))->is_last_msdu = true; 2976 2977 rxs->flag |= RX_FLAG_MMIC_ERROR | RX_FLAG_MMIC_STRIPPED | 2978 RX_FLAG_IV_STRIPPED | RX_FLAG_DECRYPTED; 2979 skb_pull(msdu, HAL_RX_DESC_SIZE); 2980 2981 ath11k_dp_rx_h_ppdu(ar, rx_desc, rxs); 2982 ath11k_dp_rx_h_undecap(ar, msdu, rx_desc, 2983 HAL_ENCRYPT_TYPE_TKIP_MIC, rxs, true); 2984 ieee80211_rx(ar->hw, msdu); 2985 return -EINVAL; 2986 } 2987 2988 static void ath11k_dp_rx_h_undecap_frag(struct ath11k *ar, struct sk_buff *msdu, 2989 enum hal_encrypt_type enctype, u32 flags) 2990 { 2991 struct ieee80211_hdr *hdr; 2992 size_t hdr_len; 2993 size_t crypto_len; 2994 2995 if (!flags) 2996 return; 2997 2998 hdr = (struct ieee80211_hdr *)(msdu->data + HAL_RX_DESC_SIZE); 2999 3000 if (flags & RX_FLAG_MIC_STRIPPED) 3001 skb_trim(msdu, msdu->len - 3002 ath11k_dp_rx_crypto_mic_len(ar, enctype)); 3003 3004 if (flags & RX_FLAG_ICV_STRIPPED) 3005 skb_trim(msdu, msdu->len - 3006 ath11k_dp_rx_crypto_icv_len(ar, enctype)); 3007 3008 if (flags & RX_FLAG_IV_STRIPPED) { 3009 hdr_len = ieee80211_hdrlen(hdr->frame_control); 3010 crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype); 3011 3012 memmove((void *)msdu->data + HAL_RX_DESC_SIZE + crypto_len, 3013 (void *)msdu->data + HAL_RX_DESC_SIZE, hdr_len); 3014 skb_pull(msdu, crypto_len); 3015 } 3016 } 3017 3018 static int ath11k_dp_rx_h_defrag(struct ath11k *ar, 3019 struct ath11k_peer *peer, 3020 struct dp_rx_tid *rx_tid, 3021 struct sk_buff **defrag_skb) 3022 { 3023 struct hal_rx_desc *rx_desc; 3024 struct sk_buff *skb, *first_frag, *last_frag; 3025 struct ieee80211_hdr *hdr; 3026 enum hal_encrypt_type enctype; 3027 bool is_decrypted = false; 3028 int msdu_len = 0; 3029 int extra_space; 3030 u32 flags; 3031 3032 first_frag = skb_peek(&rx_tid->rx_frags); 3033 last_frag = skb_peek_tail(&rx_tid->rx_frags); 3034 3035 skb_queue_walk(&rx_tid->rx_frags, skb) { 3036 flags = 0; 3037 rx_desc = (struct hal_rx_desc *)skb->data; 3038 hdr = (struct ieee80211_hdr *)(skb->data + HAL_RX_DESC_SIZE); 3039 3040 enctype = ath11k_dp_rx_h_mpdu_start_enctype(rx_desc); 3041 if (enctype != HAL_ENCRYPT_TYPE_OPEN) 3042 is_decrypted = ath11k_dp_rx_h_attn_is_decrypted(rx_desc); 3043 3044 if (is_decrypted) { 3045 if (skb != first_frag) 3046 flags |= RX_FLAG_IV_STRIPPED; 3047 if (skb != last_frag) 3048 flags |= RX_FLAG_ICV_STRIPPED | 3049 RX_FLAG_MIC_STRIPPED; 3050 } 3051 3052 /* RX fragments are always raw packets */ 3053 if (skb != last_frag) 3054 skb_trim(skb, skb->len - FCS_LEN); 3055 ath11k_dp_rx_h_undecap_frag(ar, skb, enctype, flags); 3056 3057 if (skb != first_frag) 3058 skb_pull(skb, HAL_RX_DESC_SIZE + 3059 ieee80211_hdrlen(hdr->frame_control)); 3060 msdu_len += skb->len; 3061 } 3062 3063 extra_space = msdu_len - (DP_RX_BUFFER_SIZE + skb_tailroom(first_frag)); 3064 if (extra_space > 0 && 3065 (pskb_expand_head(first_frag, 0, extra_space, GFP_ATOMIC) < 0)) 3066 return -ENOMEM; 3067 3068 __skb_unlink(first_frag, &rx_tid->rx_frags); 3069 while ((skb = __skb_dequeue(&rx_tid->rx_frags))) { 3070 skb_put_data(first_frag, skb->data, skb->len); 3071 dev_kfree_skb_any(skb); 3072 } 3073 3074 hdr = (struct ieee80211_hdr *)(first_frag->data + HAL_RX_DESC_SIZE); 3075 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_MOREFRAGS); 3076 ATH11K_SKB_RXCB(first_frag)->is_frag = 1; 3077 3078 if (ath11k_dp_rx_h_verify_tkip_mic(ar, peer, first_frag)) 3079 first_frag = NULL; 3080 3081 *defrag_skb = first_frag; 3082 return 0; 3083 } 3084 3085 static int ath11k_dp_rx_h_defrag_reo_reinject(struct ath11k *ar, struct dp_rx_tid *rx_tid, 3086 struct sk_buff *defrag_skb) 3087 { 3088 struct ath11k_base *ab = ar->ab; 3089 struct ath11k_pdev_dp *dp = &ar->dp; 3090 struct dp_rxdma_ring *rx_refill_ring = &dp->rx_refill_buf_ring; 3091 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)defrag_skb->data; 3092 struct hal_reo_entrance_ring *reo_ent_ring; 3093 struct hal_reo_dest_ring *reo_dest_ring; 3094 struct dp_link_desc_bank *link_desc_banks; 3095 struct hal_rx_msdu_link *msdu_link; 3096 struct hal_rx_msdu_details *msdu0; 3097 struct hal_srng *srng; 3098 dma_addr_t paddr; 3099 u32 desc_bank, msdu_info, mpdu_info; 3100 u32 dst_idx, cookie; 3101 u32 *msdu_len_offset; 3102 int ret, buf_id; 3103 3104 link_desc_banks = ab->dp.link_desc_banks; 3105 reo_dest_ring = rx_tid->dst_ring_desc; 3106 3107 ath11k_hal_rx_reo_ent_paddr_get(ab, reo_dest_ring, &paddr, &desc_bank); 3108 msdu_link = (struct hal_rx_msdu_link *)(link_desc_banks[desc_bank].vaddr + 3109 (paddr - link_desc_banks[desc_bank].paddr)); 3110 msdu0 = &msdu_link->msdu_link[0]; 3111 dst_idx = FIELD_GET(RX_MSDU_DESC_INFO0_REO_DEST_IND, msdu0->rx_msdu_info.info0); 3112 memset(msdu0, 0, sizeof(*msdu0)); 3113 3114 msdu_info = FIELD_PREP(RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU, 1) | 3115 FIELD_PREP(RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU, 1) | 3116 FIELD_PREP(RX_MSDU_DESC_INFO0_MSDU_CONTINUATION, 0) | 3117 FIELD_PREP(RX_MSDU_DESC_INFO0_MSDU_LENGTH, 3118 defrag_skb->len - HAL_RX_DESC_SIZE) | 3119 FIELD_PREP(RX_MSDU_DESC_INFO0_REO_DEST_IND, dst_idx) | 3120 FIELD_PREP(RX_MSDU_DESC_INFO0_VALID_SA, 1) | 3121 FIELD_PREP(RX_MSDU_DESC_INFO0_VALID_DA, 1); 3122 msdu0->rx_msdu_info.info0 = msdu_info; 3123 3124 /* change msdu len in hal rx desc */ 3125 msdu_len_offset = (u32 *)&rx_desc->msdu_start; 3126 *msdu_len_offset &= ~(RX_MSDU_START_INFO1_MSDU_LENGTH); 3127 *msdu_len_offset |= defrag_skb->len - HAL_RX_DESC_SIZE; 3128 3129 paddr = dma_map_single(ab->dev, defrag_skb->data, 3130 defrag_skb->len + skb_tailroom(defrag_skb), 3131 DMA_FROM_DEVICE); 3132 if (dma_mapping_error(ab->dev, paddr)) 3133 return -ENOMEM; 3134 3135 spin_lock_bh(&rx_refill_ring->idr_lock); 3136 buf_id = idr_alloc(&rx_refill_ring->bufs_idr, defrag_skb, 0, 3137 rx_refill_ring->bufs_max * 3, GFP_ATOMIC); 3138 spin_unlock_bh(&rx_refill_ring->idr_lock); 3139 if (buf_id < 0) { 3140 ret = -ENOMEM; 3141 goto err_unmap_dma; 3142 } 3143 3144 ATH11K_SKB_RXCB(defrag_skb)->paddr = paddr; 3145 cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, dp->mac_id) | 3146 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id); 3147 3148 ath11k_hal_rx_buf_addr_info_set(msdu0, paddr, cookie, HAL_RX_BUF_RBM_SW3_BM); 3149 3150 /* Fill mpdu details into reo entrace ring */ 3151 srng = &ab->hal.srng_list[ab->dp.reo_reinject_ring.ring_id]; 3152 3153 spin_lock_bh(&srng->lock); 3154 ath11k_hal_srng_access_begin(ab, srng); 3155 3156 reo_ent_ring = (struct hal_reo_entrance_ring *) 3157 ath11k_hal_srng_src_get_next_entry(ab, srng); 3158 if (!reo_ent_ring) { 3159 ath11k_hal_srng_access_end(ab, srng); 3160 spin_unlock_bh(&srng->lock); 3161 ret = -ENOSPC; 3162 goto err_free_idr; 3163 } 3164 memset(reo_ent_ring, 0, sizeof(*reo_ent_ring)); 3165 3166 ath11k_hal_rx_reo_ent_paddr_get(ab, reo_dest_ring, &paddr, &desc_bank); 3167 ath11k_hal_rx_buf_addr_info_set(reo_ent_ring, paddr, desc_bank, 3168 HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST); 3169 3170 mpdu_info = FIELD_PREP(RX_MPDU_DESC_INFO0_MSDU_COUNT, 1) | 3171 FIELD_PREP(RX_MPDU_DESC_INFO0_SEQ_NUM, rx_tid->cur_sn) | 3172 FIELD_PREP(RX_MPDU_DESC_INFO0_FRAG_FLAG, 0) | 3173 FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_SA, 1) | 3174 FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_DA, 1) | 3175 FIELD_PREP(RX_MPDU_DESC_INFO0_RAW_MPDU, 1) | 3176 FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_PN, 1); 3177 3178 reo_ent_ring->rx_mpdu_info.info0 = mpdu_info; 3179 reo_ent_ring->rx_mpdu_info.meta_data = reo_dest_ring->rx_mpdu_info.meta_data; 3180 reo_ent_ring->queue_addr_lo = reo_dest_ring->queue_addr_lo; 3181 reo_ent_ring->info0 = FIELD_PREP(HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI, 3182 FIELD_GET(HAL_REO_DEST_RING_INFO0_QUEUE_ADDR_HI, 3183 reo_dest_ring->info0)) | 3184 FIELD_PREP(HAL_REO_ENTR_RING_INFO0_DEST_IND, dst_idx); 3185 ath11k_hal_srng_access_end(ab, srng); 3186 spin_unlock_bh(&srng->lock); 3187 3188 return 0; 3189 3190 err_free_idr: 3191 spin_lock_bh(&rx_refill_ring->idr_lock); 3192 idr_remove(&rx_refill_ring->bufs_idr, buf_id); 3193 spin_unlock_bh(&rx_refill_ring->idr_lock); 3194 err_unmap_dma: 3195 dma_unmap_single(ab->dev, paddr, defrag_skb->len + skb_tailroom(defrag_skb), 3196 DMA_FROM_DEVICE); 3197 return ret; 3198 } 3199 3200 static int ath11k_dp_rx_h_cmp_frags(struct sk_buff *a, struct sk_buff *b) 3201 { 3202 int frag1, frag2; 3203 3204 frag1 = ath11k_dp_rx_h_mpdu_start_frag_no(a); 3205 frag2 = ath11k_dp_rx_h_mpdu_start_frag_no(b); 3206 3207 return frag1 - frag2; 3208 } 3209 3210 static void ath11k_dp_rx_h_sort_frags(struct sk_buff_head *frag_list, 3211 struct sk_buff *cur_frag) 3212 { 3213 struct sk_buff *skb; 3214 int cmp; 3215 3216 skb_queue_walk(frag_list, skb) { 3217 cmp = ath11k_dp_rx_h_cmp_frags(skb, cur_frag); 3218 if (cmp < 0) 3219 continue; 3220 __skb_queue_before(frag_list, skb, cur_frag); 3221 return; 3222 } 3223 __skb_queue_tail(frag_list, cur_frag); 3224 } 3225 3226 static u64 ath11k_dp_rx_h_get_pn(struct sk_buff *skb) 3227 { 3228 struct ieee80211_hdr *hdr; 3229 u64 pn = 0; 3230 u8 *ehdr; 3231 3232 hdr = (struct ieee80211_hdr *)(skb->data + HAL_RX_DESC_SIZE); 3233 ehdr = skb->data + HAL_RX_DESC_SIZE + ieee80211_hdrlen(hdr->frame_control); 3234 3235 pn = ehdr[0]; 3236 pn |= (u64)ehdr[1] << 8; 3237 pn |= (u64)ehdr[4] << 16; 3238 pn |= (u64)ehdr[5] << 24; 3239 pn |= (u64)ehdr[6] << 32; 3240 pn |= (u64)ehdr[7] << 40; 3241 3242 return pn; 3243 } 3244 3245 static bool 3246 ath11k_dp_rx_h_defrag_validate_incr_pn(struct ath11k *ar, struct dp_rx_tid *rx_tid) 3247 { 3248 enum hal_encrypt_type encrypt_type; 3249 struct sk_buff *first_frag, *skb; 3250 struct hal_rx_desc *desc; 3251 u64 last_pn; 3252 u64 cur_pn; 3253 3254 first_frag = skb_peek(&rx_tid->rx_frags); 3255 desc = (struct hal_rx_desc *)first_frag->data; 3256 3257 encrypt_type = ath11k_dp_rx_h_mpdu_start_enctype(desc); 3258 if (encrypt_type != HAL_ENCRYPT_TYPE_CCMP_128 && 3259 encrypt_type != HAL_ENCRYPT_TYPE_CCMP_256 && 3260 encrypt_type != HAL_ENCRYPT_TYPE_GCMP_128 && 3261 encrypt_type != HAL_ENCRYPT_TYPE_AES_GCMP_256) 3262 return true; 3263 3264 last_pn = ath11k_dp_rx_h_get_pn(first_frag); 3265 skb_queue_walk(&rx_tid->rx_frags, skb) { 3266 if (skb == first_frag) 3267 continue; 3268 3269 cur_pn = ath11k_dp_rx_h_get_pn(skb); 3270 if (cur_pn != last_pn + 1) 3271 return false; 3272 last_pn = cur_pn; 3273 } 3274 return true; 3275 } 3276 3277 static int ath11k_dp_rx_frag_h_mpdu(struct ath11k *ar, 3278 struct sk_buff *msdu, 3279 u32 *ring_desc) 3280 { 3281 struct ath11k_base *ab = ar->ab; 3282 struct hal_rx_desc *rx_desc; 3283 struct ath11k_peer *peer; 3284 struct dp_rx_tid *rx_tid; 3285 struct sk_buff *defrag_skb = NULL; 3286 u32 peer_id; 3287 u16 seqno, frag_no; 3288 u8 tid; 3289 int ret = 0; 3290 bool more_frags; 3291 3292 rx_desc = (struct hal_rx_desc *)msdu->data; 3293 peer_id = ath11k_dp_rx_h_mpdu_start_peer_id(rx_desc); 3294 tid = ath11k_dp_rx_h_mpdu_start_tid(rx_desc); 3295 seqno = ath11k_dp_rx_h_mpdu_start_seq_no(rx_desc); 3296 frag_no = ath11k_dp_rx_h_mpdu_start_frag_no(msdu); 3297 more_frags = ath11k_dp_rx_h_mpdu_start_more_frags(msdu); 3298 3299 if (!ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(rx_desc) || 3300 !ath11k_dp_rx_h_mpdu_start_fc_valid(rx_desc) || 3301 tid > IEEE80211_NUM_TIDS) 3302 return -EINVAL; 3303 3304 /* received unfragmented packet in reo 3305 * exception ring, this shouldn't happen 3306 * as these packets typically come from 3307 * reo2sw srngs. 3308 */ 3309 if (WARN_ON_ONCE(!frag_no && !more_frags)) 3310 return -EINVAL; 3311 3312 spin_lock_bh(&ab->base_lock); 3313 peer = ath11k_peer_find_by_id(ab, peer_id); 3314 if (!peer) { 3315 ath11k_warn(ab, "failed to find the peer to de-fragment received fragment peer_id %d\n", 3316 peer_id); 3317 ret = -ENOENT; 3318 goto out_unlock; 3319 } 3320 rx_tid = &peer->rx_tid[tid]; 3321 3322 if ((!skb_queue_empty(&rx_tid->rx_frags) && seqno != rx_tid->cur_sn) || 3323 skb_queue_empty(&rx_tid->rx_frags)) { 3324 /* Flush stored fragments and start a new sequence */ 3325 ath11k_dp_rx_frags_cleanup(rx_tid, true); 3326 rx_tid->cur_sn = seqno; 3327 } 3328 3329 if (rx_tid->rx_frag_bitmap & BIT(frag_no)) { 3330 /* Fragment already present */ 3331 ret = -EINVAL; 3332 goto out_unlock; 3333 } 3334 3335 if (frag_no > __fls(rx_tid->rx_frag_bitmap)) 3336 __skb_queue_tail(&rx_tid->rx_frags, msdu); 3337 else 3338 ath11k_dp_rx_h_sort_frags(&rx_tid->rx_frags, msdu); 3339 3340 rx_tid->rx_frag_bitmap |= BIT(frag_no); 3341 if (!more_frags) 3342 rx_tid->last_frag_no = frag_no; 3343 3344 if (frag_no == 0) { 3345 rx_tid->dst_ring_desc = kmemdup(ring_desc, 3346 sizeof(*rx_tid->dst_ring_desc), 3347 GFP_ATOMIC); 3348 if (!rx_tid->dst_ring_desc) { 3349 ret = -ENOMEM; 3350 goto out_unlock; 3351 } 3352 } else { 3353 ath11k_dp_rx_link_desc_return(ab, ring_desc, 3354 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 3355 } 3356 3357 if (!rx_tid->last_frag_no || 3358 rx_tid->rx_frag_bitmap != GENMASK(rx_tid->last_frag_no, 0)) { 3359 mod_timer(&rx_tid->frag_timer, jiffies + 3360 ATH11K_DP_RX_FRAGMENT_TIMEOUT_MS); 3361 goto out_unlock; 3362 } 3363 3364 spin_unlock_bh(&ab->base_lock); 3365 del_timer_sync(&rx_tid->frag_timer); 3366 spin_lock_bh(&ab->base_lock); 3367 3368 peer = ath11k_peer_find_by_id(ab, peer_id); 3369 if (!peer) 3370 goto err_frags_cleanup; 3371 3372 if (!ath11k_dp_rx_h_defrag_validate_incr_pn(ar, rx_tid)) 3373 goto err_frags_cleanup; 3374 3375 if (ath11k_dp_rx_h_defrag(ar, peer, rx_tid, &defrag_skb)) 3376 goto err_frags_cleanup; 3377 3378 if (!defrag_skb) 3379 goto err_frags_cleanup; 3380 3381 if (ath11k_dp_rx_h_defrag_reo_reinject(ar, rx_tid, defrag_skb)) 3382 goto err_frags_cleanup; 3383 3384 ath11k_dp_rx_frags_cleanup(rx_tid, false); 3385 goto out_unlock; 3386 3387 err_frags_cleanup: 3388 dev_kfree_skb_any(defrag_skb); 3389 ath11k_dp_rx_frags_cleanup(rx_tid, true); 3390 out_unlock: 3391 spin_unlock_bh(&ab->base_lock); 3392 return ret; 3393 } 3394 3395 static int 3396 ath11k_dp_process_rx_err_buf(struct ath11k *ar, u32 *ring_desc, int buf_id, bool drop) 3397 { 3398 struct ath11k_pdev_dp *dp = &ar->dp; 3399 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring; 3400 struct sk_buff *msdu; 3401 struct ath11k_skb_rxcb *rxcb; 3402 struct hal_rx_desc *rx_desc; 3403 u8 *hdr_status; 3404 u16 msdu_len; 3405 3406 spin_lock_bh(&rx_ring->idr_lock); 3407 msdu = idr_find(&rx_ring->bufs_idr, buf_id); 3408 if (!msdu) { 3409 ath11k_warn(ar->ab, "rx err buf with invalid buf_id %d\n", 3410 buf_id); 3411 spin_unlock_bh(&rx_ring->idr_lock); 3412 return -EINVAL; 3413 } 3414 3415 idr_remove(&rx_ring->bufs_idr, buf_id); 3416 spin_unlock_bh(&rx_ring->idr_lock); 3417 3418 rxcb = ATH11K_SKB_RXCB(msdu); 3419 dma_unmap_single(ar->ab->dev, rxcb->paddr, 3420 msdu->len + skb_tailroom(msdu), 3421 DMA_FROM_DEVICE); 3422 3423 if (drop) { 3424 dev_kfree_skb_any(msdu); 3425 return 0; 3426 } 3427 3428 rcu_read_lock(); 3429 if (!rcu_dereference(ar->ab->pdevs_active[ar->pdev_idx])) { 3430 dev_kfree_skb_any(msdu); 3431 goto exit; 3432 } 3433 3434 if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) { 3435 dev_kfree_skb_any(msdu); 3436 goto exit; 3437 } 3438 3439 rx_desc = (struct hal_rx_desc *)msdu->data; 3440 msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(rx_desc); 3441 if ((msdu_len + HAL_RX_DESC_SIZE) > DP_RX_BUFFER_SIZE) { 3442 hdr_status = ath11k_dp_rx_h_80211_hdr(rx_desc); 3443 ath11k_warn(ar->ab, "invalid msdu leng %u", msdu_len); 3444 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", hdr_status, 3445 sizeof(struct ieee80211_hdr)); 3446 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", rx_desc, 3447 sizeof(struct hal_rx_desc)); 3448 dev_kfree_skb_any(msdu); 3449 goto exit; 3450 } 3451 3452 skb_put(msdu, HAL_RX_DESC_SIZE + msdu_len); 3453 3454 if (ath11k_dp_rx_frag_h_mpdu(ar, msdu, ring_desc)) { 3455 dev_kfree_skb_any(msdu); 3456 ath11k_dp_rx_link_desc_return(ar->ab, ring_desc, 3457 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 3458 } 3459 exit: 3460 rcu_read_unlock(); 3461 return 0; 3462 } 3463 3464 int ath11k_dp_process_rx_err(struct ath11k_base *ab, struct napi_struct *napi, 3465 int budget) 3466 { 3467 u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC]; 3468 struct dp_link_desc_bank *link_desc_banks; 3469 enum hal_rx_buf_return_buf_manager rbm; 3470 int tot_n_bufs_reaped, quota, ret, i; 3471 int n_bufs_reaped[MAX_RADIOS] = {0}; 3472 struct dp_rxdma_ring *rx_ring; 3473 struct dp_srng *reo_except; 3474 u32 desc_bank, num_msdus; 3475 struct hal_srng *srng; 3476 struct ath11k_dp *dp; 3477 void *link_desc_va; 3478 int buf_id, mac_id; 3479 struct ath11k *ar; 3480 dma_addr_t paddr; 3481 u32 *desc; 3482 bool is_frag; 3483 u8 drop = 0; 3484 3485 tot_n_bufs_reaped = 0; 3486 quota = budget; 3487 3488 dp = &ab->dp; 3489 reo_except = &dp->reo_except_ring; 3490 link_desc_banks = dp->link_desc_banks; 3491 3492 srng = &ab->hal.srng_list[reo_except->ring_id]; 3493 3494 spin_lock_bh(&srng->lock); 3495 3496 ath11k_hal_srng_access_begin(ab, srng); 3497 3498 while (budget && 3499 (desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) { 3500 struct hal_reo_dest_ring *reo_desc = (struct hal_reo_dest_ring *)desc; 3501 3502 ab->soc_stats.err_ring_pkts++; 3503 ret = ath11k_hal_desc_reo_parse_err(ab, desc, &paddr, 3504 &desc_bank); 3505 if (ret) { 3506 ath11k_warn(ab, "failed to parse error reo desc %d\n", 3507 ret); 3508 continue; 3509 } 3510 link_desc_va = link_desc_banks[desc_bank].vaddr + 3511 (paddr - link_desc_banks[desc_bank].paddr); 3512 ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus, msdu_cookies, 3513 &rbm); 3514 if (rbm != HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST && 3515 rbm != HAL_RX_BUF_RBM_SW3_BM) { 3516 ab->soc_stats.invalid_rbm++; 3517 ath11k_warn(ab, "invalid return buffer manager %d\n", rbm); 3518 ath11k_dp_rx_link_desc_return(ab, desc, 3519 HAL_WBM_REL_BM_ACT_REL_MSDU); 3520 continue; 3521 } 3522 3523 is_frag = !!(reo_desc->rx_mpdu_info.info0 & RX_MPDU_DESC_INFO0_FRAG_FLAG); 3524 3525 /* Process only rx fragments with one msdu per link desc below, and drop 3526 * msdu's indicated due to error reasons. 3527 */ 3528 if (!is_frag || num_msdus > 1) { 3529 drop = 1; 3530 /* Return the link desc back to wbm idle list */ 3531 ath11k_dp_rx_link_desc_return(ab, desc, 3532 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 3533 } 3534 3535 for (i = 0; i < num_msdus; i++) { 3536 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, 3537 msdu_cookies[i]); 3538 3539 mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, 3540 msdu_cookies[i]); 3541 3542 ar = ab->pdevs[mac_id].ar; 3543 3544 if (!ath11k_dp_process_rx_err_buf(ar, desc, buf_id, drop)) { 3545 n_bufs_reaped[mac_id]++; 3546 tot_n_bufs_reaped++; 3547 } 3548 } 3549 3550 if (tot_n_bufs_reaped >= quota) { 3551 tot_n_bufs_reaped = quota; 3552 goto exit; 3553 } 3554 3555 budget = quota - tot_n_bufs_reaped; 3556 } 3557 3558 exit: 3559 ath11k_hal_srng_access_end(ab, srng); 3560 3561 spin_unlock_bh(&srng->lock); 3562 3563 for (i = 0; i < ab->num_radios; i++) { 3564 if (!n_bufs_reaped[i]) 3565 continue; 3566 3567 ar = ab->pdevs[i].ar; 3568 rx_ring = &ar->dp.rx_refill_buf_ring; 3569 3570 ath11k_dp_rxbufs_replenish(ab, i, rx_ring, n_bufs_reaped[i], 3571 HAL_RX_BUF_RBM_SW3_BM, GFP_ATOMIC); 3572 } 3573 3574 return tot_n_bufs_reaped; 3575 } 3576 3577 static void ath11k_dp_rx_null_q_desc_sg_drop(struct ath11k *ar, 3578 int msdu_len, 3579 struct sk_buff_head *msdu_list) 3580 { 3581 struct sk_buff *skb, *tmp; 3582 struct ath11k_skb_rxcb *rxcb; 3583 int n_buffs; 3584 3585 n_buffs = DIV_ROUND_UP(msdu_len, 3586 (DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE)); 3587 3588 skb_queue_walk_safe(msdu_list, skb, tmp) { 3589 rxcb = ATH11K_SKB_RXCB(skb); 3590 if (rxcb->err_rel_src == HAL_WBM_REL_SRC_MODULE_REO && 3591 rxcb->err_code == HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO) { 3592 if (!n_buffs) 3593 break; 3594 __skb_unlink(skb, msdu_list); 3595 dev_kfree_skb_any(skb); 3596 n_buffs--; 3597 } 3598 } 3599 } 3600 3601 static int ath11k_dp_rx_h_null_q_desc(struct ath11k *ar, struct sk_buff *msdu, 3602 struct ieee80211_rx_status *status, 3603 struct sk_buff_head *msdu_list) 3604 { 3605 u16 msdu_len; 3606 struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data; 3607 u8 l3pad_bytes; 3608 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 3609 3610 msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(desc); 3611 3612 if (!rxcb->is_frag && ((msdu_len + HAL_RX_DESC_SIZE) > DP_RX_BUFFER_SIZE)) { 3613 /* First buffer will be freed by the caller, so deduct it's length */ 3614 msdu_len = msdu_len - (DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE); 3615 ath11k_dp_rx_null_q_desc_sg_drop(ar, msdu_len, msdu_list); 3616 return -EINVAL; 3617 } 3618 3619 if (!ath11k_dp_rx_h_attn_msdu_done(desc)) { 3620 ath11k_warn(ar->ab, 3621 "msdu_done bit not set in null_q_des processing\n"); 3622 __skb_queue_purge(msdu_list); 3623 return -EIO; 3624 } 3625 3626 /* Handle NULL queue descriptor violations arising out a missing 3627 * REO queue for a given peer or a given TID. This typically 3628 * may happen if a packet is received on a QOS enabled TID before the 3629 * ADDBA negotiation for that TID, when the TID queue is setup. Or 3630 * it may also happen for MC/BC frames if they are not routed to the 3631 * non-QOS TID queue, in the absence of any other default TID queue. 3632 * This error can show up both in a REO destination or WBM release ring. 3633 */ 3634 3635 rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(desc); 3636 rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(desc); 3637 3638 if (rxcb->is_frag) { 3639 skb_pull(msdu, HAL_RX_DESC_SIZE); 3640 } else { 3641 l3pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(desc); 3642 3643 if ((HAL_RX_DESC_SIZE + l3pad_bytes + msdu_len) > DP_RX_BUFFER_SIZE) 3644 return -EINVAL; 3645 3646 skb_put(msdu, HAL_RX_DESC_SIZE + l3pad_bytes + msdu_len); 3647 skb_pull(msdu, HAL_RX_DESC_SIZE + l3pad_bytes); 3648 } 3649 ath11k_dp_rx_h_ppdu(ar, desc, status); 3650 3651 ath11k_dp_rx_h_mpdu(ar, msdu, desc, status); 3652 3653 rxcb->tid = ath11k_dp_rx_h_mpdu_start_tid(desc); 3654 3655 /* Please note that caller will having the access to msdu and completing 3656 * rx with mac80211. Need not worry about cleaning up amsdu_list. 3657 */ 3658 3659 return 0; 3660 } 3661 3662 static bool ath11k_dp_rx_h_reo_err(struct ath11k *ar, struct sk_buff *msdu, 3663 struct ieee80211_rx_status *status, 3664 struct sk_buff_head *msdu_list) 3665 { 3666 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 3667 bool drop = false; 3668 3669 ar->ab->soc_stats.reo_error[rxcb->err_code]++; 3670 3671 switch (rxcb->err_code) { 3672 case HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO: 3673 if (ath11k_dp_rx_h_null_q_desc(ar, msdu, status, msdu_list)) 3674 drop = true; 3675 break; 3676 case HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED: 3677 /* TODO: Do not drop PN failed packets in the driver; 3678 * instead, it is good to drop such packets in mac80211 3679 * after incrementing the replay counters. 3680 */ 3681 3682 /* fall through */ 3683 default: 3684 /* TODO: Review other errors and process them to mac80211 3685 * as appropriate. 3686 */ 3687 drop = true; 3688 break; 3689 } 3690 3691 return drop; 3692 } 3693 3694 static void ath11k_dp_rx_h_tkip_mic_err(struct ath11k *ar, struct sk_buff *msdu, 3695 struct ieee80211_rx_status *status) 3696 { 3697 u16 msdu_len; 3698 struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data; 3699 u8 l3pad_bytes; 3700 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 3701 3702 rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(desc); 3703 rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(desc); 3704 3705 l3pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(desc); 3706 msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(desc); 3707 skb_put(msdu, HAL_RX_DESC_SIZE + l3pad_bytes + msdu_len); 3708 skb_pull(msdu, HAL_RX_DESC_SIZE + l3pad_bytes); 3709 3710 ath11k_dp_rx_h_ppdu(ar, desc, status); 3711 3712 status->flag |= (RX_FLAG_MMIC_STRIPPED | RX_FLAG_MMIC_ERROR | 3713 RX_FLAG_DECRYPTED); 3714 3715 ath11k_dp_rx_h_undecap(ar, msdu, desc, 3716 HAL_ENCRYPT_TYPE_TKIP_MIC, status, false); 3717 } 3718 3719 static bool ath11k_dp_rx_h_rxdma_err(struct ath11k *ar, struct sk_buff *msdu, 3720 struct ieee80211_rx_status *status) 3721 { 3722 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 3723 bool drop = false; 3724 3725 ar->ab->soc_stats.rxdma_error[rxcb->err_code]++; 3726 3727 switch (rxcb->err_code) { 3728 case HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR: 3729 ath11k_dp_rx_h_tkip_mic_err(ar, msdu, status); 3730 break; 3731 default: 3732 /* TODO: Review other rxdma error code to check if anything is 3733 * worth reporting to mac80211 3734 */ 3735 drop = true; 3736 break; 3737 } 3738 3739 return drop; 3740 } 3741 3742 static void ath11k_dp_rx_wbm_err(struct ath11k *ar, 3743 struct napi_struct *napi, 3744 struct sk_buff *msdu, 3745 struct sk_buff_head *msdu_list) 3746 { 3747 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 3748 struct ieee80211_rx_status rxs = {0}; 3749 struct ieee80211_rx_status *status; 3750 bool drop = true; 3751 3752 switch (rxcb->err_rel_src) { 3753 case HAL_WBM_REL_SRC_MODULE_REO: 3754 drop = ath11k_dp_rx_h_reo_err(ar, msdu, &rxs, msdu_list); 3755 break; 3756 case HAL_WBM_REL_SRC_MODULE_RXDMA: 3757 drop = ath11k_dp_rx_h_rxdma_err(ar, msdu, &rxs); 3758 break; 3759 default: 3760 /* msdu will get freed */ 3761 break; 3762 } 3763 3764 if (drop) { 3765 dev_kfree_skb_any(msdu); 3766 return; 3767 } 3768 3769 status = IEEE80211_SKB_RXCB(msdu); 3770 *status = rxs; 3771 3772 ath11k_dp_rx_deliver_msdu(ar, napi, msdu); 3773 } 3774 3775 int ath11k_dp_rx_process_wbm_err(struct ath11k_base *ab, 3776 struct napi_struct *napi, int budget) 3777 { 3778 struct ath11k *ar; 3779 struct ath11k_dp *dp = &ab->dp; 3780 struct dp_rxdma_ring *rx_ring; 3781 struct hal_rx_wbm_rel_info err_info; 3782 struct hal_srng *srng; 3783 struct sk_buff *msdu; 3784 struct sk_buff_head msdu_list[MAX_RADIOS]; 3785 struct ath11k_skb_rxcb *rxcb; 3786 u32 *rx_desc; 3787 int buf_id, mac_id; 3788 int num_buffs_reaped[MAX_RADIOS] = {0}; 3789 int total_num_buffs_reaped = 0; 3790 int ret, i; 3791 3792 for (i = 0; i < MAX_RADIOS; i++) 3793 __skb_queue_head_init(&msdu_list[i]); 3794 3795 srng = &ab->hal.srng_list[dp->rx_rel_ring.ring_id]; 3796 3797 spin_lock_bh(&srng->lock); 3798 3799 ath11k_hal_srng_access_begin(ab, srng); 3800 3801 while (budget) { 3802 rx_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng); 3803 if (!rx_desc) 3804 break; 3805 3806 ret = ath11k_hal_wbm_desc_parse_err(ab, rx_desc, &err_info); 3807 if (ret) { 3808 ath11k_warn(ab, 3809 "failed to parse rx error in wbm_rel ring desc %d\n", 3810 ret); 3811 continue; 3812 } 3813 3814 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, err_info.cookie); 3815 mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, err_info.cookie); 3816 3817 ar = ab->pdevs[mac_id].ar; 3818 rx_ring = &ar->dp.rx_refill_buf_ring; 3819 3820 spin_lock_bh(&rx_ring->idr_lock); 3821 msdu = idr_find(&rx_ring->bufs_idr, buf_id); 3822 if (!msdu) { 3823 ath11k_warn(ab, "frame rx with invalid buf_id %d pdev %d\n", 3824 buf_id, mac_id); 3825 spin_unlock_bh(&rx_ring->idr_lock); 3826 continue; 3827 } 3828 3829 idr_remove(&rx_ring->bufs_idr, buf_id); 3830 spin_unlock_bh(&rx_ring->idr_lock); 3831 3832 rxcb = ATH11K_SKB_RXCB(msdu); 3833 dma_unmap_single(ab->dev, rxcb->paddr, 3834 msdu->len + skb_tailroom(msdu), 3835 DMA_FROM_DEVICE); 3836 3837 num_buffs_reaped[mac_id]++; 3838 total_num_buffs_reaped++; 3839 budget--; 3840 3841 if (err_info.push_reason != 3842 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) { 3843 dev_kfree_skb_any(msdu); 3844 continue; 3845 } 3846 3847 rxcb->err_rel_src = err_info.err_rel_src; 3848 rxcb->err_code = err_info.err_code; 3849 rxcb->rx_desc = (struct hal_rx_desc *)msdu->data; 3850 __skb_queue_tail(&msdu_list[mac_id], msdu); 3851 } 3852 3853 ath11k_hal_srng_access_end(ab, srng); 3854 3855 spin_unlock_bh(&srng->lock); 3856 3857 if (!total_num_buffs_reaped) 3858 goto done; 3859 3860 for (i = 0; i < ab->num_radios; i++) { 3861 if (!num_buffs_reaped[i]) 3862 continue; 3863 3864 ar = ab->pdevs[i].ar; 3865 rx_ring = &ar->dp.rx_refill_buf_ring; 3866 3867 ath11k_dp_rxbufs_replenish(ab, i, rx_ring, num_buffs_reaped[i], 3868 HAL_RX_BUF_RBM_SW3_BM, GFP_ATOMIC); 3869 } 3870 3871 rcu_read_lock(); 3872 for (i = 0; i < ab->num_radios; i++) { 3873 if (!rcu_dereference(ab->pdevs_active[i])) { 3874 __skb_queue_purge(&msdu_list[i]); 3875 continue; 3876 } 3877 3878 ar = ab->pdevs[i].ar; 3879 3880 if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) { 3881 __skb_queue_purge(&msdu_list[i]); 3882 continue; 3883 } 3884 3885 while ((msdu = __skb_dequeue(&msdu_list[i])) != NULL) 3886 ath11k_dp_rx_wbm_err(ar, napi, msdu, &msdu_list[i]); 3887 } 3888 rcu_read_unlock(); 3889 done: 3890 return total_num_buffs_reaped; 3891 } 3892 3893 int ath11k_dp_process_rxdma_err(struct ath11k_base *ab, int mac_id, int budget) 3894 { 3895 struct ath11k *ar = ab->pdevs[mac_id].ar; 3896 struct dp_srng *err_ring = &ar->dp.rxdma_err_dst_ring; 3897 struct dp_rxdma_ring *rx_ring = &ar->dp.rx_refill_buf_ring; 3898 struct dp_link_desc_bank *link_desc_banks = ab->dp.link_desc_banks; 3899 struct hal_srng *srng; 3900 u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC]; 3901 enum hal_rx_buf_return_buf_manager rbm; 3902 enum hal_reo_entr_rxdma_ecode rxdma_err_code; 3903 struct ath11k_skb_rxcb *rxcb; 3904 struct sk_buff *skb; 3905 struct hal_reo_entrance_ring *entr_ring; 3906 void *desc; 3907 int num_buf_freed = 0; 3908 int quota = budget; 3909 dma_addr_t paddr; 3910 u32 desc_bank; 3911 void *link_desc_va; 3912 int num_msdus; 3913 int i; 3914 int buf_id; 3915 3916 srng = &ab->hal.srng_list[err_ring->ring_id]; 3917 3918 spin_lock_bh(&srng->lock); 3919 3920 ath11k_hal_srng_access_begin(ab, srng); 3921 3922 while (quota-- && 3923 (desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) { 3924 ath11k_hal_rx_reo_ent_paddr_get(ab, desc, &paddr, &desc_bank); 3925 3926 entr_ring = (struct hal_reo_entrance_ring *)desc; 3927 rxdma_err_code = 3928 FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE, 3929 entr_ring->info1); 3930 ab->soc_stats.rxdma_error[rxdma_err_code]++; 3931 3932 link_desc_va = link_desc_banks[desc_bank].vaddr + 3933 (paddr - link_desc_banks[desc_bank].paddr); 3934 ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus, 3935 msdu_cookies, &rbm); 3936 3937 for (i = 0; i < num_msdus; i++) { 3938 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, 3939 msdu_cookies[i]); 3940 3941 spin_lock_bh(&rx_ring->idr_lock); 3942 skb = idr_find(&rx_ring->bufs_idr, buf_id); 3943 if (!skb) { 3944 ath11k_warn(ab, "rxdma error with invalid buf_id %d\n", 3945 buf_id); 3946 spin_unlock_bh(&rx_ring->idr_lock); 3947 continue; 3948 } 3949 3950 idr_remove(&rx_ring->bufs_idr, buf_id); 3951 spin_unlock_bh(&rx_ring->idr_lock); 3952 3953 rxcb = ATH11K_SKB_RXCB(skb); 3954 dma_unmap_single(ab->dev, rxcb->paddr, 3955 skb->len + skb_tailroom(skb), 3956 DMA_FROM_DEVICE); 3957 dev_kfree_skb_any(skb); 3958 3959 num_buf_freed++; 3960 } 3961 3962 ath11k_dp_rx_link_desc_return(ab, desc, 3963 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 3964 } 3965 3966 ath11k_hal_srng_access_end(ab, srng); 3967 3968 spin_unlock_bh(&srng->lock); 3969 3970 if (num_buf_freed) 3971 ath11k_dp_rxbufs_replenish(ab, mac_id, rx_ring, num_buf_freed, 3972 HAL_RX_BUF_RBM_SW3_BM, GFP_ATOMIC); 3973 3974 return budget - quota; 3975 } 3976 3977 void ath11k_dp_process_reo_status(struct ath11k_base *ab) 3978 { 3979 struct ath11k_dp *dp = &ab->dp; 3980 struct hal_srng *srng; 3981 struct dp_reo_cmd *cmd, *tmp; 3982 bool found = false; 3983 u32 *reo_desc; 3984 u16 tag; 3985 struct hal_reo_status reo_status; 3986 3987 srng = &ab->hal.srng_list[dp->reo_status_ring.ring_id]; 3988 3989 memset(&reo_status, 0, sizeof(reo_status)); 3990 3991 spin_lock_bh(&srng->lock); 3992 3993 ath11k_hal_srng_access_begin(ab, srng); 3994 3995 while ((reo_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) { 3996 tag = FIELD_GET(HAL_SRNG_TLV_HDR_TAG, *reo_desc); 3997 3998 switch (tag) { 3999 case HAL_REO_GET_QUEUE_STATS_STATUS: 4000 ath11k_hal_reo_status_queue_stats(ab, reo_desc, 4001 &reo_status); 4002 break; 4003 case HAL_REO_FLUSH_QUEUE_STATUS: 4004 ath11k_hal_reo_flush_queue_status(ab, reo_desc, 4005 &reo_status); 4006 break; 4007 case HAL_REO_FLUSH_CACHE_STATUS: 4008 ath11k_hal_reo_flush_cache_status(ab, reo_desc, 4009 &reo_status); 4010 break; 4011 case HAL_REO_UNBLOCK_CACHE_STATUS: 4012 ath11k_hal_reo_unblk_cache_status(ab, reo_desc, 4013 &reo_status); 4014 break; 4015 case HAL_REO_FLUSH_TIMEOUT_LIST_STATUS: 4016 ath11k_hal_reo_flush_timeout_list_status(ab, reo_desc, 4017 &reo_status); 4018 break; 4019 case HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS: 4020 ath11k_hal_reo_desc_thresh_reached_status(ab, reo_desc, 4021 &reo_status); 4022 break; 4023 case HAL_REO_UPDATE_RX_REO_QUEUE_STATUS: 4024 ath11k_hal_reo_update_rx_reo_queue_status(ab, reo_desc, 4025 &reo_status); 4026 break; 4027 default: 4028 ath11k_warn(ab, "Unknown reo status type %d\n", tag); 4029 continue; 4030 } 4031 4032 spin_lock_bh(&dp->reo_cmd_lock); 4033 list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) { 4034 if (reo_status.uniform_hdr.cmd_num == cmd->cmd_num) { 4035 found = true; 4036 list_del(&cmd->list); 4037 break; 4038 } 4039 } 4040 spin_unlock_bh(&dp->reo_cmd_lock); 4041 4042 if (found) { 4043 cmd->handler(dp, (void *)&cmd->data, 4044 reo_status.uniform_hdr.cmd_status); 4045 kfree(cmd); 4046 } 4047 4048 found = false; 4049 } 4050 4051 ath11k_hal_srng_access_end(ab, srng); 4052 4053 spin_unlock_bh(&srng->lock); 4054 } 4055 4056 void ath11k_dp_rx_pdev_free(struct ath11k_base *ab, int mac_id) 4057 { 4058 struct ath11k *ar = ab->pdevs[mac_id].ar; 4059 4060 ath11k_dp_rx_pdev_srng_free(ar); 4061 ath11k_dp_rxdma_pdev_buf_free(ar); 4062 } 4063 4064 int ath11k_dp_rx_pdev_alloc(struct ath11k_base *ab, int mac_id) 4065 { 4066 struct ath11k *ar = ab->pdevs[mac_id].ar; 4067 struct ath11k_pdev_dp *dp = &ar->dp; 4068 u32 ring_id; 4069 int ret; 4070 4071 ret = ath11k_dp_rx_pdev_srng_alloc(ar); 4072 if (ret) { 4073 ath11k_warn(ab, "failed to setup rx srngs\n"); 4074 return ret; 4075 } 4076 4077 ret = ath11k_dp_rxdma_pdev_buf_setup(ar); 4078 if (ret) { 4079 ath11k_warn(ab, "failed to setup rxdma ring\n"); 4080 return ret; 4081 } 4082 4083 ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id; 4084 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, mac_id, HAL_RXDMA_BUF); 4085 if (ret) { 4086 ath11k_warn(ab, "failed to configure rx_refill_buf_ring %d\n", 4087 ret); 4088 return ret; 4089 } 4090 4091 ring_id = dp->rxdma_err_dst_ring.ring_id; 4092 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, mac_id, HAL_RXDMA_DST); 4093 if (ret) { 4094 ath11k_warn(ab, "failed to configure rxdma_err_dest_ring %d\n", 4095 ret); 4096 return ret; 4097 } 4098 4099 ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id; 4100 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, 4101 mac_id, HAL_RXDMA_MONITOR_BUF); 4102 if (ret) { 4103 ath11k_warn(ab, "failed to configure rxdma_mon_buf_ring %d\n", 4104 ret); 4105 return ret; 4106 } 4107 ret = ath11k_dp_tx_htt_srng_setup(ab, 4108 dp->rxdma_mon_dst_ring.ring_id, 4109 mac_id, HAL_RXDMA_MONITOR_DST); 4110 if (ret) { 4111 ath11k_warn(ab, "failed to configure rxdma_mon_dst_ring %d\n", 4112 ret); 4113 return ret; 4114 } 4115 ret = ath11k_dp_tx_htt_srng_setup(ab, 4116 dp->rxdma_mon_desc_ring.ring_id, 4117 mac_id, HAL_RXDMA_MONITOR_DESC); 4118 if (ret) { 4119 ath11k_warn(ab, "failed to configure rxdma_mon_dst_ring %d\n", 4120 ret); 4121 return ret; 4122 } 4123 ring_id = dp->rx_mon_status_refill_ring.refill_buf_ring.ring_id; 4124 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, mac_id, 4125 HAL_RXDMA_MONITOR_STATUS); 4126 if (ret) { 4127 ath11k_warn(ab, 4128 "failed to configure mon_status_refill_ring %d\n", 4129 ret); 4130 return ret; 4131 } 4132 return 0; 4133 } 4134 4135 static void ath11k_dp_mon_set_frag_len(u32 *total_len, u32 *frag_len) 4136 { 4137 if (*total_len >= (DP_RX_BUFFER_SIZE - sizeof(struct hal_rx_desc))) { 4138 *frag_len = DP_RX_BUFFER_SIZE - sizeof(struct hal_rx_desc); 4139 *total_len -= *frag_len; 4140 } else { 4141 *frag_len = *total_len; 4142 *total_len = 0; 4143 } 4144 } 4145 4146 static 4147 int ath11k_dp_rx_monitor_link_desc_return(struct ath11k *ar, 4148 void *p_last_buf_addr_info, 4149 u8 mac_id) 4150 { 4151 struct ath11k_pdev_dp *dp = &ar->dp; 4152 struct dp_srng *dp_srng; 4153 void *hal_srng; 4154 void *src_srng_desc; 4155 int ret = 0; 4156 4157 dp_srng = &dp->rxdma_mon_desc_ring; 4158 hal_srng = &ar->ab->hal.srng_list[dp_srng->ring_id]; 4159 4160 ath11k_hal_srng_access_begin(ar->ab, hal_srng); 4161 4162 src_srng_desc = ath11k_hal_srng_src_get_next_entry(ar->ab, hal_srng); 4163 4164 if (src_srng_desc) { 4165 struct ath11k_buffer_addr *src_desc = 4166 (struct ath11k_buffer_addr *)src_srng_desc; 4167 4168 *src_desc = *((struct ath11k_buffer_addr *)p_last_buf_addr_info); 4169 } else { 4170 ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 4171 "Monitor Link Desc Ring %d Full", mac_id); 4172 ret = -ENOMEM; 4173 } 4174 4175 ath11k_hal_srng_access_end(ar->ab, hal_srng); 4176 return ret; 4177 } 4178 4179 static 4180 void ath11k_dp_rx_mon_next_link_desc_get(void *rx_msdu_link_desc, 4181 dma_addr_t *paddr, u32 *sw_cookie, 4182 void **pp_buf_addr_info) 4183 { 4184 struct hal_rx_msdu_link *msdu_link = 4185 (struct hal_rx_msdu_link *)rx_msdu_link_desc; 4186 struct ath11k_buffer_addr *buf_addr_info; 4187 u8 rbm = 0; 4188 4189 buf_addr_info = (struct ath11k_buffer_addr *)&msdu_link->buf_addr_info; 4190 4191 ath11k_hal_rx_buf_addr_info_get(buf_addr_info, paddr, sw_cookie, &rbm); 4192 4193 *pp_buf_addr_info = (void *)buf_addr_info; 4194 } 4195 4196 static int ath11k_dp_pkt_set_pktlen(struct sk_buff *skb, u32 len) 4197 { 4198 if (skb->len > len) { 4199 skb_trim(skb, len); 4200 } else { 4201 if (skb_tailroom(skb) < len - skb->len) { 4202 if ((pskb_expand_head(skb, 0, 4203 len - skb->len - skb_tailroom(skb), 4204 GFP_ATOMIC))) { 4205 dev_kfree_skb_any(skb); 4206 return -ENOMEM; 4207 } 4208 } 4209 skb_put(skb, (len - skb->len)); 4210 } 4211 return 0; 4212 } 4213 4214 static void ath11k_hal_rx_msdu_list_get(struct ath11k *ar, 4215 void *msdu_link_desc, 4216 struct hal_rx_msdu_list *msdu_list, 4217 u16 *num_msdus) 4218 { 4219 struct hal_rx_msdu_details *msdu_details = NULL; 4220 struct rx_msdu_desc *msdu_desc_info = NULL; 4221 struct hal_rx_msdu_link *msdu_link = NULL; 4222 int i; 4223 u32 last = FIELD_PREP(RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU, 1); 4224 u32 first = FIELD_PREP(RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU, 1); 4225 u8 tmp = 0; 4226 4227 msdu_link = (struct hal_rx_msdu_link *)msdu_link_desc; 4228 msdu_details = &msdu_link->msdu_link[0]; 4229 4230 for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) { 4231 if (FIELD_GET(BUFFER_ADDR_INFO0_ADDR, 4232 msdu_details[i].buf_addr_info.info0) == 0) { 4233 msdu_desc_info = &msdu_details[i - 1].rx_msdu_info; 4234 msdu_desc_info->info0 |= last; 4235 ; 4236 break; 4237 } 4238 msdu_desc_info = &msdu_details[i].rx_msdu_info; 4239 4240 if (!i) 4241 msdu_desc_info->info0 |= first; 4242 else if (i == (HAL_RX_NUM_MSDU_DESC - 1)) 4243 msdu_desc_info->info0 |= last; 4244 msdu_list->msdu_info[i].msdu_flags = msdu_desc_info->info0; 4245 msdu_list->msdu_info[i].msdu_len = 4246 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info->info0); 4247 msdu_list->sw_cookie[i] = 4248 FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, 4249 msdu_details[i].buf_addr_info.info1); 4250 tmp = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR, 4251 msdu_details[i].buf_addr_info.info1); 4252 msdu_list->rbm[i] = tmp; 4253 } 4254 *num_msdus = i; 4255 } 4256 4257 static u32 ath11k_dp_rx_mon_comp_ppduid(u32 msdu_ppdu_id, u32 *ppdu_id, 4258 u32 *rx_bufs_used) 4259 { 4260 u32 ret = 0; 4261 4262 if ((*ppdu_id < msdu_ppdu_id) && 4263 ((msdu_ppdu_id - *ppdu_id) < DP_NOT_PPDU_ID_WRAP_AROUND)) { 4264 *ppdu_id = msdu_ppdu_id; 4265 ret = msdu_ppdu_id; 4266 } else if ((*ppdu_id > msdu_ppdu_id) && 4267 ((*ppdu_id - msdu_ppdu_id) > DP_NOT_PPDU_ID_WRAP_AROUND)) { 4268 /* mon_dst is behind than mon_status 4269 * skip dst_ring and free it 4270 */ 4271 *rx_bufs_used += 1; 4272 *ppdu_id = msdu_ppdu_id; 4273 ret = msdu_ppdu_id; 4274 } 4275 return ret; 4276 } 4277 4278 static void ath11k_dp_mon_get_buf_len(struct hal_rx_msdu_desc_info *info, 4279 bool *is_frag, u32 *total_len, 4280 u32 *frag_len, u32 *msdu_cnt) 4281 { 4282 if (info->msdu_flags & RX_MSDU_DESC_INFO0_MSDU_CONTINUATION) { 4283 if (!*is_frag) { 4284 *total_len = info->msdu_len; 4285 *is_frag = true; 4286 } 4287 ath11k_dp_mon_set_frag_len(total_len, 4288 frag_len); 4289 } else { 4290 if (*is_frag) { 4291 ath11k_dp_mon_set_frag_len(total_len, 4292 frag_len); 4293 } else { 4294 *frag_len = info->msdu_len; 4295 } 4296 *is_frag = false; 4297 *msdu_cnt -= 1; 4298 } 4299 } 4300 4301 static u32 4302 ath11k_dp_rx_mon_mpdu_pop(struct ath11k *ar, 4303 void *ring_entry, struct sk_buff **head_msdu, 4304 struct sk_buff **tail_msdu, u32 *npackets, 4305 u32 *ppdu_id) 4306 { 4307 struct ath11k_pdev_dp *dp = &ar->dp; 4308 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data; 4309 struct dp_rxdma_ring *rx_ring = &dp->rxdma_mon_buf_ring; 4310 struct sk_buff *msdu = NULL, *last = NULL; 4311 struct hal_rx_msdu_list msdu_list; 4312 void *p_buf_addr_info, *p_last_buf_addr_info; 4313 struct hal_rx_desc *rx_desc; 4314 void *rx_msdu_link_desc; 4315 dma_addr_t paddr; 4316 u16 num_msdus = 0; 4317 u32 rx_buf_size, rx_pkt_offset, sw_cookie; 4318 u32 rx_bufs_used = 0, i = 0; 4319 u32 msdu_ppdu_id = 0, msdu_cnt = 0; 4320 u32 total_len = 0, frag_len = 0; 4321 bool is_frag, is_first_msdu; 4322 bool drop_mpdu = false; 4323 struct ath11k_skb_rxcb *rxcb; 4324 struct hal_reo_entrance_ring *ent_desc = 4325 (struct hal_reo_entrance_ring *)ring_entry; 4326 int buf_id; 4327 4328 ath11k_hal_rx_reo_ent_buf_paddr_get(ring_entry, &paddr, 4329 &sw_cookie, &p_last_buf_addr_info, 4330 &msdu_cnt); 4331 4332 if (FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_PUSH_REASON, 4333 ent_desc->info1) == 4334 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) { 4335 u8 rxdma_err = 4336 FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE, 4337 ent_desc->info1); 4338 if (rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR || 4339 rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR || 4340 rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR) { 4341 drop_mpdu = true; 4342 pmon->rx_mon_stats.dest_mpdu_drop++; 4343 } 4344 } 4345 4346 is_frag = false; 4347 is_first_msdu = true; 4348 4349 do { 4350 if (pmon->mon_last_linkdesc_paddr == paddr) { 4351 pmon->rx_mon_stats.dup_mon_linkdesc_cnt++; 4352 return rx_bufs_used; 4353 } 4354 4355 rx_msdu_link_desc = 4356 (void *)pmon->link_desc_banks[sw_cookie].vaddr + 4357 (paddr - pmon->link_desc_banks[sw_cookie].paddr); 4358 4359 ath11k_hal_rx_msdu_list_get(ar, rx_msdu_link_desc, &msdu_list, 4360 &num_msdus); 4361 4362 for (i = 0; i < num_msdus; i++) { 4363 u32 l2_hdr_offset; 4364 4365 if (pmon->mon_last_buf_cookie == msdu_list.sw_cookie[i]) { 4366 ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 4367 "i %d last_cookie %d is same\n", 4368 i, pmon->mon_last_buf_cookie); 4369 drop_mpdu = true; 4370 pmon->rx_mon_stats.dup_mon_buf_cnt++; 4371 continue; 4372 } 4373 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, 4374 msdu_list.sw_cookie[i]); 4375 4376 spin_lock_bh(&rx_ring->idr_lock); 4377 msdu = idr_find(&rx_ring->bufs_idr, buf_id); 4378 spin_unlock_bh(&rx_ring->idr_lock); 4379 if (!msdu) { 4380 ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 4381 "msdu_pop: invalid buf_id %d\n", buf_id); 4382 break; 4383 } 4384 rxcb = ATH11K_SKB_RXCB(msdu); 4385 if (!rxcb->unmapped) { 4386 dma_unmap_single(ar->ab->dev, rxcb->paddr, 4387 msdu->len + 4388 skb_tailroom(msdu), 4389 DMA_FROM_DEVICE); 4390 rxcb->unmapped = 1; 4391 } 4392 if (drop_mpdu) { 4393 ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 4394 "i %d drop msdu %p *ppdu_id %x\n", 4395 i, msdu, *ppdu_id); 4396 dev_kfree_skb_any(msdu); 4397 msdu = NULL; 4398 goto next_msdu; 4399 } 4400 4401 rx_desc = (struct hal_rx_desc *)msdu->data; 4402 4403 rx_pkt_offset = sizeof(struct hal_rx_desc); 4404 l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(rx_desc); 4405 4406 if (is_first_msdu) { 4407 if (!ath11k_dp_rxdesc_mpdu_valid(rx_desc)) { 4408 drop_mpdu = true; 4409 dev_kfree_skb_any(msdu); 4410 msdu = NULL; 4411 pmon->mon_last_linkdesc_paddr = paddr; 4412 goto next_msdu; 4413 } 4414 4415 msdu_ppdu_id = 4416 ath11k_dp_rxdesc_get_ppduid(rx_desc); 4417 4418 if (ath11k_dp_rx_mon_comp_ppduid(msdu_ppdu_id, 4419 ppdu_id, 4420 &rx_bufs_used)) { 4421 if (rx_bufs_used) { 4422 drop_mpdu = true; 4423 dev_kfree_skb_any(msdu); 4424 msdu = NULL; 4425 goto next_msdu; 4426 } 4427 return rx_bufs_used; 4428 } 4429 pmon->mon_last_linkdesc_paddr = paddr; 4430 is_first_msdu = false; 4431 } 4432 ath11k_dp_mon_get_buf_len(&msdu_list.msdu_info[i], 4433 &is_frag, &total_len, 4434 &frag_len, &msdu_cnt); 4435 rx_buf_size = rx_pkt_offset + l2_hdr_offset + frag_len; 4436 4437 ath11k_dp_pkt_set_pktlen(msdu, rx_buf_size); 4438 4439 if (!(*head_msdu)) 4440 *head_msdu = msdu; 4441 else if (last) 4442 last->next = msdu; 4443 4444 last = msdu; 4445 next_msdu: 4446 pmon->mon_last_buf_cookie = msdu_list.sw_cookie[i]; 4447 rx_bufs_used++; 4448 spin_lock_bh(&rx_ring->idr_lock); 4449 idr_remove(&rx_ring->bufs_idr, buf_id); 4450 spin_unlock_bh(&rx_ring->idr_lock); 4451 } 4452 4453 ath11k_dp_rx_mon_next_link_desc_get(rx_msdu_link_desc, &paddr, 4454 &sw_cookie, 4455 &p_buf_addr_info); 4456 4457 if (ath11k_dp_rx_monitor_link_desc_return(ar, 4458 p_last_buf_addr_info, 4459 dp->mac_id)) 4460 ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 4461 "dp_rx_monitor_link_desc_return failed"); 4462 4463 p_last_buf_addr_info = p_buf_addr_info; 4464 4465 } while (paddr && msdu_cnt); 4466 4467 if (last) 4468 last->next = NULL; 4469 4470 *tail_msdu = msdu; 4471 4472 if (msdu_cnt == 0) 4473 *npackets = 1; 4474 4475 return rx_bufs_used; 4476 } 4477 4478 static void ath11k_dp_rx_msdus_set_payload(struct sk_buff *msdu) 4479 { 4480 u32 rx_pkt_offset, l2_hdr_offset; 4481 4482 rx_pkt_offset = sizeof(struct hal_rx_desc); 4483 l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad((struct hal_rx_desc *)msdu->data); 4484 skb_pull(msdu, rx_pkt_offset + l2_hdr_offset); 4485 } 4486 4487 static struct sk_buff * 4488 ath11k_dp_rx_mon_merg_msdus(struct ath11k *ar, 4489 u32 mac_id, struct sk_buff *head_msdu, 4490 struct sk_buff *last_msdu, 4491 struct ieee80211_rx_status *rxs) 4492 { 4493 struct sk_buff *msdu, *mpdu_buf, *prev_buf; 4494 u32 decap_format, wifi_hdr_len; 4495 struct hal_rx_desc *rx_desc; 4496 char *hdr_desc; 4497 u8 *dest; 4498 struct ieee80211_hdr_3addr *wh; 4499 4500 mpdu_buf = NULL; 4501 4502 if (!head_msdu) 4503 goto err_merge_fail; 4504 4505 rx_desc = (struct hal_rx_desc *)head_msdu->data; 4506 4507 if (ath11k_dp_rxdesc_get_mpdulen_err(rx_desc)) 4508 return NULL; 4509 4510 decap_format = ath11k_dp_rxdesc_get_decap_format(rx_desc); 4511 4512 ath11k_dp_rx_h_ppdu(ar, rx_desc, rxs); 4513 4514 if (decap_format == DP_RX_DECAP_TYPE_RAW) { 4515 ath11k_dp_rx_msdus_set_payload(head_msdu); 4516 4517 prev_buf = head_msdu; 4518 msdu = head_msdu->next; 4519 4520 while (msdu) { 4521 ath11k_dp_rx_msdus_set_payload(msdu); 4522 4523 prev_buf = msdu; 4524 msdu = msdu->next; 4525 } 4526 4527 prev_buf->next = NULL; 4528 4529 skb_trim(prev_buf, prev_buf->len - HAL_RX_FCS_LEN); 4530 } else if (decap_format == DP_RX_DECAP_TYPE_NATIVE_WIFI) { 4531 __le16 qos_field; 4532 u8 qos_pkt = 0; 4533 4534 rx_desc = (struct hal_rx_desc *)head_msdu->data; 4535 hdr_desc = ath11k_dp_rxdesc_get_80211hdr(rx_desc); 4536 4537 /* Base size */ 4538 wifi_hdr_len = sizeof(struct ieee80211_hdr_3addr); 4539 wh = (struct ieee80211_hdr_3addr *)hdr_desc; 4540 4541 if (ieee80211_is_data_qos(wh->frame_control)) { 4542 struct ieee80211_qos_hdr *qwh = 4543 (struct ieee80211_qos_hdr *)hdr_desc; 4544 4545 qos_field = qwh->qos_ctrl; 4546 qos_pkt = 1; 4547 } 4548 msdu = head_msdu; 4549 4550 while (msdu) { 4551 rx_desc = (struct hal_rx_desc *)msdu->data; 4552 hdr_desc = ath11k_dp_rxdesc_get_80211hdr(rx_desc); 4553 4554 if (qos_pkt) { 4555 dest = skb_push(msdu, sizeof(__le16)); 4556 if (!dest) 4557 goto err_merge_fail; 4558 memcpy(dest, hdr_desc, wifi_hdr_len); 4559 memcpy(dest + wifi_hdr_len, 4560 (u8 *)&qos_field, sizeof(__le16)); 4561 } 4562 ath11k_dp_rx_msdus_set_payload(msdu); 4563 prev_buf = msdu; 4564 msdu = msdu->next; 4565 } 4566 dest = skb_put(prev_buf, HAL_RX_FCS_LEN); 4567 if (!dest) 4568 goto err_merge_fail; 4569 4570 ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 4571 "mpdu_buf %pK mpdu_buf->len %u", 4572 prev_buf, prev_buf->len); 4573 } else { 4574 ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 4575 "decap format %d is not supported!\n", 4576 decap_format); 4577 goto err_merge_fail; 4578 } 4579 4580 return head_msdu; 4581 4582 err_merge_fail: 4583 if (mpdu_buf && decap_format != DP_RX_DECAP_TYPE_RAW) { 4584 ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 4585 "err_merge_fail mpdu_buf %pK", mpdu_buf); 4586 /* Free the head buffer */ 4587 dev_kfree_skb_any(mpdu_buf); 4588 } 4589 return NULL; 4590 } 4591 4592 static int ath11k_dp_rx_mon_deliver(struct ath11k *ar, u32 mac_id, 4593 struct sk_buff *head_msdu, 4594 struct sk_buff *tail_msdu, 4595 struct napi_struct *napi) 4596 { 4597 struct ath11k_pdev_dp *dp = &ar->dp; 4598 struct sk_buff *mon_skb, *skb_next, *header; 4599 struct ieee80211_rx_status *rxs = &dp->rx_status, *status; 4600 4601 mon_skb = ath11k_dp_rx_mon_merg_msdus(ar, mac_id, head_msdu, 4602 tail_msdu, rxs); 4603 4604 if (!mon_skb) 4605 goto mon_deliver_fail; 4606 4607 header = mon_skb; 4608 4609 rxs->flag = 0; 4610 do { 4611 skb_next = mon_skb->next; 4612 if (!skb_next) 4613 rxs->flag &= ~RX_FLAG_AMSDU_MORE; 4614 else 4615 rxs->flag |= RX_FLAG_AMSDU_MORE; 4616 4617 if (mon_skb == header) { 4618 header = NULL; 4619 rxs->flag &= ~RX_FLAG_ALLOW_SAME_PN; 4620 } else { 4621 rxs->flag |= RX_FLAG_ALLOW_SAME_PN; 4622 } 4623 rxs->flag |= RX_FLAG_ONLY_MONITOR; 4624 4625 status = IEEE80211_SKB_RXCB(mon_skb); 4626 *status = *rxs; 4627 4628 ath11k_dp_rx_deliver_msdu(ar, napi, mon_skb); 4629 mon_skb = skb_next; 4630 } while (mon_skb); 4631 rxs->flag = 0; 4632 4633 return 0; 4634 4635 mon_deliver_fail: 4636 mon_skb = head_msdu; 4637 while (mon_skb) { 4638 skb_next = mon_skb->next; 4639 dev_kfree_skb_any(mon_skb); 4640 mon_skb = skb_next; 4641 } 4642 return -EINVAL; 4643 } 4644 4645 static void ath11k_dp_rx_mon_dest_process(struct ath11k *ar, u32 quota, 4646 struct napi_struct *napi) 4647 { 4648 struct ath11k_pdev_dp *dp = &ar->dp; 4649 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data; 4650 void *ring_entry; 4651 void *mon_dst_srng; 4652 u32 ppdu_id; 4653 u32 rx_bufs_used; 4654 struct ath11k_pdev_mon_stats *rx_mon_stats; 4655 u32 npackets = 0; 4656 4657 mon_dst_srng = &ar->ab->hal.srng_list[dp->rxdma_mon_dst_ring.ring_id]; 4658 4659 if (!mon_dst_srng) { 4660 ath11k_warn(ar->ab, 4661 "HAL Monitor Destination Ring Init Failed -- %pK", 4662 mon_dst_srng); 4663 return; 4664 } 4665 4666 spin_lock_bh(&pmon->mon_lock); 4667 4668 ath11k_hal_srng_access_begin(ar->ab, mon_dst_srng); 4669 4670 ppdu_id = pmon->mon_ppdu_info.ppdu_id; 4671 rx_bufs_used = 0; 4672 rx_mon_stats = &pmon->rx_mon_stats; 4673 4674 while ((ring_entry = ath11k_hal_srng_dst_peek(ar->ab, mon_dst_srng))) { 4675 struct sk_buff *head_msdu, *tail_msdu; 4676 4677 head_msdu = NULL; 4678 tail_msdu = NULL; 4679 4680 rx_bufs_used += ath11k_dp_rx_mon_mpdu_pop(ar, ring_entry, 4681 &head_msdu, 4682 &tail_msdu, 4683 &npackets, &ppdu_id); 4684 4685 if (ppdu_id != pmon->mon_ppdu_info.ppdu_id) { 4686 pmon->mon_ppdu_status = DP_PPDU_STATUS_START; 4687 ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 4688 "dest_rx: new ppdu_id %x != status ppdu_id %x", 4689 ppdu_id, pmon->mon_ppdu_info.ppdu_id); 4690 break; 4691 } 4692 if (head_msdu && tail_msdu) { 4693 ath11k_dp_rx_mon_deliver(ar, dp->mac_id, head_msdu, 4694 tail_msdu, napi); 4695 rx_mon_stats->dest_mpdu_done++; 4696 } 4697 4698 ring_entry = ath11k_hal_srng_dst_get_next_entry(ar->ab, 4699 mon_dst_srng); 4700 } 4701 ath11k_hal_srng_access_end(ar->ab, mon_dst_srng); 4702 4703 spin_unlock_bh(&pmon->mon_lock); 4704 4705 if (rx_bufs_used) { 4706 rx_mon_stats->dest_ppdu_done++; 4707 ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id, 4708 &dp->rxdma_mon_buf_ring, 4709 rx_bufs_used, 4710 HAL_RX_BUF_RBM_SW3_BM, GFP_ATOMIC); 4711 } 4712 } 4713 4714 static void ath11k_dp_rx_mon_status_process_tlv(struct ath11k *ar, 4715 u32 quota, 4716 struct napi_struct *napi) 4717 { 4718 struct ath11k_pdev_dp *dp = &ar->dp; 4719 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data; 4720 struct hal_rx_mon_ppdu_info *ppdu_info; 4721 struct sk_buff *status_skb; 4722 u32 tlv_status = HAL_TLV_STATUS_BUF_DONE; 4723 struct ath11k_pdev_mon_stats *rx_mon_stats; 4724 4725 ppdu_info = &pmon->mon_ppdu_info; 4726 rx_mon_stats = &pmon->rx_mon_stats; 4727 4728 if (pmon->mon_ppdu_status != DP_PPDU_STATUS_START) 4729 return; 4730 4731 while (!skb_queue_empty(&pmon->rx_status_q)) { 4732 status_skb = skb_dequeue(&pmon->rx_status_q); 4733 4734 tlv_status = ath11k_hal_rx_parse_mon_status(ar->ab, ppdu_info, 4735 status_skb); 4736 if (tlv_status == HAL_TLV_STATUS_PPDU_DONE) { 4737 rx_mon_stats->status_ppdu_done++; 4738 pmon->mon_ppdu_status = DP_PPDU_STATUS_DONE; 4739 ath11k_dp_rx_mon_dest_process(ar, quota, napi); 4740 pmon->mon_ppdu_status = DP_PPDU_STATUS_START; 4741 } 4742 dev_kfree_skb_any(status_skb); 4743 } 4744 } 4745 4746 static int ath11k_dp_mon_process_rx(struct ath11k_base *ab, int mac_id, 4747 struct napi_struct *napi, int budget) 4748 { 4749 struct ath11k *ar = ab->pdevs[mac_id].ar; 4750 struct ath11k_pdev_dp *dp = &ar->dp; 4751 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data; 4752 int num_buffs_reaped = 0; 4753 4754 num_buffs_reaped = ath11k_dp_rx_reap_mon_status_ring(ar->ab, dp->mac_id, &budget, 4755 &pmon->rx_status_q); 4756 if (num_buffs_reaped) 4757 ath11k_dp_rx_mon_status_process_tlv(ar, budget, napi); 4758 4759 return num_buffs_reaped; 4760 } 4761 4762 int ath11k_dp_rx_process_mon_rings(struct ath11k_base *ab, int mac_id, 4763 struct napi_struct *napi, int budget) 4764 { 4765 struct ath11k *ar = ab->pdevs[mac_id].ar; 4766 int ret = 0; 4767 4768 if (test_bit(ATH11K_FLAG_MONITOR_ENABLED, &ar->monitor_flags)) 4769 ret = ath11k_dp_mon_process_rx(ab, mac_id, napi, budget); 4770 else 4771 ret = ath11k_dp_rx_process_mon_status(ab, mac_id, napi, budget); 4772 return ret; 4773 } 4774 4775 static int ath11k_dp_rx_pdev_mon_status_attach(struct ath11k *ar) 4776 { 4777 struct ath11k_pdev_dp *dp = &ar->dp; 4778 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data; 4779 4780 skb_queue_head_init(&pmon->rx_status_q); 4781 4782 pmon->mon_ppdu_status = DP_PPDU_STATUS_START; 4783 4784 memset(&pmon->rx_mon_stats, 0, 4785 sizeof(pmon->rx_mon_stats)); 4786 return 0; 4787 } 4788 4789 int ath11k_dp_rx_pdev_mon_attach(struct ath11k *ar) 4790 { 4791 struct ath11k_pdev_dp *dp = &ar->dp; 4792 struct ath11k_mon_data *pmon = &dp->mon_data; 4793 struct hal_srng *mon_desc_srng = NULL; 4794 struct dp_srng *dp_srng; 4795 int ret = 0; 4796 u32 n_link_desc = 0; 4797 4798 ret = ath11k_dp_rx_pdev_mon_status_attach(ar); 4799 if (ret) { 4800 ath11k_warn(ar->ab, "pdev_mon_status_attach() failed"); 4801 return ret; 4802 } 4803 4804 dp_srng = &dp->rxdma_mon_desc_ring; 4805 n_link_desc = dp_srng->size / 4806 ath11k_hal_srng_get_entrysize(HAL_RXDMA_MONITOR_DESC); 4807 mon_desc_srng = 4808 &ar->ab->hal.srng_list[dp->rxdma_mon_desc_ring.ring_id]; 4809 4810 ret = ath11k_dp_link_desc_setup(ar->ab, pmon->link_desc_banks, 4811 HAL_RXDMA_MONITOR_DESC, mon_desc_srng, 4812 n_link_desc); 4813 if (ret) { 4814 ath11k_warn(ar->ab, "mon_link_desc_pool_setup() failed"); 4815 return ret; 4816 } 4817 pmon->mon_last_linkdesc_paddr = 0; 4818 pmon->mon_last_buf_cookie = DP_RX_DESC_COOKIE_MAX + 1; 4819 spin_lock_init(&pmon->mon_lock); 4820 return 0; 4821 } 4822 4823 static int ath11k_dp_mon_link_free(struct ath11k *ar) 4824 { 4825 struct ath11k_pdev_dp *dp = &ar->dp; 4826 struct ath11k_mon_data *pmon = &dp->mon_data; 4827 4828 ath11k_dp_link_desc_cleanup(ar->ab, pmon->link_desc_banks, 4829 HAL_RXDMA_MONITOR_DESC, 4830 &dp->rxdma_mon_desc_ring); 4831 return 0; 4832 } 4833 4834 int ath11k_dp_rx_pdev_mon_detach(struct ath11k *ar) 4835 { 4836 ath11k_dp_mon_link_free(ar); 4837 return 0; 4838 } 4839