xref: /linux/drivers/net/wireless/ath/ath11k/dp_rx.c (revision 65aa371ea52a92dd10826a2ea74bd2c395ee90a8)
1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4  */
5 
6 #include <linux/ieee80211.h>
7 #include <linux/kernel.h>
8 #include <linux/skbuff.h>
9 #include <crypto/hash.h>
10 #include "core.h"
11 #include "debug.h"
12 #include "debugfs_htt_stats.h"
13 #include "debugfs_sta.h"
14 #include "hal_desc.h"
15 #include "hw.h"
16 #include "dp_rx.h"
17 #include "hal_rx.h"
18 #include "dp_tx.h"
19 #include "peer.h"
20 
21 #define ATH11K_DP_RX_FRAGMENT_TIMEOUT_MS (2 * HZ)
22 
23 static u8 *ath11k_dp_rx_h_80211_hdr(struct ath11k_base *ab, struct hal_rx_desc *desc)
24 {
25 	return ab->hw_params.hw_ops->rx_desc_get_hdr_status(desc);
26 }
27 
28 static enum hal_encrypt_type ath11k_dp_rx_h_mpdu_start_enctype(struct ath11k_base *ab,
29 							       struct hal_rx_desc *desc)
30 {
31 	if (!ab->hw_params.hw_ops->rx_desc_encrypt_valid(desc))
32 		return HAL_ENCRYPT_TYPE_OPEN;
33 
34 	return ab->hw_params.hw_ops->rx_desc_get_encrypt_type(desc);
35 }
36 
37 static u8 ath11k_dp_rx_h_msdu_start_decap_type(struct ath11k_base *ab,
38 					       struct hal_rx_desc *desc)
39 {
40 	return ab->hw_params.hw_ops->rx_desc_get_decap_type(desc);
41 }
42 
43 static u8 ath11k_dp_rx_h_msdu_start_mesh_ctl_present(struct ath11k_base *ab,
44 						     struct hal_rx_desc *desc)
45 {
46 	return ab->hw_params.hw_ops->rx_desc_get_mesh_ctl(desc);
47 }
48 
49 static bool ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(struct ath11k_base *ab,
50 						     struct hal_rx_desc *desc)
51 {
52 	return ab->hw_params.hw_ops->rx_desc_get_mpdu_seq_ctl_vld(desc);
53 }
54 
55 static bool ath11k_dp_rx_h_mpdu_start_fc_valid(struct ath11k_base *ab,
56 					       struct hal_rx_desc *desc)
57 {
58 	return ab->hw_params.hw_ops->rx_desc_get_mpdu_fc_valid(desc);
59 }
60 
61 static bool ath11k_dp_rx_h_mpdu_start_more_frags(struct ath11k_base *ab,
62 						 struct sk_buff *skb)
63 {
64 	struct ieee80211_hdr *hdr;
65 
66 	hdr = (struct ieee80211_hdr *)(skb->data + ab->hw_params.hal_desc_sz);
67 	return ieee80211_has_morefrags(hdr->frame_control);
68 }
69 
70 static u16 ath11k_dp_rx_h_mpdu_start_frag_no(struct ath11k_base *ab,
71 					     struct sk_buff *skb)
72 {
73 	struct ieee80211_hdr *hdr;
74 
75 	hdr = (struct ieee80211_hdr *)(skb->data + ab->hw_params.hal_desc_sz);
76 	return le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
77 }
78 
79 static u16 ath11k_dp_rx_h_mpdu_start_seq_no(struct ath11k_base *ab,
80 					    struct hal_rx_desc *desc)
81 {
82 	return ab->hw_params.hw_ops->rx_desc_get_mpdu_start_seq_no(desc);
83 }
84 
85 static void *ath11k_dp_rx_get_attention(struct ath11k_base *ab,
86 					struct hal_rx_desc *desc)
87 {
88 	return ab->hw_params.hw_ops->rx_desc_get_attention(desc);
89 }
90 
91 static bool ath11k_dp_rx_h_attn_msdu_done(struct rx_attention *attn)
92 {
93 	return !!FIELD_GET(RX_ATTENTION_INFO2_MSDU_DONE,
94 			   __le32_to_cpu(attn->info2));
95 }
96 
97 static bool ath11k_dp_rx_h_attn_l4_cksum_fail(struct rx_attention *attn)
98 {
99 	return !!FIELD_GET(RX_ATTENTION_INFO1_TCP_UDP_CKSUM_FAIL,
100 			   __le32_to_cpu(attn->info1));
101 }
102 
103 static bool ath11k_dp_rx_h_attn_ip_cksum_fail(struct rx_attention *attn)
104 {
105 	return !!FIELD_GET(RX_ATTENTION_INFO1_IP_CKSUM_FAIL,
106 			   __le32_to_cpu(attn->info1));
107 }
108 
109 static bool ath11k_dp_rx_h_attn_is_decrypted(struct rx_attention *attn)
110 {
111 	return (FIELD_GET(RX_ATTENTION_INFO2_DCRYPT_STATUS_CODE,
112 			  __le32_to_cpu(attn->info2)) ==
113 		RX_DESC_DECRYPT_STATUS_CODE_OK);
114 }
115 
116 static u32 ath11k_dp_rx_h_attn_mpdu_err(struct rx_attention *attn)
117 {
118 	u32 info = __le32_to_cpu(attn->info1);
119 	u32 errmap = 0;
120 
121 	if (info & RX_ATTENTION_INFO1_FCS_ERR)
122 		errmap |= DP_RX_MPDU_ERR_FCS;
123 
124 	if (info & RX_ATTENTION_INFO1_DECRYPT_ERR)
125 		errmap |= DP_RX_MPDU_ERR_DECRYPT;
126 
127 	if (info & RX_ATTENTION_INFO1_TKIP_MIC_ERR)
128 		errmap |= DP_RX_MPDU_ERR_TKIP_MIC;
129 
130 	if (info & RX_ATTENTION_INFO1_A_MSDU_ERROR)
131 		errmap |= DP_RX_MPDU_ERR_AMSDU_ERR;
132 
133 	if (info & RX_ATTENTION_INFO1_OVERFLOW_ERR)
134 		errmap |= DP_RX_MPDU_ERR_OVERFLOW;
135 
136 	if (info & RX_ATTENTION_INFO1_MSDU_LEN_ERR)
137 		errmap |= DP_RX_MPDU_ERR_MSDU_LEN;
138 
139 	if (info & RX_ATTENTION_INFO1_MPDU_LEN_ERR)
140 		errmap |= DP_RX_MPDU_ERR_MPDU_LEN;
141 
142 	return errmap;
143 }
144 
145 static bool ath11k_dp_rx_h_attn_msdu_len_err(struct ath11k_base *ab,
146 					     struct hal_rx_desc *desc)
147 {
148 	struct rx_attention *rx_attention;
149 	u32 errmap;
150 
151 	rx_attention = ath11k_dp_rx_get_attention(ab, desc);
152 	errmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention);
153 
154 	return errmap & DP_RX_MPDU_ERR_MSDU_LEN;
155 }
156 
157 static u16 ath11k_dp_rx_h_msdu_start_msdu_len(struct ath11k_base *ab,
158 					      struct hal_rx_desc *desc)
159 {
160 	return ab->hw_params.hw_ops->rx_desc_get_msdu_len(desc);
161 }
162 
163 static u8 ath11k_dp_rx_h_msdu_start_sgi(struct ath11k_base *ab,
164 					struct hal_rx_desc *desc)
165 {
166 	return ab->hw_params.hw_ops->rx_desc_get_msdu_sgi(desc);
167 }
168 
169 static u8 ath11k_dp_rx_h_msdu_start_rate_mcs(struct ath11k_base *ab,
170 					     struct hal_rx_desc *desc)
171 {
172 	return ab->hw_params.hw_ops->rx_desc_get_msdu_rate_mcs(desc);
173 }
174 
175 static u8 ath11k_dp_rx_h_msdu_start_rx_bw(struct ath11k_base *ab,
176 					  struct hal_rx_desc *desc)
177 {
178 	return ab->hw_params.hw_ops->rx_desc_get_msdu_rx_bw(desc);
179 }
180 
181 static u32 ath11k_dp_rx_h_msdu_start_freq(struct ath11k_base *ab,
182 					  struct hal_rx_desc *desc)
183 {
184 	return ab->hw_params.hw_ops->rx_desc_get_msdu_freq(desc);
185 }
186 
187 static u8 ath11k_dp_rx_h_msdu_start_pkt_type(struct ath11k_base *ab,
188 					     struct hal_rx_desc *desc)
189 {
190 	return ab->hw_params.hw_ops->rx_desc_get_msdu_pkt_type(desc);
191 }
192 
193 static u8 ath11k_dp_rx_h_msdu_start_nss(struct ath11k_base *ab,
194 					struct hal_rx_desc *desc)
195 {
196 	return hweight8(ab->hw_params.hw_ops->rx_desc_get_msdu_nss(desc));
197 }
198 
199 static u8 ath11k_dp_rx_h_mpdu_start_tid(struct ath11k_base *ab,
200 					struct hal_rx_desc *desc)
201 {
202 	return ab->hw_params.hw_ops->rx_desc_get_mpdu_tid(desc);
203 }
204 
205 static u16 ath11k_dp_rx_h_mpdu_start_peer_id(struct ath11k_base *ab,
206 					     struct hal_rx_desc *desc)
207 {
208 	return ab->hw_params.hw_ops->rx_desc_get_mpdu_peer_id(desc);
209 }
210 
211 static u8 ath11k_dp_rx_h_msdu_end_l3pad(struct ath11k_base *ab,
212 					struct hal_rx_desc *desc)
213 {
214 	return ab->hw_params.hw_ops->rx_desc_get_l3_pad_bytes(desc);
215 }
216 
217 static bool ath11k_dp_rx_h_msdu_end_first_msdu(struct ath11k_base *ab,
218 					       struct hal_rx_desc *desc)
219 {
220 	return ab->hw_params.hw_ops->rx_desc_get_first_msdu(desc);
221 }
222 
223 static bool ath11k_dp_rx_h_msdu_end_last_msdu(struct ath11k_base *ab,
224 					      struct hal_rx_desc *desc)
225 {
226 	return ab->hw_params.hw_ops->rx_desc_get_last_msdu(desc);
227 }
228 
229 static void ath11k_dp_rx_desc_end_tlv_copy(struct ath11k_base *ab,
230 					   struct hal_rx_desc *fdesc,
231 					   struct hal_rx_desc *ldesc)
232 {
233 	ab->hw_params.hw_ops->rx_desc_copy_attn_end_tlv(fdesc, ldesc);
234 }
235 
236 static u32 ath11k_dp_rxdesc_get_mpdulen_err(struct rx_attention *attn)
237 {
238 	return FIELD_GET(RX_ATTENTION_INFO1_MPDU_LEN_ERR,
239 			 __le32_to_cpu(attn->info1));
240 }
241 
242 static u8 *ath11k_dp_rxdesc_get_80211hdr(struct ath11k_base *ab,
243 					 struct hal_rx_desc *rx_desc)
244 {
245 	u8 *rx_pkt_hdr;
246 
247 	rx_pkt_hdr = ab->hw_params.hw_ops->rx_desc_get_msdu_payload(rx_desc);
248 
249 	return rx_pkt_hdr;
250 }
251 
252 static bool ath11k_dp_rxdesc_mpdu_valid(struct ath11k_base *ab,
253 					struct hal_rx_desc *rx_desc)
254 {
255 	u32 tlv_tag;
256 
257 	tlv_tag = ab->hw_params.hw_ops->rx_desc_get_mpdu_start_tag(rx_desc);
258 
259 	return tlv_tag == HAL_RX_MPDU_START;
260 }
261 
262 static u32 ath11k_dp_rxdesc_get_ppduid(struct ath11k_base *ab,
263 				       struct hal_rx_desc *rx_desc)
264 {
265 	return ab->hw_params.hw_ops->rx_desc_get_mpdu_ppdu_id(rx_desc);
266 }
267 
268 static void ath11k_dp_rxdesc_set_msdu_len(struct ath11k_base *ab,
269 					  struct hal_rx_desc *desc,
270 					  u16 len)
271 {
272 	ab->hw_params.hw_ops->rx_desc_set_msdu_len(desc, len);
273 }
274 
275 static bool ath11k_dp_rx_h_attn_is_mcbc(struct ath11k_base *ab,
276 					struct hal_rx_desc *desc)
277 {
278 	struct rx_attention *attn = ath11k_dp_rx_get_attention(ab, desc);
279 
280 	return ath11k_dp_rx_h_msdu_end_first_msdu(ab, desc) &&
281 		(!!FIELD_GET(RX_ATTENTION_INFO1_MCAST_BCAST,
282 		 __le32_to_cpu(attn->info1)));
283 }
284 
285 static bool ath11k_dp_rxdesc_mac_addr2_valid(struct ath11k_base *ab,
286 					     struct hal_rx_desc *desc)
287 {
288 	return ab->hw_params.hw_ops->rx_desc_mac_addr2_valid(desc);
289 }
290 
291 static u8 *ath11k_dp_rxdesc_mpdu_start_addr2(struct ath11k_base *ab,
292 					     struct hal_rx_desc *desc)
293 {
294 	return ab->hw_params.hw_ops->rx_desc_mpdu_start_addr2(desc);
295 }
296 
297 static void ath11k_dp_service_mon_ring(struct timer_list *t)
298 {
299 	struct ath11k_base *ab = from_timer(ab, t, mon_reap_timer);
300 	int i;
301 
302 	for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++)
303 		ath11k_dp_rx_process_mon_rings(ab, i, NULL, DP_MON_SERVICE_BUDGET);
304 
305 	mod_timer(&ab->mon_reap_timer, jiffies +
306 		  msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL));
307 }
308 
309 static int ath11k_dp_purge_mon_ring(struct ath11k_base *ab)
310 {
311 	int i, reaped = 0;
312 	unsigned long timeout = jiffies + msecs_to_jiffies(DP_MON_PURGE_TIMEOUT_MS);
313 
314 	do {
315 		for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++)
316 			reaped += ath11k_dp_rx_process_mon_rings(ab, i,
317 								 NULL,
318 								 DP_MON_SERVICE_BUDGET);
319 
320 		/* nothing more to reap */
321 		if (reaped < DP_MON_SERVICE_BUDGET)
322 			return 0;
323 
324 	} while (time_before(jiffies, timeout));
325 
326 	ath11k_warn(ab, "dp mon ring purge timeout");
327 
328 	return -ETIMEDOUT;
329 }
330 
331 /* Returns number of Rx buffers replenished */
332 int ath11k_dp_rxbufs_replenish(struct ath11k_base *ab, int mac_id,
333 			       struct dp_rxdma_ring *rx_ring,
334 			       int req_entries,
335 			       enum hal_rx_buf_return_buf_manager mgr)
336 {
337 	struct hal_srng *srng;
338 	u32 *desc;
339 	struct sk_buff *skb;
340 	int num_free;
341 	int num_remain;
342 	int buf_id;
343 	u32 cookie;
344 	dma_addr_t paddr;
345 
346 	req_entries = min(req_entries, rx_ring->bufs_max);
347 
348 	srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
349 
350 	spin_lock_bh(&srng->lock);
351 
352 	ath11k_hal_srng_access_begin(ab, srng);
353 
354 	num_free = ath11k_hal_srng_src_num_free(ab, srng, true);
355 	if (!req_entries && (num_free > (rx_ring->bufs_max * 3) / 4))
356 		req_entries = num_free;
357 
358 	req_entries = min(num_free, req_entries);
359 	num_remain = req_entries;
360 
361 	while (num_remain > 0) {
362 		skb = dev_alloc_skb(DP_RX_BUFFER_SIZE +
363 				    DP_RX_BUFFER_ALIGN_SIZE);
364 		if (!skb)
365 			break;
366 
367 		if (!IS_ALIGNED((unsigned long)skb->data,
368 				DP_RX_BUFFER_ALIGN_SIZE)) {
369 			skb_pull(skb,
370 				 PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) -
371 				 skb->data);
372 		}
373 
374 		paddr = dma_map_single(ab->dev, skb->data,
375 				       skb->len + skb_tailroom(skb),
376 				       DMA_FROM_DEVICE);
377 		if (dma_mapping_error(ab->dev, paddr))
378 			goto fail_free_skb;
379 
380 		spin_lock_bh(&rx_ring->idr_lock);
381 		buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 0,
382 				   rx_ring->bufs_max * 3, GFP_ATOMIC);
383 		spin_unlock_bh(&rx_ring->idr_lock);
384 		if (buf_id < 0)
385 			goto fail_dma_unmap;
386 
387 		desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
388 		if (!desc)
389 			goto fail_idr_remove;
390 
391 		ATH11K_SKB_RXCB(skb)->paddr = paddr;
392 
393 		cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
394 			 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
395 
396 		num_remain--;
397 
398 		ath11k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr);
399 	}
400 
401 	ath11k_hal_srng_access_end(ab, srng);
402 
403 	spin_unlock_bh(&srng->lock);
404 
405 	return req_entries - num_remain;
406 
407 fail_idr_remove:
408 	spin_lock_bh(&rx_ring->idr_lock);
409 	idr_remove(&rx_ring->bufs_idr, buf_id);
410 	spin_unlock_bh(&rx_ring->idr_lock);
411 fail_dma_unmap:
412 	dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
413 			 DMA_FROM_DEVICE);
414 fail_free_skb:
415 	dev_kfree_skb_any(skb);
416 
417 	ath11k_hal_srng_access_end(ab, srng);
418 
419 	spin_unlock_bh(&srng->lock);
420 
421 	return req_entries - num_remain;
422 }
423 
424 static int ath11k_dp_rxdma_buf_ring_free(struct ath11k *ar,
425 					 struct dp_rxdma_ring *rx_ring)
426 {
427 	struct ath11k_pdev_dp *dp = &ar->dp;
428 	struct sk_buff *skb;
429 	int buf_id;
430 
431 	spin_lock_bh(&rx_ring->idr_lock);
432 	idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) {
433 		idr_remove(&rx_ring->bufs_idr, buf_id);
434 		/* TODO: Understand where internal driver does this dma_unmap
435 		 * of rxdma_buffer.
436 		 */
437 		dma_unmap_single(ar->ab->dev, ATH11K_SKB_RXCB(skb)->paddr,
438 				 skb->len + skb_tailroom(skb), DMA_FROM_DEVICE);
439 		dev_kfree_skb_any(skb);
440 	}
441 
442 	idr_destroy(&rx_ring->bufs_idr);
443 	spin_unlock_bh(&rx_ring->idr_lock);
444 
445 	/* if rxdma1_enable is false, mon_status_refill_ring
446 	 * isn't setup, so don't clean.
447 	 */
448 	if (!ar->ab->hw_params.rxdma1_enable)
449 		return 0;
450 
451 	rx_ring = &dp->rx_mon_status_refill_ring[0];
452 
453 	spin_lock_bh(&rx_ring->idr_lock);
454 	idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) {
455 		idr_remove(&rx_ring->bufs_idr, buf_id);
456 		/* XXX: Understand where internal driver does this dma_unmap
457 		 * of rxdma_buffer.
458 		 */
459 		dma_unmap_single(ar->ab->dev, ATH11K_SKB_RXCB(skb)->paddr,
460 				 skb->len + skb_tailroom(skb), DMA_BIDIRECTIONAL);
461 		dev_kfree_skb_any(skb);
462 	}
463 
464 	idr_destroy(&rx_ring->bufs_idr);
465 	spin_unlock_bh(&rx_ring->idr_lock);
466 
467 	return 0;
468 }
469 
470 static int ath11k_dp_rxdma_pdev_buf_free(struct ath11k *ar)
471 {
472 	struct ath11k_pdev_dp *dp = &ar->dp;
473 	struct ath11k_base *ab = ar->ab;
474 	struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
475 	int i;
476 
477 	ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
478 
479 	rx_ring = &dp->rxdma_mon_buf_ring;
480 	ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
481 
482 	for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
483 		rx_ring = &dp->rx_mon_status_refill_ring[i];
484 		ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
485 	}
486 
487 	return 0;
488 }
489 
490 static int ath11k_dp_rxdma_ring_buf_setup(struct ath11k *ar,
491 					  struct dp_rxdma_ring *rx_ring,
492 					  u32 ringtype)
493 {
494 	struct ath11k_pdev_dp *dp = &ar->dp;
495 	int num_entries;
496 
497 	num_entries = rx_ring->refill_buf_ring.size /
498 		ath11k_hal_srng_get_entrysize(ar->ab, ringtype);
499 
500 	rx_ring->bufs_max = num_entries;
501 	ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id, rx_ring, num_entries,
502 				   HAL_RX_BUF_RBM_SW3_BM);
503 	return 0;
504 }
505 
506 static int ath11k_dp_rxdma_pdev_buf_setup(struct ath11k *ar)
507 {
508 	struct ath11k_pdev_dp *dp = &ar->dp;
509 	struct ath11k_base *ab = ar->ab;
510 	struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
511 	int i;
512 
513 	ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_BUF);
514 
515 	if (ar->ab->hw_params.rxdma1_enable) {
516 		rx_ring = &dp->rxdma_mon_buf_ring;
517 		ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_MONITOR_BUF);
518 	}
519 
520 	for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
521 		rx_ring = &dp->rx_mon_status_refill_ring[i];
522 		ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_MONITOR_STATUS);
523 	}
524 
525 	return 0;
526 }
527 
528 static void ath11k_dp_rx_pdev_srng_free(struct ath11k *ar)
529 {
530 	struct ath11k_pdev_dp *dp = &ar->dp;
531 	struct ath11k_base *ab = ar->ab;
532 	int i;
533 
534 	ath11k_dp_srng_cleanup(ab, &dp->rx_refill_buf_ring.refill_buf_ring);
535 
536 	for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
537 		if (ab->hw_params.rx_mac_buf_ring)
538 			ath11k_dp_srng_cleanup(ab, &dp->rx_mac_buf_ring[i]);
539 
540 		ath11k_dp_srng_cleanup(ab, &dp->rxdma_err_dst_ring[i]);
541 		ath11k_dp_srng_cleanup(ab,
542 				       &dp->rx_mon_status_refill_ring[i].refill_buf_ring);
543 	}
544 
545 	ath11k_dp_srng_cleanup(ab, &dp->rxdma_mon_buf_ring.refill_buf_ring);
546 }
547 
548 void ath11k_dp_pdev_reo_cleanup(struct ath11k_base *ab)
549 {
550 	struct ath11k_dp *dp = &ab->dp;
551 	int i;
552 
553 	for (i = 0; i < DP_REO_DST_RING_MAX; i++)
554 		ath11k_dp_srng_cleanup(ab, &dp->reo_dst_ring[i]);
555 }
556 
557 int ath11k_dp_pdev_reo_setup(struct ath11k_base *ab)
558 {
559 	struct ath11k_dp *dp = &ab->dp;
560 	int ret;
561 	int i;
562 
563 	for (i = 0; i < DP_REO_DST_RING_MAX; i++) {
564 		ret = ath11k_dp_srng_setup(ab, &dp->reo_dst_ring[i],
565 					   HAL_REO_DST, i, 0,
566 					   DP_REO_DST_RING_SIZE);
567 		if (ret) {
568 			ath11k_warn(ab, "failed to setup reo_dst_ring\n");
569 			goto err_reo_cleanup;
570 		}
571 	}
572 
573 	return 0;
574 
575 err_reo_cleanup:
576 	ath11k_dp_pdev_reo_cleanup(ab);
577 
578 	return ret;
579 }
580 
581 static int ath11k_dp_rx_pdev_srng_alloc(struct ath11k *ar)
582 {
583 	struct ath11k_pdev_dp *dp = &ar->dp;
584 	struct ath11k_base *ab = ar->ab;
585 	struct dp_srng *srng = NULL;
586 	int i;
587 	int ret;
588 
589 	ret = ath11k_dp_srng_setup(ar->ab,
590 				   &dp->rx_refill_buf_ring.refill_buf_ring,
591 				   HAL_RXDMA_BUF, 0,
592 				   dp->mac_id, DP_RXDMA_BUF_RING_SIZE);
593 	if (ret) {
594 		ath11k_warn(ar->ab, "failed to setup rx_refill_buf_ring\n");
595 		return ret;
596 	}
597 
598 	if (ar->ab->hw_params.rx_mac_buf_ring) {
599 		for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
600 			ret = ath11k_dp_srng_setup(ar->ab,
601 						   &dp->rx_mac_buf_ring[i],
602 						   HAL_RXDMA_BUF, 1,
603 						   dp->mac_id + i, 1024);
604 			if (ret) {
605 				ath11k_warn(ar->ab, "failed to setup rx_mac_buf_ring %d\n",
606 					    i);
607 				return ret;
608 			}
609 		}
610 	}
611 
612 	for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
613 		ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_err_dst_ring[i],
614 					   HAL_RXDMA_DST, 0, dp->mac_id + i,
615 					   DP_RXDMA_ERR_DST_RING_SIZE);
616 		if (ret) {
617 			ath11k_warn(ar->ab, "failed to setup rxdma_err_dst_ring %d\n", i);
618 			return ret;
619 		}
620 	}
621 
622 	for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
623 		srng = &dp->rx_mon_status_refill_ring[i].refill_buf_ring;
624 		ret = ath11k_dp_srng_setup(ar->ab,
625 					   srng,
626 					   HAL_RXDMA_MONITOR_STATUS, 0, dp->mac_id + i,
627 					   DP_RXDMA_MON_STATUS_RING_SIZE);
628 		if (ret) {
629 			ath11k_warn(ar->ab,
630 				    "failed to setup rx_mon_status_refill_ring %d\n", i);
631 			return ret;
632 		}
633 	}
634 
635 	/* if rxdma1_enable is false, then it doesn't need
636 	 * to setup rxdam_mon_buf_ring, rxdma_mon_dst_ring
637 	 * and rxdma_mon_desc_ring.
638 	 * init reap timer for QCA6390.
639 	 */
640 	if (!ar->ab->hw_params.rxdma1_enable) {
641 		//init mon status buffer reap timer
642 		timer_setup(&ar->ab->mon_reap_timer,
643 			    ath11k_dp_service_mon_ring, 0);
644 		return 0;
645 	}
646 
647 	ret = ath11k_dp_srng_setup(ar->ab,
648 				   &dp->rxdma_mon_buf_ring.refill_buf_ring,
649 				   HAL_RXDMA_MONITOR_BUF, 0, dp->mac_id,
650 				   DP_RXDMA_MONITOR_BUF_RING_SIZE);
651 	if (ret) {
652 		ath11k_warn(ar->ab,
653 			    "failed to setup HAL_RXDMA_MONITOR_BUF\n");
654 		return ret;
655 	}
656 
657 	ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_mon_dst_ring,
658 				   HAL_RXDMA_MONITOR_DST, 0, dp->mac_id,
659 				   DP_RXDMA_MONITOR_DST_RING_SIZE);
660 	if (ret) {
661 		ath11k_warn(ar->ab,
662 			    "failed to setup HAL_RXDMA_MONITOR_DST\n");
663 		return ret;
664 	}
665 
666 	ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_mon_desc_ring,
667 				   HAL_RXDMA_MONITOR_DESC, 0, dp->mac_id,
668 				   DP_RXDMA_MONITOR_DESC_RING_SIZE);
669 	if (ret) {
670 		ath11k_warn(ar->ab,
671 			    "failed to setup HAL_RXDMA_MONITOR_DESC\n");
672 		return ret;
673 	}
674 
675 	return 0;
676 }
677 
678 void ath11k_dp_reo_cmd_list_cleanup(struct ath11k_base *ab)
679 {
680 	struct ath11k_dp *dp = &ab->dp;
681 	struct dp_reo_cmd *cmd, *tmp;
682 	struct dp_reo_cache_flush_elem *cmd_cache, *tmp_cache;
683 
684 	spin_lock_bh(&dp->reo_cmd_lock);
685 	list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) {
686 		list_del(&cmd->list);
687 		dma_unmap_single(ab->dev, cmd->data.paddr,
688 				 cmd->data.size, DMA_BIDIRECTIONAL);
689 		kfree(cmd->data.vaddr);
690 		kfree(cmd);
691 	}
692 
693 	list_for_each_entry_safe(cmd_cache, tmp_cache,
694 				 &dp->reo_cmd_cache_flush_list, list) {
695 		list_del(&cmd_cache->list);
696 		dp->reo_cmd_cache_flush_count--;
697 		dma_unmap_single(ab->dev, cmd_cache->data.paddr,
698 				 cmd_cache->data.size, DMA_BIDIRECTIONAL);
699 		kfree(cmd_cache->data.vaddr);
700 		kfree(cmd_cache);
701 	}
702 	spin_unlock_bh(&dp->reo_cmd_lock);
703 }
704 
705 static void ath11k_dp_reo_cmd_free(struct ath11k_dp *dp, void *ctx,
706 				   enum hal_reo_cmd_status status)
707 {
708 	struct dp_rx_tid *rx_tid = ctx;
709 
710 	if (status != HAL_REO_CMD_SUCCESS)
711 		ath11k_warn(dp->ab, "failed to flush rx tid hw desc, tid %d status %d\n",
712 			    rx_tid->tid, status);
713 
714 	dma_unmap_single(dp->ab->dev, rx_tid->paddr, rx_tid->size,
715 			 DMA_BIDIRECTIONAL);
716 	kfree(rx_tid->vaddr);
717 }
718 
719 static void ath11k_dp_reo_cache_flush(struct ath11k_base *ab,
720 				      struct dp_rx_tid *rx_tid)
721 {
722 	struct ath11k_hal_reo_cmd cmd = {0};
723 	unsigned long tot_desc_sz, desc_sz;
724 	int ret;
725 
726 	tot_desc_sz = rx_tid->size;
727 	desc_sz = ath11k_hal_reo_qdesc_size(0, HAL_DESC_REO_NON_QOS_TID);
728 
729 	while (tot_desc_sz > desc_sz) {
730 		tot_desc_sz -= desc_sz;
731 		cmd.addr_lo = lower_32_bits(rx_tid->paddr + tot_desc_sz);
732 		cmd.addr_hi = upper_32_bits(rx_tid->paddr);
733 		ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
734 						HAL_REO_CMD_FLUSH_CACHE, &cmd,
735 						NULL);
736 		if (ret)
737 			ath11k_warn(ab,
738 				    "failed to send HAL_REO_CMD_FLUSH_CACHE, tid %d (%d)\n",
739 				    rx_tid->tid, ret);
740 	}
741 
742 	memset(&cmd, 0, sizeof(cmd));
743 	cmd.addr_lo = lower_32_bits(rx_tid->paddr);
744 	cmd.addr_hi = upper_32_bits(rx_tid->paddr);
745 	cmd.flag |= HAL_REO_CMD_FLG_NEED_STATUS;
746 	ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
747 					HAL_REO_CMD_FLUSH_CACHE,
748 					&cmd, ath11k_dp_reo_cmd_free);
749 	if (ret) {
750 		ath11k_err(ab, "failed to send HAL_REO_CMD_FLUSH_CACHE cmd, tid %d (%d)\n",
751 			   rx_tid->tid, ret);
752 		dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size,
753 				 DMA_BIDIRECTIONAL);
754 		kfree(rx_tid->vaddr);
755 	}
756 }
757 
758 static void ath11k_dp_rx_tid_del_func(struct ath11k_dp *dp, void *ctx,
759 				      enum hal_reo_cmd_status status)
760 {
761 	struct ath11k_base *ab = dp->ab;
762 	struct dp_rx_tid *rx_tid = ctx;
763 	struct dp_reo_cache_flush_elem *elem, *tmp;
764 
765 	if (status == HAL_REO_CMD_DRAIN) {
766 		goto free_desc;
767 	} else if (status != HAL_REO_CMD_SUCCESS) {
768 		/* Shouldn't happen! Cleanup in case of other failure? */
769 		ath11k_warn(ab, "failed to delete rx tid %d hw descriptor %d\n",
770 			    rx_tid->tid, status);
771 		return;
772 	}
773 
774 	elem = kzalloc(sizeof(*elem), GFP_ATOMIC);
775 	if (!elem)
776 		goto free_desc;
777 
778 	elem->ts = jiffies;
779 	memcpy(&elem->data, rx_tid, sizeof(*rx_tid));
780 
781 	spin_lock_bh(&dp->reo_cmd_lock);
782 	list_add_tail(&elem->list, &dp->reo_cmd_cache_flush_list);
783 	dp->reo_cmd_cache_flush_count++;
784 
785 	/* Flush and invalidate aged REO desc from HW cache */
786 	list_for_each_entry_safe(elem, tmp, &dp->reo_cmd_cache_flush_list,
787 				 list) {
788 		if (dp->reo_cmd_cache_flush_count > DP_REO_DESC_FREE_THRESHOLD ||
789 		    time_after(jiffies, elem->ts +
790 			       msecs_to_jiffies(DP_REO_DESC_FREE_TIMEOUT_MS))) {
791 			list_del(&elem->list);
792 			dp->reo_cmd_cache_flush_count--;
793 			spin_unlock_bh(&dp->reo_cmd_lock);
794 
795 			ath11k_dp_reo_cache_flush(ab, &elem->data);
796 			kfree(elem);
797 			spin_lock_bh(&dp->reo_cmd_lock);
798 		}
799 	}
800 	spin_unlock_bh(&dp->reo_cmd_lock);
801 
802 	return;
803 free_desc:
804 	dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size,
805 			 DMA_BIDIRECTIONAL);
806 	kfree(rx_tid->vaddr);
807 }
808 
809 void ath11k_peer_rx_tid_delete(struct ath11k *ar,
810 			       struct ath11k_peer *peer, u8 tid)
811 {
812 	struct ath11k_hal_reo_cmd cmd = {0};
813 	struct dp_rx_tid *rx_tid = &peer->rx_tid[tid];
814 	int ret;
815 
816 	if (!rx_tid->active)
817 		return;
818 
819 	cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
820 	cmd.addr_lo = lower_32_bits(rx_tid->paddr);
821 	cmd.addr_hi = upper_32_bits(rx_tid->paddr);
822 	cmd.upd0 |= HAL_REO_CMD_UPD0_VLD;
823 	ret = ath11k_dp_tx_send_reo_cmd(ar->ab, rx_tid,
824 					HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd,
825 					ath11k_dp_rx_tid_del_func);
826 	if (ret) {
827 		ath11k_err(ar->ab, "failed to send HAL_REO_CMD_UPDATE_RX_QUEUE cmd, tid %d (%d)\n",
828 			   tid, ret);
829 		dma_unmap_single(ar->ab->dev, rx_tid->paddr, rx_tid->size,
830 				 DMA_BIDIRECTIONAL);
831 		kfree(rx_tid->vaddr);
832 	}
833 
834 	rx_tid->active = false;
835 }
836 
837 static int ath11k_dp_rx_link_desc_return(struct ath11k_base *ab,
838 					 u32 *link_desc,
839 					 enum hal_wbm_rel_bm_act action)
840 {
841 	struct ath11k_dp *dp = &ab->dp;
842 	struct hal_srng *srng;
843 	u32 *desc;
844 	int ret = 0;
845 
846 	srng = &ab->hal.srng_list[dp->wbm_desc_rel_ring.ring_id];
847 
848 	spin_lock_bh(&srng->lock);
849 
850 	ath11k_hal_srng_access_begin(ab, srng);
851 
852 	desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
853 	if (!desc) {
854 		ret = -ENOBUFS;
855 		goto exit;
856 	}
857 
858 	ath11k_hal_rx_msdu_link_desc_set(ab, (void *)desc, (void *)link_desc,
859 					 action);
860 
861 exit:
862 	ath11k_hal_srng_access_end(ab, srng);
863 
864 	spin_unlock_bh(&srng->lock);
865 
866 	return ret;
867 }
868 
869 static void ath11k_dp_rx_frags_cleanup(struct dp_rx_tid *rx_tid, bool rel_link_desc)
870 {
871 	struct ath11k_base *ab = rx_tid->ab;
872 
873 	lockdep_assert_held(&ab->base_lock);
874 
875 	if (rx_tid->dst_ring_desc) {
876 		if (rel_link_desc)
877 			ath11k_dp_rx_link_desc_return(ab, (u32 *)rx_tid->dst_ring_desc,
878 						      HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
879 		kfree(rx_tid->dst_ring_desc);
880 		rx_tid->dst_ring_desc = NULL;
881 	}
882 
883 	rx_tid->cur_sn = 0;
884 	rx_tid->last_frag_no = 0;
885 	rx_tid->rx_frag_bitmap = 0;
886 	__skb_queue_purge(&rx_tid->rx_frags);
887 }
888 
889 void ath11k_peer_frags_flush(struct ath11k *ar, struct ath11k_peer *peer)
890 {
891 	struct dp_rx_tid *rx_tid;
892 	int i;
893 
894 	lockdep_assert_held(&ar->ab->base_lock);
895 
896 	for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
897 		rx_tid = &peer->rx_tid[i];
898 
899 		spin_unlock_bh(&ar->ab->base_lock);
900 		del_timer_sync(&rx_tid->frag_timer);
901 		spin_lock_bh(&ar->ab->base_lock);
902 
903 		ath11k_dp_rx_frags_cleanup(rx_tid, true);
904 	}
905 }
906 
907 void ath11k_peer_rx_tid_cleanup(struct ath11k *ar, struct ath11k_peer *peer)
908 {
909 	struct dp_rx_tid *rx_tid;
910 	int i;
911 
912 	lockdep_assert_held(&ar->ab->base_lock);
913 
914 	for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
915 		rx_tid = &peer->rx_tid[i];
916 
917 		ath11k_peer_rx_tid_delete(ar, peer, i);
918 		ath11k_dp_rx_frags_cleanup(rx_tid, true);
919 
920 		spin_unlock_bh(&ar->ab->base_lock);
921 		del_timer_sync(&rx_tid->frag_timer);
922 		spin_lock_bh(&ar->ab->base_lock);
923 	}
924 }
925 
926 static int ath11k_peer_rx_tid_reo_update(struct ath11k *ar,
927 					 struct ath11k_peer *peer,
928 					 struct dp_rx_tid *rx_tid,
929 					 u32 ba_win_sz, u16 ssn,
930 					 bool update_ssn)
931 {
932 	struct ath11k_hal_reo_cmd cmd = {0};
933 	int ret;
934 
935 	cmd.addr_lo = lower_32_bits(rx_tid->paddr);
936 	cmd.addr_hi = upper_32_bits(rx_tid->paddr);
937 	cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
938 	cmd.upd0 = HAL_REO_CMD_UPD0_BA_WINDOW_SIZE;
939 	cmd.ba_window_size = ba_win_sz;
940 
941 	if (update_ssn) {
942 		cmd.upd0 |= HAL_REO_CMD_UPD0_SSN;
943 		cmd.upd2 = FIELD_PREP(HAL_REO_CMD_UPD2_SSN, ssn);
944 	}
945 
946 	ret = ath11k_dp_tx_send_reo_cmd(ar->ab, rx_tid,
947 					HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd,
948 					NULL);
949 	if (ret) {
950 		ath11k_warn(ar->ab, "failed to update rx tid queue, tid %d (%d)\n",
951 			    rx_tid->tid, ret);
952 		return ret;
953 	}
954 
955 	rx_tid->ba_win_sz = ba_win_sz;
956 
957 	return 0;
958 }
959 
960 static void ath11k_dp_rx_tid_mem_free(struct ath11k_base *ab,
961 				      const u8 *peer_mac, int vdev_id, u8 tid)
962 {
963 	struct ath11k_peer *peer;
964 	struct dp_rx_tid *rx_tid;
965 
966 	spin_lock_bh(&ab->base_lock);
967 
968 	peer = ath11k_peer_find(ab, vdev_id, peer_mac);
969 	if (!peer) {
970 		ath11k_warn(ab, "failed to find the peer to free up rx tid mem\n");
971 		goto unlock_exit;
972 	}
973 
974 	rx_tid = &peer->rx_tid[tid];
975 	if (!rx_tid->active)
976 		goto unlock_exit;
977 
978 	dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size,
979 			 DMA_BIDIRECTIONAL);
980 	kfree(rx_tid->vaddr);
981 
982 	rx_tid->active = false;
983 
984 unlock_exit:
985 	spin_unlock_bh(&ab->base_lock);
986 }
987 
988 int ath11k_peer_rx_tid_setup(struct ath11k *ar, const u8 *peer_mac, int vdev_id,
989 			     u8 tid, u32 ba_win_sz, u16 ssn,
990 			     enum hal_pn_type pn_type)
991 {
992 	struct ath11k_base *ab = ar->ab;
993 	struct ath11k_peer *peer;
994 	struct dp_rx_tid *rx_tid;
995 	u32 hw_desc_sz;
996 	u32 *addr_aligned;
997 	void *vaddr;
998 	dma_addr_t paddr;
999 	int ret;
1000 
1001 	spin_lock_bh(&ab->base_lock);
1002 
1003 	peer = ath11k_peer_find(ab, vdev_id, peer_mac);
1004 	if (!peer) {
1005 		ath11k_warn(ab, "failed to find the peer to set up rx tid\n");
1006 		spin_unlock_bh(&ab->base_lock);
1007 		return -ENOENT;
1008 	}
1009 
1010 	rx_tid = &peer->rx_tid[tid];
1011 	/* Update the tid queue if it is already setup */
1012 	if (rx_tid->active) {
1013 		paddr = rx_tid->paddr;
1014 		ret = ath11k_peer_rx_tid_reo_update(ar, peer, rx_tid,
1015 						    ba_win_sz, ssn, true);
1016 		spin_unlock_bh(&ab->base_lock);
1017 		if (ret) {
1018 			ath11k_warn(ab, "failed to update reo for rx tid %d\n", tid);
1019 			return ret;
1020 		}
1021 
1022 		ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id,
1023 							     peer_mac, paddr,
1024 							     tid, 1, ba_win_sz);
1025 		if (ret)
1026 			ath11k_warn(ab, "failed to send wmi command to update rx reorder queue, tid :%d (%d)\n",
1027 				    tid, ret);
1028 		return ret;
1029 	}
1030 
1031 	rx_tid->tid = tid;
1032 
1033 	rx_tid->ba_win_sz = ba_win_sz;
1034 
1035 	/* TODO: Optimize the memory allocation for qos tid based on
1036 	 * the actual BA window size in REO tid update path.
1037 	 */
1038 	if (tid == HAL_DESC_REO_NON_QOS_TID)
1039 		hw_desc_sz = ath11k_hal_reo_qdesc_size(ba_win_sz, tid);
1040 	else
1041 		hw_desc_sz = ath11k_hal_reo_qdesc_size(DP_BA_WIN_SZ_MAX, tid);
1042 
1043 	vaddr = kzalloc(hw_desc_sz + HAL_LINK_DESC_ALIGN - 1, GFP_ATOMIC);
1044 	if (!vaddr) {
1045 		spin_unlock_bh(&ab->base_lock);
1046 		return -ENOMEM;
1047 	}
1048 
1049 	addr_aligned = PTR_ALIGN(vaddr, HAL_LINK_DESC_ALIGN);
1050 
1051 	ath11k_hal_reo_qdesc_setup(addr_aligned, tid, ba_win_sz,
1052 				   ssn, pn_type);
1053 
1054 	paddr = dma_map_single(ab->dev, addr_aligned, hw_desc_sz,
1055 			       DMA_BIDIRECTIONAL);
1056 
1057 	ret = dma_mapping_error(ab->dev, paddr);
1058 	if (ret) {
1059 		spin_unlock_bh(&ab->base_lock);
1060 		goto err_mem_free;
1061 	}
1062 
1063 	rx_tid->vaddr = vaddr;
1064 	rx_tid->paddr = paddr;
1065 	rx_tid->size = hw_desc_sz;
1066 	rx_tid->active = true;
1067 
1068 	spin_unlock_bh(&ab->base_lock);
1069 
1070 	ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, peer_mac,
1071 						     paddr, tid, 1, ba_win_sz);
1072 	if (ret) {
1073 		ath11k_warn(ar->ab, "failed to setup rx reorder queue, tid :%d (%d)\n",
1074 			    tid, ret);
1075 		ath11k_dp_rx_tid_mem_free(ab, peer_mac, vdev_id, tid);
1076 	}
1077 
1078 	return ret;
1079 
1080 err_mem_free:
1081 	kfree(vaddr);
1082 
1083 	return ret;
1084 }
1085 
1086 int ath11k_dp_rx_ampdu_start(struct ath11k *ar,
1087 			     struct ieee80211_ampdu_params *params)
1088 {
1089 	struct ath11k_base *ab = ar->ab;
1090 	struct ath11k_sta *arsta = (void *)params->sta->drv_priv;
1091 	int vdev_id = arsta->arvif->vdev_id;
1092 	int ret;
1093 
1094 	ret = ath11k_peer_rx_tid_setup(ar, params->sta->addr, vdev_id,
1095 				       params->tid, params->buf_size,
1096 				       params->ssn, arsta->pn_type);
1097 	if (ret)
1098 		ath11k_warn(ab, "failed to setup rx tid %d\n", ret);
1099 
1100 	return ret;
1101 }
1102 
1103 int ath11k_dp_rx_ampdu_stop(struct ath11k *ar,
1104 			    struct ieee80211_ampdu_params *params)
1105 {
1106 	struct ath11k_base *ab = ar->ab;
1107 	struct ath11k_peer *peer;
1108 	struct ath11k_sta *arsta = (void *)params->sta->drv_priv;
1109 	int vdev_id = arsta->arvif->vdev_id;
1110 	dma_addr_t paddr;
1111 	bool active;
1112 	int ret;
1113 
1114 	spin_lock_bh(&ab->base_lock);
1115 
1116 	peer = ath11k_peer_find(ab, vdev_id, params->sta->addr);
1117 	if (!peer) {
1118 		ath11k_warn(ab, "failed to find the peer to stop rx aggregation\n");
1119 		spin_unlock_bh(&ab->base_lock);
1120 		return -ENOENT;
1121 	}
1122 
1123 	paddr = peer->rx_tid[params->tid].paddr;
1124 	active = peer->rx_tid[params->tid].active;
1125 
1126 	if (!active) {
1127 		spin_unlock_bh(&ab->base_lock);
1128 		return 0;
1129 	}
1130 
1131 	ret = ath11k_peer_rx_tid_reo_update(ar, peer, peer->rx_tid, 1, 0, false);
1132 	spin_unlock_bh(&ab->base_lock);
1133 	if (ret) {
1134 		ath11k_warn(ab, "failed to update reo for rx tid %d: %d\n",
1135 			    params->tid, ret);
1136 		return ret;
1137 	}
1138 
1139 	ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id,
1140 						     params->sta->addr, paddr,
1141 						     params->tid, 1, 1);
1142 	if (ret)
1143 		ath11k_warn(ab, "failed to send wmi to delete rx tid %d\n",
1144 			    ret);
1145 
1146 	return ret;
1147 }
1148 
1149 int ath11k_dp_peer_rx_pn_replay_config(struct ath11k_vif *arvif,
1150 				       const u8 *peer_addr,
1151 				       enum set_key_cmd key_cmd,
1152 				       struct ieee80211_key_conf *key)
1153 {
1154 	struct ath11k *ar = arvif->ar;
1155 	struct ath11k_base *ab = ar->ab;
1156 	struct ath11k_hal_reo_cmd cmd = {0};
1157 	struct ath11k_peer *peer;
1158 	struct dp_rx_tid *rx_tid;
1159 	u8 tid;
1160 	int ret = 0;
1161 
1162 	/* NOTE: Enable PN/TSC replay check offload only for unicast frames.
1163 	 * We use mac80211 PN/TSC replay check functionality for bcast/mcast
1164 	 * for now.
1165 	 */
1166 	if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
1167 		return 0;
1168 
1169 	cmd.flag |= HAL_REO_CMD_FLG_NEED_STATUS;
1170 	cmd.upd0 |= HAL_REO_CMD_UPD0_PN |
1171 		    HAL_REO_CMD_UPD0_PN_SIZE |
1172 		    HAL_REO_CMD_UPD0_PN_VALID |
1173 		    HAL_REO_CMD_UPD0_PN_CHECK |
1174 		    HAL_REO_CMD_UPD0_SVLD;
1175 
1176 	switch (key->cipher) {
1177 	case WLAN_CIPHER_SUITE_TKIP:
1178 	case WLAN_CIPHER_SUITE_CCMP:
1179 	case WLAN_CIPHER_SUITE_CCMP_256:
1180 	case WLAN_CIPHER_SUITE_GCMP:
1181 	case WLAN_CIPHER_SUITE_GCMP_256:
1182 		if (key_cmd == SET_KEY) {
1183 			cmd.upd1 |= HAL_REO_CMD_UPD1_PN_CHECK;
1184 			cmd.pn_size = 48;
1185 		}
1186 		break;
1187 	default:
1188 		break;
1189 	}
1190 
1191 	spin_lock_bh(&ab->base_lock);
1192 
1193 	peer = ath11k_peer_find(ab, arvif->vdev_id, peer_addr);
1194 	if (!peer) {
1195 		ath11k_warn(ab, "failed to find the peer to configure pn replay detection\n");
1196 		spin_unlock_bh(&ab->base_lock);
1197 		return -ENOENT;
1198 	}
1199 
1200 	for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) {
1201 		rx_tid = &peer->rx_tid[tid];
1202 		if (!rx_tid->active)
1203 			continue;
1204 		cmd.addr_lo = lower_32_bits(rx_tid->paddr);
1205 		cmd.addr_hi = upper_32_bits(rx_tid->paddr);
1206 		ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
1207 						HAL_REO_CMD_UPDATE_RX_QUEUE,
1208 						&cmd, NULL);
1209 		if (ret) {
1210 			ath11k_warn(ab, "failed to configure rx tid %d queue for pn replay detection %d\n",
1211 				    tid, ret);
1212 			break;
1213 		}
1214 	}
1215 
1216 	spin_unlock_bh(&ab->base_lock);
1217 
1218 	return ret;
1219 }
1220 
1221 static inline int ath11k_get_ppdu_user_index(struct htt_ppdu_stats *ppdu_stats,
1222 					     u16 peer_id)
1223 {
1224 	int i;
1225 
1226 	for (i = 0; i < HTT_PPDU_STATS_MAX_USERS - 1; i++) {
1227 		if (ppdu_stats->user_stats[i].is_valid_peer_id) {
1228 			if (peer_id == ppdu_stats->user_stats[i].peer_id)
1229 				return i;
1230 		} else {
1231 			return i;
1232 		}
1233 	}
1234 
1235 	return -EINVAL;
1236 }
1237 
1238 static int ath11k_htt_tlv_ppdu_stats_parse(struct ath11k_base *ab,
1239 					   u16 tag, u16 len, const void *ptr,
1240 					   void *data)
1241 {
1242 	struct htt_ppdu_stats_info *ppdu_info;
1243 	struct htt_ppdu_user_stats *user_stats;
1244 	int cur_user;
1245 	u16 peer_id;
1246 
1247 	ppdu_info = (struct htt_ppdu_stats_info *)data;
1248 
1249 	switch (tag) {
1250 	case HTT_PPDU_STATS_TAG_COMMON:
1251 		if (len < sizeof(struct htt_ppdu_stats_common)) {
1252 			ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1253 				    len, tag);
1254 			return -EINVAL;
1255 		}
1256 		memcpy((void *)&ppdu_info->ppdu_stats.common, ptr,
1257 		       sizeof(struct htt_ppdu_stats_common));
1258 		break;
1259 	case HTT_PPDU_STATS_TAG_USR_RATE:
1260 		if (len < sizeof(struct htt_ppdu_stats_user_rate)) {
1261 			ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1262 				    len, tag);
1263 			return -EINVAL;
1264 		}
1265 
1266 		peer_id = ((struct htt_ppdu_stats_user_rate *)ptr)->sw_peer_id;
1267 		cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1268 						      peer_id);
1269 		if (cur_user < 0)
1270 			return -EINVAL;
1271 		user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1272 		user_stats->peer_id = peer_id;
1273 		user_stats->is_valid_peer_id = true;
1274 		memcpy((void *)&user_stats->rate, ptr,
1275 		       sizeof(struct htt_ppdu_stats_user_rate));
1276 		user_stats->tlv_flags |= BIT(tag);
1277 		break;
1278 	case HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON:
1279 		if (len < sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)) {
1280 			ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1281 				    len, tag);
1282 			return -EINVAL;
1283 		}
1284 
1285 		peer_id = ((struct htt_ppdu_stats_usr_cmpltn_cmn *)ptr)->sw_peer_id;
1286 		cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1287 						      peer_id);
1288 		if (cur_user < 0)
1289 			return -EINVAL;
1290 		user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1291 		user_stats->peer_id = peer_id;
1292 		user_stats->is_valid_peer_id = true;
1293 		memcpy((void *)&user_stats->cmpltn_cmn, ptr,
1294 		       sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn));
1295 		user_stats->tlv_flags |= BIT(tag);
1296 		break;
1297 	case HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS:
1298 		if (len <
1299 		    sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)) {
1300 			ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1301 				    len, tag);
1302 			return -EINVAL;
1303 		}
1304 
1305 		peer_id =
1306 		((struct htt_ppdu_stats_usr_cmpltn_ack_ba_status *)ptr)->sw_peer_id;
1307 		cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1308 						      peer_id);
1309 		if (cur_user < 0)
1310 			return -EINVAL;
1311 		user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1312 		user_stats->peer_id = peer_id;
1313 		user_stats->is_valid_peer_id = true;
1314 		memcpy((void *)&user_stats->ack_ba, ptr,
1315 		       sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status));
1316 		user_stats->tlv_flags |= BIT(tag);
1317 		break;
1318 	}
1319 	return 0;
1320 }
1321 
1322 int ath11k_dp_htt_tlv_iter(struct ath11k_base *ab, const void *ptr, size_t len,
1323 			   int (*iter)(struct ath11k_base *ar, u16 tag, u16 len,
1324 				       const void *ptr, void *data),
1325 			   void *data)
1326 {
1327 	const struct htt_tlv *tlv;
1328 	const void *begin = ptr;
1329 	u16 tlv_tag, tlv_len;
1330 	int ret = -EINVAL;
1331 
1332 	while (len > 0) {
1333 		if (len < sizeof(*tlv)) {
1334 			ath11k_err(ab, "htt tlv parse failure at byte %zd (%zu bytes left, %zu expected)\n",
1335 				   ptr - begin, len, sizeof(*tlv));
1336 			return -EINVAL;
1337 		}
1338 		tlv = (struct htt_tlv *)ptr;
1339 		tlv_tag = FIELD_GET(HTT_TLV_TAG, tlv->header);
1340 		tlv_len = FIELD_GET(HTT_TLV_LEN, tlv->header);
1341 		ptr += sizeof(*tlv);
1342 		len -= sizeof(*tlv);
1343 
1344 		if (tlv_len > len) {
1345 			ath11k_err(ab, "htt tlv parse failure of tag %u at byte %zd (%zu bytes left, %u expected)\n",
1346 				   tlv_tag, ptr - begin, len, tlv_len);
1347 			return -EINVAL;
1348 		}
1349 		ret = iter(ab, tlv_tag, tlv_len, ptr, data);
1350 		if (ret == -ENOMEM)
1351 			return ret;
1352 
1353 		ptr += tlv_len;
1354 		len -= tlv_len;
1355 	}
1356 	return 0;
1357 }
1358 
1359 static inline u32 ath11k_he_gi_to_nl80211_he_gi(u8 sgi)
1360 {
1361 	u32 ret = 0;
1362 
1363 	switch (sgi) {
1364 	case RX_MSDU_START_SGI_0_8_US:
1365 		ret = NL80211_RATE_INFO_HE_GI_0_8;
1366 		break;
1367 	case RX_MSDU_START_SGI_1_6_US:
1368 		ret = NL80211_RATE_INFO_HE_GI_1_6;
1369 		break;
1370 	case RX_MSDU_START_SGI_3_2_US:
1371 		ret = NL80211_RATE_INFO_HE_GI_3_2;
1372 		break;
1373 	}
1374 
1375 	return ret;
1376 }
1377 
1378 static void
1379 ath11k_update_per_peer_tx_stats(struct ath11k *ar,
1380 				struct htt_ppdu_stats *ppdu_stats, u8 user)
1381 {
1382 	struct ath11k_base *ab = ar->ab;
1383 	struct ath11k_peer *peer;
1384 	struct ieee80211_sta *sta;
1385 	struct ath11k_sta *arsta;
1386 	struct htt_ppdu_stats_user_rate *user_rate;
1387 	struct ath11k_per_peer_tx_stats *peer_stats = &ar->peer_tx_stats;
1388 	struct htt_ppdu_user_stats *usr_stats = &ppdu_stats->user_stats[user];
1389 	struct htt_ppdu_stats_common *common = &ppdu_stats->common;
1390 	int ret;
1391 	u8 flags, mcs, nss, bw, sgi, dcm, rate_idx = 0;
1392 	u32 succ_bytes = 0;
1393 	u16 rate = 0, succ_pkts = 0;
1394 	u32 tx_duration = 0;
1395 	u8 tid = HTT_PPDU_STATS_NON_QOS_TID;
1396 	bool is_ampdu = false;
1397 
1398 	if (!usr_stats)
1399 		return;
1400 
1401 	if (!(usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_RATE)))
1402 		return;
1403 
1404 	if (usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON))
1405 		is_ampdu =
1406 			HTT_USR_CMPLTN_IS_AMPDU(usr_stats->cmpltn_cmn.flags);
1407 
1408 	if (usr_stats->tlv_flags &
1409 	    BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS)) {
1410 		succ_bytes = usr_stats->ack_ba.success_bytes;
1411 		succ_pkts = FIELD_GET(HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M,
1412 				      usr_stats->ack_ba.info);
1413 		tid = FIELD_GET(HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM,
1414 				usr_stats->ack_ba.info);
1415 	}
1416 
1417 	if (common->fes_duration_us)
1418 		tx_duration = common->fes_duration_us;
1419 
1420 	user_rate = &usr_stats->rate;
1421 	flags = HTT_USR_RATE_PREAMBLE(user_rate->rate_flags);
1422 	bw = HTT_USR_RATE_BW(user_rate->rate_flags) - 2;
1423 	nss = HTT_USR_RATE_NSS(user_rate->rate_flags) + 1;
1424 	mcs = HTT_USR_RATE_MCS(user_rate->rate_flags);
1425 	sgi = HTT_USR_RATE_GI(user_rate->rate_flags);
1426 	dcm = HTT_USR_RATE_DCM(user_rate->rate_flags);
1427 
1428 	/* Note: If host configured fixed rates and in some other special
1429 	 * cases, the broadcast/management frames are sent in different rates.
1430 	 * Firmware rate's control to be skipped for this?
1431 	 */
1432 
1433 	if (flags == WMI_RATE_PREAMBLE_HE && mcs > ATH11K_HE_MCS_MAX) {
1434 		ath11k_warn(ab, "Invalid HE mcs %d peer stats",  mcs);
1435 		return;
1436 	}
1437 
1438 	if (flags == WMI_RATE_PREAMBLE_VHT && mcs > ATH11K_VHT_MCS_MAX) {
1439 		ath11k_warn(ab, "Invalid VHT mcs %d peer stats",  mcs);
1440 		return;
1441 	}
1442 
1443 	if (flags == WMI_RATE_PREAMBLE_HT && (mcs > ATH11K_HT_MCS_MAX || nss < 1)) {
1444 		ath11k_warn(ab, "Invalid HT mcs %d nss %d peer stats",
1445 			    mcs, nss);
1446 		return;
1447 	}
1448 
1449 	if (flags == WMI_RATE_PREAMBLE_CCK || flags == WMI_RATE_PREAMBLE_OFDM) {
1450 		ret = ath11k_mac_hw_ratecode_to_legacy_rate(mcs,
1451 							    flags,
1452 							    &rate_idx,
1453 							    &rate);
1454 		if (ret < 0)
1455 			return;
1456 	}
1457 
1458 	rcu_read_lock();
1459 	spin_lock_bh(&ab->base_lock);
1460 	peer = ath11k_peer_find_by_id(ab, usr_stats->peer_id);
1461 
1462 	if (!peer || !peer->sta) {
1463 		spin_unlock_bh(&ab->base_lock);
1464 		rcu_read_unlock();
1465 		return;
1466 	}
1467 
1468 	sta = peer->sta;
1469 	arsta = (struct ath11k_sta *)sta->drv_priv;
1470 
1471 	memset(&arsta->txrate, 0, sizeof(arsta->txrate));
1472 
1473 	switch (flags) {
1474 	case WMI_RATE_PREAMBLE_OFDM:
1475 		arsta->txrate.legacy = rate;
1476 		break;
1477 	case WMI_RATE_PREAMBLE_CCK:
1478 		arsta->txrate.legacy = rate;
1479 		break;
1480 	case WMI_RATE_PREAMBLE_HT:
1481 		arsta->txrate.mcs = mcs + 8 * (nss - 1);
1482 		arsta->txrate.flags = RATE_INFO_FLAGS_MCS;
1483 		if (sgi)
1484 			arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
1485 		break;
1486 	case WMI_RATE_PREAMBLE_VHT:
1487 		arsta->txrate.mcs = mcs;
1488 		arsta->txrate.flags = RATE_INFO_FLAGS_VHT_MCS;
1489 		if (sgi)
1490 			arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
1491 		break;
1492 	case WMI_RATE_PREAMBLE_HE:
1493 		arsta->txrate.mcs = mcs;
1494 		arsta->txrate.flags = RATE_INFO_FLAGS_HE_MCS;
1495 		arsta->txrate.he_dcm = dcm;
1496 		arsta->txrate.he_gi = ath11k_he_gi_to_nl80211_he_gi(sgi);
1497 		arsta->txrate.he_ru_alloc = ath11k_he_ru_tones_to_nl80211_he_ru_alloc(
1498 						(user_rate->ru_end -
1499 						 user_rate->ru_start) + 1);
1500 		break;
1501 	}
1502 
1503 	arsta->txrate.nss = nss;
1504 	arsta->txrate.bw = ath11k_mac_bw_to_mac80211_bw(bw);
1505 	arsta->tx_duration += tx_duration;
1506 	memcpy(&arsta->last_txrate, &arsta->txrate, sizeof(struct rate_info));
1507 
1508 	/* PPDU stats reported for mgmt packet doesn't have valid tx bytes.
1509 	 * So skip peer stats update for mgmt packets.
1510 	 */
1511 	if (tid < HTT_PPDU_STATS_NON_QOS_TID) {
1512 		memset(peer_stats, 0, sizeof(*peer_stats));
1513 		peer_stats->succ_pkts = succ_pkts;
1514 		peer_stats->succ_bytes = succ_bytes;
1515 		peer_stats->is_ampdu = is_ampdu;
1516 		peer_stats->duration = tx_duration;
1517 		peer_stats->ba_fails =
1518 			HTT_USR_CMPLTN_LONG_RETRY(usr_stats->cmpltn_cmn.flags) +
1519 			HTT_USR_CMPLTN_SHORT_RETRY(usr_stats->cmpltn_cmn.flags);
1520 
1521 		if (ath11k_debugfs_is_extd_tx_stats_enabled(ar))
1522 			ath11k_debugfs_sta_add_tx_stats(arsta, peer_stats, rate_idx);
1523 	}
1524 
1525 	spin_unlock_bh(&ab->base_lock);
1526 	rcu_read_unlock();
1527 }
1528 
1529 static void ath11k_htt_update_ppdu_stats(struct ath11k *ar,
1530 					 struct htt_ppdu_stats *ppdu_stats)
1531 {
1532 	u8 user;
1533 
1534 	for (user = 0; user < HTT_PPDU_STATS_MAX_USERS - 1; user++)
1535 		ath11k_update_per_peer_tx_stats(ar, ppdu_stats, user);
1536 }
1537 
1538 static
1539 struct htt_ppdu_stats_info *ath11k_dp_htt_get_ppdu_desc(struct ath11k *ar,
1540 							u32 ppdu_id)
1541 {
1542 	struct htt_ppdu_stats_info *ppdu_info;
1543 
1544 	spin_lock_bh(&ar->data_lock);
1545 	if (!list_empty(&ar->ppdu_stats_info)) {
1546 		list_for_each_entry(ppdu_info, &ar->ppdu_stats_info, list) {
1547 			if (ppdu_info->ppdu_id == ppdu_id) {
1548 				spin_unlock_bh(&ar->data_lock);
1549 				return ppdu_info;
1550 			}
1551 		}
1552 
1553 		if (ar->ppdu_stat_list_depth > HTT_PPDU_DESC_MAX_DEPTH) {
1554 			ppdu_info = list_first_entry(&ar->ppdu_stats_info,
1555 						     typeof(*ppdu_info), list);
1556 			list_del(&ppdu_info->list);
1557 			ar->ppdu_stat_list_depth--;
1558 			ath11k_htt_update_ppdu_stats(ar, &ppdu_info->ppdu_stats);
1559 			kfree(ppdu_info);
1560 		}
1561 	}
1562 	spin_unlock_bh(&ar->data_lock);
1563 
1564 	ppdu_info = kzalloc(sizeof(*ppdu_info), GFP_ATOMIC);
1565 	if (!ppdu_info)
1566 		return NULL;
1567 
1568 	spin_lock_bh(&ar->data_lock);
1569 	list_add_tail(&ppdu_info->list, &ar->ppdu_stats_info);
1570 	ar->ppdu_stat_list_depth++;
1571 	spin_unlock_bh(&ar->data_lock);
1572 
1573 	return ppdu_info;
1574 }
1575 
1576 static int ath11k_htt_pull_ppdu_stats(struct ath11k_base *ab,
1577 				      struct sk_buff *skb)
1578 {
1579 	struct ath11k_htt_ppdu_stats_msg *msg;
1580 	struct htt_ppdu_stats_info *ppdu_info;
1581 	struct ath11k *ar;
1582 	int ret;
1583 	u8 pdev_id;
1584 	u32 ppdu_id, len;
1585 
1586 	msg = (struct ath11k_htt_ppdu_stats_msg *)skb->data;
1587 	len = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE, msg->info);
1588 	pdev_id = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PDEV_ID, msg->info);
1589 	ppdu_id = msg->ppdu_id;
1590 
1591 	rcu_read_lock();
1592 	ar = ath11k_mac_get_ar_by_pdev_id(ab, pdev_id);
1593 	if (!ar) {
1594 		ret = -EINVAL;
1595 		goto exit;
1596 	}
1597 
1598 	if (ath11k_debugfs_is_pktlog_lite_mode_enabled(ar))
1599 		trace_ath11k_htt_ppdu_stats(ar, skb->data, len);
1600 
1601 	ppdu_info = ath11k_dp_htt_get_ppdu_desc(ar, ppdu_id);
1602 	if (!ppdu_info) {
1603 		ret = -EINVAL;
1604 		goto exit;
1605 	}
1606 
1607 	ppdu_info->ppdu_id = ppdu_id;
1608 	ret = ath11k_dp_htt_tlv_iter(ab, msg->data, len,
1609 				     ath11k_htt_tlv_ppdu_stats_parse,
1610 				     (void *)ppdu_info);
1611 	if (ret) {
1612 		ath11k_warn(ab, "Failed to parse tlv %d\n", ret);
1613 		goto exit;
1614 	}
1615 
1616 exit:
1617 	rcu_read_unlock();
1618 
1619 	return ret;
1620 }
1621 
1622 static void ath11k_htt_pktlog(struct ath11k_base *ab, struct sk_buff *skb)
1623 {
1624 	struct htt_pktlog_msg *data = (struct htt_pktlog_msg *)skb->data;
1625 	struct ath_pktlog_hdr *hdr = (struct ath_pktlog_hdr *)data;
1626 	struct ath11k *ar;
1627 	u8 pdev_id;
1628 
1629 	pdev_id = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PDEV_ID, data->hdr);
1630 	ar = ath11k_mac_get_ar_by_pdev_id(ab, pdev_id);
1631 	if (!ar) {
1632 		ath11k_warn(ab, "invalid pdev id %d on htt pktlog\n", pdev_id);
1633 		return;
1634 	}
1635 
1636 	trace_ath11k_htt_pktlog(ar, data->payload, hdr->size,
1637 				ar->ab->pktlog_defs_checksum);
1638 }
1639 
1640 static void ath11k_htt_backpressure_event_handler(struct ath11k_base *ab,
1641 						  struct sk_buff *skb)
1642 {
1643 	u32 *data = (u32 *)skb->data;
1644 	u8 pdev_id, ring_type, ring_id, pdev_idx;
1645 	u16 hp, tp;
1646 	u32 backpressure_time;
1647 	struct ath11k_bp_stats *bp_stats;
1648 
1649 	pdev_id = FIELD_GET(HTT_BACKPRESSURE_EVENT_PDEV_ID_M, *data);
1650 	ring_type = FIELD_GET(HTT_BACKPRESSURE_EVENT_RING_TYPE_M, *data);
1651 	ring_id = FIELD_GET(HTT_BACKPRESSURE_EVENT_RING_ID_M, *data);
1652 	++data;
1653 
1654 	hp = FIELD_GET(HTT_BACKPRESSURE_EVENT_HP_M, *data);
1655 	tp = FIELD_GET(HTT_BACKPRESSURE_EVENT_TP_M, *data);
1656 	++data;
1657 
1658 	backpressure_time = *data;
1659 
1660 	ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "htt backpressure event, pdev %d, ring type %d,ring id %d, hp %d tp %d, backpressure time %d\n",
1661 		   pdev_id, ring_type, ring_id, hp, tp, backpressure_time);
1662 
1663 	if (ring_type == HTT_BACKPRESSURE_UMAC_RING_TYPE) {
1664 		if (ring_id >= HTT_SW_UMAC_RING_IDX_MAX)
1665 			return;
1666 
1667 		bp_stats = &ab->soc_stats.bp_stats.umac_ring_bp_stats[ring_id];
1668 	} else if (ring_type == HTT_BACKPRESSURE_LMAC_RING_TYPE) {
1669 		pdev_idx = DP_HW2SW_MACID(pdev_id);
1670 
1671 		if (ring_id >= HTT_SW_LMAC_RING_IDX_MAX || pdev_idx >= MAX_RADIOS)
1672 			return;
1673 
1674 		bp_stats = &ab->soc_stats.bp_stats.lmac_ring_bp_stats[ring_id][pdev_idx];
1675 	} else {
1676 		ath11k_warn(ab, "unknown ring type received in htt bp event %d\n",
1677 			    ring_type);
1678 		return;
1679 	}
1680 
1681 	spin_lock_bh(&ab->base_lock);
1682 	bp_stats->hp = hp;
1683 	bp_stats->tp = tp;
1684 	bp_stats->count++;
1685 	bp_stats->jiffies = jiffies;
1686 	spin_unlock_bh(&ab->base_lock);
1687 }
1688 
1689 void ath11k_dp_htt_htc_t2h_msg_handler(struct ath11k_base *ab,
1690 				       struct sk_buff *skb)
1691 {
1692 	struct ath11k_dp *dp = &ab->dp;
1693 	struct htt_resp_msg *resp = (struct htt_resp_msg *)skb->data;
1694 	enum htt_t2h_msg_type type = FIELD_GET(HTT_T2H_MSG_TYPE, *(u32 *)resp);
1695 	u16 peer_id;
1696 	u8 vdev_id;
1697 	u8 mac_addr[ETH_ALEN];
1698 	u16 peer_mac_h16;
1699 	u16 ast_hash;
1700 	u16 hw_peer_id;
1701 
1702 	ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "dp_htt rx msg type :0x%0x\n", type);
1703 
1704 	switch (type) {
1705 	case HTT_T2H_MSG_TYPE_VERSION_CONF:
1706 		dp->htt_tgt_ver_major = FIELD_GET(HTT_T2H_VERSION_CONF_MAJOR,
1707 						  resp->version_msg.version);
1708 		dp->htt_tgt_ver_minor = FIELD_GET(HTT_T2H_VERSION_CONF_MINOR,
1709 						  resp->version_msg.version);
1710 		complete(&dp->htt_tgt_version_received);
1711 		break;
1712 	case HTT_T2H_MSG_TYPE_PEER_MAP:
1713 		vdev_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_VDEV_ID,
1714 				    resp->peer_map_ev.info);
1715 		peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_PEER_ID,
1716 				    resp->peer_map_ev.info);
1717 		peer_mac_h16 = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16,
1718 					 resp->peer_map_ev.info1);
1719 		ath11k_dp_get_mac_addr(resp->peer_map_ev.mac_addr_l32,
1720 				       peer_mac_h16, mac_addr);
1721 		ath11k_peer_map_event(ab, vdev_id, peer_id, mac_addr, 0, 0);
1722 		break;
1723 	case HTT_T2H_MSG_TYPE_PEER_MAP2:
1724 		vdev_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_VDEV_ID,
1725 				    resp->peer_map_ev.info);
1726 		peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_PEER_ID,
1727 				    resp->peer_map_ev.info);
1728 		peer_mac_h16 = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16,
1729 					 resp->peer_map_ev.info1);
1730 		ath11k_dp_get_mac_addr(resp->peer_map_ev.mac_addr_l32,
1731 				       peer_mac_h16, mac_addr);
1732 		ast_hash = FIELD_GET(HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL,
1733 				     resp->peer_map_ev.info2);
1734 		hw_peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID,
1735 				       resp->peer_map_ev.info1);
1736 		ath11k_peer_map_event(ab, vdev_id, peer_id, mac_addr, ast_hash,
1737 				      hw_peer_id);
1738 		break;
1739 	case HTT_T2H_MSG_TYPE_PEER_UNMAP:
1740 	case HTT_T2H_MSG_TYPE_PEER_UNMAP2:
1741 		peer_id = FIELD_GET(HTT_T2H_PEER_UNMAP_INFO_PEER_ID,
1742 				    resp->peer_unmap_ev.info);
1743 		ath11k_peer_unmap_event(ab, peer_id);
1744 		break;
1745 	case HTT_T2H_MSG_TYPE_PPDU_STATS_IND:
1746 		ath11k_htt_pull_ppdu_stats(ab, skb);
1747 		break;
1748 	case HTT_T2H_MSG_TYPE_EXT_STATS_CONF:
1749 		ath11k_debugfs_htt_ext_stats_handler(ab, skb);
1750 		break;
1751 	case HTT_T2H_MSG_TYPE_PKTLOG:
1752 		ath11k_htt_pktlog(ab, skb);
1753 		break;
1754 	case HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND:
1755 		ath11k_htt_backpressure_event_handler(ab, skb);
1756 		break;
1757 	default:
1758 		ath11k_warn(ab, "htt event %d not handled\n", type);
1759 		break;
1760 	}
1761 
1762 	dev_kfree_skb_any(skb);
1763 }
1764 
1765 static int ath11k_dp_rx_msdu_coalesce(struct ath11k *ar,
1766 				      struct sk_buff_head *msdu_list,
1767 				      struct sk_buff *first, struct sk_buff *last,
1768 				      u8 l3pad_bytes, int msdu_len)
1769 {
1770 	struct ath11k_base *ab = ar->ab;
1771 	struct sk_buff *skb;
1772 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(first);
1773 	int buf_first_hdr_len, buf_first_len;
1774 	struct hal_rx_desc *ldesc;
1775 	int space_extra, rem_len, buf_len;
1776 	u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
1777 
1778 	/* As the msdu is spread across multiple rx buffers,
1779 	 * find the offset to the start of msdu for computing
1780 	 * the length of the msdu in the first buffer.
1781 	 */
1782 	buf_first_hdr_len = hal_rx_desc_sz + l3pad_bytes;
1783 	buf_first_len = DP_RX_BUFFER_SIZE - buf_first_hdr_len;
1784 
1785 	if (WARN_ON_ONCE(msdu_len <= buf_first_len)) {
1786 		skb_put(first, buf_first_hdr_len + msdu_len);
1787 		skb_pull(first, buf_first_hdr_len);
1788 		return 0;
1789 	}
1790 
1791 	ldesc = (struct hal_rx_desc *)last->data;
1792 	rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ab, ldesc);
1793 	rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ab, ldesc);
1794 
1795 	/* MSDU spans over multiple buffers because the length of the MSDU
1796 	 * exceeds DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. So assume the data
1797 	 * in the first buf is of length DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE.
1798 	 */
1799 	skb_put(first, DP_RX_BUFFER_SIZE);
1800 	skb_pull(first, buf_first_hdr_len);
1801 
1802 	/* When an MSDU spread over multiple buffers attention, MSDU_END and
1803 	 * MPDU_END tlvs are valid only in the last buffer. Copy those tlvs.
1804 	 */
1805 	ath11k_dp_rx_desc_end_tlv_copy(ab, rxcb->rx_desc, ldesc);
1806 
1807 	space_extra = msdu_len - (buf_first_len + skb_tailroom(first));
1808 	if (space_extra > 0 &&
1809 	    (pskb_expand_head(first, 0, space_extra, GFP_ATOMIC) < 0)) {
1810 		/* Free up all buffers of the MSDU */
1811 		while ((skb = __skb_dequeue(msdu_list)) != NULL) {
1812 			rxcb = ATH11K_SKB_RXCB(skb);
1813 			if (!rxcb->is_continuation) {
1814 				dev_kfree_skb_any(skb);
1815 				break;
1816 			}
1817 			dev_kfree_skb_any(skb);
1818 		}
1819 		return -ENOMEM;
1820 	}
1821 
1822 	rem_len = msdu_len - buf_first_len;
1823 	while ((skb = __skb_dequeue(msdu_list)) != NULL && rem_len > 0) {
1824 		rxcb = ATH11K_SKB_RXCB(skb);
1825 		if (rxcb->is_continuation)
1826 			buf_len = DP_RX_BUFFER_SIZE - hal_rx_desc_sz;
1827 		else
1828 			buf_len = rem_len;
1829 
1830 		if (buf_len > (DP_RX_BUFFER_SIZE - hal_rx_desc_sz)) {
1831 			WARN_ON_ONCE(1);
1832 			dev_kfree_skb_any(skb);
1833 			return -EINVAL;
1834 		}
1835 
1836 		skb_put(skb, buf_len + hal_rx_desc_sz);
1837 		skb_pull(skb, hal_rx_desc_sz);
1838 		skb_copy_from_linear_data(skb, skb_put(first, buf_len),
1839 					  buf_len);
1840 		dev_kfree_skb_any(skb);
1841 
1842 		rem_len -= buf_len;
1843 		if (!rxcb->is_continuation)
1844 			break;
1845 	}
1846 
1847 	return 0;
1848 }
1849 
1850 static struct sk_buff *ath11k_dp_rx_get_msdu_last_buf(struct sk_buff_head *msdu_list,
1851 						      struct sk_buff *first)
1852 {
1853 	struct sk_buff *skb;
1854 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(first);
1855 
1856 	if (!rxcb->is_continuation)
1857 		return first;
1858 
1859 	skb_queue_walk(msdu_list, skb) {
1860 		rxcb = ATH11K_SKB_RXCB(skb);
1861 		if (!rxcb->is_continuation)
1862 			return skb;
1863 	}
1864 
1865 	return NULL;
1866 }
1867 
1868 static void ath11k_dp_rx_h_csum_offload(struct ath11k *ar, struct sk_buff *msdu)
1869 {
1870 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
1871 	struct rx_attention *rx_attention;
1872 	bool ip_csum_fail, l4_csum_fail;
1873 
1874 	rx_attention = ath11k_dp_rx_get_attention(ar->ab, rxcb->rx_desc);
1875 	ip_csum_fail = ath11k_dp_rx_h_attn_ip_cksum_fail(rx_attention);
1876 	l4_csum_fail = ath11k_dp_rx_h_attn_l4_cksum_fail(rx_attention);
1877 
1878 	msdu->ip_summed = (ip_csum_fail || l4_csum_fail) ?
1879 			  CHECKSUM_NONE : CHECKSUM_UNNECESSARY;
1880 }
1881 
1882 static int ath11k_dp_rx_crypto_mic_len(struct ath11k *ar,
1883 				       enum hal_encrypt_type enctype)
1884 {
1885 	switch (enctype) {
1886 	case HAL_ENCRYPT_TYPE_OPEN:
1887 	case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1888 	case HAL_ENCRYPT_TYPE_TKIP_MIC:
1889 		return 0;
1890 	case HAL_ENCRYPT_TYPE_CCMP_128:
1891 		return IEEE80211_CCMP_MIC_LEN;
1892 	case HAL_ENCRYPT_TYPE_CCMP_256:
1893 		return IEEE80211_CCMP_256_MIC_LEN;
1894 	case HAL_ENCRYPT_TYPE_GCMP_128:
1895 	case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1896 		return IEEE80211_GCMP_MIC_LEN;
1897 	case HAL_ENCRYPT_TYPE_WEP_40:
1898 	case HAL_ENCRYPT_TYPE_WEP_104:
1899 	case HAL_ENCRYPT_TYPE_WEP_128:
1900 	case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1901 	case HAL_ENCRYPT_TYPE_WAPI:
1902 		break;
1903 	}
1904 
1905 	ath11k_warn(ar->ab, "unsupported encryption type %d for mic len\n", enctype);
1906 	return 0;
1907 }
1908 
1909 static int ath11k_dp_rx_crypto_param_len(struct ath11k *ar,
1910 					 enum hal_encrypt_type enctype)
1911 {
1912 	switch (enctype) {
1913 	case HAL_ENCRYPT_TYPE_OPEN:
1914 		return 0;
1915 	case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1916 	case HAL_ENCRYPT_TYPE_TKIP_MIC:
1917 		return IEEE80211_TKIP_IV_LEN;
1918 	case HAL_ENCRYPT_TYPE_CCMP_128:
1919 		return IEEE80211_CCMP_HDR_LEN;
1920 	case HAL_ENCRYPT_TYPE_CCMP_256:
1921 		return IEEE80211_CCMP_256_HDR_LEN;
1922 	case HAL_ENCRYPT_TYPE_GCMP_128:
1923 	case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1924 		return IEEE80211_GCMP_HDR_LEN;
1925 	case HAL_ENCRYPT_TYPE_WEP_40:
1926 	case HAL_ENCRYPT_TYPE_WEP_104:
1927 	case HAL_ENCRYPT_TYPE_WEP_128:
1928 	case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1929 	case HAL_ENCRYPT_TYPE_WAPI:
1930 		break;
1931 	}
1932 
1933 	ath11k_warn(ar->ab, "unsupported encryption type %d\n", enctype);
1934 	return 0;
1935 }
1936 
1937 static int ath11k_dp_rx_crypto_icv_len(struct ath11k *ar,
1938 				       enum hal_encrypt_type enctype)
1939 {
1940 	switch (enctype) {
1941 	case HAL_ENCRYPT_TYPE_OPEN:
1942 	case HAL_ENCRYPT_TYPE_CCMP_128:
1943 	case HAL_ENCRYPT_TYPE_CCMP_256:
1944 	case HAL_ENCRYPT_TYPE_GCMP_128:
1945 	case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1946 		return 0;
1947 	case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1948 	case HAL_ENCRYPT_TYPE_TKIP_MIC:
1949 		return IEEE80211_TKIP_ICV_LEN;
1950 	case HAL_ENCRYPT_TYPE_WEP_40:
1951 	case HAL_ENCRYPT_TYPE_WEP_104:
1952 	case HAL_ENCRYPT_TYPE_WEP_128:
1953 	case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1954 	case HAL_ENCRYPT_TYPE_WAPI:
1955 		break;
1956 	}
1957 
1958 	ath11k_warn(ar->ab, "unsupported encryption type %d\n", enctype);
1959 	return 0;
1960 }
1961 
1962 static void ath11k_dp_rx_h_undecap_nwifi(struct ath11k *ar,
1963 					 struct sk_buff *msdu,
1964 					 u8 *first_hdr,
1965 					 enum hal_encrypt_type enctype,
1966 					 struct ieee80211_rx_status *status)
1967 {
1968 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
1969 	u8 decap_hdr[DP_MAX_NWIFI_HDR_LEN];
1970 	struct ieee80211_hdr *hdr;
1971 	size_t hdr_len;
1972 	u8 da[ETH_ALEN];
1973 	u8 sa[ETH_ALEN];
1974 	u16 qos_ctl = 0;
1975 	u8 *qos;
1976 
1977 	/* copy SA & DA and pull decapped header */
1978 	hdr = (struct ieee80211_hdr *)msdu->data;
1979 	hdr_len = ieee80211_hdrlen(hdr->frame_control);
1980 	ether_addr_copy(da, ieee80211_get_DA(hdr));
1981 	ether_addr_copy(sa, ieee80211_get_SA(hdr));
1982 	skb_pull(msdu, ieee80211_hdrlen(hdr->frame_control));
1983 
1984 	if (rxcb->is_first_msdu) {
1985 		/* original 802.11 header is valid for the first msdu
1986 		 * hence we can reuse the same header
1987 		 */
1988 		hdr = (struct ieee80211_hdr *)first_hdr;
1989 		hdr_len = ieee80211_hdrlen(hdr->frame_control);
1990 
1991 		/* Each A-MSDU subframe will be reported as a separate MSDU,
1992 		 * so strip the A-MSDU bit from QoS Ctl.
1993 		 */
1994 		if (ieee80211_is_data_qos(hdr->frame_control)) {
1995 			qos = ieee80211_get_qos_ctl(hdr);
1996 			qos[0] &= ~IEEE80211_QOS_CTL_A_MSDU_PRESENT;
1997 		}
1998 	} else {
1999 		/*  Rebuild qos header if this is a middle/last msdu */
2000 		hdr->frame_control |= __cpu_to_le16(IEEE80211_STYPE_QOS_DATA);
2001 
2002 		/* Reset the order bit as the HT_Control header is stripped */
2003 		hdr->frame_control &= ~(__cpu_to_le16(IEEE80211_FCTL_ORDER));
2004 
2005 		qos_ctl = rxcb->tid;
2006 
2007 		if (ath11k_dp_rx_h_msdu_start_mesh_ctl_present(ar->ab, rxcb->rx_desc))
2008 			qos_ctl |= IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT;
2009 
2010 		/* TODO Add other QoS ctl fields when required */
2011 
2012 		/* copy decap header before overwriting for reuse below */
2013 		memcpy(decap_hdr, (uint8_t *)hdr, hdr_len);
2014 	}
2015 
2016 	if (!(status->flag & RX_FLAG_IV_STRIPPED)) {
2017 		memcpy(skb_push(msdu,
2018 				ath11k_dp_rx_crypto_param_len(ar, enctype)),
2019 		       (void *)hdr + hdr_len,
2020 		       ath11k_dp_rx_crypto_param_len(ar, enctype));
2021 	}
2022 
2023 	if (!rxcb->is_first_msdu) {
2024 		memcpy(skb_push(msdu,
2025 				IEEE80211_QOS_CTL_LEN), &qos_ctl,
2026 				IEEE80211_QOS_CTL_LEN);
2027 		memcpy(skb_push(msdu, hdr_len), decap_hdr, hdr_len);
2028 		return;
2029 	}
2030 
2031 	memcpy(skb_push(msdu, hdr_len), hdr, hdr_len);
2032 
2033 	/* original 802.11 header has a different DA and in
2034 	 * case of 4addr it may also have different SA
2035 	 */
2036 	hdr = (struct ieee80211_hdr *)msdu->data;
2037 	ether_addr_copy(ieee80211_get_DA(hdr), da);
2038 	ether_addr_copy(ieee80211_get_SA(hdr), sa);
2039 }
2040 
2041 static void ath11k_dp_rx_h_undecap_raw(struct ath11k *ar, struct sk_buff *msdu,
2042 				       enum hal_encrypt_type enctype,
2043 				       struct ieee80211_rx_status *status,
2044 				       bool decrypted)
2045 {
2046 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2047 	struct ieee80211_hdr *hdr;
2048 	size_t hdr_len;
2049 	size_t crypto_len;
2050 
2051 	if (!rxcb->is_first_msdu ||
2052 	    !(rxcb->is_first_msdu && rxcb->is_last_msdu)) {
2053 		WARN_ON_ONCE(1);
2054 		return;
2055 	}
2056 
2057 	skb_trim(msdu, msdu->len - FCS_LEN);
2058 
2059 	if (!decrypted)
2060 		return;
2061 
2062 	hdr = (void *)msdu->data;
2063 
2064 	/* Tail */
2065 	if (status->flag & RX_FLAG_IV_STRIPPED) {
2066 		skb_trim(msdu, msdu->len -
2067 			 ath11k_dp_rx_crypto_mic_len(ar, enctype));
2068 
2069 		skb_trim(msdu, msdu->len -
2070 			 ath11k_dp_rx_crypto_icv_len(ar, enctype));
2071 	} else {
2072 		/* MIC */
2073 		if (status->flag & RX_FLAG_MIC_STRIPPED)
2074 			skb_trim(msdu, msdu->len -
2075 				 ath11k_dp_rx_crypto_mic_len(ar, enctype));
2076 
2077 		/* ICV */
2078 		if (status->flag & RX_FLAG_ICV_STRIPPED)
2079 			skb_trim(msdu, msdu->len -
2080 				 ath11k_dp_rx_crypto_icv_len(ar, enctype));
2081 	}
2082 
2083 	/* MMIC */
2084 	if ((status->flag & RX_FLAG_MMIC_STRIPPED) &&
2085 	    !ieee80211_has_morefrags(hdr->frame_control) &&
2086 	    enctype == HAL_ENCRYPT_TYPE_TKIP_MIC)
2087 		skb_trim(msdu, msdu->len - IEEE80211_CCMP_MIC_LEN);
2088 
2089 	/* Head */
2090 	if (status->flag & RX_FLAG_IV_STRIPPED) {
2091 		hdr_len = ieee80211_hdrlen(hdr->frame_control);
2092 		crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
2093 
2094 		memmove((void *)msdu->data + crypto_len,
2095 			(void *)msdu->data, hdr_len);
2096 		skb_pull(msdu, crypto_len);
2097 	}
2098 }
2099 
2100 static void *ath11k_dp_rx_h_find_rfc1042(struct ath11k *ar,
2101 					 struct sk_buff *msdu,
2102 					 enum hal_encrypt_type enctype)
2103 {
2104 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2105 	struct ieee80211_hdr *hdr;
2106 	size_t hdr_len, crypto_len;
2107 	void *rfc1042;
2108 	bool is_amsdu;
2109 
2110 	is_amsdu = !(rxcb->is_first_msdu && rxcb->is_last_msdu);
2111 	hdr = (struct ieee80211_hdr *)ath11k_dp_rx_h_80211_hdr(ar->ab, rxcb->rx_desc);
2112 	rfc1042 = hdr;
2113 
2114 	if (rxcb->is_first_msdu) {
2115 		hdr_len = ieee80211_hdrlen(hdr->frame_control);
2116 		crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
2117 
2118 		rfc1042 += hdr_len + crypto_len;
2119 	}
2120 
2121 	if (is_amsdu)
2122 		rfc1042 += sizeof(struct ath11k_dp_amsdu_subframe_hdr);
2123 
2124 	return rfc1042;
2125 }
2126 
2127 static void ath11k_dp_rx_h_undecap_eth(struct ath11k *ar,
2128 				       struct sk_buff *msdu,
2129 				       u8 *first_hdr,
2130 				       enum hal_encrypt_type enctype,
2131 				       struct ieee80211_rx_status *status)
2132 {
2133 	struct ieee80211_hdr *hdr;
2134 	struct ethhdr *eth;
2135 	size_t hdr_len;
2136 	u8 da[ETH_ALEN];
2137 	u8 sa[ETH_ALEN];
2138 	void *rfc1042;
2139 
2140 	rfc1042 = ath11k_dp_rx_h_find_rfc1042(ar, msdu, enctype);
2141 	if (WARN_ON_ONCE(!rfc1042))
2142 		return;
2143 
2144 	/* pull decapped header and copy SA & DA */
2145 	eth = (struct ethhdr *)msdu->data;
2146 	ether_addr_copy(da, eth->h_dest);
2147 	ether_addr_copy(sa, eth->h_source);
2148 	skb_pull(msdu, sizeof(struct ethhdr));
2149 
2150 	/* push rfc1042/llc/snap */
2151 	memcpy(skb_push(msdu, sizeof(struct ath11k_dp_rfc1042_hdr)), rfc1042,
2152 	       sizeof(struct ath11k_dp_rfc1042_hdr));
2153 
2154 	/* push original 802.11 header */
2155 	hdr = (struct ieee80211_hdr *)first_hdr;
2156 	hdr_len = ieee80211_hdrlen(hdr->frame_control);
2157 
2158 	if (!(status->flag & RX_FLAG_IV_STRIPPED)) {
2159 		memcpy(skb_push(msdu,
2160 				ath11k_dp_rx_crypto_param_len(ar, enctype)),
2161 		       (void *)hdr + hdr_len,
2162 		       ath11k_dp_rx_crypto_param_len(ar, enctype));
2163 	}
2164 
2165 	memcpy(skb_push(msdu, hdr_len), hdr, hdr_len);
2166 
2167 	/* original 802.11 header has a different DA and in
2168 	 * case of 4addr it may also have different SA
2169 	 */
2170 	hdr = (struct ieee80211_hdr *)msdu->data;
2171 	ether_addr_copy(ieee80211_get_DA(hdr), da);
2172 	ether_addr_copy(ieee80211_get_SA(hdr), sa);
2173 }
2174 
2175 static void ath11k_dp_rx_h_undecap(struct ath11k *ar, struct sk_buff *msdu,
2176 				   struct hal_rx_desc *rx_desc,
2177 				   enum hal_encrypt_type enctype,
2178 				   struct ieee80211_rx_status *status,
2179 				   bool decrypted)
2180 {
2181 	u8 *first_hdr;
2182 	u8 decap;
2183 	struct ethhdr *ehdr;
2184 
2185 	first_hdr = ath11k_dp_rx_h_80211_hdr(ar->ab, rx_desc);
2186 	decap = ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rx_desc);
2187 
2188 	switch (decap) {
2189 	case DP_RX_DECAP_TYPE_NATIVE_WIFI:
2190 		ath11k_dp_rx_h_undecap_nwifi(ar, msdu, first_hdr,
2191 					     enctype, status);
2192 		break;
2193 	case DP_RX_DECAP_TYPE_RAW:
2194 		ath11k_dp_rx_h_undecap_raw(ar, msdu, enctype, status,
2195 					   decrypted);
2196 		break;
2197 	case DP_RX_DECAP_TYPE_ETHERNET2_DIX:
2198 		ehdr = (struct ethhdr *)msdu->data;
2199 
2200 		/* mac80211 allows fast path only for authorized STA */
2201 		if (ehdr->h_proto == cpu_to_be16(ETH_P_PAE)) {
2202 			ATH11K_SKB_RXCB(msdu)->is_eapol = true;
2203 			ath11k_dp_rx_h_undecap_eth(ar, msdu, first_hdr,
2204 						   enctype, status);
2205 			break;
2206 		}
2207 
2208 		/* PN for mcast packets will be validated in mac80211;
2209 		 * remove eth header and add 802.11 header.
2210 		 */
2211 		if (ATH11K_SKB_RXCB(msdu)->is_mcbc && decrypted)
2212 			ath11k_dp_rx_h_undecap_eth(ar, msdu, first_hdr,
2213 						   enctype, status);
2214 		break;
2215 	case DP_RX_DECAP_TYPE_8023:
2216 		/* TODO: Handle undecap for these formats */
2217 		break;
2218 	}
2219 }
2220 
2221 static struct ath11k_peer *
2222 ath11k_dp_rx_h_find_peer(struct ath11k_base *ab, struct sk_buff *msdu)
2223 {
2224 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2225 	struct hal_rx_desc *rx_desc = rxcb->rx_desc;
2226 	struct ath11k_peer *peer = NULL;
2227 
2228 	lockdep_assert_held(&ab->base_lock);
2229 
2230 	if (rxcb->peer_id)
2231 		peer = ath11k_peer_find_by_id(ab, rxcb->peer_id);
2232 
2233 	if (peer)
2234 		return peer;
2235 
2236 	if (!rx_desc || !(ath11k_dp_rxdesc_mac_addr2_valid(ab, rx_desc)))
2237 		return NULL;
2238 
2239 	peer = ath11k_peer_find_by_addr(ab,
2240 					ath11k_dp_rxdesc_mpdu_start_addr2(ab, rx_desc));
2241 	return peer;
2242 }
2243 
2244 static void ath11k_dp_rx_h_mpdu(struct ath11k *ar,
2245 				struct sk_buff *msdu,
2246 				struct hal_rx_desc *rx_desc,
2247 				struct ieee80211_rx_status *rx_status)
2248 {
2249 	bool  fill_crypto_hdr;
2250 	enum hal_encrypt_type enctype;
2251 	bool is_decrypted = false;
2252 	struct ath11k_skb_rxcb *rxcb;
2253 	struct ieee80211_hdr *hdr;
2254 	struct ath11k_peer *peer;
2255 	struct rx_attention *rx_attention;
2256 	u32 err_bitmap;
2257 
2258 	/* PN for multicast packets will be checked in mac80211 */
2259 	rxcb = ATH11K_SKB_RXCB(msdu);
2260 	fill_crypto_hdr = ath11k_dp_rx_h_attn_is_mcbc(ar->ab, rx_desc);
2261 	rxcb->is_mcbc = fill_crypto_hdr;
2262 
2263 	if (rxcb->is_mcbc) {
2264 		rxcb->peer_id = ath11k_dp_rx_h_mpdu_start_peer_id(ar->ab, rx_desc);
2265 		rxcb->seq_no = ath11k_dp_rx_h_mpdu_start_seq_no(ar->ab, rx_desc);
2266 	}
2267 
2268 	spin_lock_bh(&ar->ab->base_lock);
2269 	peer = ath11k_dp_rx_h_find_peer(ar->ab, msdu);
2270 	if (peer) {
2271 		if (rxcb->is_mcbc)
2272 			enctype = peer->sec_type_grp;
2273 		else
2274 			enctype = peer->sec_type;
2275 	} else {
2276 		enctype = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc);
2277 	}
2278 	spin_unlock_bh(&ar->ab->base_lock);
2279 
2280 	rx_attention = ath11k_dp_rx_get_attention(ar->ab, rx_desc);
2281 	err_bitmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention);
2282 	if (enctype != HAL_ENCRYPT_TYPE_OPEN && !err_bitmap)
2283 		is_decrypted = ath11k_dp_rx_h_attn_is_decrypted(rx_attention);
2284 
2285 	/* Clear per-MPDU flags while leaving per-PPDU flags intact */
2286 	rx_status->flag &= ~(RX_FLAG_FAILED_FCS_CRC |
2287 			     RX_FLAG_MMIC_ERROR |
2288 			     RX_FLAG_DECRYPTED |
2289 			     RX_FLAG_IV_STRIPPED |
2290 			     RX_FLAG_MMIC_STRIPPED);
2291 
2292 	if (err_bitmap & DP_RX_MPDU_ERR_FCS)
2293 		rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
2294 	if (err_bitmap & DP_RX_MPDU_ERR_TKIP_MIC)
2295 		rx_status->flag |= RX_FLAG_MMIC_ERROR;
2296 
2297 	if (is_decrypted) {
2298 		rx_status->flag |= RX_FLAG_DECRYPTED | RX_FLAG_MMIC_STRIPPED;
2299 
2300 		if (fill_crypto_hdr)
2301 			rx_status->flag |= RX_FLAG_MIC_STRIPPED |
2302 					RX_FLAG_ICV_STRIPPED;
2303 		else
2304 			rx_status->flag |= RX_FLAG_IV_STRIPPED |
2305 					   RX_FLAG_PN_VALIDATED;
2306 	}
2307 
2308 	ath11k_dp_rx_h_csum_offload(ar, msdu);
2309 	ath11k_dp_rx_h_undecap(ar, msdu, rx_desc,
2310 			       enctype, rx_status, is_decrypted);
2311 
2312 	if (!is_decrypted || fill_crypto_hdr)
2313 		return;
2314 
2315 	if (ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rx_desc) !=
2316 	    DP_RX_DECAP_TYPE_ETHERNET2_DIX) {
2317 		hdr = (void *)msdu->data;
2318 		hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_PROTECTED);
2319 	}
2320 }
2321 
2322 static void ath11k_dp_rx_h_rate(struct ath11k *ar, struct hal_rx_desc *rx_desc,
2323 				struct ieee80211_rx_status *rx_status)
2324 {
2325 	struct ieee80211_supported_band *sband;
2326 	enum rx_msdu_start_pkt_type pkt_type;
2327 	u8 bw;
2328 	u8 rate_mcs, nss;
2329 	u8 sgi;
2330 	bool is_cck;
2331 
2332 	pkt_type = ath11k_dp_rx_h_msdu_start_pkt_type(ar->ab, rx_desc);
2333 	bw = ath11k_dp_rx_h_msdu_start_rx_bw(ar->ab, rx_desc);
2334 	rate_mcs = ath11k_dp_rx_h_msdu_start_rate_mcs(ar->ab, rx_desc);
2335 	nss = ath11k_dp_rx_h_msdu_start_nss(ar->ab, rx_desc);
2336 	sgi = ath11k_dp_rx_h_msdu_start_sgi(ar->ab, rx_desc);
2337 
2338 	switch (pkt_type) {
2339 	case RX_MSDU_START_PKT_TYPE_11A:
2340 	case RX_MSDU_START_PKT_TYPE_11B:
2341 		is_cck = (pkt_type == RX_MSDU_START_PKT_TYPE_11B);
2342 		sband = &ar->mac.sbands[rx_status->band];
2343 		rx_status->rate_idx = ath11k_mac_hw_rate_to_idx(sband, rate_mcs,
2344 								is_cck);
2345 		break;
2346 	case RX_MSDU_START_PKT_TYPE_11N:
2347 		rx_status->encoding = RX_ENC_HT;
2348 		if (rate_mcs > ATH11K_HT_MCS_MAX) {
2349 			ath11k_warn(ar->ab,
2350 				    "Received with invalid mcs in HT mode %d\n",
2351 				     rate_mcs);
2352 			break;
2353 		}
2354 		rx_status->rate_idx = rate_mcs + (8 * (nss - 1));
2355 		if (sgi)
2356 			rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2357 		rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
2358 		break;
2359 	case RX_MSDU_START_PKT_TYPE_11AC:
2360 		rx_status->encoding = RX_ENC_VHT;
2361 		rx_status->rate_idx = rate_mcs;
2362 		if (rate_mcs > ATH11K_VHT_MCS_MAX) {
2363 			ath11k_warn(ar->ab,
2364 				    "Received with invalid mcs in VHT mode %d\n",
2365 				     rate_mcs);
2366 			break;
2367 		}
2368 		rx_status->nss = nss;
2369 		if (sgi)
2370 			rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2371 		rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
2372 		break;
2373 	case RX_MSDU_START_PKT_TYPE_11AX:
2374 		rx_status->rate_idx = rate_mcs;
2375 		if (rate_mcs > ATH11K_HE_MCS_MAX) {
2376 			ath11k_warn(ar->ab,
2377 				    "Received with invalid mcs in HE mode %d\n",
2378 				    rate_mcs);
2379 			break;
2380 		}
2381 		rx_status->encoding = RX_ENC_HE;
2382 		rx_status->nss = nss;
2383 		rx_status->he_gi = ath11k_he_gi_to_nl80211_he_gi(sgi);
2384 		rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
2385 		break;
2386 	}
2387 }
2388 
2389 static void ath11k_dp_rx_h_ppdu(struct ath11k *ar, struct hal_rx_desc *rx_desc,
2390 				struct ieee80211_rx_status *rx_status)
2391 {
2392 	u8 channel_num;
2393 	u32 center_freq, meta_data;
2394 	struct ieee80211_channel *channel;
2395 
2396 	rx_status->freq = 0;
2397 	rx_status->rate_idx = 0;
2398 	rx_status->nss = 0;
2399 	rx_status->encoding = RX_ENC_LEGACY;
2400 	rx_status->bw = RATE_INFO_BW_20;
2401 
2402 	rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL;
2403 
2404 	meta_data = ath11k_dp_rx_h_msdu_start_freq(ar->ab, rx_desc);
2405 	channel_num = meta_data;
2406 	center_freq = meta_data >> 16;
2407 
2408 	if (center_freq >= ATH11K_MIN_6G_FREQ &&
2409 	    center_freq <= ATH11K_MAX_6G_FREQ) {
2410 		rx_status->band = NL80211_BAND_6GHZ;
2411 		rx_status->freq = center_freq;
2412 	} else if (channel_num >= 1 && channel_num <= 14) {
2413 		rx_status->band = NL80211_BAND_2GHZ;
2414 	} else if (channel_num >= 36 && channel_num <= 173) {
2415 		rx_status->band = NL80211_BAND_5GHZ;
2416 	} else {
2417 		spin_lock_bh(&ar->data_lock);
2418 		channel = ar->rx_channel;
2419 		if (channel) {
2420 			rx_status->band = channel->band;
2421 			channel_num =
2422 				ieee80211_frequency_to_channel(channel->center_freq);
2423 		}
2424 		spin_unlock_bh(&ar->data_lock);
2425 		ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "rx_desc: ",
2426 				rx_desc, sizeof(struct hal_rx_desc));
2427 	}
2428 
2429 	if (rx_status->band != NL80211_BAND_6GHZ)
2430 		rx_status->freq = ieee80211_channel_to_frequency(channel_num,
2431 								 rx_status->band);
2432 
2433 	ath11k_dp_rx_h_rate(ar, rx_desc, rx_status);
2434 }
2435 
2436 static void ath11k_dp_rx_deliver_msdu(struct ath11k *ar, struct napi_struct *napi,
2437 				      struct sk_buff *msdu,
2438 				      struct ieee80211_rx_status *status)
2439 {
2440 	static const struct ieee80211_radiotap_he known = {
2441 		.data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN |
2442 				     IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN),
2443 		.data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN),
2444 	};
2445 	struct ieee80211_rx_status *rx_status;
2446 	struct ieee80211_radiotap_he *he = NULL;
2447 	struct ieee80211_sta *pubsta = NULL;
2448 	struct ath11k_peer *peer;
2449 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2450 	u8 decap = DP_RX_DECAP_TYPE_RAW;
2451 	bool is_mcbc = rxcb->is_mcbc;
2452 	bool is_eapol = rxcb->is_eapol;
2453 
2454 	if (status->encoding == RX_ENC_HE &&
2455 	    !(status->flag & RX_FLAG_RADIOTAP_HE) &&
2456 	    !(status->flag & RX_FLAG_SKIP_MONITOR)) {
2457 		he = skb_push(msdu, sizeof(known));
2458 		memcpy(he, &known, sizeof(known));
2459 		status->flag |= RX_FLAG_RADIOTAP_HE;
2460 	}
2461 
2462 	if (!(status->flag & RX_FLAG_ONLY_MONITOR))
2463 		decap = ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rxcb->rx_desc);
2464 
2465 	spin_lock_bh(&ar->ab->base_lock);
2466 	peer = ath11k_dp_rx_h_find_peer(ar->ab, msdu);
2467 	if (peer && peer->sta)
2468 		pubsta = peer->sta;
2469 	spin_unlock_bh(&ar->ab->base_lock);
2470 
2471 	ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
2472 		   "rx skb %pK len %u peer %pM %d %s sn %u %s%s%s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n",
2473 		   msdu,
2474 		   msdu->len,
2475 		   peer ? peer->addr : NULL,
2476 		   rxcb->tid,
2477 		   is_mcbc ? "mcast" : "ucast",
2478 		   rxcb->seq_no,
2479 		   (status->encoding == RX_ENC_LEGACY) ? "legacy" : "",
2480 		   (status->encoding == RX_ENC_HT) ? "ht" : "",
2481 		   (status->encoding == RX_ENC_VHT) ? "vht" : "",
2482 		   (status->encoding == RX_ENC_HE) ? "he" : "",
2483 		   (status->bw == RATE_INFO_BW_40) ? "40" : "",
2484 		   (status->bw == RATE_INFO_BW_80) ? "80" : "",
2485 		   (status->bw == RATE_INFO_BW_160) ? "160" : "",
2486 		   status->enc_flags & RX_ENC_FLAG_SHORT_GI ? "sgi " : "",
2487 		   status->rate_idx,
2488 		   status->nss,
2489 		   status->freq,
2490 		   status->band, status->flag,
2491 		   !!(status->flag & RX_FLAG_FAILED_FCS_CRC),
2492 		   !!(status->flag & RX_FLAG_MMIC_ERROR),
2493 		   !!(status->flag & RX_FLAG_AMSDU_MORE));
2494 
2495 	ath11k_dbg_dump(ar->ab, ATH11K_DBG_DP_RX, NULL, "dp rx msdu: ",
2496 			msdu->data, msdu->len);
2497 
2498 	rx_status = IEEE80211_SKB_RXCB(msdu);
2499 	*rx_status = *status;
2500 
2501 	/* TODO: trace rx packet */
2502 
2503 	/* PN for multicast packets are not validate in HW,
2504 	 * so skip 802.3 rx path
2505 	 * Also, fast_rx expectes the STA to be authorized, hence
2506 	 * eapol packets are sent in slow path.
2507 	 */
2508 	if (decap == DP_RX_DECAP_TYPE_ETHERNET2_DIX && !is_eapol &&
2509 	    !(is_mcbc && rx_status->flag & RX_FLAG_DECRYPTED))
2510 		rx_status->flag |= RX_FLAG_8023;
2511 
2512 	ieee80211_rx_napi(ar->hw, pubsta, msdu, napi);
2513 }
2514 
2515 static int ath11k_dp_rx_process_msdu(struct ath11k *ar,
2516 				     struct sk_buff *msdu,
2517 				     struct sk_buff_head *msdu_list,
2518 				     struct ieee80211_rx_status *rx_status)
2519 {
2520 	struct ath11k_base *ab = ar->ab;
2521 	struct hal_rx_desc *rx_desc, *lrx_desc;
2522 	struct rx_attention *rx_attention;
2523 	struct ath11k_skb_rxcb *rxcb;
2524 	struct sk_buff *last_buf;
2525 	u8 l3_pad_bytes;
2526 	u8 *hdr_status;
2527 	u16 msdu_len;
2528 	int ret;
2529 	u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
2530 
2531 	last_buf = ath11k_dp_rx_get_msdu_last_buf(msdu_list, msdu);
2532 	if (!last_buf) {
2533 		ath11k_warn(ab,
2534 			    "No valid Rx buffer to access Atten/MSDU_END/MPDU_END tlvs\n");
2535 		ret = -EIO;
2536 		goto free_out;
2537 	}
2538 
2539 	rx_desc = (struct hal_rx_desc *)msdu->data;
2540 	if (ath11k_dp_rx_h_attn_msdu_len_err(ab, rx_desc)) {
2541 		ath11k_warn(ar->ab, "msdu len not valid\n");
2542 		ret = -EIO;
2543 		goto free_out;
2544 	}
2545 
2546 	lrx_desc = (struct hal_rx_desc *)last_buf->data;
2547 	rx_attention = ath11k_dp_rx_get_attention(ab, lrx_desc);
2548 	if (!ath11k_dp_rx_h_attn_msdu_done(rx_attention)) {
2549 		ath11k_warn(ab, "msdu_done bit in attention is not set\n");
2550 		ret = -EIO;
2551 		goto free_out;
2552 	}
2553 
2554 	rxcb = ATH11K_SKB_RXCB(msdu);
2555 	rxcb->rx_desc = rx_desc;
2556 	msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ab, rx_desc);
2557 	l3_pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ab, lrx_desc);
2558 
2559 	if (rxcb->is_frag) {
2560 		skb_pull(msdu, hal_rx_desc_sz);
2561 	} else if (!rxcb->is_continuation) {
2562 		if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) {
2563 			hdr_status = ath11k_dp_rx_h_80211_hdr(ab, rx_desc);
2564 			ret = -EINVAL;
2565 			ath11k_warn(ab, "invalid msdu len %u\n", msdu_len);
2566 			ath11k_dbg_dump(ab, ATH11K_DBG_DATA, NULL, "", hdr_status,
2567 					sizeof(struct ieee80211_hdr));
2568 			ath11k_dbg_dump(ab, ATH11K_DBG_DATA, NULL, "", rx_desc,
2569 					sizeof(struct hal_rx_desc));
2570 			goto free_out;
2571 		}
2572 		skb_put(msdu, hal_rx_desc_sz + l3_pad_bytes + msdu_len);
2573 		skb_pull(msdu, hal_rx_desc_sz + l3_pad_bytes);
2574 	} else {
2575 		ret = ath11k_dp_rx_msdu_coalesce(ar, msdu_list,
2576 						 msdu, last_buf,
2577 						 l3_pad_bytes, msdu_len);
2578 		if (ret) {
2579 			ath11k_warn(ab,
2580 				    "failed to coalesce msdu rx buffer%d\n", ret);
2581 			goto free_out;
2582 		}
2583 	}
2584 
2585 	ath11k_dp_rx_h_ppdu(ar, rx_desc, rx_status);
2586 	ath11k_dp_rx_h_mpdu(ar, msdu, rx_desc, rx_status);
2587 
2588 	rx_status->flag |= RX_FLAG_SKIP_MONITOR | RX_FLAG_DUP_VALIDATED;
2589 
2590 	return 0;
2591 
2592 free_out:
2593 	return ret;
2594 }
2595 
2596 static void ath11k_dp_rx_process_received_packets(struct ath11k_base *ab,
2597 						  struct napi_struct *napi,
2598 						  struct sk_buff_head *msdu_list,
2599 						  int *quota, int ring_id)
2600 {
2601 	struct ath11k_skb_rxcb *rxcb;
2602 	struct sk_buff *msdu;
2603 	struct ath11k *ar;
2604 	struct ieee80211_rx_status rx_status = {0};
2605 	u8 mac_id;
2606 	int ret;
2607 
2608 	if (skb_queue_empty(msdu_list))
2609 		return;
2610 
2611 	rcu_read_lock();
2612 
2613 	while (*quota && (msdu = __skb_dequeue(msdu_list))) {
2614 		rxcb = ATH11K_SKB_RXCB(msdu);
2615 		mac_id = rxcb->mac_id;
2616 		ar = ab->pdevs[mac_id].ar;
2617 		if (!rcu_dereference(ab->pdevs_active[mac_id])) {
2618 			dev_kfree_skb_any(msdu);
2619 			continue;
2620 		}
2621 
2622 		if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) {
2623 			dev_kfree_skb_any(msdu);
2624 			continue;
2625 		}
2626 
2627 		ret = ath11k_dp_rx_process_msdu(ar, msdu, msdu_list, &rx_status);
2628 		if (ret) {
2629 			ath11k_dbg(ab, ATH11K_DBG_DATA,
2630 				   "Unable to process msdu %d", ret);
2631 			dev_kfree_skb_any(msdu);
2632 			continue;
2633 		}
2634 
2635 		ath11k_dp_rx_deliver_msdu(ar, napi, msdu, &rx_status);
2636 		(*quota)--;
2637 	}
2638 
2639 	rcu_read_unlock();
2640 }
2641 
2642 int ath11k_dp_process_rx(struct ath11k_base *ab, int ring_id,
2643 			 struct napi_struct *napi, int budget)
2644 {
2645 	struct ath11k_dp *dp = &ab->dp;
2646 	struct dp_rxdma_ring *rx_ring;
2647 	int num_buffs_reaped[MAX_RADIOS] = {0};
2648 	struct sk_buff_head msdu_list;
2649 	struct ath11k_skb_rxcb *rxcb;
2650 	int total_msdu_reaped = 0;
2651 	struct hal_srng *srng;
2652 	struct sk_buff *msdu;
2653 	int quota = budget;
2654 	bool done = false;
2655 	int buf_id, mac_id;
2656 	struct ath11k *ar;
2657 	u32 *rx_desc;
2658 	int i;
2659 
2660 	__skb_queue_head_init(&msdu_list);
2661 
2662 	srng = &ab->hal.srng_list[dp->reo_dst_ring[ring_id].ring_id];
2663 
2664 	spin_lock_bh(&srng->lock);
2665 
2666 	ath11k_hal_srng_access_begin(ab, srng);
2667 
2668 try_again:
2669 	while ((rx_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
2670 		struct hal_reo_dest_ring desc = *(struct hal_reo_dest_ring *)rx_desc;
2671 		enum hal_reo_dest_ring_push_reason push_reason;
2672 		u32 cookie;
2673 
2674 		cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
2675 				   desc.buf_addr_info.info1);
2676 		buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
2677 				   cookie);
2678 		mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, cookie);
2679 
2680 		ar = ab->pdevs[mac_id].ar;
2681 		rx_ring = &ar->dp.rx_refill_buf_ring;
2682 		spin_lock_bh(&rx_ring->idr_lock);
2683 		msdu = idr_find(&rx_ring->bufs_idr, buf_id);
2684 		if (!msdu) {
2685 			ath11k_warn(ab, "frame rx with invalid buf_id %d\n",
2686 				    buf_id);
2687 			spin_unlock_bh(&rx_ring->idr_lock);
2688 			continue;
2689 		}
2690 
2691 		idr_remove(&rx_ring->bufs_idr, buf_id);
2692 		spin_unlock_bh(&rx_ring->idr_lock);
2693 
2694 		rxcb = ATH11K_SKB_RXCB(msdu);
2695 		dma_unmap_single(ab->dev, rxcb->paddr,
2696 				 msdu->len + skb_tailroom(msdu),
2697 				 DMA_FROM_DEVICE);
2698 
2699 		num_buffs_reaped[mac_id]++;
2700 		total_msdu_reaped++;
2701 
2702 		push_reason = FIELD_GET(HAL_REO_DEST_RING_INFO0_PUSH_REASON,
2703 					desc.info0);
2704 		if (push_reason !=
2705 		    HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION) {
2706 			dev_kfree_skb_any(msdu);
2707 			ab->soc_stats.hal_reo_error[dp->reo_dst_ring[ring_id].ring_id]++;
2708 			continue;
2709 		}
2710 
2711 		rxcb->is_first_msdu = !!(desc.rx_msdu_info.info0 &
2712 					 RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU);
2713 		rxcb->is_last_msdu = !!(desc.rx_msdu_info.info0 &
2714 					RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU);
2715 		rxcb->is_continuation = !!(desc.rx_msdu_info.info0 &
2716 					   RX_MSDU_DESC_INFO0_MSDU_CONTINUATION);
2717 		rxcb->peer_id = FIELD_GET(RX_MPDU_DESC_META_DATA_PEER_ID,
2718 					  desc.rx_mpdu_info.meta_data);
2719 		rxcb->seq_no = FIELD_GET(RX_MPDU_DESC_INFO0_SEQ_NUM,
2720 					 desc.rx_mpdu_info.info0);
2721 		rxcb->tid = FIELD_GET(HAL_REO_DEST_RING_INFO0_RX_QUEUE_NUM,
2722 				      desc.info0);
2723 
2724 		rxcb->mac_id = mac_id;
2725 		__skb_queue_tail(&msdu_list, msdu);
2726 
2727 		if (total_msdu_reaped >= quota && !rxcb->is_continuation) {
2728 			done = true;
2729 			break;
2730 		}
2731 	}
2732 
2733 	/* Hw might have updated the head pointer after we cached it.
2734 	 * In this case, even though there are entries in the ring we'll
2735 	 * get rx_desc NULL. Give the read another try with updated cached
2736 	 * head pointer so that we can reap complete MPDU in the current
2737 	 * rx processing.
2738 	 */
2739 	if (!done && ath11k_hal_srng_dst_num_free(ab, srng, true)) {
2740 		ath11k_hal_srng_access_end(ab, srng);
2741 		goto try_again;
2742 	}
2743 
2744 	ath11k_hal_srng_access_end(ab, srng);
2745 
2746 	spin_unlock_bh(&srng->lock);
2747 
2748 	if (!total_msdu_reaped)
2749 		goto exit;
2750 
2751 	for (i = 0; i < ab->num_radios; i++) {
2752 		if (!num_buffs_reaped[i])
2753 			continue;
2754 
2755 		ar = ab->pdevs[i].ar;
2756 		rx_ring = &ar->dp.rx_refill_buf_ring;
2757 
2758 		ath11k_dp_rxbufs_replenish(ab, i, rx_ring, num_buffs_reaped[i],
2759 					   HAL_RX_BUF_RBM_SW3_BM);
2760 	}
2761 
2762 	ath11k_dp_rx_process_received_packets(ab, napi, &msdu_list,
2763 					      &quota, ring_id);
2764 
2765 exit:
2766 	return budget - quota;
2767 }
2768 
2769 static void ath11k_dp_rx_update_peer_stats(struct ath11k_sta *arsta,
2770 					   struct hal_rx_mon_ppdu_info *ppdu_info)
2771 {
2772 	struct ath11k_rx_peer_stats *rx_stats = arsta->rx_stats;
2773 	u32 num_msdu;
2774 
2775 	if (!rx_stats)
2776 		return;
2777 
2778 	num_msdu = ppdu_info->tcp_msdu_count + ppdu_info->tcp_ack_msdu_count +
2779 		   ppdu_info->udp_msdu_count + ppdu_info->other_msdu_count;
2780 
2781 	rx_stats->num_msdu += num_msdu;
2782 	rx_stats->tcp_msdu_count += ppdu_info->tcp_msdu_count +
2783 				    ppdu_info->tcp_ack_msdu_count;
2784 	rx_stats->udp_msdu_count += ppdu_info->udp_msdu_count;
2785 	rx_stats->other_msdu_count += ppdu_info->other_msdu_count;
2786 
2787 	if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11A ||
2788 	    ppdu_info->preamble_type == HAL_RX_PREAMBLE_11B) {
2789 		ppdu_info->nss = 1;
2790 		ppdu_info->mcs = HAL_RX_MAX_MCS;
2791 		ppdu_info->tid = IEEE80211_NUM_TIDS;
2792 	}
2793 
2794 	if (ppdu_info->nss > 0 && ppdu_info->nss <= HAL_RX_MAX_NSS)
2795 		rx_stats->nss_count[ppdu_info->nss - 1] += num_msdu;
2796 
2797 	if (ppdu_info->mcs <= HAL_RX_MAX_MCS)
2798 		rx_stats->mcs_count[ppdu_info->mcs] += num_msdu;
2799 
2800 	if (ppdu_info->gi < HAL_RX_GI_MAX)
2801 		rx_stats->gi_count[ppdu_info->gi] += num_msdu;
2802 
2803 	if (ppdu_info->bw < HAL_RX_BW_MAX)
2804 		rx_stats->bw_count[ppdu_info->bw] += num_msdu;
2805 
2806 	if (ppdu_info->ldpc < HAL_RX_SU_MU_CODING_MAX)
2807 		rx_stats->coding_count[ppdu_info->ldpc] += num_msdu;
2808 
2809 	if (ppdu_info->tid <= IEEE80211_NUM_TIDS)
2810 		rx_stats->tid_count[ppdu_info->tid] += num_msdu;
2811 
2812 	if (ppdu_info->preamble_type < HAL_RX_PREAMBLE_MAX)
2813 		rx_stats->pream_cnt[ppdu_info->preamble_type] += num_msdu;
2814 
2815 	if (ppdu_info->reception_type < HAL_RX_RECEPTION_TYPE_MAX)
2816 		rx_stats->reception_type[ppdu_info->reception_type] += num_msdu;
2817 
2818 	if (ppdu_info->is_stbc)
2819 		rx_stats->stbc_count += num_msdu;
2820 
2821 	if (ppdu_info->beamformed)
2822 		rx_stats->beamformed_count += num_msdu;
2823 
2824 	if (ppdu_info->num_mpdu_fcs_ok > 1)
2825 		rx_stats->ampdu_msdu_count += num_msdu;
2826 	else
2827 		rx_stats->non_ampdu_msdu_count += num_msdu;
2828 
2829 	rx_stats->num_mpdu_fcs_ok += ppdu_info->num_mpdu_fcs_ok;
2830 	rx_stats->num_mpdu_fcs_err += ppdu_info->num_mpdu_fcs_err;
2831 	rx_stats->dcm_count += ppdu_info->dcm;
2832 	rx_stats->ru_alloc_cnt[ppdu_info->ru_alloc] += num_msdu;
2833 
2834 	arsta->rssi_comb = ppdu_info->rssi_comb;
2835 	rx_stats->rx_duration += ppdu_info->rx_duration;
2836 	arsta->rx_duration = rx_stats->rx_duration;
2837 }
2838 
2839 static struct sk_buff *ath11k_dp_rx_alloc_mon_status_buf(struct ath11k_base *ab,
2840 							 struct dp_rxdma_ring *rx_ring,
2841 							 int *buf_id)
2842 {
2843 	struct sk_buff *skb;
2844 	dma_addr_t paddr;
2845 
2846 	skb = dev_alloc_skb(DP_RX_BUFFER_SIZE +
2847 			    DP_RX_BUFFER_ALIGN_SIZE);
2848 
2849 	if (!skb)
2850 		goto fail_alloc_skb;
2851 
2852 	if (!IS_ALIGNED((unsigned long)skb->data,
2853 			DP_RX_BUFFER_ALIGN_SIZE)) {
2854 		skb_pull(skb, PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) -
2855 			 skb->data);
2856 	}
2857 
2858 	paddr = dma_map_single(ab->dev, skb->data,
2859 			       skb->len + skb_tailroom(skb),
2860 			       DMA_FROM_DEVICE);
2861 	if (unlikely(dma_mapping_error(ab->dev, paddr)))
2862 		goto fail_free_skb;
2863 
2864 	spin_lock_bh(&rx_ring->idr_lock);
2865 	*buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 0,
2866 			    rx_ring->bufs_max, GFP_ATOMIC);
2867 	spin_unlock_bh(&rx_ring->idr_lock);
2868 	if (*buf_id < 0)
2869 		goto fail_dma_unmap;
2870 
2871 	ATH11K_SKB_RXCB(skb)->paddr = paddr;
2872 	return skb;
2873 
2874 fail_dma_unmap:
2875 	dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
2876 			 DMA_FROM_DEVICE);
2877 fail_free_skb:
2878 	dev_kfree_skb_any(skb);
2879 fail_alloc_skb:
2880 	return NULL;
2881 }
2882 
2883 int ath11k_dp_rx_mon_status_bufs_replenish(struct ath11k_base *ab, int mac_id,
2884 					   struct dp_rxdma_ring *rx_ring,
2885 					   int req_entries,
2886 					   enum hal_rx_buf_return_buf_manager mgr)
2887 {
2888 	struct hal_srng *srng;
2889 	u32 *desc;
2890 	struct sk_buff *skb;
2891 	int num_free;
2892 	int num_remain;
2893 	int buf_id;
2894 	u32 cookie;
2895 	dma_addr_t paddr;
2896 
2897 	req_entries = min(req_entries, rx_ring->bufs_max);
2898 
2899 	srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
2900 
2901 	spin_lock_bh(&srng->lock);
2902 
2903 	ath11k_hal_srng_access_begin(ab, srng);
2904 
2905 	num_free = ath11k_hal_srng_src_num_free(ab, srng, true);
2906 
2907 	req_entries = min(num_free, req_entries);
2908 	num_remain = req_entries;
2909 
2910 	while (num_remain > 0) {
2911 		skb = ath11k_dp_rx_alloc_mon_status_buf(ab, rx_ring,
2912 							&buf_id);
2913 		if (!skb)
2914 			break;
2915 		paddr = ATH11K_SKB_RXCB(skb)->paddr;
2916 
2917 		desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
2918 		if (!desc)
2919 			goto fail_desc_get;
2920 
2921 		cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
2922 			 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
2923 
2924 		num_remain--;
2925 
2926 		ath11k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr);
2927 	}
2928 
2929 	ath11k_hal_srng_access_end(ab, srng);
2930 
2931 	spin_unlock_bh(&srng->lock);
2932 
2933 	return req_entries - num_remain;
2934 
2935 fail_desc_get:
2936 	spin_lock_bh(&rx_ring->idr_lock);
2937 	idr_remove(&rx_ring->bufs_idr, buf_id);
2938 	spin_unlock_bh(&rx_ring->idr_lock);
2939 	dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
2940 			 DMA_FROM_DEVICE);
2941 	dev_kfree_skb_any(skb);
2942 	ath11k_hal_srng_access_end(ab, srng);
2943 	spin_unlock_bh(&srng->lock);
2944 
2945 	return req_entries - num_remain;
2946 }
2947 
2948 static int ath11k_dp_rx_reap_mon_status_ring(struct ath11k_base *ab, int mac_id,
2949 					     int *budget, struct sk_buff_head *skb_list)
2950 {
2951 	struct ath11k *ar;
2952 	struct ath11k_pdev_dp *dp;
2953 	struct dp_rxdma_ring *rx_ring;
2954 	struct hal_srng *srng;
2955 	void *rx_mon_status_desc;
2956 	struct sk_buff *skb;
2957 	struct ath11k_skb_rxcb *rxcb;
2958 	struct hal_tlv_hdr *tlv;
2959 	u32 cookie;
2960 	int buf_id, srng_id;
2961 	dma_addr_t paddr;
2962 	u8 rbm;
2963 	int num_buffs_reaped = 0;
2964 
2965 	ar = ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar;
2966 	dp = &ar->dp;
2967 	srng_id = ath11k_hw_mac_id_to_srng_id(&ab->hw_params, mac_id);
2968 	rx_ring = &dp->rx_mon_status_refill_ring[srng_id];
2969 
2970 	srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
2971 
2972 	spin_lock_bh(&srng->lock);
2973 
2974 	ath11k_hal_srng_access_begin(ab, srng);
2975 	while (*budget) {
2976 		*budget -= 1;
2977 		rx_mon_status_desc =
2978 			ath11k_hal_srng_src_peek(ab, srng);
2979 		if (!rx_mon_status_desc)
2980 			break;
2981 
2982 		ath11k_hal_rx_buf_addr_info_get(rx_mon_status_desc, &paddr,
2983 						&cookie, &rbm);
2984 		if (paddr) {
2985 			buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, cookie);
2986 
2987 			spin_lock_bh(&rx_ring->idr_lock);
2988 			skb = idr_find(&rx_ring->bufs_idr, buf_id);
2989 			if (!skb) {
2990 				ath11k_warn(ab, "rx monitor status with invalid buf_id %d\n",
2991 					    buf_id);
2992 				spin_unlock_bh(&rx_ring->idr_lock);
2993 				goto move_next;
2994 			}
2995 
2996 			idr_remove(&rx_ring->bufs_idr, buf_id);
2997 			spin_unlock_bh(&rx_ring->idr_lock);
2998 
2999 			rxcb = ATH11K_SKB_RXCB(skb);
3000 
3001 			dma_unmap_single(ab->dev, rxcb->paddr,
3002 					 skb->len + skb_tailroom(skb),
3003 					 DMA_FROM_DEVICE);
3004 
3005 			tlv = (struct hal_tlv_hdr *)skb->data;
3006 			if (FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl) !=
3007 					HAL_RX_STATUS_BUFFER_DONE) {
3008 				ath11k_warn(ab, "mon status DONE not set %lx\n",
3009 					    FIELD_GET(HAL_TLV_HDR_TAG,
3010 						      tlv->tl));
3011 				dev_kfree_skb_any(skb);
3012 				goto move_next;
3013 			}
3014 
3015 			__skb_queue_tail(skb_list, skb);
3016 		}
3017 move_next:
3018 		skb = ath11k_dp_rx_alloc_mon_status_buf(ab, rx_ring,
3019 							&buf_id);
3020 
3021 		if (!skb) {
3022 			ath11k_hal_rx_buf_addr_info_set(rx_mon_status_desc, 0, 0,
3023 							HAL_RX_BUF_RBM_SW3_BM);
3024 			num_buffs_reaped++;
3025 			break;
3026 		}
3027 		rxcb = ATH11K_SKB_RXCB(skb);
3028 
3029 		cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
3030 			 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
3031 
3032 		ath11k_hal_rx_buf_addr_info_set(rx_mon_status_desc, rxcb->paddr,
3033 						cookie, HAL_RX_BUF_RBM_SW3_BM);
3034 		ath11k_hal_srng_src_get_next_entry(ab, srng);
3035 		num_buffs_reaped++;
3036 	}
3037 	ath11k_hal_srng_access_end(ab, srng);
3038 	spin_unlock_bh(&srng->lock);
3039 
3040 	return num_buffs_reaped;
3041 }
3042 
3043 int ath11k_dp_rx_process_mon_status(struct ath11k_base *ab, int mac_id,
3044 				    struct napi_struct *napi, int budget)
3045 {
3046 	struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id);
3047 	enum hal_rx_mon_status hal_status;
3048 	struct sk_buff *skb;
3049 	struct sk_buff_head skb_list;
3050 	struct hal_rx_mon_ppdu_info ppdu_info;
3051 	struct ath11k_peer *peer;
3052 	struct ath11k_sta *arsta;
3053 	int num_buffs_reaped = 0;
3054 	u32 rx_buf_sz;
3055 	u16 log_type = 0;
3056 
3057 	__skb_queue_head_init(&skb_list);
3058 
3059 	num_buffs_reaped = ath11k_dp_rx_reap_mon_status_ring(ab, mac_id, &budget,
3060 							     &skb_list);
3061 	if (!num_buffs_reaped)
3062 		goto exit;
3063 
3064 	while ((skb = __skb_dequeue(&skb_list))) {
3065 		memset(&ppdu_info, 0, sizeof(ppdu_info));
3066 		ppdu_info.peer_id = HAL_INVALID_PEERID;
3067 
3068 		if (ath11k_debugfs_is_pktlog_lite_mode_enabled(ar)) {
3069 			log_type = ATH11K_PKTLOG_TYPE_LITE_RX;
3070 			rx_buf_sz = DP_RX_BUFFER_SIZE_LITE;
3071 		} else if (ath11k_debugfs_is_pktlog_rx_stats_enabled(ar)) {
3072 			log_type = ATH11K_PKTLOG_TYPE_RX_STATBUF;
3073 			rx_buf_sz = DP_RX_BUFFER_SIZE;
3074 		}
3075 
3076 		if (log_type)
3077 			trace_ath11k_htt_rxdesc(ar, skb->data, log_type, rx_buf_sz);
3078 
3079 		hal_status = ath11k_hal_rx_parse_mon_status(ab, &ppdu_info, skb);
3080 
3081 		if (ppdu_info.peer_id == HAL_INVALID_PEERID ||
3082 		    hal_status != HAL_RX_MON_STATUS_PPDU_DONE) {
3083 			dev_kfree_skb_any(skb);
3084 			continue;
3085 		}
3086 
3087 		rcu_read_lock();
3088 		spin_lock_bh(&ab->base_lock);
3089 		peer = ath11k_peer_find_by_id(ab, ppdu_info.peer_id);
3090 
3091 		if (!peer || !peer->sta) {
3092 			ath11k_dbg(ab, ATH11K_DBG_DATA,
3093 				   "failed to find the peer with peer_id %d\n",
3094 				   ppdu_info.peer_id);
3095 			spin_unlock_bh(&ab->base_lock);
3096 			rcu_read_unlock();
3097 			dev_kfree_skb_any(skb);
3098 			continue;
3099 		}
3100 
3101 		arsta = (struct ath11k_sta *)peer->sta->drv_priv;
3102 		ath11k_dp_rx_update_peer_stats(arsta, &ppdu_info);
3103 
3104 		if (ath11k_debugfs_is_pktlog_peer_valid(ar, peer->addr))
3105 			trace_ath11k_htt_rxdesc(ar, skb->data, log_type, rx_buf_sz);
3106 
3107 		spin_unlock_bh(&ab->base_lock);
3108 		rcu_read_unlock();
3109 
3110 		dev_kfree_skb_any(skb);
3111 	}
3112 exit:
3113 	return num_buffs_reaped;
3114 }
3115 
3116 static void ath11k_dp_rx_frag_timer(struct timer_list *timer)
3117 {
3118 	struct dp_rx_tid *rx_tid = from_timer(rx_tid, timer, frag_timer);
3119 
3120 	spin_lock_bh(&rx_tid->ab->base_lock);
3121 	if (rx_tid->last_frag_no &&
3122 	    rx_tid->rx_frag_bitmap == GENMASK(rx_tid->last_frag_no, 0)) {
3123 		spin_unlock_bh(&rx_tid->ab->base_lock);
3124 		return;
3125 	}
3126 	ath11k_dp_rx_frags_cleanup(rx_tid, true);
3127 	spin_unlock_bh(&rx_tid->ab->base_lock);
3128 }
3129 
3130 int ath11k_peer_rx_frag_setup(struct ath11k *ar, const u8 *peer_mac, int vdev_id)
3131 {
3132 	struct ath11k_base *ab = ar->ab;
3133 	struct crypto_shash *tfm;
3134 	struct ath11k_peer *peer;
3135 	struct dp_rx_tid *rx_tid;
3136 	int i;
3137 
3138 	tfm = crypto_alloc_shash("michael_mic", 0, 0);
3139 	if (IS_ERR(tfm))
3140 		return PTR_ERR(tfm);
3141 
3142 	spin_lock_bh(&ab->base_lock);
3143 
3144 	peer = ath11k_peer_find(ab, vdev_id, peer_mac);
3145 	if (!peer) {
3146 		ath11k_warn(ab, "failed to find the peer to set up fragment info\n");
3147 		spin_unlock_bh(&ab->base_lock);
3148 		return -ENOENT;
3149 	}
3150 
3151 	for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
3152 		rx_tid = &peer->rx_tid[i];
3153 		rx_tid->ab = ab;
3154 		timer_setup(&rx_tid->frag_timer, ath11k_dp_rx_frag_timer, 0);
3155 		skb_queue_head_init(&rx_tid->rx_frags);
3156 	}
3157 
3158 	peer->tfm_mmic = tfm;
3159 	spin_unlock_bh(&ab->base_lock);
3160 
3161 	return 0;
3162 }
3163 
3164 static int ath11k_dp_rx_h_michael_mic(struct crypto_shash *tfm, u8 *key,
3165 				      struct ieee80211_hdr *hdr, u8 *data,
3166 				      size_t data_len, u8 *mic)
3167 {
3168 	SHASH_DESC_ON_STACK(desc, tfm);
3169 	u8 mic_hdr[16] = {0};
3170 	u8 tid = 0;
3171 	int ret;
3172 
3173 	if (!tfm)
3174 		return -EINVAL;
3175 
3176 	desc->tfm = tfm;
3177 
3178 	ret = crypto_shash_setkey(tfm, key, 8);
3179 	if (ret)
3180 		goto out;
3181 
3182 	ret = crypto_shash_init(desc);
3183 	if (ret)
3184 		goto out;
3185 
3186 	/* TKIP MIC header */
3187 	memcpy(mic_hdr, ieee80211_get_DA(hdr), ETH_ALEN);
3188 	memcpy(mic_hdr + ETH_ALEN, ieee80211_get_SA(hdr), ETH_ALEN);
3189 	if (ieee80211_is_data_qos(hdr->frame_control))
3190 		tid = ieee80211_get_tid(hdr);
3191 	mic_hdr[12] = tid;
3192 
3193 	ret = crypto_shash_update(desc, mic_hdr, 16);
3194 	if (ret)
3195 		goto out;
3196 	ret = crypto_shash_update(desc, data, data_len);
3197 	if (ret)
3198 		goto out;
3199 	ret = crypto_shash_final(desc, mic);
3200 out:
3201 	shash_desc_zero(desc);
3202 	return ret;
3203 }
3204 
3205 static int ath11k_dp_rx_h_verify_tkip_mic(struct ath11k *ar, struct ath11k_peer *peer,
3206 					  struct sk_buff *msdu)
3207 {
3208 	struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)msdu->data;
3209 	struct ieee80211_rx_status *rxs = IEEE80211_SKB_RXCB(msdu);
3210 	struct ieee80211_key_conf *key_conf;
3211 	struct ieee80211_hdr *hdr;
3212 	u8 mic[IEEE80211_CCMP_MIC_LEN];
3213 	int head_len, tail_len, ret;
3214 	size_t data_len;
3215 	u32 hdr_len, hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3216 	u8 *key, *data;
3217 	u8 key_idx;
3218 
3219 	if (ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc) !=
3220 	    HAL_ENCRYPT_TYPE_TKIP_MIC)
3221 		return 0;
3222 
3223 	hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz);
3224 	hdr_len = ieee80211_hdrlen(hdr->frame_control);
3225 	head_len = hdr_len + hal_rx_desc_sz + IEEE80211_TKIP_IV_LEN;
3226 	tail_len = IEEE80211_CCMP_MIC_LEN + IEEE80211_TKIP_ICV_LEN + FCS_LEN;
3227 
3228 	if (!is_multicast_ether_addr(hdr->addr1))
3229 		key_idx = peer->ucast_keyidx;
3230 	else
3231 		key_idx = peer->mcast_keyidx;
3232 
3233 	key_conf = peer->keys[key_idx];
3234 
3235 	data = msdu->data + head_len;
3236 	data_len = msdu->len - head_len - tail_len;
3237 	key = &key_conf->key[NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY];
3238 
3239 	ret = ath11k_dp_rx_h_michael_mic(peer->tfm_mmic, key, hdr, data, data_len, mic);
3240 	if (ret || memcmp(mic, data + data_len, IEEE80211_CCMP_MIC_LEN))
3241 		goto mic_fail;
3242 
3243 	return 0;
3244 
3245 mic_fail:
3246 	(ATH11K_SKB_RXCB(msdu))->is_first_msdu = true;
3247 	(ATH11K_SKB_RXCB(msdu))->is_last_msdu = true;
3248 
3249 	rxs->flag |= RX_FLAG_MMIC_ERROR | RX_FLAG_MMIC_STRIPPED |
3250 		    RX_FLAG_IV_STRIPPED | RX_FLAG_DECRYPTED;
3251 	skb_pull(msdu, hal_rx_desc_sz);
3252 
3253 	ath11k_dp_rx_h_ppdu(ar, rx_desc, rxs);
3254 	ath11k_dp_rx_h_undecap(ar, msdu, rx_desc,
3255 			       HAL_ENCRYPT_TYPE_TKIP_MIC, rxs, true);
3256 	ieee80211_rx(ar->hw, msdu);
3257 	return -EINVAL;
3258 }
3259 
3260 static void ath11k_dp_rx_h_undecap_frag(struct ath11k *ar, struct sk_buff *msdu,
3261 					enum hal_encrypt_type enctype, u32 flags)
3262 {
3263 	struct ieee80211_hdr *hdr;
3264 	size_t hdr_len;
3265 	size_t crypto_len;
3266 	u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3267 
3268 	if (!flags)
3269 		return;
3270 
3271 	hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz);
3272 
3273 	if (flags & RX_FLAG_MIC_STRIPPED)
3274 		skb_trim(msdu, msdu->len -
3275 			 ath11k_dp_rx_crypto_mic_len(ar, enctype));
3276 
3277 	if (flags & RX_FLAG_ICV_STRIPPED)
3278 		skb_trim(msdu, msdu->len -
3279 			 ath11k_dp_rx_crypto_icv_len(ar, enctype));
3280 
3281 	if (flags & RX_FLAG_IV_STRIPPED) {
3282 		hdr_len = ieee80211_hdrlen(hdr->frame_control);
3283 		crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
3284 
3285 		memmove((void *)msdu->data + hal_rx_desc_sz + crypto_len,
3286 			(void *)msdu->data + hal_rx_desc_sz, hdr_len);
3287 		skb_pull(msdu, crypto_len);
3288 	}
3289 }
3290 
3291 static int ath11k_dp_rx_h_defrag(struct ath11k *ar,
3292 				 struct ath11k_peer *peer,
3293 				 struct dp_rx_tid *rx_tid,
3294 				 struct sk_buff **defrag_skb)
3295 {
3296 	struct hal_rx_desc *rx_desc;
3297 	struct sk_buff *skb, *first_frag, *last_frag;
3298 	struct ieee80211_hdr *hdr;
3299 	struct rx_attention *rx_attention;
3300 	enum hal_encrypt_type enctype;
3301 	bool is_decrypted = false;
3302 	int msdu_len = 0;
3303 	int extra_space;
3304 	u32 flags, hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3305 
3306 	first_frag = skb_peek(&rx_tid->rx_frags);
3307 	last_frag = skb_peek_tail(&rx_tid->rx_frags);
3308 
3309 	skb_queue_walk(&rx_tid->rx_frags, skb) {
3310 		flags = 0;
3311 		rx_desc = (struct hal_rx_desc *)skb->data;
3312 		hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz);
3313 
3314 		enctype = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc);
3315 		if (enctype != HAL_ENCRYPT_TYPE_OPEN) {
3316 			rx_attention = ath11k_dp_rx_get_attention(ar->ab, rx_desc);
3317 			is_decrypted = ath11k_dp_rx_h_attn_is_decrypted(rx_attention);
3318 		}
3319 
3320 		if (is_decrypted) {
3321 			if (skb != first_frag)
3322 				flags |=  RX_FLAG_IV_STRIPPED;
3323 			if (skb != last_frag)
3324 				flags |= RX_FLAG_ICV_STRIPPED |
3325 					 RX_FLAG_MIC_STRIPPED;
3326 		}
3327 
3328 		/* RX fragments are always raw packets */
3329 		if (skb != last_frag)
3330 			skb_trim(skb, skb->len - FCS_LEN);
3331 		ath11k_dp_rx_h_undecap_frag(ar, skb, enctype, flags);
3332 
3333 		if (skb != first_frag)
3334 			skb_pull(skb, hal_rx_desc_sz +
3335 				      ieee80211_hdrlen(hdr->frame_control));
3336 		msdu_len += skb->len;
3337 	}
3338 
3339 	extra_space = msdu_len - (DP_RX_BUFFER_SIZE + skb_tailroom(first_frag));
3340 	if (extra_space > 0 &&
3341 	    (pskb_expand_head(first_frag, 0, extra_space, GFP_ATOMIC) < 0))
3342 		return -ENOMEM;
3343 
3344 	__skb_unlink(first_frag, &rx_tid->rx_frags);
3345 	while ((skb = __skb_dequeue(&rx_tid->rx_frags))) {
3346 		skb_put_data(first_frag, skb->data, skb->len);
3347 		dev_kfree_skb_any(skb);
3348 	}
3349 
3350 	hdr = (struct ieee80211_hdr *)(first_frag->data + hal_rx_desc_sz);
3351 	hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_MOREFRAGS);
3352 	ATH11K_SKB_RXCB(first_frag)->is_frag = 1;
3353 
3354 	if (ath11k_dp_rx_h_verify_tkip_mic(ar, peer, first_frag))
3355 		first_frag = NULL;
3356 
3357 	*defrag_skb = first_frag;
3358 	return 0;
3359 }
3360 
3361 static int ath11k_dp_rx_h_defrag_reo_reinject(struct ath11k *ar, struct dp_rx_tid *rx_tid,
3362 					      struct sk_buff *defrag_skb)
3363 {
3364 	struct ath11k_base *ab = ar->ab;
3365 	struct ath11k_pdev_dp *dp = &ar->dp;
3366 	struct dp_rxdma_ring *rx_refill_ring = &dp->rx_refill_buf_ring;
3367 	struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)defrag_skb->data;
3368 	struct hal_reo_entrance_ring *reo_ent_ring;
3369 	struct hal_reo_dest_ring *reo_dest_ring;
3370 	struct dp_link_desc_bank *link_desc_banks;
3371 	struct hal_rx_msdu_link *msdu_link;
3372 	struct hal_rx_msdu_details *msdu0;
3373 	struct hal_srng *srng;
3374 	dma_addr_t paddr;
3375 	u32 desc_bank, msdu_info, mpdu_info;
3376 	u32 dst_idx, cookie, hal_rx_desc_sz;
3377 	int ret, buf_id;
3378 
3379 	hal_rx_desc_sz = ab->hw_params.hal_desc_sz;
3380 	link_desc_banks = ab->dp.link_desc_banks;
3381 	reo_dest_ring = rx_tid->dst_ring_desc;
3382 
3383 	ath11k_hal_rx_reo_ent_paddr_get(ab, reo_dest_ring, &paddr, &desc_bank);
3384 	msdu_link = (struct hal_rx_msdu_link *)(link_desc_banks[desc_bank].vaddr +
3385 			(paddr - link_desc_banks[desc_bank].paddr));
3386 	msdu0 = &msdu_link->msdu_link[0];
3387 	dst_idx = FIELD_GET(RX_MSDU_DESC_INFO0_REO_DEST_IND, msdu0->rx_msdu_info.info0);
3388 	memset(msdu0, 0, sizeof(*msdu0));
3389 
3390 	msdu_info = FIELD_PREP(RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU, 1) |
3391 		    FIELD_PREP(RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU, 1) |
3392 		    FIELD_PREP(RX_MSDU_DESC_INFO0_MSDU_CONTINUATION, 0) |
3393 		    FIELD_PREP(RX_MSDU_DESC_INFO0_MSDU_LENGTH,
3394 			       defrag_skb->len - hal_rx_desc_sz) |
3395 		    FIELD_PREP(RX_MSDU_DESC_INFO0_REO_DEST_IND, dst_idx) |
3396 		    FIELD_PREP(RX_MSDU_DESC_INFO0_VALID_SA, 1) |
3397 		    FIELD_PREP(RX_MSDU_DESC_INFO0_VALID_DA, 1);
3398 	msdu0->rx_msdu_info.info0 = msdu_info;
3399 
3400 	/* change msdu len in hal rx desc */
3401 	ath11k_dp_rxdesc_set_msdu_len(ab, rx_desc, defrag_skb->len - hal_rx_desc_sz);
3402 
3403 	paddr = dma_map_single(ab->dev, defrag_skb->data,
3404 			       defrag_skb->len + skb_tailroom(defrag_skb),
3405 			       DMA_TO_DEVICE);
3406 	if (dma_mapping_error(ab->dev, paddr))
3407 		return -ENOMEM;
3408 
3409 	spin_lock_bh(&rx_refill_ring->idr_lock);
3410 	buf_id = idr_alloc(&rx_refill_ring->bufs_idr, defrag_skb, 0,
3411 			   rx_refill_ring->bufs_max * 3, GFP_ATOMIC);
3412 	spin_unlock_bh(&rx_refill_ring->idr_lock);
3413 	if (buf_id < 0) {
3414 		ret = -ENOMEM;
3415 		goto err_unmap_dma;
3416 	}
3417 
3418 	ATH11K_SKB_RXCB(defrag_skb)->paddr = paddr;
3419 	cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, dp->mac_id) |
3420 		 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
3421 
3422 	ath11k_hal_rx_buf_addr_info_set(msdu0, paddr, cookie, HAL_RX_BUF_RBM_SW3_BM);
3423 
3424 	/* Fill mpdu details into reo entrace ring */
3425 	srng = &ab->hal.srng_list[ab->dp.reo_reinject_ring.ring_id];
3426 
3427 	spin_lock_bh(&srng->lock);
3428 	ath11k_hal_srng_access_begin(ab, srng);
3429 
3430 	reo_ent_ring = (struct hal_reo_entrance_ring *)
3431 			ath11k_hal_srng_src_get_next_entry(ab, srng);
3432 	if (!reo_ent_ring) {
3433 		ath11k_hal_srng_access_end(ab, srng);
3434 		spin_unlock_bh(&srng->lock);
3435 		ret = -ENOSPC;
3436 		goto err_free_idr;
3437 	}
3438 	memset(reo_ent_ring, 0, sizeof(*reo_ent_ring));
3439 
3440 	ath11k_hal_rx_reo_ent_paddr_get(ab, reo_dest_ring, &paddr, &desc_bank);
3441 	ath11k_hal_rx_buf_addr_info_set(reo_ent_ring, paddr, desc_bank,
3442 					HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST);
3443 
3444 	mpdu_info = FIELD_PREP(RX_MPDU_DESC_INFO0_MSDU_COUNT, 1) |
3445 		    FIELD_PREP(RX_MPDU_DESC_INFO0_SEQ_NUM, rx_tid->cur_sn) |
3446 		    FIELD_PREP(RX_MPDU_DESC_INFO0_FRAG_FLAG, 0) |
3447 		    FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_SA, 1) |
3448 		    FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_DA, 1) |
3449 		    FIELD_PREP(RX_MPDU_DESC_INFO0_RAW_MPDU, 1) |
3450 		    FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_PN, 1);
3451 
3452 	reo_ent_ring->rx_mpdu_info.info0 = mpdu_info;
3453 	reo_ent_ring->rx_mpdu_info.meta_data = reo_dest_ring->rx_mpdu_info.meta_data;
3454 	reo_ent_ring->queue_addr_lo = reo_dest_ring->queue_addr_lo;
3455 	reo_ent_ring->info0 = FIELD_PREP(HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI,
3456 					 FIELD_GET(HAL_REO_DEST_RING_INFO0_QUEUE_ADDR_HI,
3457 						   reo_dest_ring->info0)) |
3458 			      FIELD_PREP(HAL_REO_ENTR_RING_INFO0_DEST_IND, dst_idx);
3459 	ath11k_hal_srng_access_end(ab, srng);
3460 	spin_unlock_bh(&srng->lock);
3461 
3462 	return 0;
3463 
3464 err_free_idr:
3465 	spin_lock_bh(&rx_refill_ring->idr_lock);
3466 	idr_remove(&rx_refill_ring->bufs_idr, buf_id);
3467 	spin_unlock_bh(&rx_refill_ring->idr_lock);
3468 err_unmap_dma:
3469 	dma_unmap_single(ab->dev, paddr, defrag_skb->len + skb_tailroom(defrag_skb),
3470 			 DMA_TO_DEVICE);
3471 	return ret;
3472 }
3473 
3474 static int ath11k_dp_rx_h_cmp_frags(struct ath11k *ar,
3475 				    struct sk_buff *a, struct sk_buff *b)
3476 {
3477 	int frag1, frag2;
3478 
3479 	frag1 = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, a);
3480 	frag2 = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, b);
3481 
3482 	return frag1 - frag2;
3483 }
3484 
3485 static void ath11k_dp_rx_h_sort_frags(struct ath11k *ar,
3486 				      struct sk_buff_head *frag_list,
3487 				      struct sk_buff *cur_frag)
3488 {
3489 	struct sk_buff *skb;
3490 	int cmp;
3491 
3492 	skb_queue_walk(frag_list, skb) {
3493 		cmp = ath11k_dp_rx_h_cmp_frags(ar, skb, cur_frag);
3494 		if (cmp < 0)
3495 			continue;
3496 		__skb_queue_before(frag_list, skb, cur_frag);
3497 		return;
3498 	}
3499 	__skb_queue_tail(frag_list, cur_frag);
3500 }
3501 
3502 static u64 ath11k_dp_rx_h_get_pn(struct ath11k *ar, struct sk_buff *skb)
3503 {
3504 	struct ieee80211_hdr *hdr;
3505 	u64 pn = 0;
3506 	u8 *ehdr;
3507 	u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3508 
3509 	hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz);
3510 	ehdr = skb->data + hal_rx_desc_sz + ieee80211_hdrlen(hdr->frame_control);
3511 
3512 	pn = ehdr[0];
3513 	pn |= (u64)ehdr[1] << 8;
3514 	pn |= (u64)ehdr[4] << 16;
3515 	pn |= (u64)ehdr[5] << 24;
3516 	pn |= (u64)ehdr[6] << 32;
3517 	pn |= (u64)ehdr[7] << 40;
3518 
3519 	return pn;
3520 }
3521 
3522 static bool
3523 ath11k_dp_rx_h_defrag_validate_incr_pn(struct ath11k *ar, struct dp_rx_tid *rx_tid)
3524 {
3525 	enum hal_encrypt_type encrypt_type;
3526 	struct sk_buff *first_frag, *skb;
3527 	struct hal_rx_desc *desc;
3528 	u64 last_pn;
3529 	u64 cur_pn;
3530 
3531 	first_frag = skb_peek(&rx_tid->rx_frags);
3532 	desc = (struct hal_rx_desc *)first_frag->data;
3533 
3534 	encrypt_type = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, desc);
3535 	if (encrypt_type != HAL_ENCRYPT_TYPE_CCMP_128 &&
3536 	    encrypt_type != HAL_ENCRYPT_TYPE_CCMP_256 &&
3537 	    encrypt_type != HAL_ENCRYPT_TYPE_GCMP_128 &&
3538 	    encrypt_type != HAL_ENCRYPT_TYPE_AES_GCMP_256)
3539 		return true;
3540 
3541 	last_pn = ath11k_dp_rx_h_get_pn(ar, first_frag);
3542 	skb_queue_walk(&rx_tid->rx_frags, skb) {
3543 		if (skb == first_frag)
3544 			continue;
3545 
3546 		cur_pn = ath11k_dp_rx_h_get_pn(ar, skb);
3547 		if (cur_pn != last_pn + 1)
3548 			return false;
3549 		last_pn = cur_pn;
3550 	}
3551 	return true;
3552 }
3553 
3554 static int ath11k_dp_rx_frag_h_mpdu(struct ath11k *ar,
3555 				    struct sk_buff *msdu,
3556 				    u32 *ring_desc)
3557 {
3558 	struct ath11k_base *ab = ar->ab;
3559 	struct hal_rx_desc *rx_desc;
3560 	struct ath11k_peer *peer;
3561 	struct dp_rx_tid *rx_tid;
3562 	struct sk_buff *defrag_skb = NULL;
3563 	u32 peer_id;
3564 	u16 seqno, frag_no;
3565 	u8 tid;
3566 	int ret = 0;
3567 	bool more_frags;
3568 	bool is_mcbc;
3569 
3570 	rx_desc = (struct hal_rx_desc *)msdu->data;
3571 	peer_id = ath11k_dp_rx_h_mpdu_start_peer_id(ar->ab, rx_desc);
3572 	tid = ath11k_dp_rx_h_mpdu_start_tid(ar->ab, rx_desc);
3573 	seqno = ath11k_dp_rx_h_mpdu_start_seq_no(ar->ab, rx_desc);
3574 	frag_no = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, msdu);
3575 	more_frags = ath11k_dp_rx_h_mpdu_start_more_frags(ar->ab, msdu);
3576 	is_mcbc = ath11k_dp_rx_h_attn_is_mcbc(ar->ab, rx_desc);
3577 
3578 	/* Multicast/Broadcast fragments are not expected */
3579 	if (is_mcbc)
3580 		return -EINVAL;
3581 
3582 	if (!ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(ar->ab, rx_desc) ||
3583 	    !ath11k_dp_rx_h_mpdu_start_fc_valid(ar->ab, rx_desc) ||
3584 	    tid > IEEE80211_NUM_TIDS)
3585 		return -EINVAL;
3586 
3587 	/* received unfragmented packet in reo
3588 	 * exception ring, this shouldn't happen
3589 	 * as these packets typically come from
3590 	 * reo2sw srngs.
3591 	 */
3592 	if (WARN_ON_ONCE(!frag_no && !more_frags))
3593 		return -EINVAL;
3594 
3595 	spin_lock_bh(&ab->base_lock);
3596 	peer = ath11k_peer_find_by_id(ab, peer_id);
3597 	if (!peer) {
3598 		ath11k_warn(ab, "failed to find the peer to de-fragment received fragment peer_id %d\n",
3599 			    peer_id);
3600 		ret = -ENOENT;
3601 		goto out_unlock;
3602 	}
3603 	rx_tid = &peer->rx_tid[tid];
3604 
3605 	if ((!skb_queue_empty(&rx_tid->rx_frags) && seqno != rx_tid->cur_sn) ||
3606 	    skb_queue_empty(&rx_tid->rx_frags)) {
3607 		/* Flush stored fragments and start a new sequence */
3608 		ath11k_dp_rx_frags_cleanup(rx_tid, true);
3609 		rx_tid->cur_sn = seqno;
3610 	}
3611 
3612 	if (rx_tid->rx_frag_bitmap & BIT(frag_no)) {
3613 		/* Fragment already present */
3614 		ret = -EINVAL;
3615 		goto out_unlock;
3616 	}
3617 
3618 	if (frag_no > __fls(rx_tid->rx_frag_bitmap))
3619 		__skb_queue_tail(&rx_tid->rx_frags, msdu);
3620 	else
3621 		ath11k_dp_rx_h_sort_frags(ar, &rx_tid->rx_frags, msdu);
3622 
3623 	rx_tid->rx_frag_bitmap |= BIT(frag_no);
3624 	if (!more_frags)
3625 		rx_tid->last_frag_no = frag_no;
3626 
3627 	if (frag_no == 0) {
3628 		rx_tid->dst_ring_desc = kmemdup(ring_desc,
3629 						sizeof(*rx_tid->dst_ring_desc),
3630 						GFP_ATOMIC);
3631 		if (!rx_tid->dst_ring_desc) {
3632 			ret = -ENOMEM;
3633 			goto out_unlock;
3634 		}
3635 	} else {
3636 		ath11k_dp_rx_link_desc_return(ab, ring_desc,
3637 					      HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3638 	}
3639 
3640 	if (!rx_tid->last_frag_no ||
3641 	    rx_tid->rx_frag_bitmap != GENMASK(rx_tid->last_frag_no, 0)) {
3642 		mod_timer(&rx_tid->frag_timer, jiffies +
3643 					       ATH11K_DP_RX_FRAGMENT_TIMEOUT_MS);
3644 		goto out_unlock;
3645 	}
3646 
3647 	spin_unlock_bh(&ab->base_lock);
3648 	del_timer_sync(&rx_tid->frag_timer);
3649 	spin_lock_bh(&ab->base_lock);
3650 
3651 	peer = ath11k_peer_find_by_id(ab, peer_id);
3652 	if (!peer)
3653 		goto err_frags_cleanup;
3654 
3655 	if (!ath11k_dp_rx_h_defrag_validate_incr_pn(ar, rx_tid))
3656 		goto err_frags_cleanup;
3657 
3658 	if (ath11k_dp_rx_h_defrag(ar, peer, rx_tid, &defrag_skb))
3659 		goto err_frags_cleanup;
3660 
3661 	if (!defrag_skb)
3662 		goto err_frags_cleanup;
3663 
3664 	if (ath11k_dp_rx_h_defrag_reo_reinject(ar, rx_tid, defrag_skb))
3665 		goto err_frags_cleanup;
3666 
3667 	ath11k_dp_rx_frags_cleanup(rx_tid, false);
3668 	goto out_unlock;
3669 
3670 err_frags_cleanup:
3671 	dev_kfree_skb_any(defrag_skb);
3672 	ath11k_dp_rx_frags_cleanup(rx_tid, true);
3673 out_unlock:
3674 	spin_unlock_bh(&ab->base_lock);
3675 	return ret;
3676 }
3677 
3678 static int
3679 ath11k_dp_process_rx_err_buf(struct ath11k *ar, u32 *ring_desc, int buf_id, bool drop)
3680 {
3681 	struct ath11k_pdev_dp *dp = &ar->dp;
3682 	struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
3683 	struct sk_buff *msdu;
3684 	struct ath11k_skb_rxcb *rxcb;
3685 	struct hal_rx_desc *rx_desc;
3686 	u8 *hdr_status;
3687 	u16 msdu_len;
3688 	u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3689 
3690 	spin_lock_bh(&rx_ring->idr_lock);
3691 	msdu = idr_find(&rx_ring->bufs_idr, buf_id);
3692 	if (!msdu) {
3693 		ath11k_warn(ar->ab, "rx err buf with invalid buf_id %d\n",
3694 			    buf_id);
3695 		spin_unlock_bh(&rx_ring->idr_lock);
3696 		return -EINVAL;
3697 	}
3698 
3699 	idr_remove(&rx_ring->bufs_idr, buf_id);
3700 	spin_unlock_bh(&rx_ring->idr_lock);
3701 
3702 	rxcb = ATH11K_SKB_RXCB(msdu);
3703 	dma_unmap_single(ar->ab->dev, rxcb->paddr,
3704 			 msdu->len + skb_tailroom(msdu),
3705 			 DMA_FROM_DEVICE);
3706 
3707 	if (drop) {
3708 		dev_kfree_skb_any(msdu);
3709 		return 0;
3710 	}
3711 
3712 	rcu_read_lock();
3713 	if (!rcu_dereference(ar->ab->pdevs_active[ar->pdev_idx])) {
3714 		dev_kfree_skb_any(msdu);
3715 		goto exit;
3716 	}
3717 
3718 	if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) {
3719 		dev_kfree_skb_any(msdu);
3720 		goto exit;
3721 	}
3722 
3723 	rx_desc = (struct hal_rx_desc *)msdu->data;
3724 	msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, rx_desc);
3725 	if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) {
3726 		hdr_status = ath11k_dp_rx_h_80211_hdr(ar->ab, rx_desc);
3727 		ath11k_warn(ar->ab, "invalid msdu leng %u", msdu_len);
3728 		ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", hdr_status,
3729 				sizeof(struct ieee80211_hdr));
3730 		ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", rx_desc,
3731 				sizeof(struct hal_rx_desc));
3732 		dev_kfree_skb_any(msdu);
3733 		goto exit;
3734 	}
3735 
3736 	skb_put(msdu, hal_rx_desc_sz + msdu_len);
3737 
3738 	if (ath11k_dp_rx_frag_h_mpdu(ar, msdu, ring_desc)) {
3739 		dev_kfree_skb_any(msdu);
3740 		ath11k_dp_rx_link_desc_return(ar->ab, ring_desc,
3741 					      HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3742 	}
3743 exit:
3744 	rcu_read_unlock();
3745 	return 0;
3746 }
3747 
3748 int ath11k_dp_process_rx_err(struct ath11k_base *ab, struct napi_struct *napi,
3749 			     int budget)
3750 {
3751 	u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC];
3752 	struct dp_link_desc_bank *link_desc_banks;
3753 	enum hal_rx_buf_return_buf_manager rbm;
3754 	int tot_n_bufs_reaped, quota, ret, i;
3755 	int n_bufs_reaped[MAX_RADIOS] = {0};
3756 	struct dp_rxdma_ring *rx_ring;
3757 	struct dp_srng *reo_except;
3758 	u32 desc_bank, num_msdus;
3759 	struct hal_srng *srng;
3760 	struct ath11k_dp *dp;
3761 	void *link_desc_va;
3762 	int buf_id, mac_id;
3763 	struct ath11k *ar;
3764 	dma_addr_t paddr;
3765 	u32 *desc;
3766 	bool is_frag;
3767 	u8 drop = 0;
3768 
3769 	tot_n_bufs_reaped = 0;
3770 	quota = budget;
3771 
3772 	dp = &ab->dp;
3773 	reo_except = &dp->reo_except_ring;
3774 	link_desc_banks = dp->link_desc_banks;
3775 
3776 	srng = &ab->hal.srng_list[reo_except->ring_id];
3777 
3778 	spin_lock_bh(&srng->lock);
3779 
3780 	ath11k_hal_srng_access_begin(ab, srng);
3781 
3782 	while (budget &&
3783 	       (desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
3784 		struct hal_reo_dest_ring *reo_desc = (struct hal_reo_dest_ring *)desc;
3785 
3786 		ab->soc_stats.err_ring_pkts++;
3787 		ret = ath11k_hal_desc_reo_parse_err(ab, desc, &paddr,
3788 						    &desc_bank);
3789 		if (ret) {
3790 			ath11k_warn(ab, "failed to parse error reo desc %d\n",
3791 				    ret);
3792 			continue;
3793 		}
3794 		link_desc_va = link_desc_banks[desc_bank].vaddr +
3795 			       (paddr - link_desc_banks[desc_bank].paddr);
3796 		ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus, msdu_cookies,
3797 						 &rbm);
3798 		if (rbm != HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST &&
3799 		    rbm != HAL_RX_BUF_RBM_SW3_BM) {
3800 			ab->soc_stats.invalid_rbm++;
3801 			ath11k_warn(ab, "invalid return buffer manager %d\n", rbm);
3802 			ath11k_dp_rx_link_desc_return(ab, desc,
3803 						      HAL_WBM_REL_BM_ACT_REL_MSDU);
3804 			continue;
3805 		}
3806 
3807 		is_frag = !!(reo_desc->rx_mpdu_info.info0 & RX_MPDU_DESC_INFO0_FRAG_FLAG);
3808 
3809 		/* Process only rx fragments with one msdu per link desc below, and drop
3810 		 * msdu's indicated due to error reasons.
3811 		 */
3812 		if (!is_frag || num_msdus > 1) {
3813 			drop = 1;
3814 			/* Return the link desc back to wbm idle list */
3815 			ath11k_dp_rx_link_desc_return(ab, desc,
3816 						      HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3817 		}
3818 
3819 		for (i = 0; i < num_msdus; i++) {
3820 			buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
3821 					   msdu_cookies[i]);
3822 
3823 			mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID,
3824 					   msdu_cookies[i]);
3825 
3826 			ar = ab->pdevs[mac_id].ar;
3827 
3828 			if (!ath11k_dp_process_rx_err_buf(ar, desc, buf_id, drop)) {
3829 				n_bufs_reaped[mac_id]++;
3830 				tot_n_bufs_reaped++;
3831 			}
3832 		}
3833 
3834 		if (tot_n_bufs_reaped >= quota) {
3835 			tot_n_bufs_reaped = quota;
3836 			goto exit;
3837 		}
3838 
3839 		budget = quota - tot_n_bufs_reaped;
3840 	}
3841 
3842 exit:
3843 	ath11k_hal_srng_access_end(ab, srng);
3844 
3845 	spin_unlock_bh(&srng->lock);
3846 
3847 	for (i = 0; i <  ab->num_radios; i++) {
3848 		if (!n_bufs_reaped[i])
3849 			continue;
3850 
3851 		ar = ab->pdevs[i].ar;
3852 		rx_ring = &ar->dp.rx_refill_buf_ring;
3853 
3854 		ath11k_dp_rxbufs_replenish(ab, i, rx_ring, n_bufs_reaped[i],
3855 					   HAL_RX_BUF_RBM_SW3_BM);
3856 	}
3857 
3858 	return tot_n_bufs_reaped;
3859 }
3860 
3861 static void ath11k_dp_rx_null_q_desc_sg_drop(struct ath11k *ar,
3862 					     int msdu_len,
3863 					     struct sk_buff_head *msdu_list)
3864 {
3865 	struct sk_buff *skb, *tmp;
3866 	struct ath11k_skb_rxcb *rxcb;
3867 	int n_buffs;
3868 
3869 	n_buffs = DIV_ROUND_UP(msdu_len,
3870 			       (DP_RX_BUFFER_SIZE - ar->ab->hw_params.hal_desc_sz));
3871 
3872 	skb_queue_walk_safe(msdu_list, skb, tmp) {
3873 		rxcb = ATH11K_SKB_RXCB(skb);
3874 		if (rxcb->err_rel_src == HAL_WBM_REL_SRC_MODULE_REO &&
3875 		    rxcb->err_code == HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO) {
3876 			if (!n_buffs)
3877 				break;
3878 			__skb_unlink(skb, msdu_list);
3879 			dev_kfree_skb_any(skb);
3880 			n_buffs--;
3881 		}
3882 	}
3883 }
3884 
3885 static int ath11k_dp_rx_h_null_q_desc(struct ath11k *ar, struct sk_buff *msdu,
3886 				      struct ieee80211_rx_status *status,
3887 				      struct sk_buff_head *msdu_list)
3888 {
3889 	u16 msdu_len;
3890 	struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data;
3891 	struct rx_attention *rx_attention;
3892 	u8 l3pad_bytes;
3893 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
3894 	u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3895 
3896 	msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, desc);
3897 
3898 	if (!rxcb->is_frag && ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE)) {
3899 		/* First buffer will be freed by the caller, so deduct it's length */
3900 		msdu_len = msdu_len - (DP_RX_BUFFER_SIZE - hal_rx_desc_sz);
3901 		ath11k_dp_rx_null_q_desc_sg_drop(ar, msdu_len, msdu_list);
3902 		return -EINVAL;
3903 	}
3904 
3905 	rx_attention = ath11k_dp_rx_get_attention(ar->ab, desc);
3906 	if (!ath11k_dp_rx_h_attn_msdu_done(rx_attention)) {
3907 		ath11k_warn(ar->ab,
3908 			    "msdu_done bit not set in null_q_des processing\n");
3909 		__skb_queue_purge(msdu_list);
3910 		return -EIO;
3911 	}
3912 
3913 	/* Handle NULL queue descriptor violations arising out a missing
3914 	 * REO queue for a given peer or a given TID. This typically
3915 	 * may happen if a packet is received on a QOS enabled TID before the
3916 	 * ADDBA negotiation for that TID, when the TID queue is setup. Or
3917 	 * it may also happen for MC/BC frames if they are not routed to the
3918 	 * non-QOS TID queue, in the absence of any other default TID queue.
3919 	 * This error can show up both in a REO destination or WBM release ring.
3920 	 */
3921 
3922 	rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ar->ab, desc);
3923 	rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ar->ab, desc);
3924 
3925 	if (rxcb->is_frag) {
3926 		skb_pull(msdu, hal_rx_desc_sz);
3927 	} else {
3928 		l3pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, desc);
3929 
3930 		if ((hal_rx_desc_sz + l3pad_bytes + msdu_len) > DP_RX_BUFFER_SIZE)
3931 			return -EINVAL;
3932 
3933 		skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len);
3934 		skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes);
3935 	}
3936 	ath11k_dp_rx_h_ppdu(ar, desc, status);
3937 
3938 	ath11k_dp_rx_h_mpdu(ar, msdu, desc, status);
3939 
3940 	rxcb->tid = ath11k_dp_rx_h_mpdu_start_tid(ar->ab, desc);
3941 
3942 	/* Please note that caller will having the access to msdu and completing
3943 	 * rx with mac80211. Need not worry about cleaning up amsdu_list.
3944 	 */
3945 
3946 	return 0;
3947 }
3948 
3949 static bool ath11k_dp_rx_h_reo_err(struct ath11k *ar, struct sk_buff *msdu,
3950 				   struct ieee80211_rx_status *status,
3951 				   struct sk_buff_head *msdu_list)
3952 {
3953 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
3954 	bool drop = false;
3955 
3956 	ar->ab->soc_stats.reo_error[rxcb->err_code]++;
3957 
3958 	switch (rxcb->err_code) {
3959 	case HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO:
3960 		if (ath11k_dp_rx_h_null_q_desc(ar, msdu, status, msdu_list))
3961 			drop = true;
3962 		break;
3963 	case HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED:
3964 		/* TODO: Do not drop PN failed packets in the driver;
3965 		 * instead, it is good to drop such packets in mac80211
3966 		 * after incrementing the replay counters.
3967 		 */
3968 		fallthrough;
3969 	default:
3970 		/* TODO: Review other errors and process them to mac80211
3971 		 * as appropriate.
3972 		 */
3973 		drop = true;
3974 		break;
3975 	}
3976 
3977 	return drop;
3978 }
3979 
3980 static void ath11k_dp_rx_h_tkip_mic_err(struct ath11k *ar, struct sk_buff *msdu,
3981 					struct ieee80211_rx_status *status)
3982 {
3983 	u16 msdu_len;
3984 	struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data;
3985 	u8 l3pad_bytes;
3986 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
3987 	u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3988 
3989 	rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ar->ab, desc);
3990 	rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ar->ab, desc);
3991 
3992 	l3pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, desc);
3993 	msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, desc);
3994 	skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len);
3995 	skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes);
3996 
3997 	ath11k_dp_rx_h_ppdu(ar, desc, status);
3998 
3999 	status->flag |= (RX_FLAG_MMIC_STRIPPED | RX_FLAG_MMIC_ERROR |
4000 			 RX_FLAG_DECRYPTED);
4001 
4002 	ath11k_dp_rx_h_undecap(ar, msdu, desc,
4003 			       HAL_ENCRYPT_TYPE_TKIP_MIC, status, false);
4004 }
4005 
4006 static bool ath11k_dp_rx_h_rxdma_err(struct ath11k *ar,  struct sk_buff *msdu,
4007 				     struct ieee80211_rx_status *status)
4008 {
4009 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
4010 	bool drop = false;
4011 
4012 	ar->ab->soc_stats.rxdma_error[rxcb->err_code]++;
4013 
4014 	switch (rxcb->err_code) {
4015 	case HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR:
4016 		ath11k_dp_rx_h_tkip_mic_err(ar, msdu, status);
4017 		break;
4018 	default:
4019 		/* TODO: Review other rxdma error code to check if anything is
4020 		 * worth reporting to mac80211
4021 		 */
4022 		drop = true;
4023 		break;
4024 	}
4025 
4026 	return drop;
4027 }
4028 
4029 static void ath11k_dp_rx_wbm_err(struct ath11k *ar,
4030 				 struct napi_struct *napi,
4031 				 struct sk_buff *msdu,
4032 				 struct sk_buff_head *msdu_list)
4033 {
4034 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
4035 	struct ieee80211_rx_status rxs = {0};
4036 	bool drop = true;
4037 
4038 	switch (rxcb->err_rel_src) {
4039 	case HAL_WBM_REL_SRC_MODULE_REO:
4040 		drop = ath11k_dp_rx_h_reo_err(ar, msdu, &rxs, msdu_list);
4041 		break;
4042 	case HAL_WBM_REL_SRC_MODULE_RXDMA:
4043 		drop = ath11k_dp_rx_h_rxdma_err(ar, msdu, &rxs);
4044 		break;
4045 	default:
4046 		/* msdu will get freed */
4047 		break;
4048 	}
4049 
4050 	if (drop) {
4051 		dev_kfree_skb_any(msdu);
4052 		return;
4053 	}
4054 
4055 	ath11k_dp_rx_deliver_msdu(ar, napi, msdu, &rxs);
4056 }
4057 
4058 int ath11k_dp_rx_process_wbm_err(struct ath11k_base *ab,
4059 				 struct napi_struct *napi, int budget)
4060 {
4061 	struct ath11k *ar;
4062 	struct ath11k_dp *dp = &ab->dp;
4063 	struct dp_rxdma_ring *rx_ring;
4064 	struct hal_rx_wbm_rel_info err_info;
4065 	struct hal_srng *srng;
4066 	struct sk_buff *msdu;
4067 	struct sk_buff_head msdu_list[MAX_RADIOS];
4068 	struct ath11k_skb_rxcb *rxcb;
4069 	u32 *rx_desc;
4070 	int buf_id, mac_id;
4071 	int num_buffs_reaped[MAX_RADIOS] = {0};
4072 	int total_num_buffs_reaped = 0;
4073 	int ret, i;
4074 
4075 	for (i = 0; i < ab->num_radios; i++)
4076 		__skb_queue_head_init(&msdu_list[i]);
4077 
4078 	srng = &ab->hal.srng_list[dp->rx_rel_ring.ring_id];
4079 
4080 	spin_lock_bh(&srng->lock);
4081 
4082 	ath11k_hal_srng_access_begin(ab, srng);
4083 
4084 	while (budget) {
4085 		rx_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng);
4086 		if (!rx_desc)
4087 			break;
4088 
4089 		ret = ath11k_hal_wbm_desc_parse_err(ab, rx_desc, &err_info);
4090 		if (ret) {
4091 			ath11k_warn(ab,
4092 				    "failed to parse rx error in wbm_rel ring desc %d\n",
4093 				    ret);
4094 			continue;
4095 		}
4096 
4097 		buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, err_info.cookie);
4098 		mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, err_info.cookie);
4099 
4100 		ar = ab->pdevs[mac_id].ar;
4101 		rx_ring = &ar->dp.rx_refill_buf_ring;
4102 
4103 		spin_lock_bh(&rx_ring->idr_lock);
4104 		msdu = idr_find(&rx_ring->bufs_idr, buf_id);
4105 		if (!msdu) {
4106 			ath11k_warn(ab, "frame rx with invalid buf_id %d pdev %d\n",
4107 				    buf_id, mac_id);
4108 			spin_unlock_bh(&rx_ring->idr_lock);
4109 			continue;
4110 		}
4111 
4112 		idr_remove(&rx_ring->bufs_idr, buf_id);
4113 		spin_unlock_bh(&rx_ring->idr_lock);
4114 
4115 		rxcb = ATH11K_SKB_RXCB(msdu);
4116 		dma_unmap_single(ab->dev, rxcb->paddr,
4117 				 msdu->len + skb_tailroom(msdu),
4118 				 DMA_FROM_DEVICE);
4119 
4120 		num_buffs_reaped[mac_id]++;
4121 		total_num_buffs_reaped++;
4122 		budget--;
4123 
4124 		if (err_info.push_reason !=
4125 		    HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
4126 			dev_kfree_skb_any(msdu);
4127 			continue;
4128 		}
4129 
4130 		rxcb->err_rel_src = err_info.err_rel_src;
4131 		rxcb->err_code = err_info.err_code;
4132 		rxcb->rx_desc = (struct hal_rx_desc *)msdu->data;
4133 		__skb_queue_tail(&msdu_list[mac_id], msdu);
4134 	}
4135 
4136 	ath11k_hal_srng_access_end(ab, srng);
4137 
4138 	spin_unlock_bh(&srng->lock);
4139 
4140 	if (!total_num_buffs_reaped)
4141 		goto done;
4142 
4143 	for (i = 0; i <  ab->num_radios; i++) {
4144 		if (!num_buffs_reaped[i])
4145 			continue;
4146 
4147 		ar = ab->pdevs[i].ar;
4148 		rx_ring = &ar->dp.rx_refill_buf_ring;
4149 
4150 		ath11k_dp_rxbufs_replenish(ab, i, rx_ring, num_buffs_reaped[i],
4151 					   HAL_RX_BUF_RBM_SW3_BM);
4152 	}
4153 
4154 	rcu_read_lock();
4155 	for (i = 0; i <  ab->num_radios; i++) {
4156 		if (!rcu_dereference(ab->pdevs_active[i])) {
4157 			__skb_queue_purge(&msdu_list[i]);
4158 			continue;
4159 		}
4160 
4161 		ar = ab->pdevs[i].ar;
4162 
4163 		if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) {
4164 			__skb_queue_purge(&msdu_list[i]);
4165 			continue;
4166 		}
4167 
4168 		while ((msdu = __skb_dequeue(&msdu_list[i])) != NULL)
4169 			ath11k_dp_rx_wbm_err(ar, napi, msdu, &msdu_list[i]);
4170 	}
4171 	rcu_read_unlock();
4172 done:
4173 	return total_num_buffs_reaped;
4174 }
4175 
4176 int ath11k_dp_process_rxdma_err(struct ath11k_base *ab, int mac_id, int budget)
4177 {
4178 	struct ath11k *ar;
4179 	struct dp_srng *err_ring;
4180 	struct dp_rxdma_ring *rx_ring;
4181 	struct dp_link_desc_bank *link_desc_banks = ab->dp.link_desc_banks;
4182 	struct hal_srng *srng;
4183 	u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC];
4184 	enum hal_rx_buf_return_buf_manager rbm;
4185 	enum hal_reo_entr_rxdma_ecode rxdma_err_code;
4186 	struct ath11k_skb_rxcb *rxcb;
4187 	struct sk_buff *skb;
4188 	struct hal_reo_entrance_ring *entr_ring;
4189 	void *desc;
4190 	int num_buf_freed = 0;
4191 	int quota = budget;
4192 	dma_addr_t paddr;
4193 	u32 desc_bank;
4194 	void *link_desc_va;
4195 	int num_msdus;
4196 	int i;
4197 	int buf_id;
4198 
4199 	ar = ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar;
4200 	err_ring = &ar->dp.rxdma_err_dst_ring[ath11k_hw_mac_id_to_srng_id(&ab->hw_params,
4201 									  mac_id)];
4202 	rx_ring = &ar->dp.rx_refill_buf_ring;
4203 
4204 	srng = &ab->hal.srng_list[err_ring->ring_id];
4205 
4206 	spin_lock_bh(&srng->lock);
4207 
4208 	ath11k_hal_srng_access_begin(ab, srng);
4209 
4210 	while (quota-- &&
4211 	       (desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
4212 		ath11k_hal_rx_reo_ent_paddr_get(ab, desc, &paddr, &desc_bank);
4213 
4214 		entr_ring = (struct hal_reo_entrance_ring *)desc;
4215 		rxdma_err_code =
4216 			FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE,
4217 				  entr_ring->info1);
4218 		ab->soc_stats.rxdma_error[rxdma_err_code]++;
4219 
4220 		link_desc_va = link_desc_banks[desc_bank].vaddr +
4221 			       (paddr - link_desc_banks[desc_bank].paddr);
4222 		ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus,
4223 						 msdu_cookies, &rbm);
4224 
4225 		for (i = 0; i < num_msdus; i++) {
4226 			buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
4227 					   msdu_cookies[i]);
4228 
4229 			spin_lock_bh(&rx_ring->idr_lock);
4230 			skb = idr_find(&rx_ring->bufs_idr, buf_id);
4231 			if (!skb) {
4232 				ath11k_warn(ab, "rxdma error with invalid buf_id %d\n",
4233 					    buf_id);
4234 				spin_unlock_bh(&rx_ring->idr_lock);
4235 				continue;
4236 			}
4237 
4238 			idr_remove(&rx_ring->bufs_idr, buf_id);
4239 			spin_unlock_bh(&rx_ring->idr_lock);
4240 
4241 			rxcb = ATH11K_SKB_RXCB(skb);
4242 			dma_unmap_single(ab->dev, rxcb->paddr,
4243 					 skb->len + skb_tailroom(skb),
4244 					 DMA_FROM_DEVICE);
4245 			dev_kfree_skb_any(skb);
4246 
4247 			num_buf_freed++;
4248 		}
4249 
4250 		ath11k_dp_rx_link_desc_return(ab, desc,
4251 					      HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
4252 	}
4253 
4254 	ath11k_hal_srng_access_end(ab, srng);
4255 
4256 	spin_unlock_bh(&srng->lock);
4257 
4258 	if (num_buf_freed)
4259 		ath11k_dp_rxbufs_replenish(ab, mac_id, rx_ring, num_buf_freed,
4260 					   HAL_RX_BUF_RBM_SW3_BM);
4261 
4262 	return budget - quota;
4263 }
4264 
4265 void ath11k_dp_process_reo_status(struct ath11k_base *ab)
4266 {
4267 	struct ath11k_dp *dp = &ab->dp;
4268 	struct hal_srng *srng;
4269 	struct dp_reo_cmd *cmd, *tmp;
4270 	bool found = false;
4271 	u32 *reo_desc;
4272 	u16 tag;
4273 	struct hal_reo_status reo_status;
4274 
4275 	srng = &ab->hal.srng_list[dp->reo_status_ring.ring_id];
4276 
4277 	memset(&reo_status, 0, sizeof(reo_status));
4278 
4279 	spin_lock_bh(&srng->lock);
4280 
4281 	ath11k_hal_srng_access_begin(ab, srng);
4282 
4283 	while ((reo_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
4284 		tag = FIELD_GET(HAL_SRNG_TLV_HDR_TAG, *reo_desc);
4285 
4286 		switch (tag) {
4287 		case HAL_REO_GET_QUEUE_STATS_STATUS:
4288 			ath11k_hal_reo_status_queue_stats(ab, reo_desc,
4289 							  &reo_status);
4290 			break;
4291 		case HAL_REO_FLUSH_QUEUE_STATUS:
4292 			ath11k_hal_reo_flush_queue_status(ab, reo_desc,
4293 							  &reo_status);
4294 			break;
4295 		case HAL_REO_FLUSH_CACHE_STATUS:
4296 			ath11k_hal_reo_flush_cache_status(ab, reo_desc,
4297 							  &reo_status);
4298 			break;
4299 		case HAL_REO_UNBLOCK_CACHE_STATUS:
4300 			ath11k_hal_reo_unblk_cache_status(ab, reo_desc,
4301 							  &reo_status);
4302 			break;
4303 		case HAL_REO_FLUSH_TIMEOUT_LIST_STATUS:
4304 			ath11k_hal_reo_flush_timeout_list_status(ab, reo_desc,
4305 								 &reo_status);
4306 			break;
4307 		case HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS:
4308 			ath11k_hal_reo_desc_thresh_reached_status(ab, reo_desc,
4309 								  &reo_status);
4310 			break;
4311 		case HAL_REO_UPDATE_RX_REO_QUEUE_STATUS:
4312 			ath11k_hal_reo_update_rx_reo_queue_status(ab, reo_desc,
4313 								  &reo_status);
4314 			break;
4315 		default:
4316 			ath11k_warn(ab, "Unknown reo status type %d\n", tag);
4317 			continue;
4318 		}
4319 
4320 		spin_lock_bh(&dp->reo_cmd_lock);
4321 		list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) {
4322 			if (reo_status.uniform_hdr.cmd_num == cmd->cmd_num) {
4323 				found = true;
4324 				list_del(&cmd->list);
4325 				break;
4326 			}
4327 		}
4328 		spin_unlock_bh(&dp->reo_cmd_lock);
4329 
4330 		if (found) {
4331 			cmd->handler(dp, (void *)&cmd->data,
4332 				     reo_status.uniform_hdr.cmd_status);
4333 			kfree(cmd);
4334 		}
4335 
4336 		found = false;
4337 	}
4338 
4339 	ath11k_hal_srng_access_end(ab, srng);
4340 
4341 	spin_unlock_bh(&srng->lock);
4342 }
4343 
4344 void ath11k_dp_rx_pdev_free(struct ath11k_base *ab, int mac_id)
4345 {
4346 	struct ath11k *ar = ab->pdevs[mac_id].ar;
4347 
4348 	ath11k_dp_rx_pdev_srng_free(ar);
4349 	ath11k_dp_rxdma_pdev_buf_free(ar);
4350 }
4351 
4352 int ath11k_dp_rx_pdev_alloc(struct ath11k_base *ab, int mac_id)
4353 {
4354 	struct ath11k *ar = ab->pdevs[mac_id].ar;
4355 	struct ath11k_pdev_dp *dp = &ar->dp;
4356 	u32 ring_id;
4357 	int i;
4358 	int ret;
4359 
4360 	ret = ath11k_dp_rx_pdev_srng_alloc(ar);
4361 	if (ret) {
4362 		ath11k_warn(ab, "failed to setup rx srngs\n");
4363 		return ret;
4364 	}
4365 
4366 	ret = ath11k_dp_rxdma_pdev_buf_setup(ar);
4367 	if (ret) {
4368 		ath11k_warn(ab, "failed to setup rxdma ring\n");
4369 		return ret;
4370 	}
4371 
4372 	ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id;
4373 	ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, mac_id, HAL_RXDMA_BUF);
4374 	if (ret) {
4375 		ath11k_warn(ab, "failed to configure rx_refill_buf_ring %d\n",
4376 			    ret);
4377 		return ret;
4378 	}
4379 
4380 	if (ab->hw_params.rx_mac_buf_ring) {
4381 		for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
4382 			ring_id = dp->rx_mac_buf_ring[i].ring_id;
4383 			ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
4384 							  mac_id + i, HAL_RXDMA_BUF);
4385 			if (ret) {
4386 				ath11k_warn(ab, "failed to configure rx_mac_buf_ring%d %d\n",
4387 					    i, ret);
4388 				return ret;
4389 			}
4390 		}
4391 	}
4392 
4393 	for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
4394 		ring_id = dp->rxdma_err_dst_ring[i].ring_id;
4395 		ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
4396 						  mac_id + i, HAL_RXDMA_DST);
4397 		if (ret) {
4398 			ath11k_warn(ab, "failed to configure rxdma_err_dest_ring%d %d\n",
4399 				    i, ret);
4400 			return ret;
4401 		}
4402 	}
4403 
4404 	if (!ab->hw_params.rxdma1_enable)
4405 		goto config_refill_ring;
4406 
4407 	ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id;
4408 	ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
4409 					  mac_id, HAL_RXDMA_MONITOR_BUF);
4410 	if (ret) {
4411 		ath11k_warn(ab, "failed to configure rxdma_mon_buf_ring %d\n",
4412 			    ret);
4413 		return ret;
4414 	}
4415 	ret = ath11k_dp_tx_htt_srng_setup(ab,
4416 					  dp->rxdma_mon_dst_ring.ring_id,
4417 					  mac_id, HAL_RXDMA_MONITOR_DST);
4418 	if (ret) {
4419 		ath11k_warn(ab, "failed to configure rxdma_mon_dst_ring %d\n",
4420 			    ret);
4421 		return ret;
4422 	}
4423 	ret = ath11k_dp_tx_htt_srng_setup(ab,
4424 					  dp->rxdma_mon_desc_ring.ring_id,
4425 					  mac_id, HAL_RXDMA_MONITOR_DESC);
4426 	if (ret) {
4427 		ath11k_warn(ab, "failed to configure rxdma_mon_dst_ring %d\n",
4428 			    ret);
4429 		return ret;
4430 	}
4431 
4432 config_refill_ring:
4433 	for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
4434 		ring_id = dp->rx_mon_status_refill_ring[i].refill_buf_ring.ring_id;
4435 		ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, mac_id + i,
4436 						  HAL_RXDMA_MONITOR_STATUS);
4437 		if (ret) {
4438 			ath11k_warn(ab,
4439 				    "failed to configure mon_status_refill_ring%d %d\n",
4440 				    i, ret);
4441 			return ret;
4442 		}
4443 	}
4444 
4445 	return 0;
4446 }
4447 
4448 static void ath11k_dp_mon_set_frag_len(u32 *total_len, u32 *frag_len)
4449 {
4450 	if (*total_len >= (DP_RX_BUFFER_SIZE - sizeof(struct hal_rx_desc))) {
4451 		*frag_len = DP_RX_BUFFER_SIZE - sizeof(struct hal_rx_desc);
4452 		*total_len -= *frag_len;
4453 	} else {
4454 		*frag_len = *total_len;
4455 		*total_len = 0;
4456 	}
4457 }
4458 
4459 static
4460 int ath11k_dp_rx_monitor_link_desc_return(struct ath11k *ar,
4461 					  void *p_last_buf_addr_info,
4462 					  u8 mac_id)
4463 {
4464 	struct ath11k_pdev_dp *dp = &ar->dp;
4465 	struct dp_srng *dp_srng;
4466 	void *hal_srng;
4467 	void *src_srng_desc;
4468 	int ret = 0;
4469 
4470 	if (ar->ab->hw_params.rxdma1_enable) {
4471 		dp_srng = &dp->rxdma_mon_desc_ring;
4472 		hal_srng = &ar->ab->hal.srng_list[dp_srng->ring_id];
4473 	} else {
4474 		dp_srng = &ar->ab->dp.wbm_desc_rel_ring;
4475 		hal_srng = &ar->ab->hal.srng_list[dp_srng->ring_id];
4476 	}
4477 
4478 	ath11k_hal_srng_access_begin(ar->ab, hal_srng);
4479 
4480 	src_srng_desc = ath11k_hal_srng_src_get_next_entry(ar->ab, hal_srng);
4481 
4482 	if (src_srng_desc) {
4483 		struct ath11k_buffer_addr *src_desc =
4484 				(struct ath11k_buffer_addr *)src_srng_desc;
4485 
4486 		*src_desc = *((struct ath11k_buffer_addr *)p_last_buf_addr_info);
4487 	} else {
4488 		ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4489 			   "Monitor Link Desc Ring %d Full", mac_id);
4490 		ret = -ENOMEM;
4491 	}
4492 
4493 	ath11k_hal_srng_access_end(ar->ab, hal_srng);
4494 	return ret;
4495 }
4496 
4497 static
4498 void ath11k_dp_rx_mon_next_link_desc_get(void *rx_msdu_link_desc,
4499 					 dma_addr_t *paddr, u32 *sw_cookie,
4500 					 u8 *rbm,
4501 					 void **pp_buf_addr_info)
4502 {
4503 	struct hal_rx_msdu_link *msdu_link =
4504 			(struct hal_rx_msdu_link *)rx_msdu_link_desc;
4505 	struct ath11k_buffer_addr *buf_addr_info;
4506 
4507 	buf_addr_info = (struct ath11k_buffer_addr *)&msdu_link->buf_addr_info;
4508 
4509 	ath11k_hal_rx_buf_addr_info_get(buf_addr_info, paddr, sw_cookie, rbm);
4510 
4511 	*pp_buf_addr_info = (void *)buf_addr_info;
4512 }
4513 
4514 static int ath11k_dp_pkt_set_pktlen(struct sk_buff *skb, u32 len)
4515 {
4516 	if (skb->len > len) {
4517 		skb_trim(skb, len);
4518 	} else {
4519 		if (skb_tailroom(skb) < len - skb->len) {
4520 			if ((pskb_expand_head(skb, 0,
4521 					      len - skb->len - skb_tailroom(skb),
4522 					      GFP_ATOMIC))) {
4523 				dev_kfree_skb_any(skb);
4524 				return -ENOMEM;
4525 			}
4526 		}
4527 		skb_put(skb, (len - skb->len));
4528 	}
4529 	return 0;
4530 }
4531 
4532 static void ath11k_hal_rx_msdu_list_get(struct ath11k *ar,
4533 					void *msdu_link_desc,
4534 					struct hal_rx_msdu_list *msdu_list,
4535 					u16 *num_msdus)
4536 {
4537 	struct hal_rx_msdu_details *msdu_details = NULL;
4538 	struct rx_msdu_desc *msdu_desc_info = NULL;
4539 	struct hal_rx_msdu_link *msdu_link = NULL;
4540 	int i;
4541 	u32 last = FIELD_PREP(RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU, 1);
4542 	u32 first = FIELD_PREP(RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU, 1);
4543 	u8  tmp  = 0;
4544 
4545 	msdu_link = (struct hal_rx_msdu_link *)msdu_link_desc;
4546 	msdu_details = &msdu_link->msdu_link[0];
4547 
4548 	for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) {
4549 		if (FIELD_GET(BUFFER_ADDR_INFO0_ADDR,
4550 			      msdu_details[i].buf_addr_info.info0) == 0) {
4551 			msdu_desc_info = &msdu_details[i - 1].rx_msdu_info;
4552 			msdu_desc_info->info0 |= last;
4553 			;
4554 			break;
4555 		}
4556 		msdu_desc_info = &msdu_details[i].rx_msdu_info;
4557 
4558 		if (!i)
4559 			msdu_desc_info->info0 |= first;
4560 		else if (i == (HAL_RX_NUM_MSDU_DESC - 1))
4561 			msdu_desc_info->info0 |= last;
4562 		msdu_list->msdu_info[i].msdu_flags = msdu_desc_info->info0;
4563 		msdu_list->msdu_info[i].msdu_len =
4564 			 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info->info0);
4565 		msdu_list->sw_cookie[i] =
4566 			FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
4567 				  msdu_details[i].buf_addr_info.info1);
4568 		tmp = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR,
4569 				msdu_details[i].buf_addr_info.info1);
4570 		msdu_list->rbm[i] = tmp;
4571 	}
4572 	*num_msdus = i;
4573 }
4574 
4575 static u32 ath11k_dp_rx_mon_comp_ppduid(u32 msdu_ppdu_id, u32 *ppdu_id,
4576 					u32 *rx_bufs_used)
4577 {
4578 	u32 ret = 0;
4579 
4580 	if ((*ppdu_id < msdu_ppdu_id) &&
4581 	    ((msdu_ppdu_id - *ppdu_id) < DP_NOT_PPDU_ID_WRAP_AROUND)) {
4582 		*ppdu_id = msdu_ppdu_id;
4583 		ret = msdu_ppdu_id;
4584 	} else if ((*ppdu_id > msdu_ppdu_id) &&
4585 		((*ppdu_id - msdu_ppdu_id) > DP_NOT_PPDU_ID_WRAP_AROUND)) {
4586 		/* mon_dst is behind than mon_status
4587 		 * skip dst_ring and free it
4588 		 */
4589 		*rx_bufs_used += 1;
4590 		*ppdu_id = msdu_ppdu_id;
4591 		ret = msdu_ppdu_id;
4592 	}
4593 	return ret;
4594 }
4595 
4596 static void ath11k_dp_mon_get_buf_len(struct hal_rx_msdu_desc_info *info,
4597 				      bool *is_frag, u32 *total_len,
4598 				      u32 *frag_len, u32 *msdu_cnt)
4599 {
4600 	if (info->msdu_flags & RX_MSDU_DESC_INFO0_MSDU_CONTINUATION) {
4601 		if (!*is_frag) {
4602 			*total_len = info->msdu_len;
4603 			*is_frag = true;
4604 		}
4605 		ath11k_dp_mon_set_frag_len(total_len,
4606 					   frag_len);
4607 	} else {
4608 		if (*is_frag) {
4609 			ath11k_dp_mon_set_frag_len(total_len,
4610 						   frag_len);
4611 		} else {
4612 			*frag_len = info->msdu_len;
4613 		}
4614 		*is_frag = false;
4615 		*msdu_cnt -= 1;
4616 	}
4617 }
4618 
4619 static u32
4620 ath11k_dp_rx_mon_mpdu_pop(struct ath11k *ar, int mac_id,
4621 			  void *ring_entry, struct sk_buff **head_msdu,
4622 			  struct sk_buff **tail_msdu, u32 *npackets,
4623 			  u32 *ppdu_id)
4624 {
4625 	struct ath11k_pdev_dp *dp = &ar->dp;
4626 	struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
4627 	struct dp_rxdma_ring *rx_ring = &dp->rxdma_mon_buf_ring;
4628 	struct sk_buff *msdu = NULL, *last = NULL;
4629 	struct hal_rx_msdu_list msdu_list;
4630 	void *p_buf_addr_info, *p_last_buf_addr_info;
4631 	struct hal_rx_desc *rx_desc;
4632 	void *rx_msdu_link_desc;
4633 	dma_addr_t paddr;
4634 	u16 num_msdus = 0;
4635 	u32 rx_buf_size, rx_pkt_offset, sw_cookie;
4636 	u32 rx_bufs_used = 0, i = 0;
4637 	u32 msdu_ppdu_id = 0, msdu_cnt = 0;
4638 	u32 total_len = 0, frag_len = 0;
4639 	bool is_frag, is_first_msdu;
4640 	bool drop_mpdu = false;
4641 	struct ath11k_skb_rxcb *rxcb;
4642 	struct hal_reo_entrance_ring *ent_desc =
4643 			(struct hal_reo_entrance_ring *)ring_entry;
4644 	int buf_id;
4645 	u32 rx_link_buf_info[2];
4646 	u8 rbm;
4647 
4648 	if (!ar->ab->hw_params.rxdma1_enable)
4649 		rx_ring = &dp->rx_refill_buf_ring;
4650 
4651 	ath11k_hal_rx_reo_ent_buf_paddr_get(ring_entry, &paddr,
4652 					    &sw_cookie,
4653 					    &p_last_buf_addr_info, &rbm,
4654 					    &msdu_cnt);
4655 
4656 	if (FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_PUSH_REASON,
4657 		      ent_desc->info1) ==
4658 		      HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
4659 		u8 rxdma_err =
4660 			FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE,
4661 				  ent_desc->info1);
4662 		if (rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR ||
4663 		    rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR ||
4664 		    rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR) {
4665 			drop_mpdu = true;
4666 			pmon->rx_mon_stats.dest_mpdu_drop++;
4667 		}
4668 	}
4669 
4670 	is_frag = false;
4671 	is_first_msdu = true;
4672 
4673 	do {
4674 		if (pmon->mon_last_linkdesc_paddr == paddr) {
4675 			pmon->rx_mon_stats.dup_mon_linkdesc_cnt++;
4676 			return rx_bufs_used;
4677 		}
4678 
4679 		if (ar->ab->hw_params.rxdma1_enable)
4680 			rx_msdu_link_desc =
4681 				(void *)pmon->link_desc_banks[sw_cookie].vaddr +
4682 				(paddr - pmon->link_desc_banks[sw_cookie].paddr);
4683 		else
4684 			rx_msdu_link_desc =
4685 				(void *)ar->ab->dp.link_desc_banks[sw_cookie].vaddr +
4686 				(paddr - ar->ab->dp.link_desc_banks[sw_cookie].paddr);
4687 
4688 		ath11k_hal_rx_msdu_list_get(ar, rx_msdu_link_desc, &msdu_list,
4689 					    &num_msdus);
4690 
4691 		for (i = 0; i < num_msdus; i++) {
4692 			u32 l2_hdr_offset;
4693 
4694 			if (pmon->mon_last_buf_cookie == msdu_list.sw_cookie[i]) {
4695 				ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4696 					   "i %d last_cookie %d is same\n",
4697 					   i, pmon->mon_last_buf_cookie);
4698 				drop_mpdu = true;
4699 				pmon->rx_mon_stats.dup_mon_buf_cnt++;
4700 				continue;
4701 			}
4702 			buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
4703 					   msdu_list.sw_cookie[i]);
4704 
4705 			spin_lock_bh(&rx_ring->idr_lock);
4706 			msdu = idr_find(&rx_ring->bufs_idr, buf_id);
4707 			spin_unlock_bh(&rx_ring->idr_lock);
4708 			if (!msdu) {
4709 				ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4710 					   "msdu_pop: invalid buf_id %d\n", buf_id);
4711 				break;
4712 			}
4713 			rxcb = ATH11K_SKB_RXCB(msdu);
4714 			if (!rxcb->unmapped) {
4715 				dma_unmap_single(ar->ab->dev, rxcb->paddr,
4716 						 msdu->len +
4717 						 skb_tailroom(msdu),
4718 						 DMA_FROM_DEVICE);
4719 				rxcb->unmapped = 1;
4720 			}
4721 			if (drop_mpdu) {
4722 				ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4723 					   "i %d drop msdu %p *ppdu_id %x\n",
4724 					   i, msdu, *ppdu_id);
4725 				dev_kfree_skb_any(msdu);
4726 				msdu = NULL;
4727 				goto next_msdu;
4728 			}
4729 
4730 			rx_desc = (struct hal_rx_desc *)msdu->data;
4731 
4732 			rx_pkt_offset = sizeof(struct hal_rx_desc);
4733 			l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, rx_desc);
4734 
4735 			if (is_first_msdu) {
4736 				if (!ath11k_dp_rxdesc_mpdu_valid(ar->ab, rx_desc)) {
4737 					drop_mpdu = true;
4738 					dev_kfree_skb_any(msdu);
4739 					msdu = NULL;
4740 					pmon->mon_last_linkdesc_paddr = paddr;
4741 					goto next_msdu;
4742 				}
4743 
4744 				msdu_ppdu_id =
4745 					ath11k_dp_rxdesc_get_ppduid(ar->ab, rx_desc);
4746 
4747 				if (ath11k_dp_rx_mon_comp_ppduid(msdu_ppdu_id,
4748 								 ppdu_id,
4749 								 &rx_bufs_used)) {
4750 					if (rx_bufs_used) {
4751 						drop_mpdu = true;
4752 						dev_kfree_skb_any(msdu);
4753 						msdu = NULL;
4754 						goto next_msdu;
4755 					}
4756 					return rx_bufs_used;
4757 				}
4758 				pmon->mon_last_linkdesc_paddr = paddr;
4759 				is_first_msdu = false;
4760 			}
4761 			ath11k_dp_mon_get_buf_len(&msdu_list.msdu_info[i],
4762 						  &is_frag, &total_len,
4763 						  &frag_len, &msdu_cnt);
4764 			rx_buf_size = rx_pkt_offset + l2_hdr_offset + frag_len;
4765 
4766 			ath11k_dp_pkt_set_pktlen(msdu, rx_buf_size);
4767 
4768 			if (!(*head_msdu))
4769 				*head_msdu = msdu;
4770 			else if (last)
4771 				last->next = msdu;
4772 
4773 			last = msdu;
4774 next_msdu:
4775 			pmon->mon_last_buf_cookie = msdu_list.sw_cookie[i];
4776 			rx_bufs_used++;
4777 			spin_lock_bh(&rx_ring->idr_lock);
4778 			idr_remove(&rx_ring->bufs_idr, buf_id);
4779 			spin_unlock_bh(&rx_ring->idr_lock);
4780 		}
4781 
4782 		ath11k_hal_rx_buf_addr_info_set(rx_link_buf_info, paddr, sw_cookie, rbm);
4783 
4784 		ath11k_dp_rx_mon_next_link_desc_get(rx_msdu_link_desc, &paddr,
4785 						    &sw_cookie, &rbm,
4786 						    &p_buf_addr_info);
4787 
4788 		if (ar->ab->hw_params.rxdma1_enable) {
4789 			if (ath11k_dp_rx_monitor_link_desc_return(ar,
4790 								  p_last_buf_addr_info,
4791 								  dp->mac_id))
4792 				ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4793 					   "dp_rx_monitor_link_desc_return failed");
4794 		} else {
4795 			ath11k_dp_rx_link_desc_return(ar->ab, rx_link_buf_info,
4796 						      HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
4797 		}
4798 
4799 		p_last_buf_addr_info = p_buf_addr_info;
4800 
4801 	} while (paddr && msdu_cnt);
4802 
4803 	if (last)
4804 		last->next = NULL;
4805 
4806 	*tail_msdu = msdu;
4807 
4808 	if (msdu_cnt == 0)
4809 		*npackets = 1;
4810 
4811 	return rx_bufs_used;
4812 }
4813 
4814 static void ath11k_dp_rx_msdus_set_payload(struct ath11k *ar, struct sk_buff *msdu)
4815 {
4816 	u32 rx_pkt_offset, l2_hdr_offset;
4817 
4818 	rx_pkt_offset = ar->ab->hw_params.hal_desc_sz;
4819 	l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab,
4820 						      (struct hal_rx_desc *)msdu->data);
4821 	skb_pull(msdu, rx_pkt_offset + l2_hdr_offset);
4822 }
4823 
4824 static struct sk_buff *
4825 ath11k_dp_rx_mon_merg_msdus(struct ath11k *ar,
4826 			    u32 mac_id, struct sk_buff *head_msdu,
4827 			    struct sk_buff *last_msdu,
4828 			    struct ieee80211_rx_status *rxs)
4829 {
4830 	struct ath11k_base *ab = ar->ab;
4831 	struct sk_buff *msdu, *prev_buf;
4832 	u32 wifi_hdr_len;
4833 	struct hal_rx_desc *rx_desc;
4834 	char *hdr_desc;
4835 	u8 *dest, decap_format;
4836 	struct ieee80211_hdr_3addr *wh;
4837 	struct rx_attention *rx_attention;
4838 
4839 	if (!head_msdu)
4840 		goto err_merge_fail;
4841 
4842 	rx_desc = (struct hal_rx_desc *)head_msdu->data;
4843 	rx_attention = ath11k_dp_rx_get_attention(ab, rx_desc);
4844 
4845 	if (ath11k_dp_rxdesc_get_mpdulen_err(rx_attention))
4846 		return NULL;
4847 
4848 	decap_format = ath11k_dp_rx_h_msdu_start_decap_type(ab, rx_desc);
4849 
4850 	ath11k_dp_rx_h_ppdu(ar, rx_desc, rxs);
4851 
4852 	if (decap_format == DP_RX_DECAP_TYPE_RAW) {
4853 		ath11k_dp_rx_msdus_set_payload(ar, head_msdu);
4854 
4855 		prev_buf = head_msdu;
4856 		msdu = head_msdu->next;
4857 
4858 		while (msdu) {
4859 			ath11k_dp_rx_msdus_set_payload(ar, msdu);
4860 
4861 			prev_buf = msdu;
4862 			msdu = msdu->next;
4863 		}
4864 
4865 		prev_buf->next = NULL;
4866 
4867 		skb_trim(prev_buf, prev_buf->len - HAL_RX_FCS_LEN);
4868 	} else if (decap_format == DP_RX_DECAP_TYPE_NATIVE_WIFI) {
4869 		__le16 qos_field;
4870 		u8 qos_pkt = 0;
4871 
4872 		rx_desc = (struct hal_rx_desc *)head_msdu->data;
4873 		hdr_desc = ath11k_dp_rxdesc_get_80211hdr(ab, rx_desc);
4874 
4875 		/* Base size */
4876 		wifi_hdr_len = sizeof(struct ieee80211_hdr_3addr);
4877 		wh = (struct ieee80211_hdr_3addr *)hdr_desc;
4878 
4879 		if (ieee80211_is_data_qos(wh->frame_control)) {
4880 			struct ieee80211_qos_hdr *qwh =
4881 					(struct ieee80211_qos_hdr *)hdr_desc;
4882 
4883 			qos_field = qwh->qos_ctrl;
4884 			qos_pkt = 1;
4885 		}
4886 		msdu = head_msdu;
4887 
4888 		while (msdu) {
4889 			rx_desc = (struct hal_rx_desc *)msdu->data;
4890 			hdr_desc = ath11k_dp_rxdesc_get_80211hdr(ab, rx_desc);
4891 
4892 			if (qos_pkt) {
4893 				dest = skb_push(msdu, sizeof(__le16));
4894 				if (!dest)
4895 					goto err_merge_fail;
4896 				memcpy(dest, hdr_desc, wifi_hdr_len);
4897 				memcpy(dest + wifi_hdr_len,
4898 				       (u8 *)&qos_field, sizeof(__le16));
4899 			}
4900 			ath11k_dp_rx_msdus_set_payload(ar, msdu);
4901 			prev_buf = msdu;
4902 			msdu = msdu->next;
4903 		}
4904 		dest = skb_put(prev_buf, HAL_RX_FCS_LEN);
4905 		if (!dest)
4906 			goto err_merge_fail;
4907 
4908 		ath11k_dbg(ab, ATH11K_DBG_DATA,
4909 			   "mpdu_buf %pK mpdu_buf->len %u",
4910 			   prev_buf, prev_buf->len);
4911 	} else {
4912 		ath11k_dbg(ab, ATH11K_DBG_DATA,
4913 			   "decap format %d is not supported!\n",
4914 			   decap_format);
4915 		goto err_merge_fail;
4916 	}
4917 
4918 	return head_msdu;
4919 
4920 err_merge_fail:
4921 	return NULL;
4922 }
4923 
4924 static int ath11k_dp_rx_mon_deliver(struct ath11k *ar, u32 mac_id,
4925 				    struct sk_buff *head_msdu,
4926 				    struct sk_buff *tail_msdu,
4927 				    struct napi_struct *napi)
4928 {
4929 	struct ath11k_pdev_dp *dp = &ar->dp;
4930 	struct sk_buff *mon_skb, *skb_next, *header;
4931 	struct ieee80211_rx_status *rxs = &dp->rx_status;
4932 
4933 	mon_skb = ath11k_dp_rx_mon_merg_msdus(ar, mac_id, head_msdu,
4934 					      tail_msdu, rxs);
4935 
4936 	if (!mon_skb)
4937 		goto mon_deliver_fail;
4938 
4939 	header = mon_skb;
4940 
4941 	rxs->flag = 0;
4942 	do {
4943 		skb_next = mon_skb->next;
4944 		if (!skb_next)
4945 			rxs->flag &= ~RX_FLAG_AMSDU_MORE;
4946 		else
4947 			rxs->flag |= RX_FLAG_AMSDU_MORE;
4948 
4949 		if (mon_skb == header) {
4950 			header = NULL;
4951 			rxs->flag &= ~RX_FLAG_ALLOW_SAME_PN;
4952 		} else {
4953 			rxs->flag |= RX_FLAG_ALLOW_SAME_PN;
4954 		}
4955 		rxs->flag |= RX_FLAG_ONLY_MONITOR;
4956 
4957 		ath11k_dp_rx_deliver_msdu(ar, napi, mon_skb, rxs);
4958 		mon_skb = skb_next;
4959 	} while (mon_skb);
4960 	rxs->flag = 0;
4961 
4962 	return 0;
4963 
4964 mon_deliver_fail:
4965 	mon_skb = head_msdu;
4966 	while (mon_skb) {
4967 		skb_next = mon_skb->next;
4968 		dev_kfree_skb_any(mon_skb);
4969 		mon_skb = skb_next;
4970 	}
4971 	return -EINVAL;
4972 }
4973 
4974 static void ath11k_dp_rx_mon_dest_process(struct ath11k *ar, int mac_id,
4975 					  u32 quota, struct napi_struct *napi)
4976 {
4977 	struct ath11k_pdev_dp *dp = &ar->dp;
4978 	struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
4979 	void *ring_entry;
4980 	void *mon_dst_srng;
4981 	u32 ppdu_id;
4982 	u32 rx_bufs_used;
4983 	u32 ring_id;
4984 	struct ath11k_pdev_mon_stats *rx_mon_stats;
4985 	u32	 npackets = 0;
4986 
4987 	if (ar->ab->hw_params.rxdma1_enable)
4988 		ring_id = dp->rxdma_mon_dst_ring.ring_id;
4989 	else
4990 		ring_id = dp->rxdma_err_dst_ring[mac_id].ring_id;
4991 
4992 	mon_dst_srng = &ar->ab->hal.srng_list[ring_id];
4993 
4994 	if (!mon_dst_srng) {
4995 		ath11k_warn(ar->ab,
4996 			    "HAL Monitor Destination Ring Init Failed -- %pK",
4997 			    mon_dst_srng);
4998 		return;
4999 	}
5000 
5001 	spin_lock_bh(&pmon->mon_lock);
5002 
5003 	ath11k_hal_srng_access_begin(ar->ab, mon_dst_srng);
5004 
5005 	ppdu_id = pmon->mon_ppdu_info.ppdu_id;
5006 	rx_bufs_used = 0;
5007 	rx_mon_stats = &pmon->rx_mon_stats;
5008 
5009 	while ((ring_entry = ath11k_hal_srng_dst_peek(ar->ab, mon_dst_srng))) {
5010 		struct sk_buff *head_msdu, *tail_msdu;
5011 
5012 		head_msdu = NULL;
5013 		tail_msdu = NULL;
5014 
5015 		rx_bufs_used += ath11k_dp_rx_mon_mpdu_pop(ar, mac_id, ring_entry,
5016 							  &head_msdu,
5017 							  &tail_msdu,
5018 							  &npackets, &ppdu_id);
5019 
5020 		if (ppdu_id != pmon->mon_ppdu_info.ppdu_id) {
5021 			pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5022 			ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5023 				   "dest_rx: new ppdu_id %x != status ppdu_id %x",
5024 				   ppdu_id, pmon->mon_ppdu_info.ppdu_id);
5025 			break;
5026 		}
5027 		if (head_msdu && tail_msdu) {
5028 			ath11k_dp_rx_mon_deliver(ar, dp->mac_id, head_msdu,
5029 						 tail_msdu, napi);
5030 			rx_mon_stats->dest_mpdu_done++;
5031 		}
5032 
5033 		ring_entry = ath11k_hal_srng_dst_get_next_entry(ar->ab,
5034 								mon_dst_srng);
5035 	}
5036 	ath11k_hal_srng_access_end(ar->ab, mon_dst_srng);
5037 
5038 	spin_unlock_bh(&pmon->mon_lock);
5039 
5040 	if (rx_bufs_used) {
5041 		rx_mon_stats->dest_ppdu_done++;
5042 		if (ar->ab->hw_params.rxdma1_enable)
5043 			ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id,
5044 						   &dp->rxdma_mon_buf_ring,
5045 						   rx_bufs_used,
5046 						   HAL_RX_BUF_RBM_SW3_BM);
5047 		else
5048 			ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id,
5049 						   &dp->rx_refill_buf_ring,
5050 						   rx_bufs_used,
5051 						   HAL_RX_BUF_RBM_SW3_BM);
5052 	}
5053 }
5054 
5055 static void ath11k_dp_rx_mon_status_process_tlv(struct ath11k *ar,
5056 						int mac_id, u32 quota,
5057 						struct napi_struct *napi)
5058 {
5059 	struct ath11k_pdev_dp *dp = &ar->dp;
5060 	struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
5061 	struct hal_rx_mon_ppdu_info *ppdu_info;
5062 	struct sk_buff *status_skb;
5063 	u32 tlv_status = HAL_TLV_STATUS_BUF_DONE;
5064 	struct ath11k_pdev_mon_stats *rx_mon_stats;
5065 
5066 	ppdu_info = &pmon->mon_ppdu_info;
5067 	rx_mon_stats = &pmon->rx_mon_stats;
5068 
5069 	if (pmon->mon_ppdu_status != DP_PPDU_STATUS_START)
5070 		return;
5071 
5072 	while (!skb_queue_empty(&pmon->rx_status_q)) {
5073 		status_skb = skb_dequeue(&pmon->rx_status_q);
5074 
5075 		tlv_status = ath11k_hal_rx_parse_mon_status(ar->ab, ppdu_info,
5076 							    status_skb);
5077 		if (tlv_status == HAL_TLV_STATUS_PPDU_DONE) {
5078 			rx_mon_stats->status_ppdu_done++;
5079 			pmon->mon_ppdu_status = DP_PPDU_STATUS_DONE;
5080 			ath11k_dp_rx_mon_dest_process(ar, mac_id, quota, napi);
5081 			pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5082 		}
5083 		dev_kfree_skb_any(status_skb);
5084 	}
5085 }
5086 
5087 static int ath11k_dp_mon_process_rx(struct ath11k_base *ab, int mac_id,
5088 				    struct napi_struct *napi, int budget)
5089 {
5090 	struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id);
5091 	struct ath11k_pdev_dp *dp = &ar->dp;
5092 	struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
5093 	int num_buffs_reaped = 0;
5094 
5095 	num_buffs_reaped = ath11k_dp_rx_reap_mon_status_ring(ar->ab, mac_id, &budget,
5096 							     &pmon->rx_status_q);
5097 	if (num_buffs_reaped)
5098 		ath11k_dp_rx_mon_status_process_tlv(ar, mac_id, budget, napi);
5099 
5100 	return num_buffs_reaped;
5101 }
5102 
5103 int ath11k_dp_rx_process_mon_rings(struct ath11k_base *ab, int mac_id,
5104 				   struct napi_struct *napi, int budget)
5105 {
5106 	struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id);
5107 	int ret = 0;
5108 
5109 	if (test_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags))
5110 		ret = ath11k_dp_mon_process_rx(ab, mac_id, napi, budget);
5111 	else
5112 		ret = ath11k_dp_rx_process_mon_status(ab, mac_id, napi, budget);
5113 	return ret;
5114 }
5115 
5116 static int ath11k_dp_rx_pdev_mon_status_attach(struct ath11k *ar)
5117 {
5118 	struct ath11k_pdev_dp *dp = &ar->dp;
5119 	struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
5120 
5121 	skb_queue_head_init(&pmon->rx_status_q);
5122 
5123 	pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5124 
5125 	memset(&pmon->rx_mon_stats, 0,
5126 	       sizeof(pmon->rx_mon_stats));
5127 	return 0;
5128 }
5129 
5130 int ath11k_dp_rx_pdev_mon_attach(struct ath11k *ar)
5131 {
5132 	struct ath11k_pdev_dp *dp = &ar->dp;
5133 	struct ath11k_mon_data *pmon = &dp->mon_data;
5134 	struct hal_srng *mon_desc_srng = NULL;
5135 	struct dp_srng *dp_srng;
5136 	int ret = 0;
5137 	u32 n_link_desc = 0;
5138 
5139 	ret = ath11k_dp_rx_pdev_mon_status_attach(ar);
5140 	if (ret) {
5141 		ath11k_warn(ar->ab, "pdev_mon_status_attach() failed");
5142 		return ret;
5143 	}
5144 
5145 	/* if rxdma1_enable is false, no need to setup
5146 	 * rxdma_mon_desc_ring.
5147 	 */
5148 	if (!ar->ab->hw_params.rxdma1_enable)
5149 		return 0;
5150 
5151 	dp_srng = &dp->rxdma_mon_desc_ring;
5152 	n_link_desc = dp_srng->size /
5153 		ath11k_hal_srng_get_entrysize(ar->ab, HAL_RXDMA_MONITOR_DESC);
5154 	mon_desc_srng =
5155 		&ar->ab->hal.srng_list[dp->rxdma_mon_desc_ring.ring_id];
5156 
5157 	ret = ath11k_dp_link_desc_setup(ar->ab, pmon->link_desc_banks,
5158 					HAL_RXDMA_MONITOR_DESC, mon_desc_srng,
5159 					n_link_desc);
5160 	if (ret) {
5161 		ath11k_warn(ar->ab, "mon_link_desc_pool_setup() failed");
5162 		return ret;
5163 	}
5164 	pmon->mon_last_linkdesc_paddr = 0;
5165 	pmon->mon_last_buf_cookie = DP_RX_DESC_COOKIE_MAX + 1;
5166 	spin_lock_init(&pmon->mon_lock);
5167 
5168 	return 0;
5169 }
5170 
5171 static int ath11k_dp_mon_link_free(struct ath11k *ar)
5172 {
5173 	struct ath11k_pdev_dp *dp = &ar->dp;
5174 	struct ath11k_mon_data *pmon = &dp->mon_data;
5175 
5176 	ath11k_dp_link_desc_cleanup(ar->ab, pmon->link_desc_banks,
5177 				    HAL_RXDMA_MONITOR_DESC,
5178 				    &dp->rxdma_mon_desc_ring);
5179 	return 0;
5180 }
5181 
5182 int ath11k_dp_rx_pdev_mon_detach(struct ath11k *ar)
5183 {
5184 	ath11k_dp_mon_link_free(ar);
5185 	return 0;
5186 }
5187 
5188 int ath11k_dp_rx_pktlog_start(struct ath11k_base *ab)
5189 {
5190 	/* start reap timer */
5191 	mod_timer(&ab->mon_reap_timer,
5192 		  jiffies + msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL));
5193 
5194 	return 0;
5195 }
5196 
5197 int ath11k_dp_rx_pktlog_stop(struct ath11k_base *ab, bool stop_timer)
5198 {
5199 	int ret;
5200 
5201 	if (stop_timer)
5202 		del_timer_sync(&ab->mon_reap_timer);
5203 
5204 	/* reap all the monitor related rings */
5205 	ret = ath11k_dp_purge_mon_ring(ab);
5206 	if (ret) {
5207 		ath11k_warn(ab, "failed to purge dp mon ring: %d\n", ret);
5208 		return ret;
5209 	}
5210 
5211 	return 0;
5212 }
5213