1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef ATH11K_DP_H 7 #define ATH11K_DP_H 8 9 #include "hal_rx.h" 10 11 struct ath11k_base; 12 struct ath11k_peer; 13 struct ath11k_dp; 14 struct ath11k_vif; 15 struct hal_tcl_status_ring; 16 struct ath11k_ext_irq_grp; 17 18 struct dp_rx_tid { 19 u8 tid; 20 u32 *vaddr; 21 dma_addr_t paddr; 22 u32 size; 23 u32 ba_win_sz; 24 bool active; 25 }; 26 27 #define DP_REO_DESC_FREE_TIMEOUT_MS 1000 28 29 struct dp_reo_cache_flush_elem { 30 struct list_head list; 31 struct dp_rx_tid data; 32 unsigned long ts; 33 }; 34 35 struct dp_reo_cmd { 36 struct list_head list; 37 struct dp_rx_tid data; 38 int cmd_num; 39 void (*handler)(struct ath11k_dp *, void *, 40 enum hal_reo_cmd_status status); 41 }; 42 43 struct dp_srng { 44 u32 *vaddr_unaligned; 45 u32 *vaddr; 46 dma_addr_t paddr_unaligned; 47 dma_addr_t paddr; 48 int size; 49 u32 ring_id; 50 }; 51 52 struct dp_rxdma_ring { 53 struct dp_srng refill_buf_ring; 54 struct idr bufs_idr; 55 /* Protects bufs_idr */ 56 spinlock_t idr_lock; 57 int bufs_max; 58 }; 59 60 #define ATH11K_TX_COMPL_NEXT(x) (((x) + 1) % DP_TX_COMP_RING_SIZE) 61 62 struct dp_tx_ring { 63 u8 tcl_data_ring_id; 64 struct dp_srng tcl_data_ring; 65 struct dp_srng tcl_comp_ring; 66 struct idr txbuf_idr; 67 /* Protects txbuf_idr and num_pending */ 68 spinlock_t tx_idr_lock; 69 struct hal_wbm_release_ring *tx_status; 70 int tx_status_head; 71 int tx_status_tail; 72 }; 73 74 struct ath11k_pdev_mon_stats { 75 u32 status_ppdu_state; 76 u32 status_ppdu_start; 77 u32 status_ppdu_end; 78 u32 status_ppdu_compl; 79 u32 status_ppdu_start_mis; 80 u32 status_ppdu_end_mis; 81 u32 status_ppdu_done; 82 u32 dest_ppdu_done; 83 u32 dest_mpdu_done; 84 u32 dest_mpdu_drop; 85 u32 dup_mon_linkdesc_cnt; 86 u32 dup_mon_buf_cnt; 87 }; 88 89 struct dp_link_desc_bank { 90 void *vaddr_unaligned; 91 void *vaddr; 92 dma_addr_t paddr_unaligned; 93 dma_addr_t paddr; 94 u32 size; 95 }; 96 97 /* Size to enforce scatter idle list mode */ 98 #define DP_LINK_DESC_ALLOC_SIZE_THRESH 0x200000 99 #define DP_LINK_DESC_BANKS_MAX 8 100 101 #define DP_RX_DESC_COOKIE_INDEX_MAX 0x3ffff 102 #define DP_RX_DESC_COOKIE_POOL_ID_MAX 0x1c0000 103 #define DP_RX_DESC_COOKIE_MAX \ 104 (DP_RX_DESC_COOKIE_INDEX_MAX | DP_RX_DESC_COOKIE_POOL_ID_MAX) 105 #define DP_NOT_PPDU_ID_WRAP_AROUND 20000 106 107 enum ath11k_dp_ppdu_state { 108 DP_PPDU_STATUS_START, 109 DP_PPDU_STATUS_DONE, 110 }; 111 112 struct ath11k_mon_data { 113 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX]; 114 struct hal_rx_mon_ppdu_info mon_ppdu_info; 115 116 u32 mon_ppdu_status; 117 u32 mon_last_buf_cookie; 118 u64 mon_last_linkdesc_paddr; 119 u16 chan_noise_floor; 120 121 struct ath11k_pdev_mon_stats rx_mon_stats; 122 /* lock for monitor data */ 123 spinlock_t mon_lock; 124 struct sk_buff_head rx_status_q; 125 }; 126 127 struct ath11k_pdev_dp { 128 u32 mac_id; 129 atomic_t num_tx_pending; 130 wait_queue_head_t tx_empty_waitq; 131 struct dp_srng reo_dst_ring; 132 struct dp_rxdma_ring rx_refill_buf_ring; 133 struct dp_srng rxdma_err_dst_ring; 134 struct dp_srng rxdma_mon_dst_ring; 135 struct dp_srng rxdma_mon_desc_ring; 136 137 struct dp_rxdma_ring rxdma_mon_buf_ring; 138 struct dp_rxdma_ring rx_mon_status_refill_ring; 139 struct ieee80211_rx_status rx_status; 140 struct ath11k_mon_data mon_data; 141 }; 142 143 #define DP_NUM_CLIENTS_MAX 64 144 #define DP_AVG_TIDS_PER_CLIENT 2 145 #define DP_NUM_TIDS_MAX (DP_NUM_CLIENTS_MAX * DP_AVG_TIDS_PER_CLIENT) 146 #define DP_AVG_MSDUS_PER_FLOW 128 147 #define DP_AVG_FLOWS_PER_TID 2 148 #define DP_AVG_MPDUS_PER_TID_MAX 128 149 #define DP_AVG_MSDUS_PER_MPDU 4 150 151 #define DP_RX_HASH_ENABLE 0 /* Disable hash based Rx steering */ 152 153 #define DP_BA_WIN_SZ_MAX 256 154 155 #define DP_TCL_NUM_RING_MAX 3 156 157 #define DP_IDLE_SCATTER_BUFS_MAX 16 158 159 #define DP_WBM_RELEASE_RING_SIZE 64 160 #define DP_TCL_DATA_RING_SIZE 512 161 #define DP_TX_COMP_RING_SIZE 8192 162 #define DP_TX_IDR_SIZE (DP_TX_COMP_RING_SIZE << 1) 163 #define DP_TCL_CMD_RING_SIZE 32 164 #define DP_TCL_STATUS_RING_SIZE 32 165 #define DP_REO_DST_RING_MAX 4 166 #define DP_REO_DST_RING_SIZE 2048 167 #define DP_REO_REINJECT_RING_SIZE 32 168 #define DP_RX_RELEASE_RING_SIZE 1024 169 #define DP_REO_EXCEPTION_RING_SIZE 128 170 #define DP_REO_CMD_RING_SIZE 128 171 #define DP_REO_STATUS_RING_SIZE 2048 172 #define DP_RXDMA_BUF_RING_SIZE 4096 173 #define DP_RXDMA_REFILL_RING_SIZE 2048 174 #define DP_RXDMA_ERR_DST_RING_SIZE 1024 175 #define DP_RXDMA_MON_STATUS_RING_SIZE 1024 176 #define DP_RXDMA_MONITOR_BUF_RING_SIZE 4096 177 #define DP_RXDMA_MONITOR_DST_RING_SIZE 2048 178 #define DP_RXDMA_MONITOR_DESC_RING_SIZE 4096 179 180 #define DP_RX_BUFFER_SIZE 2048 181 #define DP_RX_BUFFER_ALIGN_SIZE 128 182 183 #define DP_RXDMA_BUF_COOKIE_BUF_ID GENMASK(17, 0) 184 #define DP_RXDMA_BUF_COOKIE_PDEV_ID GENMASK(20, 18) 185 186 #define DP_HW2SW_MACID(mac_id) ((mac_id) ? ((mac_id) - 1) : 0) 187 #define DP_SW2HW_MACID(mac_id) ((mac_id) + 1) 188 189 #define DP_TX_DESC_ID_MAC_ID GENMASK(1, 0) 190 #define DP_TX_DESC_ID_MSDU_ID GENMASK(18, 2) 191 #define DP_TX_DESC_ID_POOL_ID GENMASK(20, 19) 192 193 struct ath11k_dp { 194 struct ath11k_base *ab; 195 enum ath11k_htc_ep_id eid; 196 struct completion htt_tgt_version_received; 197 u8 htt_tgt_ver_major; 198 u8 htt_tgt_ver_minor; 199 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX]; 200 struct dp_srng wbm_idle_ring; 201 struct dp_srng wbm_desc_rel_ring; 202 struct dp_srng tcl_cmd_ring; 203 struct dp_srng tcl_status_ring; 204 struct dp_srng reo_reinject_ring; 205 struct dp_srng rx_rel_ring; 206 struct dp_srng reo_except_ring; 207 struct dp_srng reo_cmd_ring; 208 struct dp_srng reo_status_ring; 209 struct dp_tx_ring tx_ring[DP_TCL_NUM_RING_MAX]; 210 struct hal_wbm_idle_scatter_list scatter_list[DP_IDLE_SCATTER_BUFS_MAX]; 211 struct list_head reo_cmd_list; 212 struct list_head reo_cmd_cache_flush_list; 213 /* protects access to reo_cmd_list and reo_cmd_cache_flush_list */ 214 spinlock_t reo_cmd_lock; 215 }; 216 217 /* HTT definitions */ 218 219 #define HTT_TCL_META_DATA_TYPE BIT(0) 220 #define HTT_TCL_META_DATA_VALID_HTT BIT(1) 221 222 /* vdev meta data */ 223 #define HTT_TCL_META_DATA_VDEV_ID GENMASK(9, 2) 224 #define HTT_TCL_META_DATA_PDEV_ID GENMASK(11, 10) 225 #define HTT_TCL_META_DATA_HOST_INSPECTED BIT(12) 226 227 /* peer meta data */ 228 #define HTT_TCL_META_DATA_PEER_ID GENMASK(15, 2) 229 230 #define HTT_TX_WBM_COMP_STATUS_OFFSET 8 231 232 /* HTT tx completion is overlayed in wbm_release_ring */ 233 #define HTT_TX_WBM_COMP_INFO0_STATUS GENMASK(12, 9) 234 #define HTT_TX_WBM_COMP_INFO0_REINJECT_REASON GENMASK(16, 13) 235 #define HTT_TX_WBM_COMP_INFO0_REINJECT_REASON GENMASK(16, 13) 236 237 #define HTT_TX_WBM_COMP_INFO1_ACK_RSSI GENMASK(31, 24) 238 239 struct htt_tx_wbm_completion { 240 u32 info0; 241 u32 info1; 242 u32 info2; 243 u32 info3; 244 } __packed; 245 246 enum htt_h2t_msg_type { 247 HTT_H2T_MSG_TYPE_VERSION_REQ = 0, 248 HTT_H2T_MSG_TYPE_SRING_SETUP = 0xb, 249 HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG = 0xc, 250 HTT_H2T_MSG_TYPE_EXT_STATS_CFG = 0x10, 251 HTT_H2T_MSG_TYPE_PPDU_STATS_CFG = 0x11, 252 }; 253 254 #define HTT_VER_REQ_INFO_MSG_ID GENMASK(7, 0) 255 256 struct htt_ver_req_cmd { 257 u32 ver_reg_info; 258 } __packed; 259 260 enum htt_srng_ring_type { 261 HTT_HW_TO_SW_RING, 262 HTT_SW_TO_HW_RING, 263 HTT_SW_TO_SW_RING, 264 }; 265 266 enum htt_srng_ring_id { 267 HTT_RXDMA_HOST_BUF_RING, 268 HTT_RXDMA_MONITOR_STATUS_RING, 269 HTT_RXDMA_MONITOR_BUF_RING, 270 HTT_RXDMA_MONITOR_DESC_RING, 271 HTT_RXDMA_MONITOR_DEST_RING, 272 HTT_HOST1_TO_FW_RXBUF_RING, 273 HTT_HOST2_TO_FW_RXBUF_RING, 274 HTT_RXDMA_NON_MONITOR_DEST_RING, 275 }; 276 277 /* host -> target HTT_SRING_SETUP message 278 * 279 * After target is booted up, Host can send SRING setup message for 280 * each host facing LMAC SRING. Target setups up HW registers based 281 * on setup message and confirms back to Host if response_required is set. 282 * Host should wait for confirmation message before sending new SRING 283 * setup message 284 * 285 * The message would appear as follows: 286 * 287 * |31 24|23 20|19|18 16|15|14 8|7 0| 288 * |--------------- +-----------------+----------------+------------------| 289 * | ring_type | ring_id | pdev_id | msg_type | 290 * |----------------------------------------------------------------------| 291 * | ring_base_addr_lo | 292 * |----------------------------------------------------------------------| 293 * | ring_base_addr_hi | 294 * |----------------------------------------------------------------------| 295 * |ring_misc_cfg_flag|ring_entry_size| ring_size | 296 * |----------------------------------------------------------------------| 297 * | ring_head_offset32_remote_addr_lo | 298 * |----------------------------------------------------------------------| 299 * | ring_head_offset32_remote_addr_hi | 300 * |----------------------------------------------------------------------| 301 * | ring_tail_offset32_remote_addr_lo | 302 * |----------------------------------------------------------------------| 303 * | ring_tail_offset32_remote_addr_hi | 304 * |----------------------------------------------------------------------| 305 * | ring_msi_addr_lo | 306 * |----------------------------------------------------------------------| 307 * | ring_msi_addr_hi | 308 * |----------------------------------------------------------------------| 309 * | ring_msi_data | 310 * |----------------------------------------------------------------------| 311 * | intr_timer_th |IM| intr_batch_counter_th | 312 * |----------------------------------------------------------------------| 313 * | reserved |RR|PTCF| intr_low_threshold | 314 * |----------------------------------------------------------------------| 315 * Where 316 * IM = sw_intr_mode 317 * RR = response_required 318 * PTCF = prefetch_timer_cfg 319 * 320 * The message is interpreted as follows: 321 * dword0 - b'0:7 - msg_type: This will be set to 322 * HTT_H2T_MSG_TYPE_SRING_SETUP 323 * b'8:15 - pdev_id: 324 * 0 (for rings at SOC/UMAC level), 325 * 1/2/3 mac id (for rings at LMAC level) 326 * b'16:23 - ring_id: identify which ring is to setup, 327 * more details can be got from enum htt_srng_ring_id 328 * b'24:31 - ring_type: identify type of host rings, 329 * more details can be got from enum htt_srng_ring_type 330 * dword1 - b'0:31 - ring_base_addr_lo: Lower 32bits of ring base address 331 * dword2 - b'0:31 - ring_base_addr_hi: Upper 32bits of ring base address 332 * dword3 - b'0:15 - ring_size: size of the ring in unit of 4-bytes words 333 * b'16:23 - ring_entry_size: Size of each entry in 4-byte word units 334 * b'24:31 - ring_misc_cfg_flag: Valid only for HW_TO_SW_RING and 335 * SW_TO_HW_RING. 336 * Refer to HTT_SRING_SETUP_RING_MISC_CFG_RING defs. 337 * dword4 - b'0:31 - ring_head_off32_remote_addr_lo: 338 * Lower 32 bits of memory address of the remote variable 339 * storing the 4-byte word offset that identifies the head 340 * element within the ring. 341 * (The head offset variable has type u32.) 342 * Valid for HW_TO_SW and SW_TO_SW rings. 343 * dword5 - b'0:31 - ring_head_off32_remote_addr_hi: 344 * Upper 32 bits of memory address of the remote variable 345 * storing the 4-byte word offset that identifies the head 346 * element within the ring. 347 * (The head offset variable has type u32.) 348 * Valid for HW_TO_SW and SW_TO_SW rings. 349 * dword6 - b'0:31 - ring_tail_off32_remote_addr_lo: 350 * Lower 32 bits of memory address of the remote variable 351 * storing the 4-byte word offset that identifies the tail 352 * element within the ring. 353 * (The tail offset variable has type u32.) 354 * Valid for HW_TO_SW and SW_TO_SW rings. 355 * dword7 - b'0:31 - ring_tail_off32_remote_addr_hi: 356 * Upper 32 bits of memory address of the remote variable 357 * storing the 4-byte word offset that identifies the tail 358 * element within the ring. 359 * (The tail offset variable has type u32.) 360 * Valid for HW_TO_SW and SW_TO_SW rings. 361 * dword8 - b'0:31 - ring_msi_addr_lo: Lower 32bits of MSI cfg address 362 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 363 * dword9 - b'0:31 - ring_msi_addr_hi: Upper 32bits of MSI cfg address 364 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 365 * dword10 - b'0:31 - ring_msi_data: MSI data 366 * Refer to HTT_SRING_SETUP_RING_MSC_CFG_xxx defs 367 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 368 * dword11 - b'0:14 - intr_batch_counter_th: 369 * batch counter threshold is in units of 4-byte words. 370 * HW internally maintains and increments batch count. 371 * (see SRING spec for detail description). 372 * When batch count reaches threshold value, an interrupt 373 * is generated by HW. 374 * b'15 - sw_intr_mode: 375 * This configuration shall be static. 376 * Only programmed at power up. 377 * 0: generate pulse style sw interrupts 378 * 1: generate level style sw interrupts 379 * b'16:31 - intr_timer_th: 380 * The timer init value when timer is idle or is 381 * initialized to start downcounting. 382 * In 8us units (to cover a range of 0 to 524 ms) 383 * dword12 - b'0:15 - intr_low_threshold: 384 * Used only by Consumer ring to generate ring_sw_int_p. 385 * Ring entries low threshold water mark, that is used 386 * in combination with the interrupt timer as well as 387 * the the clearing of the level interrupt. 388 * b'16:18 - prefetch_timer_cfg: 389 * Used only by Consumer ring to set timer mode to 390 * support Application prefetch handling. 391 * The external tail offset/pointer will be updated 392 * at following intervals: 393 * 3'b000: (Prefetch feature disabled; used only for debug) 394 * 3'b001: 1 usec 395 * 3'b010: 4 usec 396 * 3'b011: 8 usec (default) 397 * 3'b100: 16 usec 398 * Others: Reserverd 399 * b'19 - response_required: 400 * Host needs HTT_T2H_MSG_TYPE_SRING_SETUP_DONE as response 401 * b'20:31 - reserved: reserved for future use 402 */ 403 404 #define HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 405 #define HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID GENMASK(15, 8) 406 #define HTT_SRNG_SETUP_CMD_INFO0_RING_ID GENMASK(23, 16) 407 #define HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE GENMASK(31, 24) 408 409 #define HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE GENMASK(15, 0) 410 #define HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE GENMASK(23, 16) 411 #define HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS BIT(25) 412 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP BIT(27) 413 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP BIT(28) 414 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP BIT(29) 415 416 #define HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH GENMASK(14, 0) 417 #define HTT_SRNG_SETUP_CMD_INTR_INFO_SW_INTR_MODE BIT(15) 418 #define HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH GENMASK(31, 16) 419 420 #define HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH GENMASK(15, 0) 421 #define HTT_SRNG_SETUP_CMD_INFO2_PRE_FETCH_TIMER_CFG BIT(16) 422 #define HTT_SRNG_SETUP_CMD_INFO2_RESPONSE_REQUIRED BIT(19) 423 424 struct htt_srng_setup_cmd { 425 u32 info0; 426 u32 ring_base_addr_lo; 427 u32 ring_base_addr_hi; 428 u32 info1; 429 u32 ring_head_off32_remote_addr_lo; 430 u32 ring_head_off32_remote_addr_hi; 431 u32 ring_tail_off32_remote_addr_lo; 432 u32 ring_tail_off32_remote_addr_hi; 433 u32 ring_msi_addr_lo; 434 u32 ring_msi_addr_hi; 435 u32 msi_data; 436 u32 intr_info; 437 u32 info2; 438 } __packed; 439 440 /* host -> target FW PPDU_STATS config message 441 * 442 * @details 443 * The following field definitions describe the format of the HTT host 444 * to target FW for PPDU_STATS_CFG msg. 445 * The message allows the host to configure the PPDU_STATS_IND messages 446 * produced by the target. 447 * 448 * |31 24|23 16|15 8|7 0| 449 * |-----------------------------------------------------------| 450 * | REQ bit mask | pdev_mask | msg type | 451 * |-----------------------------------------------------------| 452 * Header fields: 453 * - MSG_TYPE 454 * Bits 7:0 455 * Purpose: identifies this is a req to configure ppdu_stats_ind from target 456 * Value: 0x11 457 * - PDEV_MASK 458 * Bits 8:15 459 * Purpose: identifies which pdevs this PPDU stats configuration applies to 460 * Value: This is a overloaded field, refer to usage and interpretation of 461 * PDEV in interface document. 462 * Bit 8 : Reserved for SOC stats 463 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC 464 * Indicates MACID_MASK in DBS 465 * - REQ_TLV_BIT_MASK 466 * Bits 16:31 467 * Purpose: each set bit indicates the corresponding PPDU stats TLV type 468 * needs to be included in the target's PPDU_STATS_IND messages. 469 * Value: refer htt_ppdu_stats_tlv_tag_t <<<??? 470 * 471 */ 472 473 struct htt_ppdu_stats_cfg_cmd { 474 u32 msg; 475 } __packed; 476 477 #define HTT_PPDU_STATS_CFG_MSG_TYPE GENMASK(7, 0) 478 #define HTT_PPDU_STATS_CFG_PDEV_ID GENMASK(16, 9) 479 #define HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK GENMASK(31, 16) 480 481 enum htt_ppdu_stats_tag_type { 482 HTT_PPDU_STATS_TAG_COMMON, 483 HTT_PPDU_STATS_TAG_USR_COMMON, 484 HTT_PPDU_STATS_TAG_USR_RATE, 485 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64, 486 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256, 487 HTT_PPDU_STATS_TAG_SCH_CMD_STATUS, 488 HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON, 489 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64, 490 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256, 491 HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS, 492 HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH, 493 HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY, 494 HTT_PPDU_STATS_TAG_INFO, 495 HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD, 496 497 /* New TLV's are added above to this line */ 498 HTT_PPDU_STATS_TAG_MAX, 499 }; 500 501 #define HTT_PPDU_STATS_TAG_DEFAULT (BIT(HTT_PPDU_STATS_TAG_COMMON) \ 502 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON) \ 503 | BIT(HTT_PPDU_STATS_TAG_USR_RATE) \ 504 | BIT(HTT_PPDU_STATS_TAG_SCH_CMD_STATUS) \ 505 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON) \ 506 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS) \ 507 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH) \ 508 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY)) 509 510 #define HTT_PPDU_STATS_TAG_PKTLOG (BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64) | \ 511 BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256) | \ 512 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64) | \ 513 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256) | \ 514 BIT(HTT_PPDU_STATS_TAG_INFO) | \ 515 BIT(HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD) | \ 516 HTT_PPDU_STATS_TAG_DEFAULT) 517 518 /* HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG Message 519 * 520 * details: 521 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG message is sent by host to 522 * configure RXDMA rings. 523 * The configuration is per ring based and includes both packet subtypes 524 * and PPDU/MPDU TLVs. 525 * 526 * The message would appear as follows: 527 * 528 * |31 26|25|24|23 16|15 8|7 0| 529 * |-----------------+----------------+----------------+---------------| 530 * | rsvd1 |PS|SS| ring_id | pdev_id | msg_type | 531 * |-------------------------------------------------------------------| 532 * | rsvd2 | ring_buffer_size | 533 * |-------------------------------------------------------------------| 534 * | packet_type_enable_flags_0 | 535 * |-------------------------------------------------------------------| 536 * | packet_type_enable_flags_1 | 537 * |-------------------------------------------------------------------| 538 * | packet_type_enable_flags_2 | 539 * |-------------------------------------------------------------------| 540 * | packet_type_enable_flags_3 | 541 * |-------------------------------------------------------------------| 542 * | tlv_filter_in_flags | 543 * |-------------------------------------------------------------------| 544 * Where: 545 * PS = pkt_swap 546 * SS = status_swap 547 * The message is interpreted as follows: 548 * dword0 - b'0:7 - msg_type: This will be set to 549 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG 550 * b'8:15 - pdev_id: 551 * 0 (for rings at SOC/UMAC level), 552 * 1/2/3 mac id (for rings at LMAC level) 553 * b'16:23 - ring_id : Identify the ring to configure. 554 * More details can be got from enum htt_srng_ring_id 555 * b'24 - status_swap: 1 is to swap status TLV 556 * b'25 - pkt_swap: 1 is to swap packet TLV 557 * b'26:31 - rsvd1: reserved for future use 558 * dword1 - b'0:16 - ring_buffer_size: size of bufferes referenced by rx ring, 559 * in byte units. 560 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING 561 * - b'16:31 - rsvd2: Reserved for future use 562 * dword2 - b'0:31 - packet_type_enable_flags_0: 563 * Enable MGMT packet from 0b0000 to 0b1001 564 * bits from low to high: FP, MD, MO - 3 bits 565 * FP: Filter_Pass 566 * MD: Monitor_Direct 567 * MO: Monitor_Other 568 * 10 mgmt subtypes * 3 bits -> 30 bits 569 * Refer to PKT_TYPE_ENABLE_FLAG0_xxx_MGMT_xxx defs 570 * dword3 - b'0:31 - packet_type_enable_flags_1: 571 * Enable MGMT packet from 0b1010 to 0b1111 572 * bits from low to high: FP, MD, MO - 3 bits 573 * Refer to PKT_TYPE_ENABLE_FLAG1_xxx_MGMT_xxx defs 574 * dword4 - b'0:31 - packet_type_enable_flags_2: 575 * Enable CTRL packet from 0b0000 to 0b1001 576 * bits from low to high: FP, MD, MO - 3 bits 577 * Refer to PKT_TYPE_ENABLE_FLAG2_xxx_CTRL_xxx defs 578 * dword5 - b'0:31 - packet_type_enable_flags_3: 579 * Enable CTRL packet from 0b1010 to 0b1111, 580 * MCAST_DATA, UCAST_DATA, NULL_DATA 581 * bits from low to high: FP, MD, MO - 3 bits 582 * Refer to PKT_TYPE_ENABLE_FLAG3_xxx_CTRL_xxx defs 583 * dword6 - b'0:31 - tlv_filter_in_flags: 584 * Filter in Attention/MPDU/PPDU/Header/User tlvs 585 * Refer to CFG_TLV_FILTER_IN_FLAG defs 586 */ 587 588 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 589 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8) 590 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16) 591 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS BIT(24) 592 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS BIT(25) 593 594 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE GENMASK(15, 0) 595 596 enum htt_rx_filter_tlv_flags { 597 HTT_RX_FILTER_TLV_FLAGS_MPDU_START = BIT(0), 598 HTT_RX_FILTER_TLV_FLAGS_MSDU_START = BIT(1), 599 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET = BIT(2), 600 HTT_RX_FILTER_TLV_FLAGS_MSDU_END = BIT(3), 601 HTT_RX_FILTER_TLV_FLAGS_MPDU_END = BIT(4), 602 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER = BIT(5), 603 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER = BIT(6), 604 HTT_RX_FILTER_TLV_FLAGS_ATTENTION = BIT(7), 605 HTT_RX_FILTER_TLV_FLAGS_PPDU_START = BIT(8), 606 HTT_RX_FILTER_TLV_FLAGS_PPDU_END = BIT(9), 607 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS = BIT(10), 608 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT = BIT(11), 609 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE = BIT(12), 610 }; 611 612 enum htt_rx_mgmt_pkt_filter_tlv_flags0 { 613 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(0), 614 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(1), 615 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(2), 616 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(3), 617 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(4), 618 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(5), 619 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(6), 620 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(7), 621 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(8), 622 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(9), 623 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(10), 624 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(11), 625 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(12), 626 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(13), 627 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(14), 628 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(15), 629 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(16), 630 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(17), 631 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(18), 632 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(19), 633 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(20), 634 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(21), 635 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(22), 636 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(23), 637 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(24), 638 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(25), 639 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(26), 640 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(27), 641 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(28), 642 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(29), 643 }; 644 645 enum htt_rx_mgmt_pkt_filter_tlv_flags1 { 646 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(0), 647 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(1), 648 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(2), 649 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(3), 650 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(4), 651 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(5), 652 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(6), 653 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(7), 654 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(8), 655 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(9), 656 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(10), 657 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(11), 658 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(12), 659 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(13), 660 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(14), 661 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(15), 662 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(16), 663 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(17), 664 }; 665 666 enum htt_rx_ctrl_pkt_filter_tlv_flags2 { 667 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(0), 668 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(1), 669 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(2), 670 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(3), 671 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(4), 672 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(5), 673 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(6), 674 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(7), 675 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(8), 676 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(9), 677 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(10), 678 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(11), 679 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(12), 680 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(13), 681 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(14), 682 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(15), 683 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(16), 684 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(17), 685 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(18), 686 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(19), 687 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(20), 688 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(21), 689 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(22), 690 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(23), 691 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(24), 692 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(25), 693 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(26), 694 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(27), 695 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(28), 696 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(29), 697 }; 698 699 enum htt_rx_ctrl_pkt_filter_tlv_flags3 { 700 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(0), 701 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(1), 702 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(2), 703 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(3), 704 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(4), 705 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(5), 706 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(6), 707 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(7), 708 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(8), 709 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(9), 710 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(10), 711 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(11), 712 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(12), 713 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(13), 714 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(14), 715 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(15), 716 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(16), 717 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(17), 718 }; 719 720 enum htt_rx_data_pkt_filter_tlv_flasg3 { 721 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(18), 722 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(19), 723 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(20), 724 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(21), 725 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(22), 726 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(23), 727 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(24), 728 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(25), 729 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(26), 730 }; 731 732 #define HTT_RX_FP_MGMT_FILTER_FLAGS0 \ 733 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 734 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 735 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 736 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 737 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 738 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 739 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 740 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 741 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 742 743 #define HTT_RX_MD_MGMT_FILTER_FLAGS0 \ 744 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 745 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 746 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 747 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 748 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 749 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 750 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 751 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 752 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 753 754 #define HTT_RX_MO_MGMT_FILTER_FLAGS0 \ 755 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 756 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 757 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 758 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 759 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 760 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 761 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 762 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 763 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 764 765 #define HTT_RX_FP_MGMT_FILTER_FLAGS1 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 766 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 767 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 768 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 769 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 770 771 #define HTT_RX_MD_MGMT_FILTER_FLAGS1 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 772 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 773 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 774 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 775 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 776 777 #define HTT_RX_MO_MGMT_FILTER_FLAGS1 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 778 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 779 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 780 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 781 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 782 783 #define HTT_RX_FP_CTRL_FILTER_FLASG2 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 784 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 785 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 786 787 #define HTT_RX_MD_CTRL_FILTER_FLASG2 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 788 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 789 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 790 791 #define HTT_RX_MO_CTRL_FILTER_FLASG2 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 792 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 793 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 794 795 #define HTT_RX_FP_CTRL_FILTER_FLASG3 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 796 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 797 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 798 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 799 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 800 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 801 802 #define HTT_RX_MD_CTRL_FILTER_FLASG3 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 803 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 804 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 805 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 806 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 807 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 808 809 #define HTT_RX_MO_CTRL_FILTER_FLASG3 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 810 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 811 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 812 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 813 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 814 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 815 816 #define HTT_RX_FP_DATA_FILTER_FLASG3 (HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 817 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 818 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 819 820 #define HTT_RX_MD_DATA_FILTER_FLASG3 (HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 821 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 822 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 823 824 #define HTT_RX_MO_DATA_FILTER_FLASG3 (HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 825 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 826 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 827 828 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 \ 829 (HTT_RX_FP_MGMT_FILTER_FLAGS0 | \ 830 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7) 831 832 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS0 \ 833 (HTT_RX_MO_MGMT_FILTER_FLAGS0 | \ 834 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7) 835 836 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 \ 837 (HTT_RX_FP_MGMT_FILTER_FLAGS1 | \ 838 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15) 839 840 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS1 \ 841 (HTT_RX_MO_MGMT_FILTER_FLAGS1 | \ 842 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15) 843 844 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG2 \ 845 (HTT_RX_FP_CTRL_FILTER_FLASG2 | \ 846 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \ 847 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \ 848 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \ 849 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \ 850 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \ 851 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \ 852 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT) 853 854 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG2 \ 855 (HTT_RX_MO_CTRL_FILTER_FLASG2 | \ 856 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \ 857 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \ 858 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \ 859 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \ 860 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \ 861 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \ 862 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT) 863 864 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG3 HTT_RX_FP_CTRL_FILTER_FLASG3 865 866 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG3 HTT_RX_MO_CTRL_FILTER_FLASG3 867 868 #define HTT_RX_MON_FP_DATA_FILTER_FLASG3 HTT_RX_FP_DATA_FILTER_FLASG3 869 870 #define HTT_RX_MON_MO_DATA_FILTER_FLASG3 HTT_RX_MO_DATA_FILTER_FLASG3 871 872 #define HTT_RX_MON_FILTER_TLV_FLAGS \ 873 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 874 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \ 875 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \ 876 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \ 877 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \ 878 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE) 879 880 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING \ 881 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 882 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \ 883 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \ 884 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \ 885 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \ 886 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE) 887 888 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING \ 889 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 890 HTT_RX_FILTER_TLV_FLAGS_MSDU_START | \ 891 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \ 892 HTT_RX_FILTER_TLV_FLAGS_MSDU_END | \ 893 HTT_RX_FILTER_TLV_FLAGS_MPDU_END | \ 894 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER | \ 895 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER | \ 896 HTT_RX_FILTER_TLV_FLAGS_ATTENTION) 897 898 struct htt_rx_ring_selection_cfg_cmd { 899 u32 info0; 900 u32 info1; 901 u32 pkt_type_en_flags0; 902 u32 pkt_type_en_flags1; 903 u32 pkt_type_en_flags2; 904 u32 pkt_type_en_flags3; 905 u32 rx_filter_tlv; 906 } __packed; 907 908 struct htt_rx_ring_tlv_filter { 909 u32 rx_filter; /* see htt_rx_filter_tlv_flags */ 910 u32 pkt_filter_flags0; /* MGMT */ 911 u32 pkt_filter_flags1; /* MGMT */ 912 u32 pkt_filter_flags2; /* CTRL */ 913 u32 pkt_filter_flags3; /* DATA */ 914 }; 915 916 /* HTT message target->host */ 917 918 enum htt_t2h_msg_type { 919 HTT_T2H_MSG_TYPE_VERSION_CONF, 920 HTT_T2H_MSG_TYPE_RX_ADDBA = 0x5, 921 HTT_T2H_MSG_TYPE_PKTLOG = 0x8, 922 HTT_T2H_MSG_TYPE_SEC_IND = 0xb, 923 HTT_T2H_MSG_TYPE_PEER_MAP = 0x1e, 924 HTT_T2H_MSG_TYPE_PEER_UNMAP = 0x1f, 925 HTT_T2H_MSG_TYPE_PPDU_STATS_IND = 0x1d, 926 HTT_T2H_MSG_TYPE_EXT_STATS_CONF = 0x1c, 927 }; 928 929 #define HTT_TARGET_VERSION_MAJOR 3 930 931 #define HTT_T2H_MSG_TYPE GENMASK(7, 0) 932 #define HTT_T2H_VERSION_CONF_MINOR GENMASK(15, 8) 933 #define HTT_T2H_VERSION_CONF_MAJOR GENMASK(23, 16) 934 935 struct htt_t2h_version_conf_msg { 936 u32 version; 937 } __packed; 938 939 #define HTT_T2H_PEER_MAP_INFO_VDEV_ID GENMASK(15, 8) 940 #define HTT_T2H_PEER_MAP_INFO_PEER_ID GENMASK(31, 16) 941 #define HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 GENMASK(15, 0) 942 #define HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID GENMASK(31, 16) 943 #define HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL GENMASK(15, 0) 944 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M BIT(16) 945 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 16 946 947 struct htt_t2h_peer_map_event { 948 u32 info; 949 u32 mac_addr_l32; 950 u32 info1; 951 u32 info2; 952 } __packed; 953 954 #define HTT_T2H_PEER_UNMAP_INFO_VDEV_ID HTT_T2H_PEER_MAP_INFO_VDEV_ID 955 #define HTT_T2H_PEER_UNMAP_INFO_PEER_ID HTT_T2H_PEER_MAP_INFO_PEER_ID 956 #define HTT_T2H_PEER_UNMAP_INFO1_MAC_ADDR_H16 \ 957 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 958 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_M HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M 959 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_S HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 960 961 struct htt_t2h_peer_unmap_event { 962 u32 info; 963 u32 mac_addr_l32; 964 u32 info1; 965 } __packed; 966 967 struct htt_resp_msg { 968 union { 969 struct htt_t2h_version_conf_msg version_msg; 970 struct htt_t2h_peer_map_event peer_map_ev; 971 struct htt_t2h_peer_unmap_event peer_unmap_ev; 972 }; 973 } __packed; 974 975 /* ppdu stats 976 * 977 * @details 978 * The following field definitions describe the format of the HTT target 979 * to host ppdu stats indication message. 980 * 981 * 982 * |31 16|15 12|11 10|9 8|7 0 | 983 * |----------------------------------------------------------------------| 984 * | payload_size | rsvd |pdev_id|mac_id | msg type | 985 * |----------------------------------------------------------------------| 986 * | ppdu_id | 987 * |----------------------------------------------------------------------| 988 * | Timestamp in us | 989 * |----------------------------------------------------------------------| 990 * | reserved | 991 * |----------------------------------------------------------------------| 992 * | type-specific stats info | 993 * | (see htt_ppdu_stats.h) | 994 * |----------------------------------------------------------------------| 995 * Header fields: 996 * - MSG_TYPE 997 * Bits 7:0 998 * Purpose: Identifies this is a PPDU STATS indication 999 * message. 1000 * Value: 0x1d 1001 * - mac_id 1002 * Bits 9:8 1003 * Purpose: mac_id of this ppdu_id 1004 * Value: 0-3 1005 * - pdev_id 1006 * Bits 11:10 1007 * Purpose: pdev_id of this ppdu_id 1008 * Value: 0-3 1009 * 0 (for rings at SOC level), 1010 * 1/2/3 PDEV -> 0/1/2 1011 * - payload_size 1012 * Bits 31:16 1013 * Purpose: total tlv size 1014 * Value: payload_size in bytes 1015 */ 1016 1017 #define HTT_T2H_PPDU_STATS_INFO_PDEV_ID GENMASK(11, 10) 1018 #define HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE GENMASK(31, 16) 1019 1020 struct ath11k_htt_ppdu_stats_msg { 1021 u32 info; 1022 u32 ppdu_id; 1023 u32 timestamp; 1024 u32 rsvd; 1025 u8 data[0]; 1026 } __packed; 1027 1028 struct htt_tlv { 1029 u32 header; 1030 u8 value[0]; 1031 } __packed; 1032 1033 #define HTT_TLV_TAG GENMASK(11, 0) 1034 #define HTT_TLV_LEN GENMASK(23, 12) 1035 1036 enum HTT_PPDU_STATS_BW { 1037 HTT_PPDU_STATS_BANDWIDTH_5MHZ = 0, 1038 HTT_PPDU_STATS_BANDWIDTH_10MHZ = 1, 1039 HTT_PPDU_STATS_BANDWIDTH_20MHZ = 2, 1040 HTT_PPDU_STATS_BANDWIDTH_40MHZ = 3, 1041 HTT_PPDU_STATS_BANDWIDTH_80MHZ = 4, 1042 HTT_PPDU_STATS_BANDWIDTH_160MHZ = 5, /* includes 80+80 */ 1043 HTT_PPDU_STATS_BANDWIDTH_DYN = 6, 1044 }; 1045 1046 #define HTT_PPDU_STATS_CMN_FLAGS_FRAME_TYPE_M GENMASK(7, 0) 1047 #define HTT_PPDU_STATS_CMN_FLAGS_QUEUE_TYPE_M GENMASK(15, 8) 1048 /* bw - HTT_PPDU_STATS_BW */ 1049 #define HTT_PPDU_STATS_CMN_FLAGS_BW_M GENMASK(19, 16) 1050 1051 struct htt_ppdu_stats_common { 1052 u32 ppdu_id; 1053 u16 sched_cmdid; 1054 u8 ring_id; 1055 u8 num_users; 1056 u32 flags; /* %HTT_PPDU_STATS_COMMON_FLAGS_*/ 1057 u32 chain_mask; 1058 u32 fes_duration_us; /* frame exchange sequence */ 1059 u32 ppdu_sch_eval_start_tstmp_us; 1060 u32 ppdu_sch_end_tstmp_us; 1061 u32 ppdu_start_tstmp_us; 1062 /* BIT [15 : 0] - phy mode (WLAN_PHY_MODE) with which ppdu was transmitted 1063 * BIT [31 : 16] - bandwidth (in MHz) with which ppdu was transmitted 1064 */ 1065 u16 phy_mode; 1066 u16 bw_mhz; 1067 } __packed; 1068 1069 enum htt_ppdu_stats_gi { 1070 HTT_PPDU_STATS_SGI_0_8_US, 1071 HTT_PPDU_STATS_SGI_0_4_US, 1072 HTT_PPDU_STATS_SGI_1_6_US, 1073 HTT_PPDU_STATS_SGI_3_2_US, 1074 }; 1075 1076 #define HTT_PPDU_STATS_USER_RATE_INFO0_USER_POS_M GENMASK(3, 0) 1077 #define HTT_PPDU_STATS_USER_RATE_INFO0_MU_GROUP_ID_M GENMASK(11, 4) 1078 1079 #define HTT_PPDU_STATS_USER_RATE_INFO1_RESP_TYPE_VALD_M BIT(0) 1080 #define HTT_PPDU_STATS_USER_RATE_INFO1_PPDU_TYPE_M GENMASK(5, 1) 1081 1082 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LTF_SIZE_M GENMASK(1, 0) 1083 #define HTT_PPDU_STATS_USER_RATE_FLAGS_STBC_M BIT(2) 1084 #define HTT_PPDU_STATS_USER_RATE_FLAGS_HE_RE_M BIT(3) 1085 #define HTT_PPDU_STATS_USER_RATE_FLAGS_TXBF_M GENMASK(7, 4) 1086 #define HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M GENMASK(11, 8) 1087 #define HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M GENMASK(15, 12) 1088 #define HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M GENMASK(19, 16) 1089 #define HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M GENMASK(23, 20) 1090 #define HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M GENMASK(27, 24) 1091 #define HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M BIT(28) 1092 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LDPC_M BIT(29) 1093 1094 #define HTT_USR_RATE_PREAMBLE(_val) \ 1095 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M, _val) 1096 #define HTT_USR_RATE_BW(_val) \ 1097 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M, _val) 1098 #define HTT_USR_RATE_NSS(_val) \ 1099 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M, _val) 1100 #define HTT_USR_RATE_MCS(_val) \ 1101 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M, _val) 1102 #define HTT_USR_RATE_GI(_val) \ 1103 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M, _val) 1104 #define HTT_USR_RATE_DCM(_val) \ 1105 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M, _val) 1106 1107 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LTF_SIZE_M GENMASK(1, 0) 1108 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_STBC_M BIT(2) 1109 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_HE_RE_M BIT(3) 1110 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_TXBF_M GENMASK(7, 4) 1111 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_BW_M GENMASK(11, 8) 1112 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_NSS_M GENMASK(15, 12) 1113 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_MCS_M GENMASK(19, 16) 1114 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_PREAMBLE_M GENMASK(23, 20) 1115 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_GI_M GENMASK(27, 24) 1116 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_DCM_M BIT(28) 1117 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LDPC_M BIT(29) 1118 1119 struct htt_ppdu_stats_user_rate { 1120 u8 tid_num; 1121 u8 reserved0; 1122 u16 sw_peer_id; 1123 u32 info0; /* %HTT_PPDU_STATS_USER_RATE_INFO0_*/ 1124 u16 ru_end; 1125 u16 ru_start; 1126 u16 resp_ru_end; 1127 u16 resp_ru_start; 1128 u32 info1; /* %HTT_PPDU_STATS_USER_RATE_INFO1_ */ 1129 u32 rate_flags; /* %HTT_PPDU_STATS_USER_RATE_FLAGS_ */ 1130 /* Note: resp_rate_info is only valid for if resp_type is UL */ 1131 u32 resp_rate_flags; /* %HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_ */ 1132 } __packed; 1133 1134 #define HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M GENMASK(7, 0) 1135 #define HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M BIT(8) 1136 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M GENMASK(10, 9) 1137 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BW_M GENMASK(13, 11) 1138 #define HTT_PPDU_STATS_TX_INFO_FLAGS_SGI_M BIT(14) 1139 #define HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M GENMASK(31, 16) 1140 1141 #define HTT_TX_INFO_IS_AMSDU(_flags) \ 1142 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M, _flags) 1143 #define HTT_TX_INFO_BA_ACK_FAILED(_flags) \ 1144 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M, _flags) 1145 #define HTT_TX_INFO_RATECODE(_flags) \ 1146 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M, _flags) 1147 #define HTT_TX_INFO_PEERID(_flags) \ 1148 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M, _flags) 1149 1150 struct htt_tx_ppdu_stats_info { 1151 struct htt_tlv tlv_hdr; 1152 u32 tx_success_bytes; 1153 u32 tx_retry_bytes; 1154 u32 tx_failed_bytes; 1155 u32 flags; /* %HTT_PPDU_STATS_TX_INFO_FLAGS_ */ 1156 u16 tx_success_msdus; 1157 u16 tx_retry_msdus; 1158 u16 tx_failed_msdus; 1159 u16 tx_duration; /* united in us */ 1160 } __packed; 1161 1162 enum htt_ppdu_stats_usr_compln_status { 1163 HTT_PPDU_STATS_USER_STATUS_OK, 1164 HTT_PPDU_STATS_USER_STATUS_FILTERED, 1165 HTT_PPDU_STATS_USER_STATUS_RESP_TIMEOUT, 1166 HTT_PPDU_STATS_USER_STATUS_RESP_MISMATCH, 1167 HTT_PPDU_STATS_USER_STATUS_ABORT, 1168 }; 1169 1170 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M GENMASK(3, 0) 1171 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M GENMASK(7, 4) 1172 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M BIT(8) 1173 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_RESP_TYPE_M GENMASK(12, 9) 1174 1175 #define HTT_USR_CMPLTN_IS_AMPDU(_val) \ 1176 FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M, _val) 1177 #define HTT_USR_CMPLTN_LONG_RETRY(_val) \ 1178 FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M, _val) 1179 #define HTT_USR_CMPLTN_SHORT_RETRY(_val) \ 1180 FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M, _val) 1181 1182 struct htt_ppdu_stats_usr_cmpltn_cmn { 1183 u8 status; 1184 u8 tid_num; 1185 u16 sw_peer_id; 1186 /* RSSI value of last ack packet (units = dB above noise floor) */ 1187 u32 ack_rssi; 1188 u16 mpdu_tried; 1189 u16 mpdu_success; 1190 u32 flags; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRIES*/ 1191 } __packed; 1192 1193 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MPDU_M GENMASK(8, 0) 1194 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M GENMASK(24, 9) 1195 #define HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM GENMASK(31, 25) 1196 1197 #define HTT_PPDU_STATS_NON_QOS_TID 16 1198 1199 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status { 1200 u32 ppdu_id; 1201 u16 sw_peer_id; 1202 u16 reserved0; 1203 u32 info; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_INFO_ */ 1204 u16 current_seq; 1205 u16 start_seq; 1206 u32 success_bytes; 1207 } __packed; 1208 1209 struct htt_ppdu_stats_usr_cmn_array { 1210 struct htt_tlv tlv_hdr; 1211 u32 num_ppdu_stats; 1212 /* tx_ppdu_stats_info is filled by multiple struct htt_tx_ppdu_stats_info 1213 * elements. 1214 * tx_ppdu_stats_info is variable length, with length = 1215 * number_of_ppdu_stats * sizeof (struct htt_tx_ppdu_stats_info) 1216 */ 1217 struct htt_tx_ppdu_stats_info tx_ppdu_info[0]; 1218 } __packed; 1219 1220 struct htt_ppdu_user_stats { 1221 u16 peer_id; 1222 u32 tlv_flags; 1223 bool is_valid_peer_id; 1224 struct htt_ppdu_stats_user_rate rate; 1225 struct htt_ppdu_stats_usr_cmpltn_cmn cmpltn_cmn; 1226 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status ack_ba; 1227 }; 1228 1229 #define HTT_PPDU_STATS_MAX_USERS 8 1230 #define HTT_PPDU_DESC_MAX_DEPTH 16 1231 1232 struct htt_ppdu_stats { 1233 struct htt_ppdu_stats_common common; 1234 struct htt_ppdu_user_stats user_stats[HTT_PPDU_STATS_MAX_USERS]; 1235 }; 1236 1237 struct htt_ppdu_stats_info { 1238 u32 ppdu_id; 1239 struct htt_ppdu_stats ppdu_stats; 1240 struct list_head list; 1241 }; 1242 1243 /** 1244 * @brief target -> host packet log message 1245 * 1246 * @details 1247 * The following field definitions describe the format of the packet log 1248 * message sent from the target to the host. 1249 * The message consists of a 4-octet header,followed by a variable number 1250 * of 32-bit character values. 1251 * 1252 * |31 16|15 12|11 10|9 8|7 0| 1253 * |------------------------------------------------------------------| 1254 * | payload_size | rsvd |pdev_id|mac_id| msg type | 1255 * |------------------------------------------------------------------| 1256 * | payload | 1257 * |------------------------------------------------------------------| 1258 * - MSG_TYPE 1259 * Bits 7:0 1260 * Purpose: identifies this as a pktlog message 1261 * Value: HTT_T2H_MSG_TYPE_PKTLOG 1262 * - mac_id 1263 * Bits 9:8 1264 * Purpose: identifies which MAC/PHY instance generated this pktlog info 1265 * Value: 0-3 1266 * - pdev_id 1267 * Bits 11:10 1268 * Purpose: pdev_id 1269 * Value: 0-3 1270 * 0 (for rings at SOC level), 1271 * 1/2/3 PDEV -> 0/1/2 1272 * - payload_size 1273 * Bits 31:16 1274 * Purpose: explicitly specify the payload size 1275 * Value: payload size in bytes (payload size is a multiple of 4 bytes) 1276 */ 1277 struct htt_pktlog_msg { 1278 u32 hdr; 1279 u8 payload[0]; 1280 }; 1281 1282 /** 1283 * @brief host -> target FW extended statistics retrieve 1284 * 1285 * @details 1286 * The following field definitions describe the format of the HTT host 1287 * to target FW extended stats retrieve message. 1288 * The message specifies the type of stats the host wants to retrieve. 1289 * 1290 * |31 24|23 16|15 8|7 0| 1291 * |-----------------------------------------------------------| 1292 * | reserved | stats type | pdev_mask | msg type | 1293 * |-----------------------------------------------------------| 1294 * | config param [0] | 1295 * |-----------------------------------------------------------| 1296 * | config param [1] | 1297 * |-----------------------------------------------------------| 1298 * | config param [2] | 1299 * |-----------------------------------------------------------| 1300 * | config param [3] | 1301 * |-----------------------------------------------------------| 1302 * | reserved | 1303 * |-----------------------------------------------------------| 1304 * | cookie LSBs | 1305 * |-----------------------------------------------------------| 1306 * | cookie MSBs | 1307 * |-----------------------------------------------------------| 1308 * Header fields: 1309 * - MSG_TYPE 1310 * Bits 7:0 1311 * Purpose: identifies this is a extended stats upload request message 1312 * Value: 0x10 1313 * - PDEV_MASK 1314 * Bits 8:15 1315 * Purpose: identifies the mask of PDEVs to retrieve stats from 1316 * Value: This is a overloaded field, refer to usage and interpretation of 1317 * PDEV in interface document. 1318 * Bit 8 : Reserved for SOC stats 1319 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC 1320 * Indicates MACID_MASK in DBS 1321 * - STATS_TYPE 1322 * Bits 23:16 1323 * Purpose: identifies which FW statistics to upload 1324 * Value: Defined by htt_dbg_ext_stats_type (see htt_stats.h) 1325 * - Reserved 1326 * Bits 31:24 1327 * - CONFIG_PARAM [0] 1328 * Bits 31:0 1329 * Purpose: give an opaque configuration value to the specified stats type 1330 * Value: stats-type specific configuration value 1331 * Refer to htt_stats.h for interpretation for each stats sub_type 1332 * - CONFIG_PARAM [1] 1333 * Bits 31:0 1334 * Purpose: give an opaque configuration value to the specified stats type 1335 * Value: stats-type specific configuration value 1336 * Refer to htt_stats.h for interpretation for each stats sub_type 1337 * - CONFIG_PARAM [2] 1338 * Bits 31:0 1339 * Purpose: give an opaque configuration value to the specified stats type 1340 * Value: stats-type specific configuration value 1341 * Refer to htt_stats.h for interpretation for each stats sub_type 1342 * - CONFIG_PARAM [3] 1343 * Bits 31:0 1344 * Purpose: give an opaque configuration value to the specified stats type 1345 * Value: stats-type specific configuration value 1346 * Refer to htt_stats.h for interpretation for each stats sub_type 1347 * - Reserved [31:0] for future use. 1348 * - COOKIE_LSBS 1349 * Bits 31:0 1350 * Purpose: Provide a mechanism to match a target->host stats confirmation 1351 * message with its preceding host->target stats request message. 1352 * Value: LSBs of the opaque cookie specified by the host-side requestor 1353 * - COOKIE_MSBS 1354 * Bits 31:0 1355 * Purpose: Provide a mechanism to match a target->host stats confirmation 1356 * message with its preceding host->target stats request message. 1357 * Value: MSBs of the opaque cookie specified by the host-side requestor 1358 */ 1359 1360 struct htt_ext_stats_cfg_hdr { 1361 u8 msg_type; 1362 u8 pdev_mask; 1363 u8 stats_type; 1364 u8 reserved; 1365 } __packed; 1366 1367 struct htt_ext_stats_cfg_cmd { 1368 struct htt_ext_stats_cfg_hdr hdr; 1369 u32 cfg_param0; 1370 u32 cfg_param1; 1371 u32 cfg_param2; 1372 u32 cfg_param3; 1373 u32 reserved; 1374 u32 cookie_lsb; 1375 u32 cookie_msb; 1376 } __packed; 1377 1378 /* htt stats config default params */ 1379 #define HTT_STAT_DEFAULT_RESET_START_OFFSET 0 1380 #define HTT_STAT_DEFAULT_CFG0_ALL_HWQS 0xffffffff 1381 #define HTT_STAT_DEFAULT_CFG0_ALL_TXQS 0xffffffff 1382 #define HTT_STAT_DEFAULT_CFG0_ALL_CMDQS 0xffff 1383 #define HTT_STAT_DEFAULT_CFG0_ALL_RINGS 0xffff 1384 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_PEERS 0xff 1385 #define HTT_STAT_DEFAULT_CFG0_CCA_CUMULATIVE 0x00 1386 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_VDEVS 0x00 1387 1388 /* HTT_DBG_EXT_STATS_PEER_INFO 1389 * PARAMS: 1390 * @config_param0: 1391 * [Bit0] - [0] for sw_peer_id, [1] for mac_addr based request 1392 * [Bit15 : Bit 1] htt_peer_stats_req_mode_t 1393 * [Bit31 : Bit16] sw_peer_id 1394 * @config_param1: 1395 * peer_stats_req_type_mask:32 (enum htt_peer_stats_tlv_enum) 1396 * 0 bit htt_peer_stats_cmn_tlv 1397 * 1 bit htt_peer_details_tlv 1398 * 2 bit htt_tx_peer_rate_stats_tlv 1399 * 3 bit htt_rx_peer_rate_stats_tlv 1400 * 4 bit htt_tx_tid_stats_tlv/htt_tx_tid_stats_v1_tlv 1401 * 5 bit htt_rx_tid_stats_tlv 1402 * 6 bit htt_msdu_flow_stats_tlv 1403 * @config_param2: [Bit31 : Bit0] mac_addr31to0 1404 * @config_param3: [Bit15 : Bit0] mac_addr47to32 1405 * [Bit31 : Bit16] reserved 1406 */ 1407 #define HTT_STAT_PEER_INFO_MAC_ADDR BIT(0) 1408 #define HTT_STAT_DEFAULT_PEER_REQ_TYPE 0x7f 1409 1410 /* Used to set different configs to the specified stats type.*/ 1411 struct htt_ext_stats_cfg_params { 1412 u32 cfg0; 1413 u32 cfg1; 1414 u32 cfg2; 1415 u32 cfg3; 1416 }; 1417 1418 /** 1419 * @brief target -> host extended statistics upload 1420 * 1421 * @details 1422 * The following field definitions describe the format of the HTT target 1423 * to host stats upload confirmation message. 1424 * The message contains a cookie echoed from the HTT host->target stats 1425 * upload request, which identifies which request the confirmation is 1426 * for, and a single stats can span over multiple HTT stats indication 1427 * due to the HTT message size limitation so every HTT ext stats indication 1428 * will have tag-length-value stats information elements. 1429 * The tag-length header for each HTT stats IND message also includes a 1430 * status field, to indicate whether the request for the stat type in 1431 * question was fully met, partially met, unable to be met, or invalid 1432 * (if the stat type in question is disabled in the target). 1433 * A Done bit 1's indicate the end of the of stats info elements. 1434 * 1435 * 1436 * |31 16|15 12|11|10 8|7 5|4 0| 1437 * |--------------------------------------------------------------| 1438 * | reserved | msg type | 1439 * |--------------------------------------------------------------| 1440 * | cookie LSBs | 1441 * |--------------------------------------------------------------| 1442 * | cookie MSBs | 1443 * |--------------------------------------------------------------| 1444 * | stats entry length | rsvd | D| S | stat type | 1445 * |--------------------------------------------------------------| 1446 * | type-specific stats info | 1447 * | (see htt_stats.h) | 1448 * |--------------------------------------------------------------| 1449 * Header fields: 1450 * - MSG_TYPE 1451 * Bits 7:0 1452 * Purpose: Identifies this is a extended statistics upload confirmation 1453 * message. 1454 * Value: 0x1c 1455 * - COOKIE_LSBS 1456 * Bits 31:0 1457 * Purpose: Provide a mechanism to match a target->host stats confirmation 1458 * message with its preceding host->target stats request message. 1459 * Value: LSBs of the opaque cookie specified by the host-side requestor 1460 * - COOKIE_MSBS 1461 * Bits 31:0 1462 * Purpose: Provide a mechanism to match a target->host stats confirmation 1463 * message with its preceding host->target stats request message. 1464 * Value: MSBs of the opaque cookie specified by the host-side requestor 1465 * 1466 * Stats Information Element tag-length header fields: 1467 * - STAT_TYPE 1468 * Bits 7:0 1469 * Purpose: identifies the type of statistics info held in the 1470 * following information element 1471 * Value: htt_dbg_ext_stats_type 1472 * - STATUS 1473 * Bits 10:8 1474 * Purpose: indicate whether the requested stats are present 1475 * Value: htt_dbg_ext_stats_status 1476 * - DONE 1477 * Bits 11 1478 * Purpose: 1479 * Indicates the completion of the stats entry, this will be the last 1480 * stats conf HTT segment for the requested stats type. 1481 * Value: 1482 * 0 -> the stats retrieval is ongoing 1483 * 1 -> the stats retrieval is complete 1484 * - LENGTH 1485 * Bits 31:16 1486 * Purpose: indicate the stats information size 1487 * Value: This field specifies the number of bytes of stats information 1488 * that follows the element tag-length header. 1489 * It is expected but not required that this length is a multiple of 1490 * 4 bytes. 1491 */ 1492 1493 #define HTT_T2H_EXT_STATS_INFO1_LENGTH GENMASK(31, 16) 1494 1495 struct ath11k_htt_extd_stats_msg { 1496 u32 info0; 1497 u64 cookie; 1498 u32 info1; 1499 u8 data[0]; 1500 } __packed; 1501 1502 struct htt_mac_addr { 1503 u32 mac_addr_l32; 1504 u32 mac_addr_h16; 1505 }; 1506 1507 static inline void ath11k_dp_get_mac_addr(u32 addr_l32, u16 addr_h16, u8 *addr) 1508 { 1509 if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) { 1510 addr_l32 = swab32(addr_l32); 1511 addr_h16 = swab16(addr_h16); 1512 } 1513 1514 memcpy(addr, &addr_l32, 4); 1515 memcpy(addr + 4, &addr_h16, ETH_ALEN - 4); 1516 } 1517 1518 int ath11k_dp_service_srng(struct ath11k_base *ab, 1519 struct ath11k_ext_irq_grp *irq_grp, 1520 int budget); 1521 int ath11k_dp_htt_connect(struct ath11k_dp *dp); 1522 void ath11k_dp_vdev_tx_attach(struct ath11k *ar, struct ath11k_vif *arvif); 1523 void ath11k_dp_free(struct ath11k_base *ab); 1524 int ath11k_dp_alloc(struct ath11k_base *ab); 1525 int ath11k_dp_pdev_alloc(struct ath11k_base *ab); 1526 void ath11k_dp_pdev_pre_alloc(struct ath11k_base *ab); 1527 void ath11k_dp_pdev_free(struct ath11k_base *ab); 1528 int ath11k_dp_tx_htt_srng_setup(struct ath11k_base *ab, u32 ring_id, 1529 int mac_id, enum hal_ring_type ring_type); 1530 int ath11k_dp_peer_setup(struct ath11k *ar, int vdev_id, const u8 *addr); 1531 void ath11k_dp_peer_cleanup(struct ath11k *ar, int vdev_id, const u8 *addr); 1532 void ath11k_dp_srng_cleanup(struct ath11k_base *ab, struct dp_srng *ring); 1533 int ath11k_dp_srng_setup(struct ath11k_base *ab, struct dp_srng *ring, 1534 enum hal_ring_type type, int ring_num, 1535 int mac_id, int num_entries); 1536 void ath11k_dp_link_desc_cleanup(struct ath11k_base *ab, 1537 struct dp_link_desc_bank *desc_bank, 1538 u32 ring_type, struct dp_srng *ring); 1539 int ath11k_dp_link_desc_setup(struct ath11k_base *ab, 1540 struct dp_link_desc_bank *link_desc_banks, 1541 u32 ring_type, struct hal_srng *srng, 1542 u32 n_link_desc); 1543 1544 #endif 1545