1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef ATH11K_DP_H 7 #define ATH11K_DP_H 8 9 #include "hal_rx.h" 10 11 #define MAX_RXDMA_PER_PDEV 2 12 13 struct ath11k_base; 14 struct ath11k_peer; 15 struct ath11k_dp; 16 struct ath11k_vif; 17 struct hal_tcl_status_ring; 18 struct ath11k_ext_irq_grp; 19 20 struct dp_rx_tid { 21 u8 tid; 22 u32 *vaddr; 23 dma_addr_t paddr; 24 u32 size; 25 u32 ba_win_sz; 26 bool active; 27 28 /* Info related to rx fragments */ 29 u32 cur_sn; 30 u16 last_frag_no; 31 u16 rx_frag_bitmap; 32 33 struct sk_buff_head rx_frags; 34 struct hal_reo_dest_ring *dst_ring_desc; 35 36 /* Timer info related to fragments */ 37 struct timer_list frag_timer; 38 struct ath11k_base *ab; 39 }; 40 41 #define DP_REO_DESC_FREE_THRESHOLD 64 42 #define DP_REO_DESC_FREE_TIMEOUT_MS 1000 43 #define DP_MON_PURGE_TIMEOUT_MS 100 44 #define DP_MON_SERVICE_BUDGET 128 45 46 struct dp_reo_cache_flush_elem { 47 struct list_head list; 48 struct dp_rx_tid data; 49 unsigned long ts; 50 }; 51 52 struct dp_reo_cmd { 53 struct list_head list; 54 struct dp_rx_tid data; 55 int cmd_num; 56 void (*handler)(struct ath11k_dp *, void *, 57 enum hal_reo_cmd_status status); 58 }; 59 60 struct dp_srng { 61 u32 *vaddr_unaligned; 62 u32 *vaddr; 63 dma_addr_t paddr_unaligned; 64 dma_addr_t paddr; 65 int size; 66 u32 ring_id; 67 u8 cached; 68 }; 69 70 struct dp_rxdma_ring { 71 struct dp_srng refill_buf_ring; 72 struct idr bufs_idr; 73 /* Protects bufs_idr */ 74 spinlock_t idr_lock; 75 int bufs_max; 76 }; 77 78 #define ATH11K_TX_COMPL_NEXT(x) (((x) + 1) % DP_TX_COMP_RING_SIZE) 79 80 struct dp_tx_ring { 81 u8 tcl_data_ring_id; 82 struct dp_srng tcl_data_ring; 83 struct dp_srng tcl_comp_ring; 84 struct idr txbuf_idr; 85 /* Protects txbuf_idr and num_pending */ 86 spinlock_t tx_idr_lock; 87 struct hal_wbm_release_ring *tx_status; 88 int tx_status_head; 89 int tx_status_tail; 90 }; 91 92 struct ath11k_pdev_mon_stats { 93 u32 status_ppdu_state; 94 u32 status_ppdu_start; 95 u32 status_ppdu_end; 96 u32 status_ppdu_compl; 97 u32 status_ppdu_start_mis; 98 u32 status_ppdu_end_mis; 99 u32 status_ppdu_done; 100 u32 dest_ppdu_done; 101 u32 dest_mpdu_done; 102 u32 dest_mpdu_drop; 103 u32 dup_mon_linkdesc_cnt; 104 u32 dup_mon_buf_cnt; 105 }; 106 107 struct dp_link_desc_bank { 108 void *vaddr_unaligned; 109 void *vaddr; 110 dma_addr_t paddr_unaligned; 111 dma_addr_t paddr; 112 u32 size; 113 }; 114 115 /* Size to enforce scatter idle list mode */ 116 #define DP_LINK_DESC_ALLOC_SIZE_THRESH 0x200000 117 #define DP_LINK_DESC_BANKS_MAX 8 118 119 #define DP_RX_DESC_COOKIE_INDEX_MAX 0x3ffff 120 #define DP_RX_DESC_COOKIE_POOL_ID_MAX 0x1c0000 121 #define DP_RX_DESC_COOKIE_MAX \ 122 (DP_RX_DESC_COOKIE_INDEX_MAX | DP_RX_DESC_COOKIE_POOL_ID_MAX) 123 #define DP_NOT_PPDU_ID_WRAP_AROUND 20000 124 125 enum ath11k_dp_ppdu_state { 126 DP_PPDU_STATUS_START, 127 DP_PPDU_STATUS_DONE, 128 }; 129 130 struct ath11k_mon_data { 131 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX]; 132 struct hal_rx_mon_ppdu_info mon_ppdu_info; 133 134 u32 mon_ppdu_status; 135 u32 mon_last_buf_cookie; 136 u64 mon_last_linkdesc_paddr; 137 u16 chan_noise_floor; 138 139 struct ath11k_pdev_mon_stats rx_mon_stats; 140 /* lock for monitor data */ 141 spinlock_t mon_lock; 142 struct sk_buff_head rx_status_q; 143 }; 144 145 struct ath11k_pdev_dp { 146 u32 mac_id; 147 atomic_t num_tx_pending; 148 wait_queue_head_t tx_empty_waitq; 149 struct dp_rxdma_ring rx_refill_buf_ring; 150 struct dp_srng rx_mac_buf_ring[MAX_RXDMA_PER_PDEV]; 151 struct dp_srng rxdma_err_dst_ring[MAX_RXDMA_PER_PDEV]; 152 struct dp_srng rxdma_mon_dst_ring; 153 struct dp_srng rxdma_mon_desc_ring; 154 155 struct dp_rxdma_ring rxdma_mon_buf_ring; 156 struct dp_rxdma_ring rx_mon_status_refill_ring[MAX_RXDMA_PER_PDEV]; 157 struct ieee80211_rx_status rx_status; 158 struct ath11k_mon_data mon_data; 159 }; 160 161 #define DP_NUM_CLIENTS_MAX 64 162 #define DP_AVG_TIDS_PER_CLIENT 2 163 #define DP_NUM_TIDS_MAX (DP_NUM_CLIENTS_MAX * DP_AVG_TIDS_PER_CLIENT) 164 #define DP_AVG_MSDUS_PER_FLOW 128 165 #define DP_AVG_FLOWS_PER_TID 2 166 #define DP_AVG_MPDUS_PER_TID_MAX 128 167 #define DP_AVG_MSDUS_PER_MPDU 4 168 169 #define DP_RX_HASH_ENABLE 1 /* Enable hash based Rx steering */ 170 171 #define DP_BA_WIN_SZ_MAX 256 172 173 #define DP_TCL_NUM_RING_MAX 3 174 #define DP_TCL_NUM_RING_MAX_QCA6390 1 175 176 #define DP_IDLE_SCATTER_BUFS_MAX 16 177 178 #define DP_WBM_RELEASE_RING_SIZE 64 179 #define DP_TCL_DATA_RING_SIZE 512 180 #define DP_TX_COMP_RING_SIZE 32768 181 #define DP_TX_IDR_SIZE DP_TX_COMP_RING_SIZE 182 #define DP_TCL_CMD_RING_SIZE 32 183 #define DP_TCL_STATUS_RING_SIZE 32 184 #define DP_REO_DST_RING_MAX 4 185 #define DP_REO_DST_RING_SIZE 2048 186 #define DP_REO_REINJECT_RING_SIZE 32 187 #define DP_RX_RELEASE_RING_SIZE 1024 188 #define DP_REO_EXCEPTION_RING_SIZE 128 189 #define DP_REO_CMD_RING_SIZE 128 190 #define DP_REO_STATUS_RING_SIZE 2048 191 #define DP_RXDMA_BUF_RING_SIZE 4096 192 #define DP_RXDMA_REFILL_RING_SIZE 2048 193 #define DP_RXDMA_ERR_DST_RING_SIZE 1024 194 #define DP_RXDMA_MON_STATUS_RING_SIZE 1024 195 #define DP_RXDMA_MONITOR_BUF_RING_SIZE 4096 196 #define DP_RXDMA_MONITOR_DST_RING_SIZE 2048 197 #define DP_RXDMA_MONITOR_DESC_RING_SIZE 4096 198 199 #define DP_RX_BUFFER_SIZE 2048 200 #define DP_RX_BUFFER_SIZE_LITE 1024 201 #define DP_RX_BUFFER_ALIGN_SIZE 128 202 203 #define DP_RXDMA_BUF_COOKIE_BUF_ID GENMASK(17, 0) 204 #define DP_RXDMA_BUF_COOKIE_PDEV_ID GENMASK(20, 18) 205 206 #define DP_HW2SW_MACID(mac_id) ((mac_id) ? ((mac_id) - 1) : 0) 207 #define DP_SW2HW_MACID(mac_id) ((mac_id) + 1) 208 209 #define DP_TX_DESC_ID_MAC_ID GENMASK(1, 0) 210 #define DP_TX_DESC_ID_MSDU_ID GENMASK(18, 2) 211 #define DP_TX_DESC_ID_POOL_ID GENMASK(20, 19) 212 213 #define ATH11K_SHADOW_DP_TIMER_INTERVAL 20 214 #define ATH11K_SHADOW_CTRL_TIMER_INTERVAL 10 215 216 struct ath11k_hp_update_timer { 217 struct timer_list timer; 218 bool started; 219 bool init; 220 u32 tx_num; 221 u32 timer_tx_num; 222 u32 ring_id; 223 u32 interval; 224 struct ath11k_base *ab; 225 }; 226 227 struct ath11k_dp { 228 struct ath11k_base *ab; 229 enum ath11k_htc_ep_id eid; 230 struct completion htt_tgt_version_received; 231 u8 htt_tgt_ver_major; 232 u8 htt_tgt_ver_minor; 233 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX]; 234 struct dp_srng wbm_idle_ring; 235 struct dp_srng wbm_desc_rel_ring; 236 struct dp_srng tcl_cmd_ring; 237 struct dp_srng tcl_status_ring; 238 struct dp_srng reo_reinject_ring; 239 struct dp_srng rx_rel_ring; 240 struct dp_srng reo_except_ring; 241 struct dp_srng reo_cmd_ring; 242 struct dp_srng reo_status_ring; 243 struct dp_srng reo_dst_ring[DP_REO_DST_RING_MAX]; 244 struct dp_tx_ring tx_ring[DP_TCL_NUM_RING_MAX]; 245 struct hal_wbm_idle_scatter_list scatter_list[DP_IDLE_SCATTER_BUFS_MAX]; 246 struct list_head reo_cmd_list; 247 struct list_head reo_cmd_cache_flush_list; 248 u32 reo_cmd_cache_flush_count; 249 /** 250 * protects access to below fields, 251 * - reo_cmd_list 252 * - reo_cmd_cache_flush_list 253 * - reo_cmd_cache_flush_count 254 */ 255 spinlock_t reo_cmd_lock; 256 struct ath11k_hp_update_timer reo_cmd_timer; 257 struct ath11k_hp_update_timer tx_ring_timer[DP_TCL_NUM_RING_MAX]; 258 }; 259 260 /* HTT definitions */ 261 262 #define HTT_TCL_META_DATA_TYPE BIT(0) 263 #define HTT_TCL_META_DATA_VALID_HTT BIT(1) 264 265 /* vdev meta data */ 266 #define HTT_TCL_META_DATA_VDEV_ID GENMASK(9, 2) 267 #define HTT_TCL_META_DATA_PDEV_ID GENMASK(11, 10) 268 #define HTT_TCL_META_DATA_HOST_INSPECTED BIT(12) 269 270 /* peer meta data */ 271 #define HTT_TCL_META_DATA_PEER_ID GENMASK(15, 2) 272 273 #define HTT_TX_WBM_COMP_STATUS_OFFSET 8 274 275 /* HTT tx completion is overlayed in wbm_release_ring */ 276 #define HTT_TX_WBM_COMP_INFO0_STATUS GENMASK(12, 9) 277 #define HTT_TX_WBM_COMP_INFO0_REINJECT_REASON GENMASK(16, 13) 278 #define HTT_TX_WBM_COMP_INFO0_REINJECT_REASON GENMASK(16, 13) 279 280 #define HTT_TX_WBM_COMP_INFO1_ACK_RSSI GENMASK(31, 24) 281 282 struct htt_tx_wbm_completion { 283 u32 info0; 284 u32 info1; 285 u32 info2; 286 u32 info3; 287 } __packed; 288 289 enum htt_h2t_msg_type { 290 HTT_H2T_MSG_TYPE_VERSION_REQ = 0, 291 HTT_H2T_MSG_TYPE_SRING_SETUP = 0xb, 292 HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG = 0xc, 293 HTT_H2T_MSG_TYPE_EXT_STATS_CFG = 0x10, 294 HTT_H2T_MSG_TYPE_PPDU_STATS_CFG = 0x11, 295 }; 296 297 #define HTT_VER_REQ_INFO_MSG_ID GENMASK(7, 0) 298 299 struct htt_ver_req_cmd { 300 u32 ver_reg_info; 301 } __packed; 302 303 enum htt_srng_ring_type { 304 HTT_HW_TO_SW_RING, 305 HTT_SW_TO_HW_RING, 306 HTT_SW_TO_SW_RING, 307 }; 308 309 enum htt_srng_ring_id { 310 HTT_RXDMA_HOST_BUF_RING, 311 HTT_RXDMA_MONITOR_STATUS_RING, 312 HTT_RXDMA_MONITOR_BUF_RING, 313 HTT_RXDMA_MONITOR_DESC_RING, 314 HTT_RXDMA_MONITOR_DEST_RING, 315 HTT_HOST1_TO_FW_RXBUF_RING, 316 HTT_HOST2_TO_FW_RXBUF_RING, 317 HTT_RXDMA_NON_MONITOR_DEST_RING, 318 }; 319 320 /* host -> target HTT_SRING_SETUP message 321 * 322 * After target is booted up, Host can send SRING setup message for 323 * each host facing LMAC SRING. Target setups up HW registers based 324 * on setup message and confirms back to Host if response_required is set. 325 * Host should wait for confirmation message before sending new SRING 326 * setup message 327 * 328 * The message would appear as follows: 329 * 330 * |31 24|23 20|19|18 16|15|14 8|7 0| 331 * |--------------- +-----------------+----------------+------------------| 332 * | ring_type | ring_id | pdev_id | msg_type | 333 * |----------------------------------------------------------------------| 334 * | ring_base_addr_lo | 335 * |----------------------------------------------------------------------| 336 * | ring_base_addr_hi | 337 * |----------------------------------------------------------------------| 338 * |ring_misc_cfg_flag|ring_entry_size| ring_size | 339 * |----------------------------------------------------------------------| 340 * | ring_head_offset32_remote_addr_lo | 341 * |----------------------------------------------------------------------| 342 * | ring_head_offset32_remote_addr_hi | 343 * |----------------------------------------------------------------------| 344 * | ring_tail_offset32_remote_addr_lo | 345 * |----------------------------------------------------------------------| 346 * | ring_tail_offset32_remote_addr_hi | 347 * |----------------------------------------------------------------------| 348 * | ring_msi_addr_lo | 349 * |----------------------------------------------------------------------| 350 * | ring_msi_addr_hi | 351 * |----------------------------------------------------------------------| 352 * | ring_msi_data | 353 * |----------------------------------------------------------------------| 354 * | intr_timer_th |IM| intr_batch_counter_th | 355 * |----------------------------------------------------------------------| 356 * | reserved |RR|PTCF| intr_low_threshold | 357 * |----------------------------------------------------------------------| 358 * Where 359 * IM = sw_intr_mode 360 * RR = response_required 361 * PTCF = prefetch_timer_cfg 362 * 363 * The message is interpreted as follows: 364 * dword0 - b'0:7 - msg_type: This will be set to 365 * HTT_H2T_MSG_TYPE_SRING_SETUP 366 * b'8:15 - pdev_id: 367 * 0 (for rings at SOC/UMAC level), 368 * 1/2/3 mac id (for rings at LMAC level) 369 * b'16:23 - ring_id: identify which ring is to setup, 370 * more details can be got from enum htt_srng_ring_id 371 * b'24:31 - ring_type: identify type of host rings, 372 * more details can be got from enum htt_srng_ring_type 373 * dword1 - b'0:31 - ring_base_addr_lo: Lower 32bits of ring base address 374 * dword2 - b'0:31 - ring_base_addr_hi: Upper 32bits of ring base address 375 * dword3 - b'0:15 - ring_size: size of the ring in unit of 4-bytes words 376 * b'16:23 - ring_entry_size: Size of each entry in 4-byte word units 377 * b'24:31 - ring_misc_cfg_flag: Valid only for HW_TO_SW_RING and 378 * SW_TO_HW_RING. 379 * Refer to HTT_SRING_SETUP_RING_MISC_CFG_RING defs. 380 * dword4 - b'0:31 - ring_head_off32_remote_addr_lo: 381 * Lower 32 bits of memory address of the remote variable 382 * storing the 4-byte word offset that identifies the head 383 * element within the ring. 384 * (The head offset variable has type u32.) 385 * Valid for HW_TO_SW and SW_TO_SW rings. 386 * dword5 - b'0:31 - ring_head_off32_remote_addr_hi: 387 * Upper 32 bits of memory address of the remote variable 388 * storing the 4-byte word offset that identifies the head 389 * element within the ring. 390 * (The head offset variable has type u32.) 391 * Valid for HW_TO_SW and SW_TO_SW rings. 392 * dword6 - b'0:31 - ring_tail_off32_remote_addr_lo: 393 * Lower 32 bits of memory address of the remote variable 394 * storing the 4-byte word offset that identifies the tail 395 * element within the ring. 396 * (The tail offset variable has type u32.) 397 * Valid for HW_TO_SW and SW_TO_SW rings. 398 * dword7 - b'0:31 - ring_tail_off32_remote_addr_hi: 399 * Upper 32 bits of memory address of the remote variable 400 * storing the 4-byte word offset that identifies the tail 401 * element within the ring. 402 * (The tail offset variable has type u32.) 403 * Valid for HW_TO_SW and SW_TO_SW rings. 404 * dword8 - b'0:31 - ring_msi_addr_lo: Lower 32bits of MSI cfg address 405 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 406 * dword9 - b'0:31 - ring_msi_addr_hi: Upper 32bits of MSI cfg address 407 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 408 * dword10 - b'0:31 - ring_msi_data: MSI data 409 * Refer to HTT_SRING_SETUP_RING_MSC_CFG_xxx defs 410 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 411 * dword11 - b'0:14 - intr_batch_counter_th: 412 * batch counter threshold is in units of 4-byte words. 413 * HW internally maintains and increments batch count. 414 * (see SRING spec for detail description). 415 * When batch count reaches threshold value, an interrupt 416 * is generated by HW. 417 * b'15 - sw_intr_mode: 418 * This configuration shall be static. 419 * Only programmed at power up. 420 * 0: generate pulse style sw interrupts 421 * 1: generate level style sw interrupts 422 * b'16:31 - intr_timer_th: 423 * The timer init value when timer is idle or is 424 * initialized to start downcounting. 425 * In 8us units (to cover a range of 0 to 524 ms) 426 * dword12 - b'0:15 - intr_low_threshold: 427 * Used only by Consumer ring to generate ring_sw_int_p. 428 * Ring entries low threshold water mark, that is used 429 * in combination with the interrupt timer as well as 430 * the clearing of the level interrupt. 431 * b'16:18 - prefetch_timer_cfg: 432 * Used only by Consumer ring to set timer mode to 433 * support Application prefetch handling. 434 * The external tail offset/pointer will be updated 435 * at following intervals: 436 * 3'b000: (Prefetch feature disabled; used only for debug) 437 * 3'b001: 1 usec 438 * 3'b010: 4 usec 439 * 3'b011: 8 usec (default) 440 * 3'b100: 16 usec 441 * Others: Reserverd 442 * b'19 - response_required: 443 * Host needs HTT_T2H_MSG_TYPE_SRING_SETUP_DONE as response 444 * b'20:31 - reserved: reserved for future use 445 */ 446 447 #define HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 448 #define HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID GENMASK(15, 8) 449 #define HTT_SRNG_SETUP_CMD_INFO0_RING_ID GENMASK(23, 16) 450 #define HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE GENMASK(31, 24) 451 452 #define HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE GENMASK(15, 0) 453 #define HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE GENMASK(23, 16) 454 #define HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS BIT(25) 455 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP BIT(27) 456 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP BIT(28) 457 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP BIT(29) 458 459 #define HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH GENMASK(14, 0) 460 #define HTT_SRNG_SETUP_CMD_INTR_INFO_SW_INTR_MODE BIT(15) 461 #define HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH GENMASK(31, 16) 462 463 #define HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH GENMASK(15, 0) 464 #define HTT_SRNG_SETUP_CMD_INFO2_PRE_FETCH_TIMER_CFG BIT(16) 465 #define HTT_SRNG_SETUP_CMD_INFO2_RESPONSE_REQUIRED BIT(19) 466 467 struct htt_srng_setup_cmd { 468 u32 info0; 469 u32 ring_base_addr_lo; 470 u32 ring_base_addr_hi; 471 u32 info1; 472 u32 ring_head_off32_remote_addr_lo; 473 u32 ring_head_off32_remote_addr_hi; 474 u32 ring_tail_off32_remote_addr_lo; 475 u32 ring_tail_off32_remote_addr_hi; 476 u32 ring_msi_addr_lo; 477 u32 ring_msi_addr_hi; 478 u32 msi_data; 479 u32 intr_info; 480 u32 info2; 481 } __packed; 482 483 /* host -> target FW PPDU_STATS config message 484 * 485 * @details 486 * The following field definitions describe the format of the HTT host 487 * to target FW for PPDU_STATS_CFG msg. 488 * The message allows the host to configure the PPDU_STATS_IND messages 489 * produced by the target. 490 * 491 * |31 24|23 16|15 8|7 0| 492 * |-----------------------------------------------------------| 493 * | REQ bit mask | pdev_mask | msg type | 494 * |-----------------------------------------------------------| 495 * Header fields: 496 * - MSG_TYPE 497 * Bits 7:0 498 * Purpose: identifies this is a req to configure ppdu_stats_ind from target 499 * Value: 0x11 500 * - PDEV_MASK 501 * Bits 8:15 502 * Purpose: identifies which pdevs this PPDU stats configuration applies to 503 * Value: This is a overloaded field, refer to usage and interpretation of 504 * PDEV in interface document. 505 * Bit 8 : Reserved for SOC stats 506 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC 507 * Indicates MACID_MASK in DBS 508 * - REQ_TLV_BIT_MASK 509 * Bits 16:31 510 * Purpose: each set bit indicates the corresponding PPDU stats TLV type 511 * needs to be included in the target's PPDU_STATS_IND messages. 512 * Value: refer htt_ppdu_stats_tlv_tag_t <<<??? 513 * 514 */ 515 516 struct htt_ppdu_stats_cfg_cmd { 517 u32 msg; 518 } __packed; 519 520 #define HTT_PPDU_STATS_CFG_MSG_TYPE GENMASK(7, 0) 521 #define HTT_PPDU_STATS_CFG_SOC_STATS BIT(8) 522 #define HTT_PPDU_STATS_CFG_PDEV_ID GENMASK(15, 9) 523 #define HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK GENMASK(31, 16) 524 525 enum htt_ppdu_stats_tag_type { 526 HTT_PPDU_STATS_TAG_COMMON, 527 HTT_PPDU_STATS_TAG_USR_COMMON, 528 HTT_PPDU_STATS_TAG_USR_RATE, 529 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64, 530 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256, 531 HTT_PPDU_STATS_TAG_SCH_CMD_STATUS, 532 HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON, 533 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64, 534 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256, 535 HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS, 536 HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH, 537 HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY, 538 HTT_PPDU_STATS_TAG_INFO, 539 HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD, 540 541 /* New TLV's are added above to this line */ 542 HTT_PPDU_STATS_TAG_MAX, 543 }; 544 545 #define HTT_PPDU_STATS_TAG_DEFAULT (BIT(HTT_PPDU_STATS_TAG_COMMON) \ 546 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON) \ 547 | BIT(HTT_PPDU_STATS_TAG_USR_RATE) \ 548 | BIT(HTT_PPDU_STATS_TAG_SCH_CMD_STATUS) \ 549 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON) \ 550 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS) \ 551 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH) \ 552 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY)) 553 554 #define HTT_PPDU_STATS_TAG_PKTLOG (BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64) | \ 555 BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256) | \ 556 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64) | \ 557 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256) | \ 558 BIT(HTT_PPDU_STATS_TAG_INFO) | \ 559 BIT(HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD) | \ 560 HTT_PPDU_STATS_TAG_DEFAULT) 561 562 /* HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG Message 563 * 564 * details: 565 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG message is sent by host to 566 * configure RXDMA rings. 567 * The configuration is per ring based and includes both packet subtypes 568 * and PPDU/MPDU TLVs. 569 * 570 * The message would appear as follows: 571 * 572 * |31 26|25|24|23 16|15 8|7 0| 573 * |-----------------+----------------+----------------+---------------| 574 * | rsvd1 |PS|SS| ring_id | pdev_id | msg_type | 575 * |-------------------------------------------------------------------| 576 * | rsvd2 | ring_buffer_size | 577 * |-------------------------------------------------------------------| 578 * | packet_type_enable_flags_0 | 579 * |-------------------------------------------------------------------| 580 * | packet_type_enable_flags_1 | 581 * |-------------------------------------------------------------------| 582 * | packet_type_enable_flags_2 | 583 * |-------------------------------------------------------------------| 584 * | packet_type_enable_flags_3 | 585 * |-------------------------------------------------------------------| 586 * | tlv_filter_in_flags | 587 * |-------------------------------------------------------------------| 588 * Where: 589 * PS = pkt_swap 590 * SS = status_swap 591 * The message is interpreted as follows: 592 * dword0 - b'0:7 - msg_type: This will be set to 593 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG 594 * b'8:15 - pdev_id: 595 * 0 (for rings at SOC/UMAC level), 596 * 1/2/3 mac id (for rings at LMAC level) 597 * b'16:23 - ring_id : Identify the ring to configure. 598 * More details can be got from enum htt_srng_ring_id 599 * b'24 - status_swap: 1 is to swap status TLV 600 * b'25 - pkt_swap: 1 is to swap packet TLV 601 * b'26:31 - rsvd1: reserved for future use 602 * dword1 - b'0:16 - ring_buffer_size: size of bufferes referenced by rx ring, 603 * in byte units. 604 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING 605 * - b'16:31 - rsvd2: Reserved for future use 606 * dword2 - b'0:31 - packet_type_enable_flags_0: 607 * Enable MGMT packet from 0b0000 to 0b1001 608 * bits from low to high: FP, MD, MO - 3 bits 609 * FP: Filter_Pass 610 * MD: Monitor_Direct 611 * MO: Monitor_Other 612 * 10 mgmt subtypes * 3 bits -> 30 bits 613 * Refer to PKT_TYPE_ENABLE_FLAG0_xxx_MGMT_xxx defs 614 * dword3 - b'0:31 - packet_type_enable_flags_1: 615 * Enable MGMT packet from 0b1010 to 0b1111 616 * bits from low to high: FP, MD, MO - 3 bits 617 * Refer to PKT_TYPE_ENABLE_FLAG1_xxx_MGMT_xxx defs 618 * dword4 - b'0:31 - packet_type_enable_flags_2: 619 * Enable CTRL packet from 0b0000 to 0b1001 620 * bits from low to high: FP, MD, MO - 3 bits 621 * Refer to PKT_TYPE_ENABLE_FLAG2_xxx_CTRL_xxx defs 622 * dword5 - b'0:31 - packet_type_enable_flags_3: 623 * Enable CTRL packet from 0b1010 to 0b1111, 624 * MCAST_DATA, UCAST_DATA, NULL_DATA 625 * bits from low to high: FP, MD, MO - 3 bits 626 * Refer to PKT_TYPE_ENABLE_FLAG3_xxx_CTRL_xxx defs 627 * dword6 - b'0:31 - tlv_filter_in_flags: 628 * Filter in Attention/MPDU/PPDU/Header/User tlvs 629 * Refer to CFG_TLV_FILTER_IN_FLAG defs 630 */ 631 632 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 633 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8) 634 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16) 635 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS BIT(24) 636 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS BIT(25) 637 638 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE GENMASK(15, 0) 639 640 enum htt_rx_filter_tlv_flags { 641 HTT_RX_FILTER_TLV_FLAGS_MPDU_START = BIT(0), 642 HTT_RX_FILTER_TLV_FLAGS_MSDU_START = BIT(1), 643 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET = BIT(2), 644 HTT_RX_FILTER_TLV_FLAGS_MSDU_END = BIT(3), 645 HTT_RX_FILTER_TLV_FLAGS_MPDU_END = BIT(4), 646 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER = BIT(5), 647 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER = BIT(6), 648 HTT_RX_FILTER_TLV_FLAGS_ATTENTION = BIT(7), 649 HTT_RX_FILTER_TLV_FLAGS_PPDU_START = BIT(8), 650 HTT_RX_FILTER_TLV_FLAGS_PPDU_END = BIT(9), 651 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS = BIT(10), 652 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT = BIT(11), 653 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE = BIT(12), 654 }; 655 656 enum htt_rx_mgmt_pkt_filter_tlv_flags0 { 657 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(0), 658 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(1), 659 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(2), 660 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(3), 661 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(4), 662 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(5), 663 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(6), 664 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(7), 665 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(8), 666 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(9), 667 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(10), 668 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(11), 669 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(12), 670 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(13), 671 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(14), 672 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(15), 673 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(16), 674 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(17), 675 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(18), 676 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(19), 677 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(20), 678 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(21), 679 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(22), 680 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(23), 681 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(24), 682 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(25), 683 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(26), 684 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(27), 685 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(28), 686 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(29), 687 }; 688 689 enum htt_rx_mgmt_pkt_filter_tlv_flags1 { 690 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(0), 691 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(1), 692 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(2), 693 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(3), 694 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(4), 695 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(5), 696 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(6), 697 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(7), 698 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(8), 699 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(9), 700 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(10), 701 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(11), 702 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(12), 703 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(13), 704 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(14), 705 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(15), 706 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(16), 707 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(17), 708 }; 709 710 enum htt_rx_ctrl_pkt_filter_tlv_flags2 { 711 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(0), 712 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(1), 713 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(2), 714 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(3), 715 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(4), 716 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(5), 717 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(6), 718 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(7), 719 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(8), 720 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(9), 721 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(10), 722 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(11), 723 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(12), 724 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(13), 725 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(14), 726 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(15), 727 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(16), 728 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(17), 729 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(18), 730 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(19), 731 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(20), 732 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(21), 733 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(22), 734 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(23), 735 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(24), 736 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(25), 737 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(26), 738 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(27), 739 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(28), 740 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(29), 741 }; 742 743 enum htt_rx_ctrl_pkt_filter_tlv_flags3 { 744 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(0), 745 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(1), 746 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(2), 747 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(3), 748 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(4), 749 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(5), 750 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(6), 751 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(7), 752 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(8), 753 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(9), 754 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(10), 755 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(11), 756 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(12), 757 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(13), 758 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(14), 759 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(15), 760 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(16), 761 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(17), 762 }; 763 764 enum htt_rx_data_pkt_filter_tlv_flasg3 { 765 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(18), 766 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(19), 767 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(20), 768 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(21), 769 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(22), 770 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(23), 771 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(24), 772 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(25), 773 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(26), 774 }; 775 776 #define HTT_RX_FP_MGMT_FILTER_FLAGS0 \ 777 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 778 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 779 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 780 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 781 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 782 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 783 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 784 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 785 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 786 787 #define HTT_RX_MD_MGMT_FILTER_FLAGS0 \ 788 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 789 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 790 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 791 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 792 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 793 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 794 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 795 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 796 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 797 798 #define HTT_RX_MO_MGMT_FILTER_FLAGS0 \ 799 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 800 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 801 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 802 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 803 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 804 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 805 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 806 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 807 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 808 809 #define HTT_RX_FP_MGMT_FILTER_FLAGS1 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 810 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 811 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 812 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 813 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 814 815 #define HTT_RX_MD_MGMT_FILTER_FLAGS1 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 816 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 817 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 818 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 819 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 820 821 #define HTT_RX_MO_MGMT_FILTER_FLAGS1 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 822 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 823 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 824 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 825 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 826 827 #define HTT_RX_FP_CTRL_FILTER_FLASG2 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 828 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 829 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 830 831 #define HTT_RX_MD_CTRL_FILTER_FLASG2 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 832 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 833 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 834 835 #define HTT_RX_MO_CTRL_FILTER_FLASG2 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 836 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 837 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 838 839 #define HTT_RX_FP_CTRL_FILTER_FLASG3 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 840 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 841 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 842 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 843 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 844 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 845 846 #define HTT_RX_MD_CTRL_FILTER_FLASG3 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 847 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 848 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 849 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 850 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 851 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 852 853 #define HTT_RX_MO_CTRL_FILTER_FLASG3 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 854 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 855 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 856 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 857 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 858 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 859 860 #define HTT_RX_FP_DATA_FILTER_FLASG3 (HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 861 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 862 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 863 864 #define HTT_RX_MD_DATA_FILTER_FLASG3 (HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 865 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 866 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 867 868 #define HTT_RX_MO_DATA_FILTER_FLASG3 (HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 869 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 870 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 871 872 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 \ 873 (HTT_RX_FP_MGMT_FILTER_FLAGS0 | \ 874 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7) 875 876 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS0 \ 877 (HTT_RX_MO_MGMT_FILTER_FLAGS0 | \ 878 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7) 879 880 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 \ 881 (HTT_RX_FP_MGMT_FILTER_FLAGS1 | \ 882 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15) 883 884 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS1 \ 885 (HTT_RX_MO_MGMT_FILTER_FLAGS1 | \ 886 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15) 887 888 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG2 \ 889 (HTT_RX_FP_CTRL_FILTER_FLASG2 | \ 890 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \ 891 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \ 892 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \ 893 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \ 894 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \ 895 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \ 896 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT) 897 898 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG2 \ 899 (HTT_RX_MO_CTRL_FILTER_FLASG2 | \ 900 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \ 901 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \ 902 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \ 903 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \ 904 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \ 905 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \ 906 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT) 907 908 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG3 HTT_RX_FP_CTRL_FILTER_FLASG3 909 910 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG3 HTT_RX_MO_CTRL_FILTER_FLASG3 911 912 #define HTT_RX_MON_FP_DATA_FILTER_FLASG3 HTT_RX_FP_DATA_FILTER_FLASG3 913 914 #define HTT_RX_MON_MO_DATA_FILTER_FLASG3 HTT_RX_MO_DATA_FILTER_FLASG3 915 916 #define HTT_RX_MON_FILTER_TLV_FLAGS \ 917 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 918 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \ 919 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \ 920 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \ 921 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \ 922 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE) 923 924 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING \ 925 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 926 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \ 927 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \ 928 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \ 929 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \ 930 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE) 931 932 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING \ 933 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 934 HTT_RX_FILTER_TLV_FLAGS_MSDU_START | \ 935 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \ 936 HTT_RX_FILTER_TLV_FLAGS_MSDU_END | \ 937 HTT_RX_FILTER_TLV_FLAGS_MPDU_END | \ 938 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER | \ 939 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER | \ 940 HTT_RX_FILTER_TLV_FLAGS_ATTENTION) 941 942 struct htt_rx_ring_selection_cfg_cmd { 943 u32 info0; 944 u32 info1; 945 u32 pkt_type_en_flags0; 946 u32 pkt_type_en_flags1; 947 u32 pkt_type_en_flags2; 948 u32 pkt_type_en_flags3; 949 u32 rx_filter_tlv; 950 } __packed; 951 952 struct htt_rx_ring_tlv_filter { 953 u32 rx_filter; /* see htt_rx_filter_tlv_flags */ 954 u32 pkt_filter_flags0; /* MGMT */ 955 u32 pkt_filter_flags1; /* MGMT */ 956 u32 pkt_filter_flags2; /* CTRL */ 957 u32 pkt_filter_flags3; /* DATA */ 958 }; 959 960 /* HTT message target->host */ 961 962 enum htt_t2h_msg_type { 963 HTT_T2H_MSG_TYPE_VERSION_CONF, 964 HTT_T2H_MSG_TYPE_PEER_MAP = 0x3, 965 HTT_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 966 HTT_T2H_MSG_TYPE_RX_ADDBA = 0x5, 967 HTT_T2H_MSG_TYPE_PKTLOG = 0x8, 968 HTT_T2H_MSG_TYPE_SEC_IND = 0xb, 969 HTT_T2H_MSG_TYPE_PEER_MAP2 = 0x1e, 970 HTT_T2H_MSG_TYPE_PEER_UNMAP2 = 0x1f, 971 HTT_T2H_MSG_TYPE_PPDU_STATS_IND = 0x1d, 972 HTT_T2H_MSG_TYPE_EXT_STATS_CONF = 0x1c, 973 HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND = 0x24, 974 }; 975 976 #define HTT_TARGET_VERSION_MAJOR 3 977 978 #define HTT_T2H_MSG_TYPE GENMASK(7, 0) 979 #define HTT_T2H_VERSION_CONF_MINOR GENMASK(15, 8) 980 #define HTT_T2H_VERSION_CONF_MAJOR GENMASK(23, 16) 981 982 struct htt_t2h_version_conf_msg { 983 u32 version; 984 } __packed; 985 986 #define HTT_T2H_PEER_MAP_INFO_VDEV_ID GENMASK(15, 8) 987 #define HTT_T2H_PEER_MAP_INFO_PEER_ID GENMASK(31, 16) 988 #define HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 GENMASK(15, 0) 989 #define HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID GENMASK(31, 16) 990 #define HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL GENMASK(15, 0) 991 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M BIT(16) 992 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 16 993 994 struct htt_t2h_peer_map_event { 995 u32 info; 996 u32 mac_addr_l32; 997 u32 info1; 998 u32 info2; 999 } __packed; 1000 1001 #define HTT_T2H_PEER_UNMAP_INFO_VDEV_ID HTT_T2H_PEER_MAP_INFO_VDEV_ID 1002 #define HTT_T2H_PEER_UNMAP_INFO_PEER_ID HTT_T2H_PEER_MAP_INFO_PEER_ID 1003 #define HTT_T2H_PEER_UNMAP_INFO1_MAC_ADDR_H16 \ 1004 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 1005 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_M HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M 1006 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_S HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 1007 1008 struct htt_t2h_peer_unmap_event { 1009 u32 info; 1010 u32 mac_addr_l32; 1011 u32 info1; 1012 } __packed; 1013 1014 struct htt_resp_msg { 1015 union { 1016 struct htt_t2h_version_conf_msg version_msg; 1017 struct htt_t2h_peer_map_event peer_map_ev; 1018 struct htt_t2h_peer_unmap_event peer_unmap_ev; 1019 }; 1020 } __packed; 1021 1022 #define HTT_BACKPRESSURE_EVENT_PDEV_ID_M GENMASK(15, 8) 1023 #define HTT_BACKPRESSURE_EVENT_RING_TYPE_M GENMASK(23, 16) 1024 #define HTT_BACKPRESSURE_EVENT_RING_ID_M GENMASK(31, 24) 1025 1026 #define HTT_BACKPRESSURE_EVENT_HP_M GENMASK(15, 0) 1027 #define HTT_BACKPRESSURE_EVENT_TP_M GENMASK(31, 16) 1028 1029 #define HTT_BACKPRESSURE_UMAC_RING_TYPE 0 1030 #define HTT_BACKPRESSURE_LMAC_RING_TYPE 1 1031 1032 enum htt_backpressure_umac_ringid { 1033 HTT_SW_RING_IDX_REO_REO2SW1_RING, 1034 HTT_SW_RING_IDX_REO_REO2SW2_RING, 1035 HTT_SW_RING_IDX_REO_REO2SW3_RING, 1036 HTT_SW_RING_IDX_REO_REO2SW4_RING, 1037 HTT_SW_RING_IDX_REO_WBM2REO_LINK_RING, 1038 HTT_SW_RING_IDX_REO_REO2TCL_RING, 1039 HTT_SW_RING_IDX_REO_REO2FW_RING, 1040 HTT_SW_RING_IDX_REO_REO_RELEASE_RING, 1041 HTT_SW_RING_IDX_WBM_PPE_RELEASE_RING, 1042 HTT_SW_RING_IDX_TCL_TCL2TQM_RING, 1043 HTT_SW_RING_IDX_WBM_TQM_RELEASE_RING, 1044 HTT_SW_RING_IDX_WBM_REO_RELEASE_RING, 1045 HTT_SW_RING_IDX_WBM_WBM2SW0_RELEASE_RING, 1046 HTT_SW_RING_IDX_WBM_WBM2SW1_RELEASE_RING, 1047 HTT_SW_RING_IDX_WBM_WBM2SW2_RELEASE_RING, 1048 HTT_SW_RING_IDX_WBM_WBM2SW3_RELEASE_RING, 1049 HTT_SW_RING_IDX_REO_REO_CMD_RING, 1050 HTT_SW_RING_IDX_REO_REO_STATUS_RING, 1051 HTT_SW_UMAC_RING_IDX_MAX, 1052 }; 1053 1054 enum htt_backpressure_lmac_ringid { 1055 HTT_SW_RING_IDX_FW2RXDMA_BUF_RING, 1056 HTT_SW_RING_IDX_FW2RXDMA_STATUS_RING, 1057 HTT_SW_RING_IDX_FW2RXDMA_LINK_RING, 1058 HTT_SW_RING_IDX_SW2RXDMA_BUF_RING, 1059 HTT_SW_RING_IDX_WBM2RXDMA_LINK_RING, 1060 HTT_SW_RING_IDX_RXDMA2FW_RING, 1061 HTT_SW_RING_IDX_RXDMA2SW_RING, 1062 HTT_SW_RING_IDX_RXDMA2RELEASE_RING, 1063 HTT_SW_RING_IDX_RXDMA2REO_RING, 1064 HTT_SW_RING_IDX_MONITOR_STATUS_RING, 1065 HTT_SW_RING_IDX_MONITOR_BUF_RING, 1066 HTT_SW_RING_IDX_MONITOR_DESC_RING, 1067 HTT_SW_RING_IDX_MONITOR_DEST_RING, 1068 HTT_SW_LMAC_RING_IDX_MAX, 1069 }; 1070 1071 /* ppdu stats 1072 * 1073 * @details 1074 * The following field definitions describe the format of the HTT target 1075 * to host ppdu stats indication message. 1076 * 1077 * 1078 * |31 16|15 12|11 10|9 8|7 0 | 1079 * |----------------------------------------------------------------------| 1080 * | payload_size | rsvd |pdev_id|mac_id | msg type | 1081 * |----------------------------------------------------------------------| 1082 * | ppdu_id | 1083 * |----------------------------------------------------------------------| 1084 * | Timestamp in us | 1085 * |----------------------------------------------------------------------| 1086 * | reserved | 1087 * |----------------------------------------------------------------------| 1088 * | type-specific stats info | 1089 * | (see htt_ppdu_stats.h) | 1090 * |----------------------------------------------------------------------| 1091 * Header fields: 1092 * - MSG_TYPE 1093 * Bits 7:0 1094 * Purpose: Identifies this is a PPDU STATS indication 1095 * message. 1096 * Value: 0x1d 1097 * - mac_id 1098 * Bits 9:8 1099 * Purpose: mac_id of this ppdu_id 1100 * Value: 0-3 1101 * - pdev_id 1102 * Bits 11:10 1103 * Purpose: pdev_id of this ppdu_id 1104 * Value: 0-3 1105 * 0 (for rings at SOC level), 1106 * 1/2/3 PDEV -> 0/1/2 1107 * - payload_size 1108 * Bits 31:16 1109 * Purpose: total tlv size 1110 * Value: payload_size in bytes 1111 */ 1112 1113 #define HTT_T2H_PPDU_STATS_INFO_PDEV_ID GENMASK(11, 10) 1114 #define HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE GENMASK(31, 16) 1115 1116 struct ath11k_htt_ppdu_stats_msg { 1117 u32 info; 1118 u32 ppdu_id; 1119 u32 timestamp; 1120 u32 rsvd; 1121 u8 data[0]; 1122 } __packed; 1123 1124 struct htt_tlv { 1125 u32 header; 1126 u8 value[0]; 1127 } __packed; 1128 1129 #define HTT_TLV_TAG GENMASK(11, 0) 1130 #define HTT_TLV_LEN GENMASK(23, 12) 1131 1132 enum HTT_PPDU_STATS_BW { 1133 HTT_PPDU_STATS_BANDWIDTH_5MHZ = 0, 1134 HTT_PPDU_STATS_BANDWIDTH_10MHZ = 1, 1135 HTT_PPDU_STATS_BANDWIDTH_20MHZ = 2, 1136 HTT_PPDU_STATS_BANDWIDTH_40MHZ = 3, 1137 HTT_PPDU_STATS_BANDWIDTH_80MHZ = 4, 1138 HTT_PPDU_STATS_BANDWIDTH_160MHZ = 5, /* includes 80+80 */ 1139 HTT_PPDU_STATS_BANDWIDTH_DYN = 6, 1140 }; 1141 1142 #define HTT_PPDU_STATS_CMN_FLAGS_FRAME_TYPE_M GENMASK(7, 0) 1143 #define HTT_PPDU_STATS_CMN_FLAGS_QUEUE_TYPE_M GENMASK(15, 8) 1144 /* bw - HTT_PPDU_STATS_BW */ 1145 #define HTT_PPDU_STATS_CMN_FLAGS_BW_M GENMASK(19, 16) 1146 1147 struct htt_ppdu_stats_common { 1148 u32 ppdu_id; 1149 u16 sched_cmdid; 1150 u8 ring_id; 1151 u8 num_users; 1152 u32 flags; /* %HTT_PPDU_STATS_COMMON_FLAGS_*/ 1153 u32 chain_mask; 1154 u32 fes_duration_us; /* frame exchange sequence */ 1155 u32 ppdu_sch_eval_start_tstmp_us; 1156 u32 ppdu_sch_end_tstmp_us; 1157 u32 ppdu_start_tstmp_us; 1158 /* BIT [15 : 0] - phy mode (WLAN_PHY_MODE) with which ppdu was transmitted 1159 * BIT [31 : 16] - bandwidth (in MHz) with which ppdu was transmitted 1160 */ 1161 u16 phy_mode; 1162 u16 bw_mhz; 1163 } __packed; 1164 1165 enum htt_ppdu_stats_gi { 1166 HTT_PPDU_STATS_SGI_0_8_US, 1167 HTT_PPDU_STATS_SGI_0_4_US, 1168 HTT_PPDU_STATS_SGI_1_6_US, 1169 HTT_PPDU_STATS_SGI_3_2_US, 1170 }; 1171 1172 #define HTT_PPDU_STATS_USER_RATE_INFO0_USER_POS_M GENMASK(3, 0) 1173 #define HTT_PPDU_STATS_USER_RATE_INFO0_MU_GROUP_ID_M GENMASK(11, 4) 1174 1175 #define HTT_PPDU_STATS_USER_RATE_INFO1_RESP_TYPE_VALD_M BIT(0) 1176 #define HTT_PPDU_STATS_USER_RATE_INFO1_PPDU_TYPE_M GENMASK(5, 1) 1177 1178 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LTF_SIZE_M GENMASK(1, 0) 1179 #define HTT_PPDU_STATS_USER_RATE_FLAGS_STBC_M BIT(2) 1180 #define HTT_PPDU_STATS_USER_RATE_FLAGS_HE_RE_M BIT(3) 1181 #define HTT_PPDU_STATS_USER_RATE_FLAGS_TXBF_M GENMASK(7, 4) 1182 #define HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M GENMASK(11, 8) 1183 #define HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M GENMASK(15, 12) 1184 #define HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M GENMASK(19, 16) 1185 #define HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M GENMASK(23, 20) 1186 #define HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M GENMASK(27, 24) 1187 #define HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M BIT(28) 1188 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LDPC_M BIT(29) 1189 1190 #define HTT_USR_RATE_PREAMBLE(_val) \ 1191 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M, _val) 1192 #define HTT_USR_RATE_BW(_val) \ 1193 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M, _val) 1194 #define HTT_USR_RATE_NSS(_val) \ 1195 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M, _val) 1196 #define HTT_USR_RATE_MCS(_val) \ 1197 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M, _val) 1198 #define HTT_USR_RATE_GI(_val) \ 1199 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M, _val) 1200 #define HTT_USR_RATE_DCM(_val) \ 1201 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M, _val) 1202 1203 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LTF_SIZE_M GENMASK(1, 0) 1204 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_STBC_M BIT(2) 1205 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_HE_RE_M BIT(3) 1206 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_TXBF_M GENMASK(7, 4) 1207 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_BW_M GENMASK(11, 8) 1208 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_NSS_M GENMASK(15, 12) 1209 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_MCS_M GENMASK(19, 16) 1210 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_PREAMBLE_M GENMASK(23, 20) 1211 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_GI_M GENMASK(27, 24) 1212 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_DCM_M BIT(28) 1213 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LDPC_M BIT(29) 1214 1215 struct htt_ppdu_stats_user_rate { 1216 u8 tid_num; 1217 u8 reserved0; 1218 u16 sw_peer_id; 1219 u32 info0; /* %HTT_PPDU_STATS_USER_RATE_INFO0_*/ 1220 u16 ru_end; 1221 u16 ru_start; 1222 u16 resp_ru_end; 1223 u16 resp_ru_start; 1224 u32 info1; /* %HTT_PPDU_STATS_USER_RATE_INFO1_ */ 1225 u32 rate_flags; /* %HTT_PPDU_STATS_USER_RATE_FLAGS_ */ 1226 /* Note: resp_rate_info is only valid for if resp_type is UL */ 1227 u32 resp_rate_flags; /* %HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_ */ 1228 } __packed; 1229 1230 #define HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M GENMASK(7, 0) 1231 #define HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M BIT(8) 1232 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M GENMASK(10, 9) 1233 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BW_M GENMASK(13, 11) 1234 #define HTT_PPDU_STATS_TX_INFO_FLAGS_SGI_M BIT(14) 1235 #define HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M GENMASK(31, 16) 1236 1237 #define HTT_TX_INFO_IS_AMSDU(_flags) \ 1238 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M, _flags) 1239 #define HTT_TX_INFO_BA_ACK_FAILED(_flags) \ 1240 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M, _flags) 1241 #define HTT_TX_INFO_RATECODE(_flags) \ 1242 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M, _flags) 1243 #define HTT_TX_INFO_PEERID(_flags) \ 1244 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M, _flags) 1245 1246 struct htt_tx_ppdu_stats_info { 1247 struct htt_tlv tlv_hdr; 1248 u32 tx_success_bytes; 1249 u32 tx_retry_bytes; 1250 u32 tx_failed_bytes; 1251 u32 flags; /* %HTT_PPDU_STATS_TX_INFO_FLAGS_ */ 1252 u16 tx_success_msdus; 1253 u16 tx_retry_msdus; 1254 u16 tx_failed_msdus; 1255 u16 tx_duration; /* united in us */ 1256 } __packed; 1257 1258 enum htt_ppdu_stats_usr_compln_status { 1259 HTT_PPDU_STATS_USER_STATUS_OK, 1260 HTT_PPDU_STATS_USER_STATUS_FILTERED, 1261 HTT_PPDU_STATS_USER_STATUS_RESP_TIMEOUT, 1262 HTT_PPDU_STATS_USER_STATUS_RESP_MISMATCH, 1263 HTT_PPDU_STATS_USER_STATUS_ABORT, 1264 }; 1265 1266 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M GENMASK(3, 0) 1267 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M GENMASK(7, 4) 1268 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M BIT(8) 1269 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_RESP_TYPE_M GENMASK(12, 9) 1270 1271 #define HTT_USR_CMPLTN_IS_AMPDU(_val) \ 1272 FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M, _val) 1273 #define HTT_USR_CMPLTN_LONG_RETRY(_val) \ 1274 FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M, _val) 1275 #define HTT_USR_CMPLTN_SHORT_RETRY(_val) \ 1276 FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M, _val) 1277 1278 struct htt_ppdu_stats_usr_cmpltn_cmn { 1279 u8 status; 1280 u8 tid_num; 1281 u16 sw_peer_id; 1282 /* RSSI value of last ack packet (units = dB above noise floor) */ 1283 u32 ack_rssi; 1284 u16 mpdu_tried; 1285 u16 mpdu_success; 1286 u32 flags; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRIES*/ 1287 } __packed; 1288 1289 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MPDU_M GENMASK(8, 0) 1290 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M GENMASK(24, 9) 1291 #define HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM GENMASK(31, 25) 1292 1293 #define HTT_PPDU_STATS_NON_QOS_TID 16 1294 1295 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status { 1296 u32 ppdu_id; 1297 u16 sw_peer_id; 1298 u16 reserved0; 1299 u32 info; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_INFO_ */ 1300 u16 current_seq; 1301 u16 start_seq; 1302 u32 success_bytes; 1303 } __packed; 1304 1305 struct htt_ppdu_stats_usr_cmn_array { 1306 struct htt_tlv tlv_hdr; 1307 u32 num_ppdu_stats; 1308 /* tx_ppdu_stats_info is filled by multiple struct htt_tx_ppdu_stats_info 1309 * elements. 1310 * tx_ppdu_stats_info is variable length, with length = 1311 * number_of_ppdu_stats * sizeof (struct htt_tx_ppdu_stats_info) 1312 */ 1313 struct htt_tx_ppdu_stats_info tx_ppdu_info[0]; 1314 } __packed; 1315 1316 struct htt_ppdu_user_stats { 1317 u16 peer_id; 1318 u32 tlv_flags; 1319 bool is_valid_peer_id; 1320 struct htt_ppdu_stats_user_rate rate; 1321 struct htt_ppdu_stats_usr_cmpltn_cmn cmpltn_cmn; 1322 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status ack_ba; 1323 }; 1324 1325 #define HTT_PPDU_STATS_MAX_USERS 8 1326 #define HTT_PPDU_DESC_MAX_DEPTH 16 1327 1328 struct htt_ppdu_stats { 1329 struct htt_ppdu_stats_common common; 1330 struct htt_ppdu_user_stats user_stats[HTT_PPDU_STATS_MAX_USERS]; 1331 }; 1332 1333 struct htt_ppdu_stats_info { 1334 u32 ppdu_id; 1335 struct htt_ppdu_stats ppdu_stats; 1336 struct list_head list; 1337 }; 1338 1339 /** 1340 * @brief target -> host packet log message 1341 * 1342 * @details 1343 * The following field definitions describe the format of the packet log 1344 * message sent from the target to the host. 1345 * The message consists of a 4-octet header,followed by a variable number 1346 * of 32-bit character values. 1347 * 1348 * |31 16|15 12|11 10|9 8|7 0| 1349 * |------------------------------------------------------------------| 1350 * | payload_size | rsvd |pdev_id|mac_id| msg type | 1351 * |------------------------------------------------------------------| 1352 * | payload | 1353 * |------------------------------------------------------------------| 1354 * - MSG_TYPE 1355 * Bits 7:0 1356 * Purpose: identifies this as a pktlog message 1357 * Value: HTT_T2H_MSG_TYPE_PKTLOG 1358 * - mac_id 1359 * Bits 9:8 1360 * Purpose: identifies which MAC/PHY instance generated this pktlog info 1361 * Value: 0-3 1362 * - pdev_id 1363 * Bits 11:10 1364 * Purpose: pdev_id 1365 * Value: 0-3 1366 * 0 (for rings at SOC level), 1367 * 1/2/3 PDEV -> 0/1/2 1368 * - payload_size 1369 * Bits 31:16 1370 * Purpose: explicitly specify the payload size 1371 * Value: payload size in bytes (payload size is a multiple of 4 bytes) 1372 */ 1373 struct htt_pktlog_msg { 1374 u32 hdr; 1375 u8 payload[0]; 1376 }; 1377 1378 /** 1379 * @brief host -> target FW extended statistics retrieve 1380 * 1381 * @details 1382 * The following field definitions describe the format of the HTT host 1383 * to target FW extended stats retrieve message. 1384 * The message specifies the type of stats the host wants to retrieve. 1385 * 1386 * |31 24|23 16|15 8|7 0| 1387 * |-----------------------------------------------------------| 1388 * | reserved | stats type | pdev_mask | msg type | 1389 * |-----------------------------------------------------------| 1390 * | config param [0] | 1391 * |-----------------------------------------------------------| 1392 * | config param [1] | 1393 * |-----------------------------------------------------------| 1394 * | config param [2] | 1395 * |-----------------------------------------------------------| 1396 * | config param [3] | 1397 * |-----------------------------------------------------------| 1398 * | reserved | 1399 * |-----------------------------------------------------------| 1400 * | cookie LSBs | 1401 * |-----------------------------------------------------------| 1402 * | cookie MSBs | 1403 * |-----------------------------------------------------------| 1404 * Header fields: 1405 * - MSG_TYPE 1406 * Bits 7:0 1407 * Purpose: identifies this is a extended stats upload request message 1408 * Value: 0x10 1409 * - PDEV_MASK 1410 * Bits 8:15 1411 * Purpose: identifies the mask of PDEVs to retrieve stats from 1412 * Value: This is a overloaded field, refer to usage and interpretation of 1413 * PDEV in interface document. 1414 * Bit 8 : Reserved for SOC stats 1415 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC 1416 * Indicates MACID_MASK in DBS 1417 * - STATS_TYPE 1418 * Bits 23:16 1419 * Purpose: identifies which FW statistics to upload 1420 * Value: Defined by htt_dbg_ext_stats_type (see htt_stats.h) 1421 * - Reserved 1422 * Bits 31:24 1423 * - CONFIG_PARAM [0] 1424 * Bits 31:0 1425 * Purpose: give an opaque configuration value to the specified stats type 1426 * Value: stats-type specific configuration value 1427 * Refer to htt_stats.h for interpretation for each stats sub_type 1428 * - CONFIG_PARAM [1] 1429 * Bits 31:0 1430 * Purpose: give an opaque configuration value to the specified stats type 1431 * Value: stats-type specific configuration value 1432 * Refer to htt_stats.h for interpretation for each stats sub_type 1433 * - CONFIG_PARAM [2] 1434 * Bits 31:0 1435 * Purpose: give an opaque configuration value to the specified stats type 1436 * Value: stats-type specific configuration value 1437 * Refer to htt_stats.h for interpretation for each stats sub_type 1438 * - CONFIG_PARAM [3] 1439 * Bits 31:0 1440 * Purpose: give an opaque configuration value to the specified stats type 1441 * Value: stats-type specific configuration value 1442 * Refer to htt_stats.h for interpretation for each stats sub_type 1443 * - Reserved [31:0] for future use. 1444 * - COOKIE_LSBS 1445 * Bits 31:0 1446 * Purpose: Provide a mechanism to match a target->host stats confirmation 1447 * message with its preceding host->target stats request message. 1448 * Value: LSBs of the opaque cookie specified by the host-side requestor 1449 * - COOKIE_MSBS 1450 * Bits 31:0 1451 * Purpose: Provide a mechanism to match a target->host stats confirmation 1452 * message with its preceding host->target stats request message. 1453 * Value: MSBs of the opaque cookie specified by the host-side requestor 1454 */ 1455 1456 struct htt_ext_stats_cfg_hdr { 1457 u8 msg_type; 1458 u8 pdev_mask; 1459 u8 stats_type; 1460 u8 reserved; 1461 } __packed; 1462 1463 struct htt_ext_stats_cfg_cmd { 1464 struct htt_ext_stats_cfg_hdr hdr; 1465 u32 cfg_param0; 1466 u32 cfg_param1; 1467 u32 cfg_param2; 1468 u32 cfg_param3; 1469 u32 reserved; 1470 u32 cookie_lsb; 1471 u32 cookie_msb; 1472 } __packed; 1473 1474 /* htt stats config default params */ 1475 #define HTT_STAT_DEFAULT_RESET_START_OFFSET 0 1476 #define HTT_STAT_DEFAULT_CFG0_ALL_HWQS 0xffffffff 1477 #define HTT_STAT_DEFAULT_CFG0_ALL_TXQS 0xffffffff 1478 #define HTT_STAT_DEFAULT_CFG0_ALL_CMDQS 0xffff 1479 #define HTT_STAT_DEFAULT_CFG0_ALL_RINGS 0xffff 1480 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_PEERS 0xff 1481 #define HTT_STAT_DEFAULT_CFG0_CCA_CUMULATIVE 0x00 1482 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_VDEVS 0x00 1483 1484 /* HTT_DBG_EXT_STATS_PEER_INFO 1485 * PARAMS: 1486 * @config_param0: 1487 * [Bit0] - [0] for sw_peer_id, [1] for mac_addr based request 1488 * [Bit15 : Bit 1] htt_peer_stats_req_mode_t 1489 * [Bit31 : Bit16] sw_peer_id 1490 * @config_param1: 1491 * peer_stats_req_type_mask:32 (enum htt_peer_stats_tlv_enum) 1492 * 0 bit htt_peer_stats_cmn_tlv 1493 * 1 bit htt_peer_details_tlv 1494 * 2 bit htt_tx_peer_rate_stats_tlv 1495 * 3 bit htt_rx_peer_rate_stats_tlv 1496 * 4 bit htt_tx_tid_stats_tlv/htt_tx_tid_stats_v1_tlv 1497 * 5 bit htt_rx_tid_stats_tlv 1498 * 6 bit htt_msdu_flow_stats_tlv 1499 * @config_param2: [Bit31 : Bit0] mac_addr31to0 1500 * @config_param3: [Bit15 : Bit0] mac_addr47to32 1501 * [Bit31 : Bit16] reserved 1502 */ 1503 #define HTT_STAT_PEER_INFO_MAC_ADDR BIT(0) 1504 #define HTT_STAT_DEFAULT_PEER_REQ_TYPE 0x7f 1505 1506 /* Used to set different configs to the specified stats type.*/ 1507 struct htt_ext_stats_cfg_params { 1508 u32 cfg0; 1509 u32 cfg1; 1510 u32 cfg2; 1511 u32 cfg3; 1512 }; 1513 1514 /** 1515 * @brief target -> host extended statistics upload 1516 * 1517 * @details 1518 * The following field definitions describe the format of the HTT target 1519 * to host stats upload confirmation message. 1520 * The message contains a cookie echoed from the HTT host->target stats 1521 * upload request, which identifies which request the confirmation is 1522 * for, and a single stats can span over multiple HTT stats indication 1523 * due to the HTT message size limitation so every HTT ext stats indication 1524 * will have tag-length-value stats information elements. 1525 * The tag-length header for each HTT stats IND message also includes a 1526 * status field, to indicate whether the request for the stat type in 1527 * question was fully met, partially met, unable to be met, or invalid 1528 * (if the stat type in question is disabled in the target). 1529 * A Done bit 1's indicate the end of the of stats info elements. 1530 * 1531 * 1532 * |31 16|15 12|11|10 8|7 5|4 0| 1533 * |--------------------------------------------------------------| 1534 * | reserved | msg type | 1535 * |--------------------------------------------------------------| 1536 * | cookie LSBs | 1537 * |--------------------------------------------------------------| 1538 * | cookie MSBs | 1539 * |--------------------------------------------------------------| 1540 * | stats entry length | rsvd | D| S | stat type | 1541 * |--------------------------------------------------------------| 1542 * | type-specific stats info | 1543 * | (see htt_stats.h) | 1544 * |--------------------------------------------------------------| 1545 * Header fields: 1546 * - MSG_TYPE 1547 * Bits 7:0 1548 * Purpose: Identifies this is a extended statistics upload confirmation 1549 * message. 1550 * Value: 0x1c 1551 * - COOKIE_LSBS 1552 * Bits 31:0 1553 * Purpose: Provide a mechanism to match a target->host stats confirmation 1554 * message with its preceding host->target stats request message. 1555 * Value: LSBs of the opaque cookie specified by the host-side requestor 1556 * - COOKIE_MSBS 1557 * Bits 31:0 1558 * Purpose: Provide a mechanism to match a target->host stats confirmation 1559 * message with its preceding host->target stats request message. 1560 * Value: MSBs of the opaque cookie specified by the host-side requestor 1561 * 1562 * Stats Information Element tag-length header fields: 1563 * - STAT_TYPE 1564 * Bits 7:0 1565 * Purpose: identifies the type of statistics info held in the 1566 * following information element 1567 * Value: htt_dbg_ext_stats_type 1568 * - STATUS 1569 * Bits 10:8 1570 * Purpose: indicate whether the requested stats are present 1571 * Value: htt_dbg_ext_stats_status 1572 * - DONE 1573 * Bits 11 1574 * Purpose: 1575 * Indicates the completion of the stats entry, this will be the last 1576 * stats conf HTT segment for the requested stats type. 1577 * Value: 1578 * 0 -> the stats retrieval is ongoing 1579 * 1 -> the stats retrieval is complete 1580 * - LENGTH 1581 * Bits 31:16 1582 * Purpose: indicate the stats information size 1583 * Value: This field specifies the number of bytes of stats information 1584 * that follows the element tag-length header. 1585 * It is expected but not required that this length is a multiple of 1586 * 4 bytes. 1587 */ 1588 1589 #define HTT_T2H_EXT_STATS_INFO1_DONE BIT(11) 1590 #define HTT_T2H_EXT_STATS_INFO1_LENGTH GENMASK(31, 16) 1591 1592 struct ath11k_htt_extd_stats_msg { 1593 u32 info0; 1594 u64 cookie; 1595 u32 info1; 1596 u8 data[0]; 1597 } __packed; 1598 1599 #define HTT_MAC_ADDR_L32_0 GENMASK(7, 0) 1600 #define HTT_MAC_ADDR_L32_1 GENMASK(15, 8) 1601 #define HTT_MAC_ADDR_L32_2 GENMASK(23, 16) 1602 #define HTT_MAC_ADDR_L32_3 GENMASK(31, 24) 1603 #define HTT_MAC_ADDR_H16_0 GENMASK(7, 0) 1604 #define HTT_MAC_ADDR_H16_1 GENMASK(15, 8) 1605 1606 struct htt_mac_addr { 1607 u32 mac_addr_l32; 1608 u32 mac_addr_h16; 1609 }; 1610 1611 static inline void ath11k_dp_get_mac_addr(u32 addr_l32, u16 addr_h16, u8 *addr) 1612 { 1613 if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) { 1614 addr_l32 = swab32(addr_l32); 1615 addr_h16 = swab16(addr_h16); 1616 } 1617 1618 memcpy(addr, &addr_l32, 4); 1619 memcpy(addr + 4, &addr_h16, ETH_ALEN - 4); 1620 } 1621 1622 int ath11k_dp_service_srng(struct ath11k_base *ab, 1623 struct ath11k_ext_irq_grp *irq_grp, 1624 int budget); 1625 int ath11k_dp_htt_connect(struct ath11k_dp *dp); 1626 void ath11k_dp_vdev_tx_attach(struct ath11k *ar, struct ath11k_vif *arvif); 1627 void ath11k_dp_free(struct ath11k_base *ab); 1628 int ath11k_dp_alloc(struct ath11k_base *ab); 1629 int ath11k_dp_pdev_alloc(struct ath11k_base *ab); 1630 void ath11k_dp_pdev_pre_alloc(struct ath11k_base *ab); 1631 void ath11k_dp_pdev_free(struct ath11k_base *ab); 1632 int ath11k_dp_tx_htt_srng_setup(struct ath11k_base *ab, u32 ring_id, 1633 int mac_id, enum hal_ring_type ring_type); 1634 int ath11k_dp_peer_setup(struct ath11k *ar, int vdev_id, const u8 *addr); 1635 void ath11k_dp_peer_cleanup(struct ath11k *ar, int vdev_id, const u8 *addr); 1636 void ath11k_dp_srng_cleanup(struct ath11k_base *ab, struct dp_srng *ring); 1637 int ath11k_dp_srng_setup(struct ath11k_base *ab, struct dp_srng *ring, 1638 enum hal_ring_type type, int ring_num, 1639 int mac_id, int num_entries); 1640 void ath11k_dp_link_desc_cleanup(struct ath11k_base *ab, 1641 struct dp_link_desc_bank *desc_bank, 1642 u32 ring_type, struct dp_srng *ring); 1643 int ath11k_dp_link_desc_setup(struct ath11k_base *ab, 1644 struct dp_link_desc_bank *link_desc_banks, 1645 u32 ring_type, struct hal_srng *srng, 1646 u32 n_link_desc); 1647 void ath11k_dp_shadow_start_timer(struct ath11k_base *ab, 1648 struct hal_srng *srng, 1649 struct ath11k_hp_update_timer *update_timer); 1650 void ath11k_dp_shadow_stop_timer(struct ath11k_base *ab, 1651 struct ath11k_hp_update_timer *update_timer); 1652 void ath11k_dp_shadow_init_timer(struct ath11k_base *ab, 1653 struct ath11k_hp_update_timer *update_timer, 1654 u32 interval, u32 ring_id); 1655 void ath11k_dp_stop_shadow_timers(struct ath11k_base *ab); 1656 1657 #endif 1658