1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef DEBUG_HTT_STATS_H 8 #define DEBUG_HTT_STATS_H 9 10 #define HTT_STATS_COOKIE_LSB GENMASK_ULL(31, 0) 11 #define HTT_STATS_COOKIE_MSB GENMASK_ULL(63, 32) 12 #define HTT_STATS_MAGIC_VALUE 0xF0F0F0F0 13 14 enum htt_tlv_tag_t { 15 HTT_STATS_TX_PDEV_CMN_TAG = 0, 16 HTT_STATS_TX_PDEV_UNDERRUN_TAG = 1, 17 HTT_STATS_TX_PDEV_SIFS_TAG = 2, 18 HTT_STATS_TX_PDEV_FLUSH_TAG = 3, 19 HTT_STATS_TX_PDEV_PHY_ERR_TAG = 4, 20 HTT_STATS_STRING_TAG = 5, 21 HTT_STATS_TX_HWQ_CMN_TAG = 6, 22 HTT_STATS_TX_HWQ_DIFS_LATENCY_TAG = 7, 23 HTT_STATS_TX_HWQ_CMD_RESULT_TAG = 8, 24 HTT_STATS_TX_HWQ_CMD_STALL_TAG = 9, 25 HTT_STATS_TX_HWQ_FES_STATUS_TAG = 10, 26 HTT_STATS_TX_TQM_GEN_MPDU_TAG = 11, 27 HTT_STATS_TX_TQM_LIST_MPDU_TAG = 12, 28 HTT_STATS_TX_TQM_LIST_MPDU_CNT_TAG = 13, 29 HTT_STATS_TX_TQM_CMN_TAG = 14, 30 HTT_STATS_TX_TQM_PDEV_TAG = 15, 31 HTT_STATS_TX_TQM_CMDQ_STATUS_TAG = 16, 32 HTT_STATS_TX_DE_EAPOL_PACKETS_TAG = 17, 33 HTT_STATS_TX_DE_CLASSIFY_FAILED_TAG = 18, 34 HTT_STATS_TX_DE_CLASSIFY_STATS_TAG = 19, 35 HTT_STATS_TX_DE_CLASSIFY_STATUS_TAG = 20, 36 HTT_STATS_TX_DE_ENQUEUE_PACKETS_TAG = 21, 37 HTT_STATS_TX_DE_ENQUEUE_DISCARD_TAG = 22, 38 HTT_STATS_TX_DE_CMN_TAG = 23, 39 HTT_STATS_RING_IF_TAG = 24, 40 HTT_STATS_TX_PDEV_MU_MIMO_STATS_TAG = 25, 41 HTT_STATS_SFM_CMN_TAG = 26, 42 HTT_STATS_SRING_STATS_TAG = 27, 43 HTT_STATS_RX_PDEV_FW_STATS_TAG = 28, 44 HTT_STATS_RX_PDEV_FW_RING_MPDU_ERR_TAG = 29, 45 HTT_STATS_RX_PDEV_FW_MPDU_DROP_TAG = 30, 46 HTT_STATS_RX_SOC_FW_STATS_TAG = 31, 47 HTT_STATS_RX_SOC_FW_REFILL_RING_EMPTY_TAG = 32, 48 HTT_STATS_RX_SOC_FW_REFILL_RING_NUM_REFILL_TAG = 33, 49 HTT_STATS_TX_PDEV_RATE_STATS_TAG = 34, 50 HTT_STATS_RX_PDEV_RATE_STATS_TAG = 35, 51 HTT_STATS_TX_PDEV_SCHEDULER_TXQ_STATS_TAG = 36, 52 HTT_STATS_TX_SCHED_CMN_TAG = 37, 53 HTT_STATS_TX_PDEV_MUMIMO_MPDU_STATS_TAG = 38, 54 HTT_STATS_SCHED_TXQ_CMD_POSTED_TAG = 39, 55 HTT_STATS_RING_IF_CMN_TAG = 40, 56 HTT_STATS_SFM_CLIENT_USER_TAG = 41, 57 HTT_STATS_SFM_CLIENT_TAG = 42, 58 HTT_STATS_TX_TQM_ERROR_STATS_TAG = 43, 59 HTT_STATS_SCHED_TXQ_CMD_REAPED_TAG = 44, 60 HTT_STATS_SRING_CMN_TAG = 45, 61 HTT_STATS_TX_SELFGEN_AC_ERR_STATS_TAG = 46, 62 HTT_STATS_TX_SELFGEN_CMN_STATS_TAG = 47, 63 HTT_STATS_TX_SELFGEN_AC_STATS_TAG = 48, 64 HTT_STATS_TX_SELFGEN_AX_STATS_TAG = 49, 65 HTT_STATS_TX_SELFGEN_AX_ERR_STATS_TAG = 50, 66 HTT_STATS_TX_HWQ_MUMIMO_SCH_STATS_TAG = 51, 67 HTT_STATS_TX_HWQ_MUMIMO_MPDU_STATS_TAG = 52, 68 HTT_STATS_TX_HWQ_MUMIMO_CMN_STATS_TAG = 53, 69 HTT_STATS_HW_INTR_MISC_TAG = 54, 70 HTT_STATS_HW_WD_TIMEOUT_TAG = 55, 71 HTT_STATS_HW_PDEV_ERRS_TAG = 56, 72 HTT_STATS_COUNTER_NAME_TAG = 57, 73 HTT_STATS_TX_TID_DETAILS_TAG = 58, 74 HTT_STATS_RX_TID_DETAILS_TAG = 59, 75 HTT_STATS_PEER_STATS_CMN_TAG = 60, 76 HTT_STATS_PEER_DETAILS_TAG = 61, 77 HTT_STATS_PEER_TX_RATE_STATS_TAG = 62, 78 HTT_STATS_PEER_RX_RATE_STATS_TAG = 63, 79 HTT_STATS_PEER_MSDU_FLOWQ_TAG = 64, 80 HTT_STATS_TX_DE_COMPL_STATS_TAG = 65, 81 HTT_STATS_WHAL_TX_TAG = 66, 82 HTT_STATS_TX_PDEV_SIFS_HIST_TAG = 67, 83 HTT_STATS_RX_PDEV_FW_STATS_PHY_ERR_TAG = 68, 84 HTT_STATS_TX_TID_DETAILS_V1_TAG = 69, 85 HTT_STATS_PDEV_CCA_1SEC_HIST_TAG = 70, 86 HTT_STATS_PDEV_CCA_100MSEC_HIST_TAG = 71, 87 HTT_STATS_PDEV_CCA_STAT_CUMULATIVE_TAG = 72, 88 HTT_STATS_PDEV_CCA_COUNTERS_TAG = 73, 89 HTT_STATS_TX_PDEV_MPDU_STATS_TAG = 74, 90 HTT_STATS_PDEV_TWT_SESSIONS_TAG = 75, 91 HTT_STATS_PDEV_TWT_SESSION_TAG = 76, 92 HTT_STATS_RX_REFILL_RXDMA_ERR_TAG = 77, 93 HTT_STATS_RX_REFILL_REO_ERR_TAG = 78, 94 HTT_STATS_RX_REO_RESOURCE_STATS_TAG = 79, 95 HTT_STATS_TX_SOUNDING_STATS_TAG = 80, 96 HTT_STATS_TX_PDEV_TX_PPDU_STATS_TAG = 81, 97 HTT_STATS_TX_PDEV_TRIED_MPDU_CNT_HIST_TAG = 82, 98 HTT_STATS_TX_HWQ_TRIED_MPDU_CNT_HIST_TAG = 83, 99 HTT_STATS_TX_HWQ_TXOP_USED_CNT_HIST_TAG = 84, 100 HTT_STATS_TX_DE_FW2WBM_RING_FULL_HIST_TAG = 85, 101 HTT_STATS_SCHED_TXQ_SCHED_ORDER_SU_TAG = 86, 102 HTT_STATS_SCHED_TXQ_SCHED_INELIGIBILITY_TAG = 87, 103 HTT_STATS_PDEV_OBSS_PD_TAG = 88, 104 HTT_STATS_HW_WAR_TAG = 89, 105 HTT_STATS_RING_BACKPRESSURE_STATS_TAG = 90, 106 HTT_STATS_PEER_CTRL_PATH_TXRX_STATS_TAG = 101, 107 HTT_STATS_PDEV_TX_RATE_TXBF_STATS_TAG = 108, 108 HTT_STATS_TXBF_OFDMA_NDPA_STATS_TAG = 113, 109 HTT_STATS_TXBF_OFDMA_NDP_STATS_TAG = 114, 110 HTT_STATS_TXBF_OFDMA_BRP_STATS_TAG = 115, 111 HTT_STATS_TXBF_OFDMA_STEER_STATS_TAG = 116, 112 HTT_STATS_PHY_COUNTERS_TAG = 121, 113 HTT_STATS_PHY_STATS_TAG = 122, 114 HTT_STATS_PHY_RESET_COUNTERS_TAG = 123, 115 HTT_STATS_PHY_RESET_STATS_TAG = 124, 116 117 HTT_STATS_MAX_TAG, 118 }; 119 120 #define HTT_STATS_MAX_STRING_SZ32 4 121 #define HTT_STATS_MACID_INVALID 0xff 122 #define HTT_TX_HWQ_MAX_DIFS_LATENCY_BINS 10 123 #define HTT_TX_HWQ_MAX_CMD_RESULT_STATS 13 124 #define HTT_TX_HWQ_MAX_CMD_STALL_STATS 5 125 #define HTT_TX_HWQ_MAX_FES_RESULT_STATS 10 126 127 enum htt_tx_pdev_underrun_enum { 128 HTT_STATS_TX_PDEV_NO_DATA_UNDERRUN = 0, 129 HTT_STATS_TX_PDEV_DATA_UNDERRUN_BETWEEN_MPDU = 1, 130 HTT_STATS_TX_PDEV_DATA_UNDERRUN_WITHIN_MPDU = 2, 131 HTT_TX_PDEV_MAX_URRN_STATS = 3, 132 }; 133 134 #define HTT_TX_PDEV_MAX_FLUSH_REASON_STATS 71 135 #define HTT_TX_PDEV_MAX_SIFS_BURST_STATS 9 136 #define HTT_TX_PDEV_MAX_SIFS_BURST_HIST_STATS 10 137 #define HTT_TX_PDEV_MAX_PHY_ERR_STATS 18 138 #define HTT_TX_PDEV_SCHED_TX_MODE_MAX 4 139 #define HTT_TX_PDEV_NUM_SCHED_ORDER_LOG 20 140 141 #define HTT_RX_STATS_REFILL_MAX_RING 4 142 #define HTT_RX_STATS_RXDMA_MAX_ERR 16 143 #define HTT_RX_STATS_FW_DROP_REASON_MAX 16 144 145 /* Bytes stored in little endian order */ 146 /* Length should be multiple of DWORD */ 147 struct htt_stats_string_tlv { 148 /* Can be variable length */ 149 DECLARE_FLEX_ARRAY(u32, data); 150 } __packed; 151 152 #define HTT_STATS_MAC_ID GENMASK(7, 0) 153 154 /* == TX PDEV STATS == */ 155 struct htt_tx_pdev_stats_cmn_tlv { 156 u32 mac_id__word; 157 u32 hw_queued; 158 u32 hw_reaped; 159 u32 underrun; 160 u32 hw_paused; 161 u32 hw_flush; 162 u32 hw_filt; 163 u32 tx_abort; 164 u32 mpdu_requeued; 165 u32 tx_xretry; 166 u32 data_rc; 167 u32 mpdu_dropped_xretry; 168 u32 illgl_rate_phy_err; 169 u32 cont_xretry; 170 u32 tx_timeout; 171 u32 pdev_resets; 172 u32 phy_underrun; 173 u32 txop_ovf; 174 u32 seq_posted; 175 u32 seq_failed_queueing; 176 u32 seq_completed; 177 u32 seq_restarted; 178 u32 mu_seq_posted; 179 u32 seq_switch_hw_paused; 180 u32 next_seq_posted_dsr; 181 u32 seq_posted_isr; 182 u32 seq_ctrl_cached; 183 u32 mpdu_count_tqm; 184 u32 msdu_count_tqm; 185 u32 mpdu_removed_tqm; 186 u32 msdu_removed_tqm; 187 u32 mpdus_sw_flush; 188 u32 mpdus_hw_filter; 189 u32 mpdus_truncated; 190 u32 mpdus_ack_failed; 191 u32 mpdus_expired; 192 u32 mpdus_seq_hw_retry; 193 u32 ack_tlv_proc; 194 u32 coex_abort_mpdu_cnt_valid; 195 u32 coex_abort_mpdu_cnt; 196 u32 num_total_ppdus_tried_ota; 197 u32 num_data_ppdus_tried_ota; 198 u32 local_ctrl_mgmt_enqued; 199 u32 local_ctrl_mgmt_freed; 200 u32 local_data_enqued; 201 u32 local_data_freed; 202 u32 mpdu_tried; 203 u32 isr_wait_seq_posted; 204 205 u32 tx_active_dur_us_low; 206 u32 tx_active_dur_us_high; 207 }; 208 209 /* NOTE: Variable length TLV, use length spec to infer array size */ 210 struct htt_tx_pdev_stats_urrn_tlv_v { 211 /* HTT_TX_PDEV_MAX_URRN_STATS */ 212 DECLARE_FLEX_ARRAY(u32, urrn_stats); 213 }; 214 215 /* NOTE: Variable length TLV, use length spec to infer array size */ 216 struct htt_tx_pdev_stats_flush_tlv_v { 217 /* HTT_TX_PDEV_MAX_FLUSH_REASON_STATS */ 218 DECLARE_FLEX_ARRAY(u32, flush_errs); 219 }; 220 221 /* NOTE: Variable length TLV, use length spec to infer array size */ 222 struct htt_tx_pdev_stats_sifs_tlv_v { 223 /* HTT_TX_PDEV_MAX_SIFS_BURST_STATS */ 224 DECLARE_FLEX_ARRAY(u32, sifs_status); 225 }; 226 227 /* NOTE: Variable length TLV, use length spec to infer array size */ 228 struct htt_tx_pdev_stats_phy_err_tlv_v { 229 /* HTT_TX_PDEV_MAX_PHY_ERR_STATS */ 230 DECLARE_FLEX_ARRAY(u32, phy_errs); 231 }; 232 233 /* NOTE: Variable length TLV, use length spec to infer array size */ 234 struct htt_tx_pdev_stats_sifs_hist_tlv_v { 235 /* HTT_TX_PDEV_SIFS_BURST_HIST_STATS */ 236 DECLARE_FLEX_ARRAY(u32, sifs_hist_status); 237 }; 238 239 struct htt_tx_pdev_stats_tx_ppdu_stats_tlv_v { 240 u32 num_data_ppdus_legacy_su; 241 u32 num_data_ppdus_ac_su; 242 u32 num_data_ppdus_ax_su; 243 u32 num_data_ppdus_ac_su_txbf; 244 u32 num_data_ppdus_ax_su_txbf; 245 }; 246 247 /* NOTE: Variable length TLV, use length spec to infer array size . 248 * 249 * Tried_mpdu_cnt_hist is the histogram of MPDUs tries per HWQ. 250 * The tries here is the count of the MPDUS within a PPDU that the 251 * HW had attempted to transmit on air, for the HWSCH Schedule 252 * command submitted by FW.It is not the retry attempts. 253 * The histogram bins are 0-29, 30-59, 60-89 and so on. The are 254 * 10 bins in this histogram. They are defined in FW using the 255 * following macros 256 * #define WAL_MAX_TRIED_MPDU_CNT_HISTOGRAM 9 257 * #define WAL_TRIED_MPDU_CNT_HISTOGRAM_INTERVAL 30 258 */ 259 struct htt_tx_pdev_stats_tried_mpdu_cnt_hist_tlv_v { 260 u32 hist_bin_size; 261 u32 tried_mpdu_cnt_hist[]; /* HTT_TX_PDEV_TRIED_MPDU_CNT_HIST */ 262 }; 263 264 /* == SOC ERROR STATS == */ 265 266 /* =============== PDEV ERROR STATS ============== */ 267 #define HTT_STATS_MAX_HW_INTR_NAME_LEN 8 268 struct htt_hw_stats_intr_misc_tlv { 269 /* Stored as little endian */ 270 u8 hw_intr_name[HTT_STATS_MAX_HW_INTR_NAME_LEN]; 271 u32 mask; 272 u32 count; 273 }; 274 275 #define HTT_STATS_MAX_HW_MODULE_NAME_LEN 8 276 struct htt_hw_stats_wd_timeout_tlv { 277 /* Stored as little endian */ 278 u8 hw_module_name[HTT_STATS_MAX_HW_MODULE_NAME_LEN]; 279 u32 count; 280 }; 281 282 struct htt_hw_stats_pdev_errs_tlv { 283 u32 mac_id__word; /* BIT [ 7 : 0] : mac_id */ 284 u32 tx_abort; 285 u32 tx_abort_fail_count; 286 u32 rx_abort; 287 u32 rx_abort_fail_count; 288 u32 warm_reset; 289 u32 cold_reset; 290 u32 tx_flush; 291 u32 tx_glb_reset; 292 u32 tx_txq_reset; 293 u32 rx_timeout_reset; 294 }; 295 296 struct htt_hw_stats_whal_tx_tlv { 297 u32 mac_id__word; 298 u32 last_unpause_ppdu_id; 299 u32 hwsch_unpause_wait_tqm_write; 300 u32 hwsch_dummy_tlv_skipped; 301 u32 hwsch_misaligned_offset_received; 302 u32 hwsch_reset_count; 303 u32 hwsch_dev_reset_war; 304 u32 hwsch_delayed_pause; 305 u32 hwsch_long_delayed_pause; 306 u32 sch_rx_ppdu_no_response; 307 u32 sch_selfgen_response; 308 u32 sch_rx_sifs_resp_trigger; 309 }; 310 311 /* ============ PEER STATS ============ */ 312 #define HTT_MSDU_FLOW_STATS_TX_FLOW_NO GENMASK(15, 0) 313 #define HTT_MSDU_FLOW_STATS_TID_NUM GENMASK(19, 16) 314 #define HTT_MSDU_FLOW_STATS_DROP_RULE BIT(20) 315 316 struct htt_msdu_flow_stats_tlv { 317 u32 last_update_timestamp; 318 u32 last_add_timestamp; 319 u32 last_remove_timestamp; 320 u32 total_processed_msdu_count; 321 u32 cur_msdu_count_in_flowq; 322 u32 sw_peer_id; 323 u32 tx_flow_no__tid_num__drop_rule; 324 u32 last_cycle_enqueue_count; 325 u32 last_cycle_dequeue_count; 326 u32 last_cycle_drop_count; 327 u32 current_drop_th; 328 }; 329 330 #define MAX_HTT_TID_NAME 8 331 332 #define HTT_TX_TID_STATS_SW_PEER_ID GENMASK(15, 0) 333 #define HTT_TX_TID_STATS_TID_NUM GENMASK(31, 16) 334 #define HTT_TX_TID_STATS_NUM_SCHED_PENDING GENMASK(7, 0) 335 #define HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ GENMASK(15, 8) 336 337 /* Tidq stats */ 338 struct htt_tx_tid_stats_tlv { 339 /* Stored as little endian */ 340 u8 tid_name[MAX_HTT_TID_NAME]; 341 u32 sw_peer_id__tid_num; 342 u32 num_sched_pending__num_ppdu_in_hwq; 343 u32 tid_flags; 344 u32 hw_queued; 345 u32 hw_reaped; 346 u32 mpdus_hw_filter; 347 348 u32 qdepth_bytes; 349 u32 qdepth_num_msdu; 350 u32 qdepth_num_mpdu; 351 u32 last_scheduled_tsmp; 352 u32 pause_module_id; 353 u32 block_module_id; 354 u32 tid_tx_airtime; 355 }; 356 357 #define HTT_TX_TID_STATS_V1_SW_PEER_ID GENMASK(15, 0) 358 #define HTT_TX_TID_STATS_V1_TID_NUM GENMASK(31, 16) 359 #define HTT_TX_TID_STATS_V1_NUM_SCHED_PENDING GENMASK(7, 0) 360 #define HTT_TX_TID_STATS_V1_NUM_PPDU_IN_HWQ GENMASK(15, 8) 361 362 /* Tidq stats */ 363 struct htt_tx_tid_stats_v1_tlv { 364 /* Stored as little endian */ 365 u8 tid_name[MAX_HTT_TID_NAME]; 366 u32 sw_peer_id__tid_num; 367 u32 num_sched_pending__num_ppdu_in_hwq; 368 u32 tid_flags; 369 u32 max_qdepth_bytes; 370 u32 max_qdepth_n_msdus; 371 u32 rsvd; 372 373 u32 qdepth_bytes; 374 u32 qdepth_num_msdu; 375 u32 qdepth_num_mpdu; 376 u32 last_scheduled_tsmp; 377 u32 pause_module_id; 378 u32 block_module_id; 379 u32 tid_tx_airtime; 380 u32 allow_n_flags; 381 u32 sendn_frms_allowed; 382 }; 383 384 #define HTT_RX_TID_STATS_SW_PEER_ID GENMASK(15, 0) 385 #define HTT_RX_TID_STATS_TID_NUM GENMASK(31, 16) 386 387 struct htt_rx_tid_stats_tlv { 388 u32 sw_peer_id__tid_num; 389 u8 tid_name[MAX_HTT_TID_NAME]; 390 u32 dup_in_reorder; 391 u32 dup_past_outside_window; 392 u32 dup_past_within_window; 393 u32 rxdesc_err_decrypt; 394 u32 tid_rx_airtime; 395 }; 396 397 #define HTT_MAX_COUNTER_NAME 8 398 struct htt_counter_tlv { 399 u8 counter_name[HTT_MAX_COUNTER_NAME]; 400 u32 count; 401 }; 402 403 struct htt_peer_stats_cmn_tlv { 404 u32 ppdu_cnt; 405 u32 mpdu_cnt; 406 u32 msdu_cnt; 407 u32 pause_bitmap; 408 u32 block_bitmap; 409 u32 current_timestamp; 410 u32 peer_tx_airtime; 411 u32 peer_rx_airtime; 412 s32 rssi; 413 u32 peer_enqueued_count_low; 414 u32 peer_enqueued_count_high; 415 u32 peer_dequeued_count_low; 416 u32 peer_dequeued_count_high; 417 u32 peer_dropped_count_low; 418 u32 peer_dropped_count_high; 419 u32 ppdu_transmitted_bytes_low; 420 u32 ppdu_transmitted_bytes_high; 421 u32 peer_ttl_removed_count; 422 u32 inactive_time; 423 }; 424 425 #define HTT_PEER_DETAILS_VDEV_ID GENMASK(7, 0) 426 #define HTT_PEER_DETAILS_PDEV_ID GENMASK(15, 8) 427 #define HTT_PEER_DETAILS_AST_IDX GENMASK(31, 16) 428 429 struct htt_peer_details_tlv { 430 u32 peer_type; 431 u32 sw_peer_id; 432 u32 vdev_pdev_ast_idx; 433 struct htt_mac_addr mac_addr; 434 u32 peer_flags; 435 u32 qpeer_flags; 436 }; 437 438 enum htt_stats_param_type { 439 HTT_STATS_PREAM_OFDM, 440 HTT_STATS_PREAM_CCK, 441 HTT_STATS_PREAM_HT, 442 HTT_STATS_PREAM_VHT, 443 HTT_STATS_PREAM_HE, 444 HTT_STATS_PREAM_RSVD, 445 HTT_STATS_PREAM_RSVD1, 446 447 HTT_STATS_PREAM_COUNT, 448 }; 449 450 #define HTT_TX_PEER_STATS_NUM_MCS_COUNTERS 12 451 #define HTT_TX_PEER_STATS_NUM_GI_COUNTERS 4 452 #define HTT_TX_PEER_STATS_NUM_DCM_COUNTERS 5 453 #define HTT_TX_PEER_STATS_NUM_BW_COUNTERS 4 454 #define HTT_TX_PEER_STATS_NUM_SPATIAL_STREAMS 8 455 #define HTT_TX_PEER_STATS_NUM_PREAMBLE_TYPES HTT_STATS_PREAM_COUNT 456 457 struct htt_tx_peer_rate_stats_tlv { 458 u32 tx_ldpc; 459 u32 rts_cnt; 460 u32 ack_rssi; 461 462 u32 tx_mcs[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS]; 463 u32 tx_su_mcs[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS]; 464 u32 tx_mu_mcs[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS]; 465 /* element 0,1, ...7 -> NSS 1,2, ...8 */ 466 u32 tx_nss[HTT_TX_PEER_STATS_NUM_SPATIAL_STREAMS]; 467 /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */ 468 u32 tx_bw[HTT_TX_PEER_STATS_NUM_BW_COUNTERS]; 469 u32 tx_stbc[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS]; 470 u32 tx_pream[HTT_TX_PEER_STATS_NUM_PREAMBLE_TYPES]; 471 472 /* Counters to track number of tx packets in each GI 473 * (400us, 800us, 1600us & 3200us) in each mcs (0-11) 474 */ 475 u32 tx_gi[HTT_TX_PEER_STATS_NUM_GI_COUNTERS][HTT_TX_PEER_STATS_NUM_MCS_COUNTERS]; 476 477 /* Counters to track packets in dcm mcs (MCS 0, 1, 3, 4) */ 478 u32 tx_dcm[HTT_TX_PEER_STATS_NUM_DCM_COUNTERS]; 479 480 }; 481 482 #define HTT_RX_PEER_STATS_NUM_MCS_COUNTERS 12 483 #define HTT_RX_PEER_STATS_NUM_GI_COUNTERS 4 484 #define HTT_RX_PEER_STATS_NUM_DCM_COUNTERS 5 485 #define HTT_RX_PEER_STATS_NUM_BW_COUNTERS 4 486 #define HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS 8 487 #define HTT_RX_PEER_STATS_NUM_PREAMBLE_TYPES HTT_STATS_PREAM_COUNT 488 489 struct htt_rx_peer_rate_stats_tlv { 490 u32 nsts; 491 492 /* Number of rx ldpc packets */ 493 u32 rx_ldpc; 494 /* Number of rx rts packets */ 495 u32 rts_cnt; 496 497 u32 rssi_mgmt; /* units = dB above noise floor */ 498 u32 rssi_data; /* units = dB above noise floor */ 499 u32 rssi_comb; /* units = dB above noise floor */ 500 u32 rx_mcs[HTT_RX_PEER_STATS_NUM_MCS_COUNTERS]; 501 /* element 0,1, ...7 -> NSS 1,2, ...8 */ 502 u32 rx_nss[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS]; 503 u32 rx_dcm[HTT_RX_PEER_STATS_NUM_DCM_COUNTERS]; 504 u32 rx_stbc[HTT_RX_PEER_STATS_NUM_MCS_COUNTERS]; 505 /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */ 506 u32 rx_bw[HTT_RX_PEER_STATS_NUM_BW_COUNTERS]; 507 u32 rx_pream[HTT_RX_PEER_STATS_NUM_PREAMBLE_TYPES]; 508 /* units = dB above noise floor */ 509 u8 rssi_chain[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS] 510 [HTT_RX_PEER_STATS_NUM_BW_COUNTERS]; 511 512 /* Counters to track number of rx packets in each GI in each mcs (0-11) */ 513 u32 rx_gi[HTT_RX_PEER_STATS_NUM_GI_COUNTERS] 514 [HTT_RX_PEER_STATS_NUM_MCS_COUNTERS]; 515 }; 516 517 enum htt_peer_stats_req_mode { 518 HTT_PEER_STATS_REQ_MODE_NO_QUERY, 519 HTT_PEER_STATS_REQ_MODE_QUERY_TQM, 520 HTT_PEER_STATS_REQ_MODE_FLUSH_TQM, 521 }; 522 523 enum htt_peer_stats_tlv_enum { 524 HTT_PEER_STATS_CMN_TLV = 0, 525 HTT_PEER_DETAILS_TLV = 1, 526 HTT_TX_PEER_RATE_STATS_TLV = 2, 527 HTT_RX_PEER_RATE_STATS_TLV = 3, 528 HTT_TX_TID_STATS_TLV = 4, 529 HTT_RX_TID_STATS_TLV = 5, 530 HTT_MSDU_FLOW_STATS_TLV = 6, 531 532 HTT_PEER_STATS_MAX_TLV = 31, 533 }; 534 535 /* =========== MUMIMO HWQ stats =========== */ 536 /* MU MIMO stats per hwQ */ 537 struct htt_tx_hwq_mu_mimo_sch_stats_tlv { 538 u32 mu_mimo_sch_posted; 539 u32 mu_mimo_sch_failed; 540 u32 mu_mimo_ppdu_posted; 541 }; 542 543 struct htt_tx_hwq_mu_mimo_mpdu_stats_tlv { 544 u32 mu_mimo_mpdus_queued_usr; 545 u32 mu_mimo_mpdus_tried_usr; 546 u32 mu_mimo_mpdus_failed_usr; 547 u32 mu_mimo_mpdus_requeued_usr; 548 u32 mu_mimo_err_no_ba_usr; 549 u32 mu_mimo_mpdu_underrun_usr; 550 u32 mu_mimo_ampdu_underrun_usr; 551 }; 552 553 #define HTT_TX_HWQ_STATS_MAC_ID GENMASK(7, 0) 554 #define HTT_TX_HWQ_STATS_HWQ_ID GENMASK(15, 8) 555 556 struct htt_tx_hwq_mu_mimo_cmn_stats_tlv { 557 u32 mac_id__hwq_id__word; 558 }; 559 560 /* == TX HWQ STATS == */ 561 struct htt_tx_hwq_stats_cmn_tlv { 562 u32 mac_id__hwq_id__word; 563 564 /* PPDU level stats */ 565 u32 xretry; 566 u32 underrun_cnt; 567 u32 flush_cnt; 568 u32 filt_cnt; 569 u32 null_mpdu_bmap; 570 u32 user_ack_failure; 571 u32 ack_tlv_proc; 572 u32 sched_id_proc; 573 u32 null_mpdu_tx_count; 574 u32 mpdu_bmap_not_recvd; 575 576 /* Selfgen stats per hwQ */ 577 u32 num_bar; 578 u32 rts; 579 u32 cts2self; 580 u32 qos_null; 581 582 /* MPDU level stats */ 583 u32 mpdu_tried_cnt; 584 u32 mpdu_queued_cnt; 585 u32 mpdu_ack_fail_cnt; 586 u32 mpdu_filt_cnt; 587 u32 false_mpdu_ack_count; 588 589 u32 txq_timeout; 590 }; 591 592 /* NOTE: Variable length TLV, use length spec to infer array size */ 593 struct htt_tx_hwq_difs_latency_stats_tlv_v { 594 u32 hist_intvl; 595 /* histogram of ppdu post to hwsch - > cmd status received */ 596 u32 difs_latency_hist[]; /* HTT_TX_HWQ_MAX_DIFS_LATENCY_BINS */ 597 }; 598 599 /* NOTE: Variable length TLV, use length spec to infer array size */ 600 struct htt_tx_hwq_cmd_result_stats_tlv_v { 601 /* Histogram of sched cmd result, HTT_TX_HWQ_MAX_CMD_RESULT_STATS */ 602 DECLARE_FLEX_ARRAY(u32, cmd_result); 603 }; 604 605 /* NOTE: Variable length TLV, use length spec to infer array size */ 606 struct htt_tx_hwq_cmd_stall_stats_tlv_v { 607 /* Histogram of various pause conitions, HTT_TX_HWQ_MAX_CMD_STALL_STATS */ 608 DECLARE_FLEX_ARRAY(u32, cmd_stall_status); 609 }; 610 611 /* NOTE: Variable length TLV, use length spec to infer array size */ 612 struct htt_tx_hwq_fes_result_stats_tlv_v { 613 /* Histogram of number of user fes result, HTT_TX_HWQ_MAX_FES_RESULT_STATS */ 614 DECLARE_FLEX_ARRAY(u32, fes_result); 615 }; 616 617 /* NOTE: Variable length TLV, use length spec to infer array size 618 * 619 * The hwq_tried_mpdu_cnt_hist is a histogram of MPDUs tries per HWQ. 620 * The tries here is the count of the MPDUS within a PPDU that the HW 621 * had attempted to transmit on air, for the HWSCH Schedule command 622 * submitted by FW in this HWQ .It is not the retry attempts. The 623 * histogram bins are 0-29, 30-59, 60-89 and so on. The are 10 bins 624 * in this histogram. 625 * they are defined in FW using the following macros 626 * #define WAL_MAX_TRIED_MPDU_CNT_HISTOGRAM 9 627 * #define WAL_TRIED_MPDU_CNT_HISTOGRAM_INTERVAL 30 628 */ 629 struct htt_tx_hwq_tried_mpdu_cnt_hist_tlv_v { 630 u32 hist_bin_size; 631 /* Histogram of number of mpdus on tried mpdu */ 632 u32 tried_mpdu_cnt_hist[]; /* HTT_TX_HWQ_TRIED_MPDU_CNT_HIST */ 633 }; 634 635 /* NOTE: Variable length TLV, use length spec to infer array size 636 * 637 * The txop_used_cnt_hist is the histogram of txop per burst. After 638 * completing the burst, we identify the txop used in the burst and 639 * incr the corresponding bin. 640 * Each bin represents 1ms & we have 10 bins in this histogram. 641 * they are defined in FW using the following macros 642 * #define WAL_MAX_TXOP_USED_CNT_HISTOGRAM 10 643 * #define WAL_TXOP_USED_HISTOGRAM_INTERVAL 1000 ( 1 ms ) 644 */ 645 struct htt_tx_hwq_txop_used_cnt_hist_tlv_v { 646 /* Histogram of txop used cnt, HTT_TX_HWQ_TXOP_USED_CNT_HIST */ 647 DECLARE_FLEX_ARRAY(u32, txop_used_cnt_hist); 648 }; 649 650 /* == TX SELFGEN STATS == */ 651 struct htt_tx_selfgen_cmn_stats_tlv { 652 u32 mac_id__word; 653 u32 su_bar; 654 u32 rts; 655 u32 cts2self; 656 u32 qos_null; 657 u32 delayed_bar_1; /* MU user 1 */ 658 u32 delayed_bar_2; /* MU user 2 */ 659 u32 delayed_bar_3; /* MU user 3 */ 660 u32 delayed_bar_4; /* MU user 4 */ 661 u32 delayed_bar_5; /* MU user 5 */ 662 u32 delayed_bar_6; /* MU user 6 */ 663 u32 delayed_bar_7; /* MU user 7 */ 664 }; 665 666 struct htt_tx_selfgen_ac_stats_tlv { 667 /* 11AC */ 668 u32 ac_su_ndpa; 669 u32 ac_su_ndp; 670 u32 ac_mu_mimo_ndpa; 671 u32 ac_mu_mimo_ndp; 672 u32 ac_mu_mimo_brpoll_1; /* MU user 1 */ 673 u32 ac_mu_mimo_brpoll_2; /* MU user 2 */ 674 u32 ac_mu_mimo_brpoll_3; /* MU user 3 */ 675 }; 676 677 struct htt_tx_selfgen_ax_stats_tlv { 678 /* 11AX */ 679 u32 ax_su_ndpa; 680 u32 ax_su_ndp; 681 u32 ax_mu_mimo_ndpa; 682 u32 ax_mu_mimo_ndp; 683 u32 ax_mu_mimo_brpoll_1; /* MU user 1 */ 684 u32 ax_mu_mimo_brpoll_2; /* MU user 2 */ 685 u32 ax_mu_mimo_brpoll_3; /* MU user 3 */ 686 u32 ax_mu_mimo_brpoll_4; /* MU user 4 */ 687 u32 ax_mu_mimo_brpoll_5; /* MU user 5 */ 688 u32 ax_mu_mimo_brpoll_6; /* MU user 6 */ 689 u32 ax_mu_mimo_brpoll_7; /* MU user 7 */ 690 u32 ax_basic_trigger; 691 u32 ax_bsr_trigger; 692 u32 ax_mu_bar_trigger; 693 u32 ax_mu_rts_trigger; 694 u32 ax_ulmumimo_trigger; 695 }; 696 697 struct htt_tx_selfgen_ac_err_stats_tlv { 698 /* 11AC error stats */ 699 u32 ac_su_ndp_err; 700 u32 ac_su_ndpa_err; 701 u32 ac_mu_mimo_ndpa_err; 702 u32 ac_mu_mimo_ndp_err; 703 u32 ac_mu_mimo_brp1_err; 704 u32 ac_mu_mimo_brp2_err; 705 u32 ac_mu_mimo_brp3_err; 706 }; 707 708 struct htt_tx_selfgen_ax_err_stats_tlv { 709 /* 11AX error stats */ 710 u32 ax_su_ndp_err; 711 u32 ax_su_ndpa_err; 712 u32 ax_mu_mimo_ndpa_err; 713 u32 ax_mu_mimo_ndp_err; 714 u32 ax_mu_mimo_brp1_err; 715 u32 ax_mu_mimo_brp2_err; 716 u32 ax_mu_mimo_brp3_err; 717 u32 ax_mu_mimo_brp4_err; 718 u32 ax_mu_mimo_brp5_err; 719 u32 ax_mu_mimo_brp6_err; 720 u32 ax_mu_mimo_brp7_err; 721 u32 ax_basic_trigger_err; 722 u32 ax_bsr_trigger_err; 723 u32 ax_mu_bar_trigger_err; 724 u32 ax_mu_rts_trigger_err; 725 u32 ax_ulmumimo_trigger_err; 726 }; 727 728 /* == TX MU STATS == */ 729 #define HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS 4 730 #define HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS 8 731 #define HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS 74 732 #define HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS 8 733 734 struct htt_tx_pdev_mu_mimo_sch_stats_tlv { 735 /* mu-mimo sw sched cmd stats */ 736 u32 mu_mimo_sch_posted; 737 u32 mu_mimo_sch_failed; 738 /* MU PPDU stats per hwQ */ 739 u32 mu_mimo_ppdu_posted; 740 /* 741 * Counts the number of users in each transmission of 742 * the given TX mode. 743 * 744 * Index is the number of users - 1. 745 */ 746 u32 ac_mu_mimo_sch_nusers[HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS]; 747 u32 ax_mu_mimo_sch_nusers[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS]; 748 u32 ax_ofdma_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 749 u32 ax_ul_ofdma_basic_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 750 u32 ax_ul_ofdma_bsr_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 751 u32 ax_ul_ofdma_bar_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 752 u32 ax_ul_ofdma_brp_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 753 754 /* UL MU-MIMO */ 755 /* ax_ul_mumimo_basic_sch_nusers[i] is the number of basic triggers sent 756 * for (i+1) users 757 */ 758 u32 ax_ul_mumimo_basic_sch_nusers[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS]; 759 760 /* ax_ul_mumimo_brp_sch_nusers[i] is the number of brp triggers sent 761 * for (i+1) users 762 */ 763 u32 ax_ul_mumimo_brp_sch_nusers[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS]; 764 765 u32 ac_mu_mimo_sch_posted_per_grp_sz[HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS]; 766 u32 ax_mu_mimo_sch_posted_per_grp_sz[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS]; 767 }; 768 769 struct htt_tx_pdev_mu_mimo_mpdu_stats_tlv { 770 u32 mu_mimo_mpdus_queued_usr; 771 u32 mu_mimo_mpdus_tried_usr; 772 u32 mu_mimo_mpdus_failed_usr; 773 u32 mu_mimo_mpdus_requeued_usr; 774 u32 mu_mimo_err_no_ba_usr; 775 u32 mu_mimo_mpdu_underrun_usr; 776 u32 mu_mimo_ampdu_underrun_usr; 777 778 u32 ax_mu_mimo_mpdus_queued_usr; 779 u32 ax_mu_mimo_mpdus_tried_usr; 780 u32 ax_mu_mimo_mpdus_failed_usr; 781 u32 ax_mu_mimo_mpdus_requeued_usr; 782 u32 ax_mu_mimo_err_no_ba_usr; 783 u32 ax_mu_mimo_mpdu_underrun_usr; 784 u32 ax_mu_mimo_ampdu_underrun_usr; 785 786 u32 ax_ofdma_mpdus_queued_usr; 787 u32 ax_ofdma_mpdus_tried_usr; 788 u32 ax_ofdma_mpdus_failed_usr; 789 u32 ax_ofdma_mpdus_requeued_usr; 790 u32 ax_ofdma_err_no_ba_usr; 791 u32 ax_ofdma_mpdu_underrun_usr; 792 u32 ax_ofdma_ampdu_underrun_usr; 793 }; 794 795 #define HTT_STATS_TX_SCHED_MODE_MU_MIMO_AC 1 796 #define HTT_STATS_TX_SCHED_MODE_MU_MIMO_AX 2 797 #define HTT_STATS_TX_SCHED_MODE_MU_OFDMA_AX 3 798 799 struct htt_tx_pdev_mpdu_stats_tlv { 800 /* mpdu level stats */ 801 u32 mpdus_queued_usr; 802 u32 mpdus_tried_usr; 803 u32 mpdus_failed_usr; 804 u32 mpdus_requeued_usr; 805 u32 err_no_ba_usr; 806 u32 mpdu_underrun_usr; 807 u32 ampdu_underrun_usr; 808 u32 user_index; 809 u32 tx_sched_mode; /* HTT_STATS_TX_SCHED_MODE_xxx */ 810 }; 811 812 /* == TX SCHED STATS == */ 813 /* NOTE: Variable length TLV, use length spec to infer array size */ 814 struct htt_sched_txq_cmd_posted_tlv_v { 815 /* HTT_TX_PDEV_SCHED_TX_MODE_MAX */ 816 DECLARE_FLEX_ARRAY(u32, sched_cmd_posted); 817 }; 818 819 /* NOTE: Variable length TLV, use length spec to infer array size */ 820 struct htt_sched_txq_cmd_reaped_tlv_v { 821 /* HTT_TX_PDEV_SCHED_TX_MODE_MAX */ 822 DECLARE_FLEX_ARRAY(u32, sched_cmd_reaped); 823 }; 824 825 /* NOTE: Variable length TLV, use length spec to infer array size */ 826 struct htt_sched_txq_sched_order_su_tlv_v { 827 /* HTT_TX_PDEV_NUM_SCHED_ORDER_LOG */ 828 DECLARE_FLEX_ARRAY(u32, sched_order_su); 829 }; 830 831 enum htt_sched_txq_sched_ineligibility_tlv_enum { 832 HTT_SCHED_TID_SKIP_SCHED_MASK_DISABLED = 0, 833 HTT_SCHED_TID_SKIP_NOTIFY_MPDU, 834 HTT_SCHED_TID_SKIP_MPDU_STATE_INVALID, 835 HTT_SCHED_TID_SKIP_SCHED_DISABLED, 836 HTT_SCHED_TID_SKIP_TQM_BYPASS_CMD_PENDING, 837 HTT_SCHED_TID_SKIP_SECOND_SU_SCHEDULE, 838 839 HTT_SCHED_TID_SKIP_CMD_SLOT_NOT_AVAIL, 840 HTT_SCHED_TID_SKIP_NO_ENQ, 841 HTT_SCHED_TID_SKIP_LOW_ENQ, 842 HTT_SCHED_TID_SKIP_PAUSED, 843 HTT_SCHED_TID_SKIP_UL, 844 HTT_SCHED_TID_REMOVE_PAUSED, 845 HTT_SCHED_TID_REMOVE_NO_ENQ, 846 HTT_SCHED_TID_REMOVE_UL, 847 HTT_SCHED_TID_QUERY, 848 HTT_SCHED_TID_SU_ONLY, 849 HTT_SCHED_TID_ELIGIBLE, 850 HTT_SCHED_INELIGIBILITY_MAX, 851 }; 852 853 /* NOTE: Variable length TLV, use length spec to infer array size */ 854 struct htt_sched_txq_sched_ineligibility_tlv_v { 855 /* indexed by htt_sched_txq_sched_ineligibility_tlv_enum */ 856 DECLARE_FLEX_ARRAY(u32, sched_ineligibility); 857 }; 858 859 #define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID GENMASK(7, 0) 860 #define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_ID GENMASK(15, 8) 861 862 struct htt_tx_pdev_stats_sched_per_txq_tlv { 863 u32 mac_id__txq_id__word; 864 u32 sched_policy; 865 u32 last_sched_cmd_posted_timestamp; 866 u32 last_sched_cmd_compl_timestamp; 867 u32 sched_2_tac_lwm_count; 868 u32 sched_2_tac_ring_full; 869 u32 sched_cmd_post_failure; 870 u32 num_active_tids; 871 u32 num_ps_schedules; 872 u32 sched_cmds_pending; 873 u32 num_tid_register; 874 u32 num_tid_unregister; 875 u32 num_qstats_queried; 876 u32 qstats_update_pending; 877 u32 last_qstats_query_timestamp; 878 u32 num_tqm_cmdq_full; 879 u32 num_de_sched_algo_trigger; 880 u32 num_rt_sched_algo_trigger; 881 u32 num_tqm_sched_algo_trigger; 882 u32 notify_sched; 883 u32 dur_based_sendn_term; 884 }; 885 886 struct htt_stats_tx_sched_cmn_tlv { 887 /* BIT [ 7 : 0] :- mac_id 888 * BIT [31 : 8] :- reserved 889 */ 890 u32 mac_id__word; 891 /* Current timestamp */ 892 u32 current_timestamp; 893 }; 894 895 /* == TQM STATS == */ 896 #define HTT_TX_TQM_MAX_GEN_MPDU_END_REASON 16 897 #define HTT_TX_TQM_MAX_LIST_MPDU_END_REASON 16 898 #define HTT_TX_TQM_MAX_LIST_MPDU_CNT_HISTOGRAM_BINS 16 899 900 /* NOTE: Variable length TLV, use length spec to infer array size */ 901 struct htt_tx_tqm_gen_mpdu_stats_tlv_v { 902 /* HTT_TX_TQM_MAX_GEN_MPDU_END_REASON */ 903 DECLARE_FLEX_ARRAY(u32, gen_mpdu_end_reason); 904 }; 905 906 /* NOTE: Variable length TLV, use length spec to infer array size */ 907 struct htt_tx_tqm_list_mpdu_stats_tlv_v { 908 /* HTT_TX_TQM_MAX_LIST_MPDU_END_REASON */ 909 DECLARE_FLEX_ARRAY(u32, list_mpdu_end_reason); 910 }; 911 912 /* NOTE: Variable length TLV, use length spec to infer array size */ 913 struct htt_tx_tqm_list_mpdu_cnt_tlv_v { 914 /* HTT_TX_TQM_MAX_LIST_MPDU_CNT_HISTOGRAM_BINS */ 915 DECLARE_FLEX_ARRAY(u32, list_mpdu_cnt_hist); 916 }; 917 918 struct htt_tx_tqm_pdev_stats_tlv_v { 919 u32 msdu_count; 920 u32 mpdu_count; 921 u32 remove_msdu; 922 u32 remove_mpdu; 923 u32 remove_msdu_ttl; 924 u32 send_bar; 925 u32 bar_sync; 926 u32 notify_mpdu; 927 u32 sync_cmd; 928 u32 write_cmd; 929 u32 hwsch_trigger; 930 u32 ack_tlv_proc; 931 u32 gen_mpdu_cmd; 932 u32 gen_list_cmd; 933 u32 remove_mpdu_cmd; 934 u32 remove_mpdu_tried_cmd; 935 u32 mpdu_queue_stats_cmd; 936 u32 mpdu_head_info_cmd; 937 u32 msdu_flow_stats_cmd; 938 u32 remove_msdu_cmd; 939 u32 remove_msdu_ttl_cmd; 940 u32 flush_cache_cmd; 941 u32 update_mpduq_cmd; 942 u32 enqueue; 943 u32 enqueue_notify; 944 u32 notify_mpdu_at_head; 945 u32 notify_mpdu_state_valid; 946 /* 947 * On receiving TQM_FLOW_NOT_EMPTY_STATUS from TQM, (on MSDUs being enqueued 948 * the flow is non empty), if the number of MSDUs is greater than the threshold, 949 * notify is incremented. UDP_THRESH counters are for UDP MSDUs, and NONUDP are 950 * for non-UDP MSDUs. 951 * MSDUQ_SWNOTIFY_UDP_THRESH1 threshold - sched_udp_notify1 is incremented 952 * MSDUQ_SWNOTIFY_UDP_THRESH2 threshold - sched_udp_notify2 is incremented 953 * MSDUQ_SWNOTIFY_NONUDP_THRESH1 threshold - sched_nonudp_notify1 is incremented 954 * MSDUQ_SWNOTIFY_NONUDP_THRESH2 threshold - sched_nonudp_notify2 is incremented 955 * 956 * Notify signifies that we trigger the scheduler. 957 */ 958 u32 sched_udp_notify1; 959 u32 sched_udp_notify2; 960 u32 sched_nonudp_notify1; 961 u32 sched_nonudp_notify2; 962 }; 963 964 struct htt_tx_tqm_cmn_stats_tlv { 965 u32 mac_id__word; 966 u32 max_cmdq_id; 967 u32 list_mpdu_cnt_hist_intvl; 968 969 /* Global stats */ 970 u32 add_msdu; 971 u32 q_empty; 972 u32 q_not_empty; 973 u32 drop_notification; 974 u32 desc_threshold; 975 }; 976 977 struct htt_tx_tqm_error_stats_tlv { 978 /* Error stats */ 979 u32 q_empty_failure; 980 u32 q_not_empty_failure; 981 u32 add_msdu_failure; 982 }; 983 984 /* == TQM CMDQ stats == */ 985 #define HTT_TX_TQM_CMDQ_STATUS_MAC_ID GENMASK(7, 0) 986 #define HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID GENMASK(15, 8) 987 988 struct htt_tx_tqm_cmdq_status_tlv { 989 u32 mac_id__cmdq_id__word; 990 u32 sync_cmd; 991 u32 write_cmd; 992 u32 gen_mpdu_cmd; 993 u32 mpdu_queue_stats_cmd; 994 u32 mpdu_head_info_cmd; 995 u32 msdu_flow_stats_cmd; 996 u32 remove_mpdu_cmd; 997 u32 remove_msdu_cmd; 998 u32 flush_cache_cmd; 999 u32 update_mpduq_cmd; 1000 u32 update_msduq_cmd; 1001 }; 1002 1003 /* == TX-DE STATS == */ 1004 /* Structures for tx de stats */ 1005 struct htt_tx_de_eapol_packets_stats_tlv { 1006 u32 m1_packets; 1007 u32 m2_packets; 1008 u32 m3_packets; 1009 u32 m4_packets; 1010 u32 g1_packets; 1011 u32 g2_packets; 1012 }; 1013 1014 struct htt_tx_de_classify_failed_stats_tlv { 1015 u32 ap_bss_peer_not_found; 1016 u32 ap_bcast_mcast_no_peer; 1017 u32 sta_delete_in_progress; 1018 u32 ibss_no_bss_peer; 1019 u32 invalid_vdev_type; 1020 u32 invalid_ast_peer_entry; 1021 u32 peer_entry_invalid; 1022 u32 ethertype_not_ip; 1023 u32 eapol_lookup_failed; 1024 u32 qpeer_not_allow_data; 1025 u32 fse_tid_override; 1026 u32 ipv6_jumbogram_zero_length; 1027 u32 qos_to_non_qos_in_prog; 1028 }; 1029 1030 struct htt_tx_de_classify_stats_tlv { 1031 u32 arp_packets; 1032 u32 igmp_packets; 1033 u32 dhcp_packets; 1034 u32 host_inspected; 1035 u32 htt_included; 1036 u32 htt_valid_mcs; 1037 u32 htt_valid_nss; 1038 u32 htt_valid_preamble_type; 1039 u32 htt_valid_chainmask; 1040 u32 htt_valid_guard_interval; 1041 u32 htt_valid_retries; 1042 u32 htt_valid_bw_info; 1043 u32 htt_valid_power; 1044 u32 htt_valid_key_flags; 1045 u32 htt_valid_no_encryption; 1046 u32 fse_entry_count; 1047 u32 fse_priority_be; 1048 u32 fse_priority_high; 1049 u32 fse_priority_low; 1050 u32 fse_traffic_ptrn_be; 1051 u32 fse_traffic_ptrn_over_sub; 1052 u32 fse_traffic_ptrn_bursty; 1053 u32 fse_traffic_ptrn_interactive; 1054 u32 fse_traffic_ptrn_periodic; 1055 u32 fse_hwqueue_alloc; 1056 u32 fse_hwqueue_created; 1057 u32 fse_hwqueue_send_to_host; 1058 u32 mcast_entry; 1059 u32 bcast_entry; 1060 u32 htt_update_peer_cache; 1061 u32 htt_learning_frame; 1062 u32 fse_invalid_peer; 1063 /* 1064 * mec_notify is HTT TX WBM multicast echo check notification 1065 * from firmware to host. FW sends SA addresses to host for all 1066 * multicast/broadcast packets received on STA side. 1067 */ 1068 u32 mec_notify; 1069 }; 1070 1071 struct htt_tx_de_classify_status_stats_tlv { 1072 u32 eok; 1073 u32 classify_done; 1074 u32 lookup_failed; 1075 u32 send_host_dhcp; 1076 u32 send_host_mcast; 1077 u32 send_host_unknown_dest; 1078 u32 send_host; 1079 u32 status_invalid; 1080 }; 1081 1082 struct htt_tx_de_enqueue_packets_stats_tlv { 1083 u32 enqueued_pkts; 1084 u32 to_tqm; 1085 u32 to_tqm_bypass; 1086 }; 1087 1088 struct htt_tx_de_enqueue_discard_stats_tlv { 1089 u32 discarded_pkts; 1090 u32 local_frames; 1091 u32 is_ext_msdu; 1092 }; 1093 1094 struct htt_tx_de_compl_stats_tlv { 1095 u32 tcl_dummy_frame; 1096 u32 tqm_dummy_frame; 1097 u32 tqm_notify_frame; 1098 u32 fw2wbm_enq; 1099 u32 tqm_bypass_frame; 1100 }; 1101 1102 /* 1103 * The htt_tx_de_fw2wbm_ring_full_hist_tlv is a histogram of time we waited 1104 * for the fw2wbm ring buffer. we are requesting a buffer in FW2WBM release 1105 * ring,which may fail, due to non availability of buffer. Hence we sleep for 1106 * 200us & again request for it. This is a histogram of time we wait, with 1107 * bin of 200ms & there are 10 bin (2 seconds max) 1108 * They are defined by the following macros in FW 1109 * #define ENTRIES_PER_BIN_COUNT 1000 // per bin 1000 * 200us = 200ms 1110 * #define RING_FULL_BIN_ENTRIES (WAL_TX_DE_FW2WBM_ALLOC_TIMEOUT_COUNT / 1111 * ENTRIES_PER_BIN_COUNT) 1112 */ 1113 struct htt_tx_de_fw2wbm_ring_full_hist_tlv { 1114 DECLARE_FLEX_ARRAY(u32, fw2wbm_ring_full_hist); 1115 }; 1116 1117 struct htt_tx_de_cmn_stats_tlv { 1118 u32 mac_id__word; 1119 1120 /* Global Stats */ 1121 u32 tcl2fw_entry_count; 1122 u32 not_to_fw; 1123 u32 invalid_pdev_vdev_peer; 1124 u32 tcl_res_invalid_addrx; 1125 u32 wbm2fw_entry_count; 1126 u32 invalid_pdev; 1127 }; 1128 1129 /* == RING-IF STATS == */ 1130 #define HTT_STATS_LOW_WM_BINS 5 1131 #define HTT_STATS_HIGH_WM_BINS 5 1132 1133 #define HTT_RING_IF_STATS_NUM_ELEMS GENMASK(15, 0) 1134 #define HTT_RING_IF_STATS_PREFETCH_TAIL_INDEX GENMASK(31, 16) 1135 #define HTT_RING_IF_STATS_HEAD_IDX GENMASK(15, 0) 1136 #define HTT_RING_IF_STATS_TAIL_IDX GENMASK(31, 16) 1137 #define HTT_RING_IF_STATS_SHADOW_HEAD_IDX GENMASK(15, 0) 1138 #define HTT_RING_IF_STATS_SHADOW_TAIL_IDX GENMASK(31, 16) 1139 #define HTT_RING_IF_STATS_LWM_THRESH GENMASK(15, 0) 1140 #define HTT_RING_IF_STATS_HWM_THRESH GENMASK(31, 16) 1141 1142 struct htt_ring_if_stats_tlv { 1143 u32 base_addr; /* DWORD aligned base memory address of the ring */ 1144 u32 elem_size; 1145 u32 num_elems__prefetch_tail_idx; 1146 u32 head_idx__tail_idx; 1147 u32 shadow_head_idx__shadow_tail_idx; 1148 u32 num_tail_incr; 1149 u32 lwm_thresh__hwm_thresh; 1150 u32 overrun_hit_count; 1151 u32 underrun_hit_count; 1152 u32 prod_blockwait_count; 1153 u32 cons_blockwait_count; 1154 u32 low_wm_hit_count[HTT_STATS_LOW_WM_BINS]; 1155 u32 high_wm_hit_count[HTT_STATS_HIGH_WM_BINS]; 1156 }; 1157 1158 struct htt_ring_if_cmn_tlv { 1159 u32 mac_id__word; 1160 u32 num_records; 1161 }; 1162 1163 /* == SFM STATS == */ 1164 /* NOTE: Variable length TLV, use length spec to infer array size */ 1165 struct htt_sfm_client_user_tlv_v { 1166 /* Number of DWORDS used per user and per client */ 1167 DECLARE_FLEX_ARRAY(u32, dwords_used_by_user_n); 1168 }; 1169 1170 struct htt_sfm_client_tlv { 1171 /* Client ID */ 1172 u32 client_id; 1173 /* Minimum number of buffers */ 1174 u32 buf_min; 1175 /* Maximum number of buffers */ 1176 u32 buf_max; 1177 /* Number of Busy buffers */ 1178 u32 buf_busy; 1179 /* Number of Allocated buffers */ 1180 u32 buf_alloc; 1181 /* Number of Available/Usable buffers */ 1182 u32 buf_avail; 1183 /* Number of users */ 1184 u32 num_users; 1185 }; 1186 1187 struct htt_sfm_cmn_tlv { 1188 u32 mac_id__word; 1189 /* Indicates the total number of 128 byte buffers 1190 * in the CMEM that are available for buffer sharing 1191 */ 1192 u32 buf_total; 1193 /* Indicates for certain client or all the clients 1194 * there is no dowrd saved in SFM, refer to SFM_R1_MEM_EMPTY 1195 */ 1196 u32 mem_empty; 1197 /* DEALLOCATE_BUFFERS, refer to register SFM_R0_DEALLOCATE_BUFFERS */ 1198 u32 deallocate_bufs; 1199 /* Number of Records */ 1200 u32 num_records; 1201 }; 1202 1203 /* == SRNG STATS == */ 1204 #define HTT_SRING_STATS_MAC_ID GENMASK(7, 0) 1205 #define HTT_SRING_STATS_RING_ID GENMASK(15, 8) 1206 #define HTT_SRING_STATS_ARENA GENMASK(23, 16) 1207 #define HTT_SRING_STATS_EP BIT(24) 1208 #define HTT_SRING_STATS_NUM_AVAIL_WORDS GENMASK(15, 0) 1209 #define HTT_SRING_STATS_NUM_VALID_WORDS GENMASK(31, 16) 1210 #define HTT_SRING_STATS_HEAD_PTR GENMASK(15, 0) 1211 #define HTT_SRING_STATS_TAIL_PTR GENMASK(31, 16) 1212 #define HTT_SRING_STATS_CONSUMER_EMPTY GENMASK(15, 0) 1213 #define HTT_SRING_STATS_PRODUCER_FULL GENMASK(31, 16) 1214 #define HTT_SRING_STATS_PREFETCH_COUNT GENMASK(15, 0) 1215 #define HTT_SRING_STATS_INTERNAL_TAIL_PTR GENMASK(31, 16) 1216 1217 struct htt_sring_stats_tlv { 1218 u32 mac_id__ring_id__arena__ep; 1219 u32 base_addr_lsb; /* DWORD aligned base memory address of the ring */ 1220 u32 base_addr_msb; 1221 u32 ring_size; 1222 u32 elem_size; 1223 1224 u32 num_avail_words__num_valid_words; 1225 u32 head_ptr__tail_ptr; 1226 u32 consumer_empty__producer_full; 1227 u32 prefetch_count__internal_tail_ptr; 1228 }; 1229 1230 struct htt_sring_cmn_tlv { 1231 u32 num_records; 1232 }; 1233 1234 /* == PDEV TX RATE CTRL STATS == */ 1235 #define HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS 12 1236 #define HTT_TX_PDEV_STATS_NUM_GI_COUNTERS 4 1237 #define HTT_TX_PDEV_STATS_NUM_DCM_COUNTERS 5 1238 #define HTT_TX_PDEV_STATS_NUM_BW_COUNTERS 4 1239 #define HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS 8 1240 #define HTT_TX_PDEV_STATS_NUM_PREAMBLE_TYPES HTT_STATS_PREAM_COUNT 1241 #define HTT_TX_PDEV_STATS_NUM_LEGACY_CCK_STATS 4 1242 #define HTT_TX_PDEV_STATS_NUM_LEGACY_OFDM_STATS 8 1243 #define HTT_TX_PDEV_STATS_NUM_LTF 4 1244 1245 #define HTT_TX_NUM_OF_SOUNDING_STATS_WORDS \ 1246 (HTT_TX_PDEV_STATS_NUM_BW_COUNTERS * \ 1247 HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS) 1248 1249 struct htt_tx_pdev_rate_stats_tlv { 1250 u32 mac_id__word; 1251 u32 tx_ldpc; 1252 u32 rts_cnt; 1253 /* RSSI value of last ack packet (units = dB above noise floor) */ 1254 u32 ack_rssi; 1255 1256 u32 tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 1257 1258 u32 tx_su_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 1259 u32 tx_mu_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 1260 1261 /* element 0,1, ...7 -> NSS 1,2, ...8 */ 1262 u32 tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1263 /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */ 1264 u32 tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 1265 u32 tx_stbc[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 1266 u32 tx_pream[HTT_TX_PDEV_STATS_NUM_PREAMBLE_TYPES]; 1267 1268 /* Counters to track number of tx packets 1269 * in each GI (400us, 800us, 1600us & 3200us) in each mcs (0-11) 1270 */ 1271 u32 tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 1272 1273 /* Counters to track packets in dcm mcs (MCS 0, 1, 3, 4) */ 1274 u32 tx_dcm[HTT_TX_PDEV_STATS_NUM_DCM_COUNTERS]; 1275 /* Number of CTS-acknowledged RTS packets */ 1276 u32 rts_success; 1277 1278 /* 1279 * Counters for legacy 11a and 11b transmissions. 1280 * 1281 * The index corresponds to: 1282 * 1283 * CCK: 0: 1 Mbps, 1: 2 Mbps, 2: 5.5 Mbps, 3: 11 Mbps 1284 * 1285 * OFDM: 0: 6 Mbps, 1: 9 Mbps, 2: 12 Mbps, 3: 18 Mbps, 1286 * 4: 24 Mbps, 5: 36 Mbps, 6: 48 Mbps, 7: 54 Mbps 1287 */ 1288 u32 tx_legacy_cck_rate[HTT_TX_PDEV_STATS_NUM_LEGACY_CCK_STATS]; 1289 u32 tx_legacy_ofdm_rate[HTT_TX_PDEV_STATS_NUM_LEGACY_OFDM_STATS]; 1290 1291 u32 ac_mu_mimo_tx_ldpc; 1292 u32 ax_mu_mimo_tx_ldpc; 1293 u32 ofdma_tx_ldpc; 1294 1295 /* 1296 * Counters for 11ax HE LTF selection during TX. 1297 * 1298 * The index corresponds to: 1299 * 1300 * 0: unused, 1: 1x LTF, 2: 2x LTF, 3: 4x LTF 1301 */ 1302 u32 tx_he_ltf[HTT_TX_PDEV_STATS_NUM_LTF]; 1303 1304 u32 ac_mu_mimo_tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 1305 u32 ax_mu_mimo_tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 1306 u32 ofdma_tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 1307 1308 u32 ac_mu_mimo_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1309 u32 ax_mu_mimo_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1310 u32 ofdma_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1311 1312 u32 ac_mu_mimo_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 1313 u32 ax_mu_mimo_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 1314 u32 ofdma_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 1315 1316 u32 ac_mu_mimo_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] 1317 [HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 1318 u32 ax_mu_mimo_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] 1319 [HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 1320 u32 ofdma_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] 1321 [HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 1322 }; 1323 1324 /* == PDEV RX RATE CTRL STATS == */ 1325 #define HTT_RX_PDEV_STATS_NUM_LEGACY_CCK_STATS 4 1326 #define HTT_RX_PDEV_STATS_NUM_LEGACY_OFDM_STATS 8 1327 #define HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS 12 1328 #define HTT_RX_PDEV_STATS_NUM_GI_COUNTERS 4 1329 #define HTT_RX_PDEV_STATS_NUM_DCM_COUNTERS 5 1330 #define HTT_RX_PDEV_STATS_NUM_BW_COUNTERS 4 1331 #define HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS 8 1332 #define HTT_RX_PDEV_STATS_NUM_PREAMBLE_TYPES HTT_STATS_PREAM_COUNT 1333 #define HTT_RX_PDEV_MAX_OFDMA_NUM_USER 8 1334 #define HTT_RX_PDEV_STATS_RXEVM_MAX_PILOTS_PER_NSS 16 1335 #define HTT_RX_PDEV_STATS_NUM_RU_SIZE_COUNTERS 6 1336 #define HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER 8 1337 1338 struct htt_rx_pdev_rate_stats_tlv { 1339 u32 mac_id__word; 1340 u32 nsts; 1341 1342 u32 rx_ldpc; 1343 u32 rts_cnt; 1344 1345 u32 rssi_mgmt; /* units = dB above noise floor */ 1346 u32 rssi_data; /* units = dB above noise floor */ 1347 u32 rssi_comb; /* units = dB above noise floor */ 1348 u32 rx_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 1349 /* element 0,1, ...7 -> NSS 1,2, ...8 */ 1350 u32 rx_nss[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1351 u32 rx_dcm[HTT_RX_PDEV_STATS_NUM_DCM_COUNTERS]; 1352 u32 rx_stbc[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 1353 /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */ 1354 u32 rx_bw[HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; 1355 u32 rx_pream[HTT_RX_PDEV_STATS_NUM_PREAMBLE_TYPES]; 1356 u8 rssi_chain[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS] 1357 [HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; 1358 /* units = dB above noise floor */ 1359 1360 /* Counters to track number of rx packets 1361 * in each GI in each mcs (0-11) 1362 */ 1363 u32 rx_gi[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 1364 s32 rssi_in_dbm; /* rx Signal Strength value in dBm unit */ 1365 1366 u32 rx_11ax_su_ext; 1367 u32 rx_11ac_mumimo; 1368 u32 rx_11ax_mumimo; 1369 u32 rx_11ax_ofdma; 1370 u32 txbf; 1371 u32 rx_legacy_cck_rate[HTT_RX_PDEV_STATS_NUM_LEGACY_CCK_STATS]; 1372 u32 rx_legacy_ofdm_rate[HTT_RX_PDEV_STATS_NUM_LEGACY_OFDM_STATS]; 1373 u32 rx_active_dur_us_low; 1374 u32 rx_active_dur_us_high; 1375 1376 u32 rx_11ax_ul_ofdma; 1377 1378 u32 ul_ofdma_rx_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 1379 u32 ul_ofdma_rx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] 1380 [HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 1381 u32 ul_ofdma_rx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1382 u32 ul_ofdma_rx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 1383 u32 ul_ofdma_rx_stbc; 1384 u32 ul_ofdma_rx_ldpc; 1385 1386 /* record the stats for each user index */ 1387 u32 rx_ulofdma_non_data_ppdu[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; /* ppdu level */ 1388 u32 rx_ulofdma_data_ppdu[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; /* ppdu level */ 1389 u32 rx_ulofdma_mpdu_ok[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; /* mpdu level */ 1390 u32 rx_ulofdma_mpdu_fail[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; /* mpdu level */ 1391 1392 u32 nss_count; 1393 u32 pilot_count; 1394 /* RxEVM stats in dB */ 1395 s32 rx_pilot_evm_db[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS] 1396 [HTT_RX_PDEV_STATS_RXEVM_MAX_PILOTS_PER_NSS]; 1397 /* rx_pilot_evm_db_mean: 1398 * EVM mean across pilots, computed as 1399 * mean(10*log10(rx_pilot_evm_linear)) = mean(rx_pilot_evm_db) 1400 */ 1401 s32 rx_pilot_evm_db_mean[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1402 s8 rx_ul_fd_rssi[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS] 1403 [HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; /* dBm units */ 1404 /* per_chain_rssi_pkt_type: 1405 * This field shows what type of rx frame the per-chain RSSI was computed 1406 * on, by recording the frame type and sub-type as bit-fields within this 1407 * field: 1408 * BIT [3 : 0] :- IEEE80211_FC0_TYPE 1409 * BIT [7 : 4] :- IEEE80211_FC0_SUBTYPE 1410 * BIT [31 : 8] :- Reserved 1411 */ 1412 u32 per_chain_rssi_pkt_type; 1413 s8 rx_per_chain_rssi_in_dbm[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS] 1414 [HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; 1415 1416 u32 rx_su_ndpa; 1417 u32 rx_11ax_su_txbf_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 1418 u32 rx_mu_ndpa; 1419 u32 rx_11ax_mu_txbf_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 1420 u32 rx_br_poll; 1421 u32 rx_11ax_dl_ofdma_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 1422 u32 rx_11ax_dl_ofdma_ru[HTT_RX_PDEV_STATS_NUM_RU_SIZE_COUNTERS]; 1423 1424 u32 rx_ulmumimo_non_data_ppdu[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER]; 1425 u32 rx_ulmumimo_data_ppdu[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER]; 1426 u32 rx_ulmumimo_mpdu_ok[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER]; 1427 u32 rx_ulmumimo_mpdu_fail[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER]; 1428 u32 rx_ulofdma_non_data_nusers[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 1429 u32 rx_ulofdma_data_nusers[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 1430 }; 1431 1432 /* == RX PDEV/SOC STATS == */ 1433 struct htt_rx_soc_fw_stats_tlv { 1434 u32 fw_reo_ring_data_msdu; 1435 u32 fw_to_host_data_msdu_bcmc; 1436 u32 fw_to_host_data_msdu_uc; 1437 u32 ofld_remote_data_buf_recycle_cnt; 1438 u32 ofld_remote_free_buf_indication_cnt; 1439 1440 u32 ofld_buf_to_host_data_msdu_uc; 1441 u32 reo_fw_ring_to_host_data_msdu_uc; 1442 1443 u32 wbm_sw_ring_reap; 1444 u32 wbm_forward_to_host_cnt; 1445 u32 wbm_target_recycle_cnt; 1446 1447 u32 target_refill_ring_recycle_cnt; 1448 }; 1449 1450 /* NOTE: Variable length TLV, use length spec to infer array size */ 1451 struct htt_rx_soc_fw_refill_ring_empty_tlv_v { 1452 /* HTT_RX_STATS_REFILL_MAX_RING */ 1453 DECLARE_FLEX_ARRAY(u32, refill_ring_empty_cnt); 1454 }; 1455 1456 /* NOTE: Variable length TLV, use length spec to infer array size */ 1457 struct htt_rx_soc_fw_refill_ring_num_refill_tlv_v { 1458 /* HTT_RX_STATS_REFILL_MAX_RING */ 1459 DECLARE_FLEX_ARRAY(u32, refill_ring_num_refill); 1460 }; 1461 1462 /* RXDMA error code from WBM released packets */ 1463 enum htt_rx_rxdma_error_code_enum { 1464 HTT_RX_RXDMA_OVERFLOW_ERR = 0, 1465 HTT_RX_RXDMA_MPDU_LENGTH_ERR = 1, 1466 HTT_RX_RXDMA_FCS_ERR = 2, 1467 HTT_RX_RXDMA_DECRYPT_ERR = 3, 1468 HTT_RX_RXDMA_TKIP_MIC_ERR = 4, 1469 HTT_RX_RXDMA_UNECRYPTED_ERR = 5, 1470 HTT_RX_RXDMA_MSDU_LEN_ERR = 6, 1471 HTT_RX_RXDMA_MSDU_LIMIT_ERR = 7, 1472 HTT_RX_RXDMA_WIFI_PARSE_ERR = 8, 1473 HTT_RX_RXDMA_AMSDU_PARSE_ERR = 9, 1474 HTT_RX_RXDMA_SA_TIMEOUT_ERR = 10, 1475 HTT_RX_RXDMA_DA_TIMEOUT_ERR = 11, 1476 HTT_RX_RXDMA_FLOW_TIMEOUT_ERR = 12, 1477 HTT_RX_RXDMA_FLUSH_REQUEST = 13, 1478 HTT_RX_RXDMA_ERR_CODE_RVSD0 = 14, 1479 HTT_RX_RXDMA_ERR_CODE_RVSD1 = 15, 1480 1481 /* This MAX_ERR_CODE should not be used in any host/target messages, 1482 * so that even though it is defined within a host/target interface 1483 * definition header file, it isn't actually part of the host/target 1484 * interface, and thus can be modified. 1485 */ 1486 HTT_RX_RXDMA_MAX_ERR_CODE 1487 }; 1488 1489 /* NOTE: Variable length TLV, use length spec to infer array size */ 1490 struct htt_rx_soc_fw_refill_ring_num_rxdma_err_tlv_v { 1491 DECLARE_FLEX_ARRAY(u32, rxdma_err); /* HTT_RX_RXDMA_MAX_ERR_CODE */ 1492 }; 1493 1494 /* REO error code from WBM released packets */ 1495 enum htt_rx_reo_error_code_enum { 1496 HTT_RX_REO_QUEUE_DESC_ADDR_ZERO = 0, 1497 HTT_RX_REO_QUEUE_DESC_NOT_VALID = 1, 1498 HTT_RX_AMPDU_IN_NON_BA = 2, 1499 HTT_RX_NON_BA_DUPLICATE = 3, 1500 HTT_RX_BA_DUPLICATE = 4, 1501 HTT_RX_REGULAR_FRAME_2K_JUMP = 5, 1502 HTT_RX_BAR_FRAME_2K_JUMP = 6, 1503 HTT_RX_REGULAR_FRAME_OOR = 7, 1504 HTT_RX_BAR_FRAME_OOR = 8, 1505 HTT_RX_BAR_FRAME_NO_BA_SESSION = 9, 1506 HTT_RX_BAR_FRAME_SN_EQUALS_SSN = 10, 1507 HTT_RX_PN_CHECK_FAILED = 11, 1508 HTT_RX_2K_ERROR_HANDLING_FLAG_SET = 12, 1509 HTT_RX_PN_ERROR_HANDLING_FLAG_SET = 13, 1510 HTT_RX_QUEUE_DESCRIPTOR_BLOCKED_SET = 14, 1511 HTT_RX_REO_ERR_CODE_RVSD = 15, 1512 1513 /* This MAX_ERR_CODE should not be used in any host/target messages, 1514 * so that even though it is defined within a host/target interface 1515 * definition header file, it isn't actually part of the host/target 1516 * interface, and thus can be modified. 1517 */ 1518 HTT_RX_REO_MAX_ERR_CODE 1519 }; 1520 1521 /* NOTE: Variable length TLV, use length spec to infer array size */ 1522 struct htt_rx_soc_fw_refill_ring_num_reo_err_tlv_v { 1523 DECLARE_FLEX_ARRAY(u32, reo_err); /* HTT_RX_REO_MAX_ERR_CODE */ 1524 }; 1525 1526 /* == RX PDEV STATS == */ 1527 #define HTT_STATS_SUBTYPE_MAX 16 1528 1529 struct htt_rx_pdev_fw_stats_tlv { 1530 u32 mac_id__word; 1531 u32 ppdu_recvd; 1532 u32 mpdu_cnt_fcs_ok; 1533 u32 mpdu_cnt_fcs_err; 1534 u32 tcp_msdu_cnt; 1535 u32 tcp_ack_msdu_cnt; 1536 u32 udp_msdu_cnt; 1537 u32 other_msdu_cnt; 1538 u32 fw_ring_mpdu_ind; 1539 u32 fw_ring_mgmt_subtype[HTT_STATS_SUBTYPE_MAX]; 1540 u32 fw_ring_ctrl_subtype[HTT_STATS_SUBTYPE_MAX]; 1541 u32 fw_ring_mcast_data_msdu; 1542 u32 fw_ring_bcast_data_msdu; 1543 u32 fw_ring_ucast_data_msdu; 1544 u32 fw_ring_null_data_msdu; 1545 u32 fw_ring_mpdu_drop; 1546 u32 ofld_local_data_ind_cnt; 1547 u32 ofld_local_data_buf_recycle_cnt; 1548 u32 drx_local_data_ind_cnt; 1549 u32 drx_local_data_buf_recycle_cnt; 1550 u32 local_nondata_ind_cnt; 1551 u32 local_nondata_buf_recycle_cnt; 1552 1553 u32 fw_status_buf_ring_refill_cnt; 1554 u32 fw_status_buf_ring_empty_cnt; 1555 u32 fw_pkt_buf_ring_refill_cnt; 1556 u32 fw_pkt_buf_ring_empty_cnt; 1557 u32 fw_link_buf_ring_refill_cnt; 1558 u32 fw_link_buf_ring_empty_cnt; 1559 1560 u32 host_pkt_buf_ring_refill_cnt; 1561 u32 host_pkt_buf_ring_empty_cnt; 1562 u32 mon_pkt_buf_ring_refill_cnt; 1563 u32 mon_pkt_buf_ring_empty_cnt; 1564 u32 mon_status_buf_ring_refill_cnt; 1565 u32 mon_status_buf_ring_empty_cnt; 1566 u32 mon_desc_buf_ring_refill_cnt; 1567 u32 mon_desc_buf_ring_empty_cnt; 1568 u32 mon_dest_ring_update_cnt; 1569 u32 mon_dest_ring_full_cnt; 1570 1571 u32 rx_suspend_cnt; 1572 u32 rx_suspend_fail_cnt; 1573 u32 rx_resume_cnt; 1574 u32 rx_resume_fail_cnt; 1575 u32 rx_ring_switch_cnt; 1576 u32 rx_ring_restore_cnt; 1577 u32 rx_flush_cnt; 1578 u32 rx_recovery_reset_cnt; 1579 }; 1580 1581 #define HTT_STATS_PHY_ERR_MAX 43 1582 1583 struct htt_rx_pdev_fw_stats_phy_err_tlv { 1584 u32 mac_id__word; 1585 u32 total_phy_err_cnt; 1586 /* Counts of different types of phy errs 1587 * The mapping of PHY error types to phy_err array elements is HW dependent. 1588 * The only currently-supported mapping is shown below: 1589 * 1590 * 0 phyrx_err_phy_off Reception aborted due to receiving a PHY_OFF TLV 1591 * 1 phyrx_err_synth_off 1592 * 2 phyrx_err_ofdma_timing 1593 * 3 phyrx_err_ofdma_signal_parity 1594 * 4 phyrx_err_ofdma_rate_illegal 1595 * 5 phyrx_err_ofdma_length_illegal 1596 * 6 phyrx_err_ofdma_restart 1597 * 7 phyrx_err_ofdma_service 1598 * 8 phyrx_err_ppdu_ofdma_power_drop 1599 * 9 phyrx_err_cck_blokker 1600 * 10 phyrx_err_cck_timing 1601 * 11 phyrx_err_cck_header_crc 1602 * 12 phyrx_err_cck_rate_illegal 1603 * 13 phyrx_err_cck_length_illegal 1604 * 14 phyrx_err_cck_restart 1605 * 15 phyrx_err_cck_service 1606 * 16 phyrx_err_cck_power_drop 1607 * 17 phyrx_err_ht_crc_err 1608 * 18 phyrx_err_ht_length_illegal 1609 * 19 phyrx_err_ht_rate_illegal 1610 * 20 phyrx_err_ht_zlf 1611 * 21 phyrx_err_false_radar_ext 1612 * 22 phyrx_err_green_field 1613 * 23 phyrx_err_bw_gt_dyn_bw 1614 * 24 phyrx_err_leg_ht_mismatch 1615 * 25 phyrx_err_vht_crc_error 1616 * 26 phyrx_err_vht_siga_unsupported 1617 * 27 phyrx_err_vht_lsig_len_invalid 1618 * 28 phyrx_err_vht_ndp_or_zlf 1619 * 29 phyrx_err_vht_nsym_lt_zero 1620 * 30 phyrx_err_vht_rx_extra_symbol_mismatch 1621 * 31 phyrx_err_vht_rx_skip_group_id0 1622 * 32 phyrx_err_vht_rx_skip_group_id1to62 1623 * 33 phyrx_err_vht_rx_skip_group_id63 1624 * 34 phyrx_err_ofdm_ldpc_decoder_disabled 1625 * 35 phyrx_err_defer_nap 1626 * 36 phyrx_err_fdomain_timeout 1627 * 37 phyrx_err_lsig_rel_check 1628 * 38 phyrx_err_bt_collision 1629 * 39 phyrx_err_unsupported_mu_feedback 1630 * 40 phyrx_err_ppdu_tx_interrupt_rx 1631 * 41 phyrx_err_unsupported_cbf 1632 * 42 phyrx_err_other 1633 */ 1634 u32 phy_err[HTT_STATS_PHY_ERR_MAX]; 1635 }; 1636 1637 /* NOTE: Variable length TLV, use length spec to infer array size */ 1638 struct htt_rx_pdev_fw_ring_mpdu_err_tlv_v { 1639 /* Num error MPDU for each RxDMA error type */ 1640 DECLARE_FLEX_ARRAY(u32, fw_ring_mpdu_err); /* HTT_RX_STATS_RXDMA_MAX_ERR */ 1641 }; 1642 1643 /* NOTE: Variable length TLV, use length spec to infer array size */ 1644 struct htt_rx_pdev_fw_mpdu_drop_tlv_v { 1645 /* Num MPDU dropped */ 1646 DECLARE_FLEX_ARRAY(u32, fw_mpdu_drop); /* HTT_RX_STATS_FW_DROP_REASON_MAX */ 1647 }; 1648 1649 #define HTT_PDEV_CCA_STATS_TX_FRAME_INFO_PRESENT (0x1) 1650 #define HTT_PDEV_CCA_STATS_RX_FRAME_INFO_PRESENT (0x2) 1651 #define HTT_PDEV_CCA_STATS_RX_CLEAR_INFO_PRESENT (0x4) 1652 #define HTT_PDEV_CCA_STATS_MY_RX_FRAME_INFO_PRESENT (0x8) 1653 #define HTT_PDEV_CCA_STATS_USEC_CNT_INFO_PRESENT (0x10) 1654 #define HTT_PDEV_CCA_STATS_MED_RX_IDLE_INFO_PRESENT (0x20) 1655 #define HTT_PDEV_CCA_STATS_MED_TX_IDLE_GLOBAL_INFO_PRESENT (0x40) 1656 #define HTT_PDEV_CCA_STATS_CCA_OBBS_USEC_INFO_PRESENT (0x80) 1657 1658 struct htt_pdev_stats_cca_counters_tlv { 1659 /* Below values are obtained from the HW Cycles counter registers */ 1660 u32 tx_frame_usec; 1661 u32 rx_frame_usec; 1662 u32 rx_clear_usec; 1663 u32 my_rx_frame_usec; 1664 u32 usec_cnt; 1665 u32 med_rx_idle_usec; 1666 u32 med_tx_idle_global_usec; 1667 u32 cca_obss_usec; 1668 }; 1669 1670 struct htt_pdev_cca_stats_hist_v1_tlv { 1671 u32 chan_num; 1672 /* num of CCA records (Num of htt_pdev_stats_cca_counters_tlv)*/ 1673 u32 num_records; 1674 u32 valid_cca_counters_bitmap; 1675 u32 collection_interval; 1676 1677 /* This will be followed by an array which contains the CCA stats 1678 * collected in the last N intervals, 1679 * if the indication is for last N intervals CCA stats. 1680 * Then the pdev_cca_stats[0] element contains the oldest CCA stats 1681 * and pdev_cca_stats[N-1] will have the most recent CCA stats. 1682 * htt_pdev_stats_cca_counters_tlv cca_hist_tlv[1]; 1683 */ 1684 }; 1685 1686 struct htt_pdev_stats_twt_session_tlv { 1687 u32 vdev_id; 1688 struct htt_mac_addr peer_mac; 1689 u32 flow_id_flags; 1690 1691 /* TWT_DIALOG_ID_UNAVAILABLE is used 1692 * when TWT session is not initiated by host 1693 */ 1694 u32 dialog_id; 1695 u32 wake_dura_us; 1696 u32 wake_intvl_us; 1697 u32 sp_offset_us; 1698 }; 1699 1700 struct htt_pdev_stats_twt_sessions_tlv { 1701 u32 pdev_id; 1702 u32 num_sessions; 1703 struct htt_pdev_stats_twt_session_tlv twt_session[]; 1704 }; 1705 1706 enum htt_rx_reo_resource_sample_id_enum { 1707 /* Global link descriptor queued in REO */ 1708 HTT_RX_REO_RESOURCE_GLOBAL_LINK_DESC_COUNT_0 = 0, 1709 HTT_RX_REO_RESOURCE_GLOBAL_LINK_DESC_COUNT_1 = 1, 1710 HTT_RX_REO_RESOURCE_GLOBAL_LINK_DESC_COUNT_2 = 2, 1711 /*Number of queue descriptors of this aging group */ 1712 HTT_RX_REO_RESOURCE_BUFFERS_USED_AC0 = 3, 1713 HTT_RX_REO_RESOURCE_BUFFERS_USED_AC1 = 4, 1714 HTT_RX_REO_RESOURCE_BUFFERS_USED_AC2 = 5, 1715 HTT_RX_REO_RESOURCE_BUFFERS_USED_AC3 = 6, 1716 /* Total number of MSDUs buffered in AC */ 1717 HTT_RX_REO_RESOURCE_AGING_NUM_QUEUES_AC0 = 7, 1718 HTT_RX_REO_RESOURCE_AGING_NUM_QUEUES_AC1 = 8, 1719 HTT_RX_REO_RESOURCE_AGING_NUM_QUEUES_AC2 = 9, 1720 HTT_RX_REO_RESOURCE_AGING_NUM_QUEUES_AC3 = 10, 1721 1722 HTT_RX_REO_RESOURCE_STATS_MAX = 16 1723 }; 1724 1725 struct htt_rx_reo_resource_stats_tlv_v { 1726 /* Variable based on the Number of records. HTT_RX_REO_RESOURCE_STATS_MAX */ 1727 u32 sample_id; 1728 u32 total_max; 1729 u32 total_avg; 1730 u32 total_sample; 1731 u32 non_zeros_avg; 1732 u32 non_zeros_sample; 1733 u32 last_non_zeros_max; 1734 u32 last_non_zeros_min; 1735 u32 last_non_zeros_avg; 1736 u32 last_non_zeros_sample; 1737 }; 1738 1739 /* == TX SOUNDING STATS == */ 1740 1741 enum htt_txbf_sound_steer_modes { 1742 HTT_IMPLICIT_TXBF_STEER_STATS = 0, 1743 HTT_EXPLICIT_TXBF_SU_SIFS_STEER_STATS = 1, 1744 HTT_EXPLICIT_TXBF_SU_RBO_STEER_STATS = 2, 1745 HTT_EXPLICIT_TXBF_MU_SIFS_STEER_STATS = 3, 1746 HTT_EXPLICIT_TXBF_MU_RBO_STEER_STATS = 4, 1747 HTT_TXBF_MAX_NUM_OF_MODES = 5 1748 }; 1749 1750 enum htt_stats_sounding_tx_mode { 1751 HTT_TX_AC_SOUNDING_MODE = 0, 1752 HTT_TX_AX_SOUNDING_MODE = 1, 1753 }; 1754 1755 struct htt_tx_sounding_stats_tlv { 1756 u32 tx_sounding_mode; /* HTT_TX_XX_SOUNDING_MODE */ 1757 /* Counts number of soundings for all steering modes in each bw */ 1758 u32 cbf_20[HTT_TXBF_MAX_NUM_OF_MODES]; 1759 u32 cbf_40[HTT_TXBF_MAX_NUM_OF_MODES]; 1760 u32 cbf_80[HTT_TXBF_MAX_NUM_OF_MODES]; 1761 u32 cbf_160[HTT_TXBF_MAX_NUM_OF_MODES]; 1762 /* 1763 * The sounding array is a 2-D array stored as an 1-D array of 1764 * u32. The stats for a particular user/bw combination is 1765 * referenced with the following: 1766 * 1767 * sounding[(user* max_bw) + bw] 1768 * 1769 * ... where max_bw == 4 for 160mhz 1770 */ 1771 u32 sounding[HTT_TX_NUM_OF_SOUNDING_STATS_WORDS]; 1772 }; 1773 1774 struct htt_pdev_obss_pd_stats_tlv { 1775 u32 num_obss_tx_ppdu_success; 1776 u32 num_obss_tx_ppdu_failure; 1777 u32 num_sr_tx_transmissions; 1778 u32 num_spatial_reuse_opportunities; 1779 u32 num_non_srg_opportunities; 1780 u32 num_non_srg_ppdu_tried; 1781 u32 num_non_srg_ppdu_success; 1782 u32 num_srg_opportunities; 1783 u32 num_srg_ppdu_tried; 1784 u32 num_srg_ppdu_success; 1785 u32 num_psr_opportunities; 1786 u32 num_psr_ppdu_tried; 1787 u32 num_psr_ppdu_success; 1788 }; 1789 1790 struct htt_ring_backpressure_stats_tlv { 1791 u32 pdev_id; 1792 u32 current_head_idx; 1793 u32 current_tail_idx; 1794 u32 num_htt_msgs_sent; 1795 /* Time in milliseconds for which the ring has been in 1796 * its current backpressure condition 1797 */ 1798 u32 backpressure_time_ms; 1799 /* backpressure_hist - histogram showing how many times 1800 * different degrees of backpressure duration occurred: 1801 * Index 0 indicates the number of times ring was 1802 * continuously in backpressure state for 100 - 200ms. 1803 * Index 1 indicates the number of times ring was 1804 * continuously in backpressure state for 200 - 300ms. 1805 * Index 2 indicates the number of times ring was 1806 * continuously in backpressure state for 300 - 400ms. 1807 * Index 3 indicates the number of times ring was 1808 * continuously in backpressure state for 400 - 500ms. 1809 * Index 4 indicates the number of times ring was 1810 * continuously in backpressure state beyond 500ms. 1811 */ 1812 u32 backpressure_hist[5]; 1813 }; 1814 1815 #define HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS 14 1816 #define HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS 5 1817 #define HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS 8 1818 1819 struct htt_pdev_txrate_txbf_stats_tlv { 1820 /* SU TxBF TX MCS stats */ 1821 u32 tx_su_txbf_mcs[HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS]; 1822 /* Implicit BF TX MCS stats */ 1823 u32 tx_su_ibf_mcs[HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS]; 1824 /* Open loop TX MCS stats */ 1825 u32 tx_su_ol_mcs[HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS]; 1826 /* SU TxBF TX NSS stats */ 1827 u32 tx_su_txbf_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1828 /* Implicit BF TX NSS stats */ 1829 u32 tx_su_ibf_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1830 /* Open loop TX NSS stats */ 1831 u32 tx_su_ol_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1832 /* SU TxBF TX BW stats */ 1833 u32 tx_su_txbf_bw[HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS]; 1834 /* Implicit BF TX BW stats */ 1835 u32 tx_su_ibf_bw[HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS]; 1836 /* Open loop TX BW stats */ 1837 u32 tx_su_ol_bw[HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS]; 1838 }; 1839 1840 struct htt_txbf_ofdma_ndpa_stats_tlv { 1841 /* 11AX HE OFDMA NDPA frame queued to the HW */ 1842 u32 ax_ofdma_ndpa_queued[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1843 /* 11AX HE OFDMA NDPA frame sent over the air */ 1844 u32 ax_ofdma_ndpa_tried[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1845 /* 11AX HE OFDMA NDPA frame flushed by HW */ 1846 u32 ax_ofdma_ndpa_flushed[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1847 /* 11AX HE OFDMA NDPA frame completed with error(s) */ 1848 u32 ax_ofdma_ndpa_err[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1849 }; 1850 1851 struct htt_txbf_ofdma_ndp_stats_tlv { 1852 /* 11AX HE OFDMA NDP frame queued to the HW */ 1853 u32 ax_ofdma_ndp_queued[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1854 /* 11AX HE OFDMA NDPA frame sent over the air */ 1855 u32 ax_ofdma_ndp_tried[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1856 /* 11AX HE OFDMA NDPA frame flushed by HW */ 1857 u32 ax_ofdma_ndp_flushed[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1858 /* 11AX HE OFDMA NDPA frame completed with error(s) */ 1859 u32 ax_ofdma_ndp_err[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1860 }; 1861 1862 struct htt_txbf_ofdma_brp_stats_tlv { 1863 /* 11AX HE OFDMA MU BRPOLL frame queued to the HW */ 1864 u32 ax_ofdma_brpoll_queued[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1865 /* 11AX HE OFDMA MU BRPOLL frame sent over the air */ 1866 u32 ax_ofdma_brpoll_tried[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1867 /* 11AX HE OFDMA MU BRPOLL frame flushed by HW */ 1868 u32 ax_ofdma_brpoll_flushed[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1869 /* 11AX HE OFDMA MU BRPOLL frame completed with error(s) */ 1870 u32 ax_ofdma_brp_err[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1871 /* Number of CBF(s) received when 11AX HE OFDMA MU BRPOLL frame 1872 * completed with error(s). 1873 */ 1874 u32 ax_ofdma_brp_err_num_cbf_rcvd[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS + 1]; 1875 }; 1876 1877 struct htt_txbf_ofdma_steer_stats_tlv { 1878 /* 11AX HE OFDMA PPDUs that were sent over the air with steering (TXBF + OFDMA) */ 1879 u32 ax_ofdma_num_ppdu_steer[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1880 /* 11AX HE OFDMA PPDUs that were sent over the air in open loop */ 1881 u32 ax_ofdma_num_ppdu_ol[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1882 /* 11AX HE OFDMA number of users for which CBF prefetch was 1883 * initiated to PHY HW during TX. 1884 */ 1885 u32 ax_ofdma_num_usrs_prefetch[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1886 /* 11AX HE OFDMA number of users for which sounding was initiated during TX */ 1887 u32 ax_ofdma_num_usrs_sound[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1888 /* 11AX HE OFDMA number of users for which sounding was forced during TX */ 1889 u32 ax_ofdma_num_usrs_force_sound[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1890 }; 1891 1892 #define HTT_MAX_RX_PKT_CNT 8 1893 #define HTT_MAX_RX_PKT_CRC_PASS_CNT 8 1894 #define HTT_MAX_PER_BLK_ERR_CNT 20 1895 #define HTT_MAX_RX_OTA_ERR_CNT 14 1896 #define HTT_STATS_MAX_CHAINS 8 1897 #define ATH11K_STATS_MGMT_FRM_TYPE_MAX 16 1898 1899 struct htt_phy_counters_tlv { 1900 /* number of RXTD OFDMA OTA error counts except power surge and drop */ 1901 u32 rx_ofdma_timing_err_cnt; 1902 /* rx_cck_fail_cnt: 1903 * number of cck error counts due to rx reception failure because of 1904 * timing error in cck 1905 */ 1906 u32 rx_cck_fail_cnt; 1907 /* number of times tx abort initiated by mac */ 1908 u32 mactx_abort_cnt; 1909 /* number of times rx abort initiated by mac */ 1910 u32 macrx_abort_cnt; 1911 /* number of times tx abort initiated by phy */ 1912 u32 phytx_abort_cnt; 1913 /* number of times rx abort initiated by phy */ 1914 u32 phyrx_abort_cnt; 1915 /* number of rx deferred count initiated by phy */ 1916 u32 phyrx_defer_abort_cnt; 1917 /* number of sizing events generated at LSTF */ 1918 u32 rx_gain_adj_lstf_event_cnt; 1919 /* number of sizing events generated at non-legacy LTF */ 1920 u32 rx_gain_adj_non_legacy_cnt; 1921 /* rx_pkt_cnt - 1922 * Received EOP (end-of-packet) count per packet type; 1923 * [0] = 11a; [1] = 11b; [2] = 11n; [3] = 11ac; [4] = 11ax; [5] = GF 1924 * [6-7]=RSVD 1925 */ 1926 u32 rx_pkt_cnt[HTT_MAX_RX_PKT_CNT]; 1927 /* rx_pkt_crc_pass_cnt - 1928 * Received EOP (end-of-packet) count per packet type; 1929 * [0] = 11a; [1] = 11b; [2] = 11n; [3] = 11ac; [4] = 11ax; [5] = GF 1930 * [6-7]=RSVD 1931 */ 1932 u32 rx_pkt_crc_pass_cnt[HTT_MAX_RX_PKT_CRC_PASS_CNT]; 1933 /* per_blk_err_cnt - 1934 * Error count per error source; 1935 * [0] = unknown; [1] = LSIG; [2] = HTSIG; [3] = VHTSIG; [4] = HESIG; 1936 * [5] = RXTD_OTA; [6] = RXTD_FATAL; [7] = DEMF; [8] = ROBE; 1937 * [9] = PMI; [10] = TXFD; [11] = TXTD; [12] = PHYRF 1938 * [13-19]=RSVD 1939 */ 1940 u32 per_blk_err_cnt[HTT_MAX_PER_BLK_ERR_CNT]; 1941 /* rx_ota_err_cnt - 1942 * RXTD OTA (over-the-air) error count per error reason; 1943 * [0] = voting fail; [1] = weak det fail; [2] = strong sig fail; 1944 * [3] = cck fail; [4] = power surge; [5] = power drop; 1945 * [6] = btcf timing timeout error; [7] = btcf packet detect error; 1946 * [8] = coarse timing timeout error 1947 * [9-13]=RSVD 1948 */ 1949 u32 rx_ota_err_cnt[HTT_MAX_RX_OTA_ERR_CNT]; 1950 }; 1951 1952 struct htt_phy_stats_tlv { 1953 /* per chain hw noise floor values in dBm */ 1954 s32 nf_chain[HTT_STATS_MAX_CHAINS]; 1955 /* number of false radars detected */ 1956 u32 false_radar_cnt; 1957 /* number of channel switches happened due to radar detection */ 1958 u32 radar_cs_cnt; 1959 /* ani_level - 1960 * ANI level (noise interference) corresponds to the channel 1961 * the desense levels range from -5 to 15 in dB units, 1962 * higher values indicating more noise interference. 1963 */ 1964 s32 ani_level; 1965 /* running time in minutes since FW boot */ 1966 u32 fw_run_time; 1967 }; 1968 1969 struct htt_phy_reset_counters_tlv { 1970 u32 pdev_id; 1971 u32 cf_active_low_fail_cnt; 1972 u32 cf_active_low_pass_cnt; 1973 u32 phy_off_through_vreg_cnt; 1974 u32 force_calibration_cnt; 1975 u32 rf_mode_switch_phy_off_cnt; 1976 }; 1977 1978 struct htt_phy_reset_stats_tlv { 1979 u32 pdev_id; 1980 u32 chan_mhz; 1981 u32 chan_band_center_freq1; 1982 u32 chan_band_center_freq2; 1983 u32 chan_phy_mode; 1984 u32 chan_flags; 1985 u32 chan_num; 1986 u32 reset_cause; 1987 u32 prev_reset_cause; 1988 u32 phy_warm_reset_src; 1989 u32 rx_gain_tbl_mode; 1990 u32 xbar_val; 1991 u32 force_calibration; 1992 u32 phyrf_mode; 1993 u32 phy_homechan; 1994 u32 phy_tx_ch_mask; 1995 u32 phy_rx_ch_mask; 1996 u32 phybb_ini_mask; 1997 u32 phyrf_ini_mask; 1998 u32 phy_dfs_en_mask; 1999 u32 phy_sscan_en_mask; 2000 u32 phy_synth_sel_mask; 2001 u32 phy_adfs_freq; 2002 u32 cck_fir_settings; 2003 u32 phy_dyn_pri_chan; 2004 u32 cca_thresh; 2005 u32 dyn_cca_status; 2006 u32 rxdesense_thresh_hw; 2007 u32 rxdesense_thresh_sw; 2008 }; 2009 2010 struct htt_peer_ctrl_path_txrx_stats_tlv { 2011 /* peer mac address */ 2012 u8 peer_mac_addr[ETH_ALEN]; 2013 u8 rsvd[2]; 2014 /* Num of tx mgmt frames with subtype on peer level */ 2015 u32 peer_tx_mgmt_subtype[ATH11K_STATS_MGMT_FRM_TYPE_MAX]; 2016 /* Num of rx mgmt frames with subtype on peer level */ 2017 u32 peer_rx_mgmt_subtype[ATH11K_STATS_MGMT_FRM_TYPE_MAX]; 2018 }; 2019 2020 #ifdef CONFIG_ATH11K_DEBUGFS 2021 2022 void ath11k_debugfs_htt_stats_init(struct ath11k *ar); 2023 void ath11k_debugfs_htt_ext_stats_handler(struct ath11k_base *ab, 2024 struct sk_buff *skb); 2025 int ath11k_debugfs_htt_stats_req(struct ath11k *ar); 2026 2027 #else /* CONFIG_ATH11K_DEBUGFS */ 2028 2029 static inline void ath11k_debugfs_htt_stats_init(struct ath11k *ar) 2030 { 2031 } 2032 2033 static inline void ath11k_debugfs_htt_ext_stats_handler(struct ath11k_base *ab, 2034 struct sk_buff *skb) 2035 { 2036 } 2037 2038 static inline int ath11k_debugfs_htt_stats_req(struct ath11k *ar) 2039 { 2040 return 0; 2041 } 2042 2043 #endif /* CONFIG_ATH11K_DEBUGFS */ 2044 2045 #endif 2046