1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef DEBUG_HTT_STATS_H 8 #define DEBUG_HTT_STATS_H 9 10 #define HTT_STATS_COOKIE_LSB GENMASK_ULL(31, 0) 11 #define HTT_STATS_COOKIE_MSB GENMASK_ULL(63, 32) 12 #define HTT_STATS_MAGIC_VALUE 0xF0F0F0F0 13 14 enum htt_tlv_tag_t { 15 HTT_STATS_TX_PDEV_CMN_TAG = 0, 16 HTT_STATS_TX_PDEV_UNDERRUN_TAG = 1, 17 HTT_STATS_TX_PDEV_SIFS_TAG = 2, 18 HTT_STATS_TX_PDEV_FLUSH_TAG = 3, 19 HTT_STATS_TX_PDEV_PHY_ERR_TAG = 4, 20 HTT_STATS_STRING_TAG = 5, 21 HTT_STATS_TX_HWQ_CMN_TAG = 6, 22 HTT_STATS_TX_HWQ_DIFS_LATENCY_TAG = 7, 23 HTT_STATS_TX_HWQ_CMD_RESULT_TAG = 8, 24 HTT_STATS_TX_HWQ_CMD_STALL_TAG = 9, 25 HTT_STATS_TX_HWQ_FES_STATUS_TAG = 10, 26 HTT_STATS_TX_TQM_GEN_MPDU_TAG = 11, 27 HTT_STATS_TX_TQM_LIST_MPDU_TAG = 12, 28 HTT_STATS_TX_TQM_LIST_MPDU_CNT_TAG = 13, 29 HTT_STATS_TX_TQM_CMN_TAG = 14, 30 HTT_STATS_TX_TQM_PDEV_TAG = 15, 31 HTT_STATS_TX_TQM_CMDQ_STATUS_TAG = 16, 32 HTT_STATS_TX_DE_EAPOL_PACKETS_TAG = 17, 33 HTT_STATS_TX_DE_CLASSIFY_FAILED_TAG = 18, 34 HTT_STATS_TX_DE_CLASSIFY_STATS_TAG = 19, 35 HTT_STATS_TX_DE_CLASSIFY_STATUS_TAG = 20, 36 HTT_STATS_TX_DE_ENQUEUE_PACKETS_TAG = 21, 37 HTT_STATS_TX_DE_ENQUEUE_DISCARD_TAG = 22, 38 HTT_STATS_TX_DE_CMN_TAG = 23, 39 HTT_STATS_RING_IF_TAG = 24, 40 HTT_STATS_TX_PDEV_MU_MIMO_STATS_TAG = 25, 41 HTT_STATS_SFM_CMN_TAG = 26, 42 HTT_STATS_SRING_STATS_TAG = 27, 43 HTT_STATS_RX_PDEV_FW_STATS_TAG = 28, 44 HTT_STATS_RX_PDEV_FW_RING_MPDU_ERR_TAG = 29, 45 HTT_STATS_RX_PDEV_FW_MPDU_DROP_TAG = 30, 46 HTT_STATS_RX_SOC_FW_STATS_TAG = 31, 47 HTT_STATS_RX_SOC_FW_REFILL_RING_EMPTY_TAG = 32, 48 HTT_STATS_RX_SOC_FW_REFILL_RING_NUM_REFILL_TAG = 33, 49 HTT_STATS_TX_PDEV_RATE_STATS_TAG = 34, 50 HTT_STATS_RX_PDEV_RATE_STATS_TAG = 35, 51 HTT_STATS_TX_PDEV_SCHEDULER_TXQ_STATS_TAG = 36, 52 HTT_STATS_TX_SCHED_CMN_TAG = 37, 53 HTT_STATS_TX_PDEV_MUMIMO_MPDU_STATS_TAG = 38, 54 HTT_STATS_SCHED_TXQ_CMD_POSTED_TAG = 39, 55 HTT_STATS_RING_IF_CMN_TAG = 40, 56 HTT_STATS_SFM_CLIENT_USER_TAG = 41, 57 HTT_STATS_SFM_CLIENT_TAG = 42, 58 HTT_STATS_TX_TQM_ERROR_STATS_TAG = 43, 59 HTT_STATS_SCHED_TXQ_CMD_REAPED_TAG = 44, 60 HTT_STATS_SRING_CMN_TAG = 45, 61 HTT_STATS_TX_SELFGEN_AC_ERR_STATS_TAG = 46, 62 HTT_STATS_TX_SELFGEN_CMN_STATS_TAG = 47, 63 HTT_STATS_TX_SELFGEN_AC_STATS_TAG = 48, 64 HTT_STATS_TX_SELFGEN_AX_STATS_TAG = 49, 65 HTT_STATS_TX_SELFGEN_AX_ERR_STATS_TAG = 50, 66 HTT_STATS_TX_HWQ_MUMIMO_SCH_STATS_TAG = 51, 67 HTT_STATS_TX_HWQ_MUMIMO_MPDU_STATS_TAG = 52, 68 HTT_STATS_TX_HWQ_MUMIMO_CMN_STATS_TAG = 53, 69 HTT_STATS_HW_INTR_MISC_TAG = 54, 70 HTT_STATS_HW_WD_TIMEOUT_TAG = 55, 71 HTT_STATS_HW_PDEV_ERRS_TAG = 56, 72 HTT_STATS_COUNTER_NAME_TAG = 57, 73 HTT_STATS_TX_TID_DETAILS_TAG = 58, 74 HTT_STATS_RX_TID_DETAILS_TAG = 59, 75 HTT_STATS_PEER_STATS_CMN_TAG = 60, 76 HTT_STATS_PEER_DETAILS_TAG = 61, 77 HTT_STATS_PEER_TX_RATE_STATS_TAG = 62, 78 HTT_STATS_PEER_RX_RATE_STATS_TAG = 63, 79 HTT_STATS_PEER_MSDU_FLOWQ_TAG = 64, 80 HTT_STATS_TX_DE_COMPL_STATS_TAG = 65, 81 HTT_STATS_WHAL_TX_TAG = 66, 82 HTT_STATS_TX_PDEV_SIFS_HIST_TAG = 67, 83 HTT_STATS_RX_PDEV_FW_STATS_PHY_ERR_TAG = 68, 84 HTT_STATS_TX_TID_DETAILS_V1_TAG = 69, 85 HTT_STATS_PDEV_CCA_1SEC_HIST_TAG = 70, 86 HTT_STATS_PDEV_CCA_100MSEC_HIST_TAG = 71, 87 HTT_STATS_PDEV_CCA_STAT_CUMULATIVE_TAG = 72, 88 HTT_STATS_PDEV_CCA_COUNTERS_TAG = 73, 89 HTT_STATS_TX_PDEV_MPDU_STATS_TAG = 74, 90 HTT_STATS_PDEV_TWT_SESSIONS_TAG = 75, 91 HTT_STATS_PDEV_TWT_SESSION_TAG = 76, 92 HTT_STATS_RX_REFILL_RXDMA_ERR_TAG = 77, 93 HTT_STATS_RX_REFILL_REO_ERR_TAG = 78, 94 HTT_STATS_RX_REO_RESOURCE_STATS_TAG = 79, 95 HTT_STATS_TX_SOUNDING_STATS_TAG = 80, 96 HTT_STATS_TX_PDEV_TX_PPDU_STATS_TAG = 81, 97 HTT_STATS_TX_PDEV_TRIED_MPDU_CNT_HIST_TAG = 82, 98 HTT_STATS_TX_HWQ_TRIED_MPDU_CNT_HIST_TAG = 83, 99 HTT_STATS_TX_HWQ_TXOP_USED_CNT_HIST_TAG = 84, 100 HTT_STATS_TX_DE_FW2WBM_RING_FULL_HIST_TAG = 85, 101 HTT_STATS_SCHED_TXQ_SCHED_ORDER_SU_TAG = 86, 102 HTT_STATS_SCHED_TXQ_SCHED_INELIGIBILITY_TAG = 87, 103 HTT_STATS_PDEV_OBSS_PD_TAG = 88, 104 HTT_STATS_HW_WAR_TAG = 89, 105 HTT_STATS_RING_BACKPRESSURE_STATS_TAG = 90, 106 HTT_STATS_PEER_CTRL_PATH_TXRX_STATS_TAG = 101, 107 HTT_STATS_PDEV_TX_RATE_TXBF_STATS_TAG = 108, 108 HTT_STATS_TXBF_OFDMA_NDPA_STATS_TAG = 113, 109 HTT_STATS_TXBF_OFDMA_NDP_STATS_TAG = 114, 110 HTT_STATS_TXBF_OFDMA_BRP_STATS_TAG = 115, 111 HTT_STATS_TXBF_OFDMA_STEER_STATS_TAG = 116, 112 HTT_STATS_PHY_COUNTERS_TAG = 121, 113 HTT_STATS_PHY_STATS_TAG = 122, 114 115 HTT_STATS_MAX_TAG, 116 }; 117 118 #define HTT_STATS_MAX_STRING_SZ32 4 119 #define HTT_STATS_MACID_INVALID 0xff 120 #define HTT_TX_HWQ_MAX_DIFS_LATENCY_BINS 10 121 #define HTT_TX_HWQ_MAX_CMD_RESULT_STATS 13 122 #define HTT_TX_HWQ_MAX_CMD_STALL_STATS 5 123 #define HTT_TX_HWQ_MAX_FES_RESULT_STATS 10 124 125 enum htt_tx_pdev_underrun_enum { 126 HTT_STATS_TX_PDEV_NO_DATA_UNDERRUN = 0, 127 HTT_STATS_TX_PDEV_DATA_UNDERRUN_BETWEEN_MPDU = 1, 128 HTT_STATS_TX_PDEV_DATA_UNDERRUN_WITHIN_MPDU = 2, 129 HTT_TX_PDEV_MAX_URRN_STATS = 3, 130 }; 131 132 #define HTT_TX_PDEV_MAX_FLUSH_REASON_STATS 71 133 #define HTT_TX_PDEV_MAX_SIFS_BURST_STATS 9 134 #define HTT_TX_PDEV_MAX_SIFS_BURST_HIST_STATS 10 135 #define HTT_TX_PDEV_MAX_PHY_ERR_STATS 18 136 #define HTT_TX_PDEV_SCHED_TX_MODE_MAX 4 137 #define HTT_TX_PDEV_NUM_SCHED_ORDER_LOG 20 138 139 #define HTT_RX_STATS_REFILL_MAX_RING 4 140 #define HTT_RX_STATS_RXDMA_MAX_ERR 16 141 #define HTT_RX_STATS_FW_DROP_REASON_MAX 16 142 143 /* Bytes stored in little endian order */ 144 /* Length should be multiple of DWORD */ 145 struct htt_stats_string_tlv { 146 /* Can be variable length */ 147 DECLARE_FLEX_ARRAY(u32, data); 148 } __packed; 149 150 #define HTT_STATS_MAC_ID GENMASK(7, 0) 151 152 /* == TX PDEV STATS == */ 153 struct htt_tx_pdev_stats_cmn_tlv { 154 u32 mac_id__word; 155 u32 hw_queued; 156 u32 hw_reaped; 157 u32 underrun; 158 u32 hw_paused; 159 u32 hw_flush; 160 u32 hw_filt; 161 u32 tx_abort; 162 u32 mpdu_requeued; 163 u32 tx_xretry; 164 u32 data_rc; 165 u32 mpdu_dropped_xretry; 166 u32 illgl_rate_phy_err; 167 u32 cont_xretry; 168 u32 tx_timeout; 169 u32 pdev_resets; 170 u32 phy_underrun; 171 u32 txop_ovf; 172 u32 seq_posted; 173 u32 seq_failed_queueing; 174 u32 seq_completed; 175 u32 seq_restarted; 176 u32 mu_seq_posted; 177 u32 seq_switch_hw_paused; 178 u32 next_seq_posted_dsr; 179 u32 seq_posted_isr; 180 u32 seq_ctrl_cached; 181 u32 mpdu_count_tqm; 182 u32 msdu_count_tqm; 183 u32 mpdu_removed_tqm; 184 u32 msdu_removed_tqm; 185 u32 mpdus_sw_flush; 186 u32 mpdus_hw_filter; 187 u32 mpdus_truncated; 188 u32 mpdus_ack_failed; 189 u32 mpdus_expired; 190 u32 mpdus_seq_hw_retry; 191 u32 ack_tlv_proc; 192 u32 coex_abort_mpdu_cnt_valid; 193 u32 coex_abort_mpdu_cnt; 194 u32 num_total_ppdus_tried_ota; 195 u32 num_data_ppdus_tried_ota; 196 u32 local_ctrl_mgmt_enqued; 197 u32 local_ctrl_mgmt_freed; 198 u32 local_data_enqued; 199 u32 local_data_freed; 200 u32 mpdu_tried; 201 u32 isr_wait_seq_posted; 202 203 u32 tx_active_dur_us_low; 204 u32 tx_active_dur_us_high; 205 }; 206 207 /* NOTE: Variable length TLV, use length spec to infer array size */ 208 struct htt_tx_pdev_stats_urrn_tlv_v { 209 /* HTT_TX_PDEV_MAX_URRN_STATS */ 210 DECLARE_FLEX_ARRAY(u32, urrn_stats); 211 }; 212 213 /* NOTE: Variable length TLV, use length spec to infer array size */ 214 struct htt_tx_pdev_stats_flush_tlv_v { 215 /* HTT_TX_PDEV_MAX_FLUSH_REASON_STATS */ 216 DECLARE_FLEX_ARRAY(u32, flush_errs); 217 }; 218 219 /* NOTE: Variable length TLV, use length spec to infer array size */ 220 struct htt_tx_pdev_stats_sifs_tlv_v { 221 /* HTT_TX_PDEV_MAX_SIFS_BURST_STATS */ 222 DECLARE_FLEX_ARRAY(u32, sifs_status); 223 }; 224 225 /* NOTE: Variable length TLV, use length spec to infer array size */ 226 struct htt_tx_pdev_stats_phy_err_tlv_v { 227 /* HTT_TX_PDEV_MAX_PHY_ERR_STATS */ 228 DECLARE_FLEX_ARRAY(u32, phy_errs); 229 }; 230 231 /* NOTE: Variable length TLV, use length spec to infer array size */ 232 struct htt_tx_pdev_stats_sifs_hist_tlv_v { 233 /* HTT_TX_PDEV_SIFS_BURST_HIST_STATS */ 234 DECLARE_FLEX_ARRAY(u32, sifs_hist_status); 235 }; 236 237 struct htt_tx_pdev_stats_tx_ppdu_stats_tlv_v { 238 u32 num_data_ppdus_legacy_su; 239 u32 num_data_ppdus_ac_su; 240 u32 num_data_ppdus_ax_su; 241 u32 num_data_ppdus_ac_su_txbf; 242 u32 num_data_ppdus_ax_su_txbf; 243 }; 244 245 /* NOTE: Variable length TLV, use length spec to infer array size . 246 * 247 * Tried_mpdu_cnt_hist is the histogram of MPDUs tries per HWQ. 248 * The tries here is the count of the MPDUS within a PPDU that the 249 * HW had attempted to transmit on air, for the HWSCH Schedule 250 * command submitted by FW.It is not the retry attempts. 251 * The histogram bins are 0-29, 30-59, 60-89 and so on. The are 252 * 10 bins in this histogram. They are defined in FW using the 253 * following macros 254 * #define WAL_MAX_TRIED_MPDU_CNT_HISTOGRAM 9 255 * #define WAL_TRIED_MPDU_CNT_HISTOGRAM_INTERVAL 30 256 */ 257 struct htt_tx_pdev_stats_tried_mpdu_cnt_hist_tlv_v { 258 u32 hist_bin_size; 259 u32 tried_mpdu_cnt_hist[]; /* HTT_TX_PDEV_TRIED_MPDU_CNT_HIST */ 260 }; 261 262 /* == SOC ERROR STATS == */ 263 264 /* =============== PDEV ERROR STATS ============== */ 265 #define HTT_STATS_MAX_HW_INTR_NAME_LEN 8 266 struct htt_hw_stats_intr_misc_tlv { 267 /* Stored as little endian */ 268 u8 hw_intr_name[HTT_STATS_MAX_HW_INTR_NAME_LEN]; 269 u32 mask; 270 u32 count; 271 }; 272 273 #define HTT_STATS_MAX_HW_MODULE_NAME_LEN 8 274 struct htt_hw_stats_wd_timeout_tlv { 275 /* Stored as little endian */ 276 u8 hw_module_name[HTT_STATS_MAX_HW_MODULE_NAME_LEN]; 277 u32 count; 278 }; 279 280 struct htt_hw_stats_pdev_errs_tlv { 281 u32 mac_id__word; /* BIT [ 7 : 0] : mac_id */ 282 u32 tx_abort; 283 u32 tx_abort_fail_count; 284 u32 rx_abort; 285 u32 rx_abort_fail_count; 286 u32 warm_reset; 287 u32 cold_reset; 288 u32 tx_flush; 289 u32 tx_glb_reset; 290 u32 tx_txq_reset; 291 u32 rx_timeout_reset; 292 }; 293 294 struct htt_hw_stats_whal_tx_tlv { 295 u32 mac_id__word; 296 u32 last_unpause_ppdu_id; 297 u32 hwsch_unpause_wait_tqm_write; 298 u32 hwsch_dummy_tlv_skipped; 299 u32 hwsch_misaligned_offset_received; 300 u32 hwsch_reset_count; 301 u32 hwsch_dev_reset_war; 302 u32 hwsch_delayed_pause; 303 u32 hwsch_long_delayed_pause; 304 u32 sch_rx_ppdu_no_response; 305 u32 sch_selfgen_response; 306 u32 sch_rx_sifs_resp_trigger; 307 }; 308 309 /* ============ PEER STATS ============ */ 310 #define HTT_MSDU_FLOW_STATS_TX_FLOW_NO GENMASK(15, 0) 311 #define HTT_MSDU_FLOW_STATS_TID_NUM GENMASK(19, 16) 312 #define HTT_MSDU_FLOW_STATS_DROP_RULE BIT(20) 313 314 struct htt_msdu_flow_stats_tlv { 315 u32 last_update_timestamp; 316 u32 last_add_timestamp; 317 u32 last_remove_timestamp; 318 u32 total_processed_msdu_count; 319 u32 cur_msdu_count_in_flowq; 320 u32 sw_peer_id; 321 u32 tx_flow_no__tid_num__drop_rule; 322 u32 last_cycle_enqueue_count; 323 u32 last_cycle_dequeue_count; 324 u32 last_cycle_drop_count; 325 u32 current_drop_th; 326 }; 327 328 #define MAX_HTT_TID_NAME 8 329 330 #define HTT_TX_TID_STATS_SW_PEER_ID GENMASK(15, 0) 331 #define HTT_TX_TID_STATS_TID_NUM GENMASK(31, 16) 332 #define HTT_TX_TID_STATS_NUM_SCHED_PENDING GENMASK(7, 0) 333 #define HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ GENMASK(15, 8) 334 335 /* Tidq stats */ 336 struct htt_tx_tid_stats_tlv { 337 /* Stored as little endian */ 338 u8 tid_name[MAX_HTT_TID_NAME]; 339 u32 sw_peer_id__tid_num; 340 u32 num_sched_pending__num_ppdu_in_hwq; 341 u32 tid_flags; 342 u32 hw_queued; 343 u32 hw_reaped; 344 u32 mpdus_hw_filter; 345 346 u32 qdepth_bytes; 347 u32 qdepth_num_msdu; 348 u32 qdepth_num_mpdu; 349 u32 last_scheduled_tsmp; 350 u32 pause_module_id; 351 u32 block_module_id; 352 u32 tid_tx_airtime; 353 }; 354 355 #define HTT_TX_TID_STATS_V1_SW_PEER_ID GENMASK(15, 0) 356 #define HTT_TX_TID_STATS_V1_TID_NUM GENMASK(31, 16) 357 #define HTT_TX_TID_STATS_V1_NUM_SCHED_PENDING GENMASK(7, 0) 358 #define HTT_TX_TID_STATS_V1_NUM_PPDU_IN_HWQ GENMASK(15, 8) 359 360 /* Tidq stats */ 361 struct htt_tx_tid_stats_v1_tlv { 362 /* Stored as little endian */ 363 u8 tid_name[MAX_HTT_TID_NAME]; 364 u32 sw_peer_id__tid_num; 365 u32 num_sched_pending__num_ppdu_in_hwq; 366 u32 tid_flags; 367 u32 max_qdepth_bytes; 368 u32 max_qdepth_n_msdus; 369 u32 rsvd; 370 371 u32 qdepth_bytes; 372 u32 qdepth_num_msdu; 373 u32 qdepth_num_mpdu; 374 u32 last_scheduled_tsmp; 375 u32 pause_module_id; 376 u32 block_module_id; 377 u32 tid_tx_airtime; 378 u32 allow_n_flags; 379 u32 sendn_frms_allowed; 380 }; 381 382 #define HTT_RX_TID_STATS_SW_PEER_ID GENMASK(15, 0) 383 #define HTT_RX_TID_STATS_TID_NUM GENMASK(31, 16) 384 385 struct htt_rx_tid_stats_tlv { 386 u32 sw_peer_id__tid_num; 387 u8 tid_name[MAX_HTT_TID_NAME]; 388 u32 dup_in_reorder; 389 u32 dup_past_outside_window; 390 u32 dup_past_within_window; 391 u32 rxdesc_err_decrypt; 392 u32 tid_rx_airtime; 393 }; 394 395 #define HTT_MAX_COUNTER_NAME 8 396 struct htt_counter_tlv { 397 u8 counter_name[HTT_MAX_COUNTER_NAME]; 398 u32 count; 399 }; 400 401 struct htt_peer_stats_cmn_tlv { 402 u32 ppdu_cnt; 403 u32 mpdu_cnt; 404 u32 msdu_cnt; 405 u32 pause_bitmap; 406 u32 block_bitmap; 407 u32 current_timestamp; 408 u32 peer_tx_airtime; 409 u32 peer_rx_airtime; 410 s32 rssi; 411 u32 peer_enqueued_count_low; 412 u32 peer_enqueued_count_high; 413 u32 peer_dequeued_count_low; 414 u32 peer_dequeued_count_high; 415 u32 peer_dropped_count_low; 416 u32 peer_dropped_count_high; 417 u32 ppdu_transmitted_bytes_low; 418 u32 ppdu_transmitted_bytes_high; 419 u32 peer_ttl_removed_count; 420 u32 inactive_time; 421 }; 422 423 #define HTT_PEER_DETAILS_VDEV_ID GENMASK(7, 0) 424 #define HTT_PEER_DETAILS_PDEV_ID GENMASK(15, 8) 425 #define HTT_PEER_DETAILS_AST_IDX GENMASK(31, 16) 426 427 struct htt_peer_details_tlv { 428 u32 peer_type; 429 u32 sw_peer_id; 430 u32 vdev_pdev_ast_idx; 431 struct htt_mac_addr mac_addr; 432 u32 peer_flags; 433 u32 qpeer_flags; 434 }; 435 436 enum htt_stats_param_type { 437 HTT_STATS_PREAM_OFDM, 438 HTT_STATS_PREAM_CCK, 439 HTT_STATS_PREAM_HT, 440 HTT_STATS_PREAM_VHT, 441 HTT_STATS_PREAM_HE, 442 HTT_STATS_PREAM_RSVD, 443 HTT_STATS_PREAM_RSVD1, 444 445 HTT_STATS_PREAM_COUNT, 446 }; 447 448 #define HTT_TX_PEER_STATS_NUM_MCS_COUNTERS 12 449 #define HTT_TX_PEER_STATS_NUM_GI_COUNTERS 4 450 #define HTT_TX_PEER_STATS_NUM_DCM_COUNTERS 5 451 #define HTT_TX_PEER_STATS_NUM_BW_COUNTERS 4 452 #define HTT_TX_PEER_STATS_NUM_SPATIAL_STREAMS 8 453 #define HTT_TX_PEER_STATS_NUM_PREAMBLE_TYPES HTT_STATS_PREAM_COUNT 454 455 struct htt_tx_peer_rate_stats_tlv { 456 u32 tx_ldpc; 457 u32 rts_cnt; 458 u32 ack_rssi; 459 460 u32 tx_mcs[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS]; 461 u32 tx_su_mcs[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS]; 462 u32 tx_mu_mcs[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS]; 463 /* element 0,1, ...7 -> NSS 1,2, ...8 */ 464 u32 tx_nss[HTT_TX_PEER_STATS_NUM_SPATIAL_STREAMS]; 465 /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */ 466 u32 tx_bw[HTT_TX_PEER_STATS_NUM_BW_COUNTERS]; 467 u32 tx_stbc[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS]; 468 u32 tx_pream[HTT_TX_PEER_STATS_NUM_PREAMBLE_TYPES]; 469 470 /* Counters to track number of tx packets in each GI 471 * (400us, 800us, 1600us & 3200us) in each mcs (0-11) 472 */ 473 u32 tx_gi[HTT_TX_PEER_STATS_NUM_GI_COUNTERS][HTT_TX_PEER_STATS_NUM_MCS_COUNTERS]; 474 475 /* Counters to track packets in dcm mcs (MCS 0, 1, 3, 4) */ 476 u32 tx_dcm[HTT_TX_PEER_STATS_NUM_DCM_COUNTERS]; 477 478 }; 479 480 #define HTT_RX_PEER_STATS_NUM_MCS_COUNTERS 12 481 #define HTT_RX_PEER_STATS_NUM_GI_COUNTERS 4 482 #define HTT_RX_PEER_STATS_NUM_DCM_COUNTERS 5 483 #define HTT_RX_PEER_STATS_NUM_BW_COUNTERS 4 484 #define HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS 8 485 #define HTT_RX_PEER_STATS_NUM_PREAMBLE_TYPES HTT_STATS_PREAM_COUNT 486 487 struct htt_rx_peer_rate_stats_tlv { 488 u32 nsts; 489 490 /* Number of rx ldpc packets */ 491 u32 rx_ldpc; 492 /* Number of rx rts packets */ 493 u32 rts_cnt; 494 495 u32 rssi_mgmt; /* units = dB above noise floor */ 496 u32 rssi_data; /* units = dB above noise floor */ 497 u32 rssi_comb; /* units = dB above noise floor */ 498 u32 rx_mcs[HTT_RX_PEER_STATS_NUM_MCS_COUNTERS]; 499 /* element 0,1, ...7 -> NSS 1,2, ...8 */ 500 u32 rx_nss[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS]; 501 u32 rx_dcm[HTT_RX_PEER_STATS_NUM_DCM_COUNTERS]; 502 u32 rx_stbc[HTT_RX_PEER_STATS_NUM_MCS_COUNTERS]; 503 /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */ 504 u32 rx_bw[HTT_RX_PEER_STATS_NUM_BW_COUNTERS]; 505 u32 rx_pream[HTT_RX_PEER_STATS_NUM_PREAMBLE_TYPES]; 506 /* units = dB above noise floor */ 507 u8 rssi_chain[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS] 508 [HTT_RX_PEER_STATS_NUM_BW_COUNTERS]; 509 510 /* Counters to track number of rx packets in each GI in each mcs (0-11) */ 511 u32 rx_gi[HTT_RX_PEER_STATS_NUM_GI_COUNTERS] 512 [HTT_RX_PEER_STATS_NUM_MCS_COUNTERS]; 513 }; 514 515 enum htt_peer_stats_req_mode { 516 HTT_PEER_STATS_REQ_MODE_NO_QUERY, 517 HTT_PEER_STATS_REQ_MODE_QUERY_TQM, 518 HTT_PEER_STATS_REQ_MODE_FLUSH_TQM, 519 }; 520 521 enum htt_peer_stats_tlv_enum { 522 HTT_PEER_STATS_CMN_TLV = 0, 523 HTT_PEER_DETAILS_TLV = 1, 524 HTT_TX_PEER_RATE_STATS_TLV = 2, 525 HTT_RX_PEER_RATE_STATS_TLV = 3, 526 HTT_TX_TID_STATS_TLV = 4, 527 HTT_RX_TID_STATS_TLV = 5, 528 HTT_MSDU_FLOW_STATS_TLV = 6, 529 530 HTT_PEER_STATS_MAX_TLV = 31, 531 }; 532 533 /* =========== MUMIMO HWQ stats =========== */ 534 /* MU MIMO stats per hwQ */ 535 struct htt_tx_hwq_mu_mimo_sch_stats_tlv { 536 u32 mu_mimo_sch_posted; 537 u32 mu_mimo_sch_failed; 538 u32 mu_mimo_ppdu_posted; 539 }; 540 541 struct htt_tx_hwq_mu_mimo_mpdu_stats_tlv { 542 u32 mu_mimo_mpdus_queued_usr; 543 u32 mu_mimo_mpdus_tried_usr; 544 u32 mu_mimo_mpdus_failed_usr; 545 u32 mu_mimo_mpdus_requeued_usr; 546 u32 mu_mimo_err_no_ba_usr; 547 u32 mu_mimo_mpdu_underrun_usr; 548 u32 mu_mimo_ampdu_underrun_usr; 549 }; 550 551 #define HTT_TX_HWQ_STATS_MAC_ID GENMASK(7, 0) 552 #define HTT_TX_HWQ_STATS_HWQ_ID GENMASK(15, 8) 553 554 struct htt_tx_hwq_mu_mimo_cmn_stats_tlv { 555 u32 mac_id__hwq_id__word; 556 }; 557 558 /* == TX HWQ STATS == */ 559 struct htt_tx_hwq_stats_cmn_tlv { 560 u32 mac_id__hwq_id__word; 561 562 /* PPDU level stats */ 563 u32 xretry; 564 u32 underrun_cnt; 565 u32 flush_cnt; 566 u32 filt_cnt; 567 u32 null_mpdu_bmap; 568 u32 user_ack_failure; 569 u32 ack_tlv_proc; 570 u32 sched_id_proc; 571 u32 null_mpdu_tx_count; 572 u32 mpdu_bmap_not_recvd; 573 574 /* Selfgen stats per hwQ */ 575 u32 num_bar; 576 u32 rts; 577 u32 cts2self; 578 u32 qos_null; 579 580 /* MPDU level stats */ 581 u32 mpdu_tried_cnt; 582 u32 mpdu_queued_cnt; 583 u32 mpdu_ack_fail_cnt; 584 u32 mpdu_filt_cnt; 585 u32 false_mpdu_ack_count; 586 587 u32 txq_timeout; 588 }; 589 590 /* NOTE: Variable length TLV, use length spec to infer array size */ 591 struct htt_tx_hwq_difs_latency_stats_tlv_v { 592 u32 hist_intvl; 593 /* histogram of ppdu post to hwsch - > cmd status received */ 594 u32 difs_latency_hist[]; /* HTT_TX_HWQ_MAX_DIFS_LATENCY_BINS */ 595 }; 596 597 /* NOTE: Variable length TLV, use length spec to infer array size */ 598 struct htt_tx_hwq_cmd_result_stats_tlv_v { 599 /* Histogram of sched cmd result, HTT_TX_HWQ_MAX_CMD_RESULT_STATS */ 600 DECLARE_FLEX_ARRAY(u32, cmd_result); 601 }; 602 603 /* NOTE: Variable length TLV, use length spec to infer array size */ 604 struct htt_tx_hwq_cmd_stall_stats_tlv_v { 605 /* Histogram of various pause conitions, HTT_TX_HWQ_MAX_CMD_STALL_STATS */ 606 DECLARE_FLEX_ARRAY(u32, cmd_stall_status); 607 }; 608 609 /* NOTE: Variable length TLV, use length spec to infer array size */ 610 struct htt_tx_hwq_fes_result_stats_tlv_v { 611 /* Histogram of number of user fes result, HTT_TX_HWQ_MAX_FES_RESULT_STATS */ 612 DECLARE_FLEX_ARRAY(u32, fes_result); 613 }; 614 615 /* NOTE: Variable length TLV, use length spec to infer array size 616 * 617 * The hwq_tried_mpdu_cnt_hist is a histogram of MPDUs tries per HWQ. 618 * The tries here is the count of the MPDUS within a PPDU that the HW 619 * had attempted to transmit on air, for the HWSCH Schedule command 620 * submitted by FW in this HWQ .It is not the retry attempts. The 621 * histogram bins are 0-29, 30-59, 60-89 and so on. The are 10 bins 622 * in this histogram. 623 * they are defined in FW using the following macros 624 * #define WAL_MAX_TRIED_MPDU_CNT_HISTOGRAM 9 625 * #define WAL_TRIED_MPDU_CNT_HISTOGRAM_INTERVAL 30 626 */ 627 struct htt_tx_hwq_tried_mpdu_cnt_hist_tlv_v { 628 u32 hist_bin_size; 629 /* Histogram of number of mpdus on tried mpdu */ 630 u32 tried_mpdu_cnt_hist[]; /* HTT_TX_HWQ_TRIED_MPDU_CNT_HIST */ 631 }; 632 633 /* NOTE: Variable length TLV, use length spec to infer array size 634 * 635 * The txop_used_cnt_hist is the histogram of txop per burst. After 636 * completing the burst, we identify the txop used in the burst and 637 * incr the corresponding bin. 638 * Each bin represents 1ms & we have 10 bins in this histogram. 639 * they are defined in FW using the following macros 640 * #define WAL_MAX_TXOP_USED_CNT_HISTOGRAM 10 641 * #define WAL_TXOP_USED_HISTOGRAM_INTERVAL 1000 ( 1 ms ) 642 */ 643 struct htt_tx_hwq_txop_used_cnt_hist_tlv_v { 644 /* Histogram of txop used cnt, HTT_TX_HWQ_TXOP_USED_CNT_HIST */ 645 DECLARE_FLEX_ARRAY(u32, txop_used_cnt_hist); 646 }; 647 648 /* == TX SELFGEN STATS == */ 649 struct htt_tx_selfgen_cmn_stats_tlv { 650 u32 mac_id__word; 651 u32 su_bar; 652 u32 rts; 653 u32 cts2self; 654 u32 qos_null; 655 u32 delayed_bar_1; /* MU user 1 */ 656 u32 delayed_bar_2; /* MU user 2 */ 657 u32 delayed_bar_3; /* MU user 3 */ 658 u32 delayed_bar_4; /* MU user 4 */ 659 u32 delayed_bar_5; /* MU user 5 */ 660 u32 delayed_bar_6; /* MU user 6 */ 661 u32 delayed_bar_7; /* MU user 7 */ 662 }; 663 664 struct htt_tx_selfgen_ac_stats_tlv { 665 /* 11AC */ 666 u32 ac_su_ndpa; 667 u32 ac_su_ndp; 668 u32 ac_mu_mimo_ndpa; 669 u32 ac_mu_mimo_ndp; 670 u32 ac_mu_mimo_brpoll_1; /* MU user 1 */ 671 u32 ac_mu_mimo_brpoll_2; /* MU user 2 */ 672 u32 ac_mu_mimo_brpoll_3; /* MU user 3 */ 673 }; 674 675 struct htt_tx_selfgen_ax_stats_tlv { 676 /* 11AX */ 677 u32 ax_su_ndpa; 678 u32 ax_su_ndp; 679 u32 ax_mu_mimo_ndpa; 680 u32 ax_mu_mimo_ndp; 681 u32 ax_mu_mimo_brpoll_1; /* MU user 1 */ 682 u32 ax_mu_mimo_brpoll_2; /* MU user 2 */ 683 u32 ax_mu_mimo_brpoll_3; /* MU user 3 */ 684 u32 ax_mu_mimo_brpoll_4; /* MU user 4 */ 685 u32 ax_mu_mimo_brpoll_5; /* MU user 5 */ 686 u32 ax_mu_mimo_brpoll_6; /* MU user 6 */ 687 u32 ax_mu_mimo_brpoll_7; /* MU user 7 */ 688 u32 ax_basic_trigger; 689 u32 ax_bsr_trigger; 690 u32 ax_mu_bar_trigger; 691 u32 ax_mu_rts_trigger; 692 u32 ax_ulmumimo_trigger; 693 }; 694 695 struct htt_tx_selfgen_ac_err_stats_tlv { 696 /* 11AC error stats */ 697 u32 ac_su_ndp_err; 698 u32 ac_su_ndpa_err; 699 u32 ac_mu_mimo_ndpa_err; 700 u32 ac_mu_mimo_ndp_err; 701 u32 ac_mu_mimo_brp1_err; 702 u32 ac_mu_mimo_brp2_err; 703 u32 ac_mu_mimo_brp3_err; 704 }; 705 706 struct htt_tx_selfgen_ax_err_stats_tlv { 707 /* 11AX error stats */ 708 u32 ax_su_ndp_err; 709 u32 ax_su_ndpa_err; 710 u32 ax_mu_mimo_ndpa_err; 711 u32 ax_mu_mimo_ndp_err; 712 u32 ax_mu_mimo_brp1_err; 713 u32 ax_mu_mimo_brp2_err; 714 u32 ax_mu_mimo_brp3_err; 715 u32 ax_mu_mimo_brp4_err; 716 u32 ax_mu_mimo_brp5_err; 717 u32 ax_mu_mimo_brp6_err; 718 u32 ax_mu_mimo_brp7_err; 719 u32 ax_basic_trigger_err; 720 u32 ax_bsr_trigger_err; 721 u32 ax_mu_bar_trigger_err; 722 u32 ax_mu_rts_trigger_err; 723 u32 ax_ulmumimo_trigger_err; 724 }; 725 726 /* == TX MU STATS == */ 727 #define HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS 4 728 #define HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS 8 729 #define HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS 74 730 #define HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS 8 731 732 struct htt_tx_pdev_mu_mimo_sch_stats_tlv { 733 /* mu-mimo sw sched cmd stats */ 734 u32 mu_mimo_sch_posted; 735 u32 mu_mimo_sch_failed; 736 /* MU PPDU stats per hwQ */ 737 u32 mu_mimo_ppdu_posted; 738 /* 739 * Counts the number of users in each transmission of 740 * the given TX mode. 741 * 742 * Index is the number of users - 1. 743 */ 744 u32 ac_mu_mimo_sch_nusers[HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS]; 745 u32 ax_mu_mimo_sch_nusers[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS]; 746 u32 ax_ofdma_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 747 u32 ax_ul_ofdma_basic_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 748 u32 ax_ul_ofdma_bsr_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 749 u32 ax_ul_ofdma_bar_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 750 u32 ax_ul_ofdma_brp_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 751 752 /* UL MU-MIMO */ 753 /* ax_ul_mumimo_basic_sch_nusers[i] is the number of basic triggers sent 754 * for (i+1) users 755 */ 756 u32 ax_ul_mumimo_basic_sch_nusers[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS]; 757 758 /* ax_ul_mumimo_brp_sch_nusers[i] is the number of brp triggers sent 759 * for (i+1) users 760 */ 761 u32 ax_ul_mumimo_brp_sch_nusers[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS]; 762 763 u32 ac_mu_mimo_sch_posted_per_grp_sz[HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS]; 764 u32 ax_mu_mimo_sch_posted_per_grp_sz[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS]; 765 }; 766 767 struct htt_tx_pdev_mu_mimo_mpdu_stats_tlv { 768 u32 mu_mimo_mpdus_queued_usr; 769 u32 mu_mimo_mpdus_tried_usr; 770 u32 mu_mimo_mpdus_failed_usr; 771 u32 mu_mimo_mpdus_requeued_usr; 772 u32 mu_mimo_err_no_ba_usr; 773 u32 mu_mimo_mpdu_underrun_usr; 774 u32 mu_mimo_ampdu_underrun_usr; 775 776 u32 ax_mu_mimo_mpdus_queued_usr; 777 u32 ax_mu_mimo_mpdus_tried_usr; 778 u32 ax_mu_mimo_mpdus_failed_usr; 779 u32 ax_mu_mimo_mpdus_requeued_usr; 780 u32 ax_mu_mimo_err_no_ba_usr; 781 u32 ax_mu_mimo_mpdu_underrun_usr; 782 u32 ax_mu_mimo_ampdu_underrun_usr; 783 784 u32 ax_ofdma_mpdus_queued_usr; 785 u32 ax_ofdma_mpdus_tried_usr; 786 u32 ax_ofdma_mpdus_failed_usr; 787 u32 ax_ofdma_mpdus_requeued_usr; 788 u32 ax_ofdma_err_no_ba_usr; 789 u32 ax_ofdma_mpdu_underrun_usr; 790 u32 ax_ofdma_ampdu_underrun_usr; 791 }; 792 793 #define HTT_STATS_TX_SCHED_MODE_MU_MIMO_AC 1 794 #define HTT_STATS_TX_SCHED_MODE_MU_MIMO_AX 2 795 #define HTT_STATS_TX_SCHED_MODE_MU_OFDMA_AX 3 796 797 struct htt_tx_pdev_mpdu_stats_tlv { 798 /* mpdu level stats */ 799 u32 mpdus_queued_usr; 800 u32 mpdus_tried_usr; 801 u32 mpdus_failed_usr; 802 u32 mpdus_requeued_usr; 803 u32 err_no_ba_usr; 804 u32 mpdu_underrun_usr; 805 u32 ampdu_underrun_usr; 806 u32 user_index; 807 u32 tx_sched_mode; /* HTT_STATS_TX_SCHED_MODE_xxx */ 808 }; 809 810 /* == TX SCHED STATS == */ 811 /* NOTE: Variable length TLV, use length spec to infer array size */ 812 struct htt_sched_txq_cmd_posted_tlv_v { 813 /* HTT_TX_PDEV_SCHED_TX_MODE_MAX */ 814 DECLARE_FLEX_ARRAY(u32, sched_cmd_posted); 815 }; 816 817 /* NOTE: Variable length TLV, use length spec to infer array size */ 818 struct htt_sched_txq_cmd_reaped_tlv_v { 819 /* HTT_TX_PDEV_SCHED_TX_MODE_MAX */ 820 DECLARE_FLEX_ARRAY(u32, sched_cmd_reaped); 821 }; 822 823 /* NOTE: Variable length TLV, use length spec to infer array size */ 824 struct htt_sched_txq_sched_order_su_tlv_v { 825 /* HTT_TX_PDEV_NUM_SCHED_ORDER_LOG */ 826 DECLARE_FLEX_ARRAY(u32, sched_order_su); 827 }; 828 829 enum htt_sched_txq_sched_ineligibility_tlv_enum { 830 HTT_SCHED_TID_SKIP_SCHED_MASK_DISABLED = 0, 831 HTT_SCHED_TID_SKIP_NOTIFY_MPDU, 832 HTT_SCHED_TID_SKIP_MPDU_STATE_INVALID, 833 HTT_SCHED_TID_SKIP_SCHED_DISABLED, 834 HTT_SCHED_TID_SKIP_TQM_BYPASS_CMD_PENDING, 835 HTT_SCHED_TID_SKIP_SECOND_SU_SCHEDULE, 836 837 HTT_SCHED_TID_SKIP_CMD_SLOT_NOT_AVAIL, 838 HTT_SCHED_TID_SKIP_NO_ENQ, 839 HTT_SCHED_TID_SKIP_LOW_ENQ, 840 HTT_SCHED_TID_SKIP_PAUSED, 841 HTT_SCHED_TID_SKIP_UL, 842 HTT_SCHED_TID_REMOVE_PAUSED, 843 HTT_SCHED_TID_REMOVE_NO_ENQ, 844 HTT_SCHED_TID_REMOVE_UL, 845 HTT_SCHED_TID_QUERY, 846 HTT_SCHED_TID_SU_ONLY, 847 HTT_SCHED_TID_ELIGIBLE, 848 HTT_SCHED_INELIGIBILITY_MAX, 849 }; 850 851 /* NOTE: Variable length TLV, use length spec to infer array size */ 852 struct htt_sched_txq_sched_ineligibility_tlv_v { 853 /* indexed by htt_sched_txq_sched_ineligibility_tlv_enum */ 854 DECLARE_FLEX_ARRAY(u32, sched_ineligibility); 855 }; 856 857 #define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID GENMASK(7, 0) 858 #define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_ID GENMASK(15, 8) 859 860 struct htt_tx_pdev_stats_sched_per_txq_tlv { 861 u32 mac_id__txq_id__word; 862 u32 sched_policy; 863 u32 last_sched_cmd_posted_timestamp; 864 u32 last_sched_cmd_compl_timestamp; 865 u32 sched_2_tac_lwm_count; 866 u32 sched_2_tac_ring_full; 867 u32 sched_cmd_post_failure; 868 u32 num_active_tids; 869 u32 num_ps_schedules; 870 u32 sched_cmds_pending; 871 u32 num_tid_register; 872 u32 num_tid_unregister; 873 u32 num_qstats_queried; 874 u32 qstats_update_pending; 875 u32 last_qstats_query_timestamp; 876 u32 num_tqm_cmdq_full; 877 u32 num_de_sched_algo_trigger; 878 u32 num_rt_sched_algo_trigger; 879 u32 num_tqm_sched_algo_trigger; 880 u32 notify_sched; 881 u32 dur_based_sendn_term; 882 }; 883 884 struct htt_stats_tx_sched_cmn_tlv { 885 /* BIT [ 7 : 0] :- mac_id 886 * BIT [31 : 8] :- reserved 887 */ 888 u32 mac_id__word; 889 /* Current timestamp */ 890 u32 current_timestamp; 891 }; 892 893 /* == TQM STATS == */ 894 #define HTT_TX_TQM_MAX_GEN_MPDU_END_REASON 16 895 #define HTT_TX_TQM_MAX_LIST_MPDU_END_REASON 16 896 #define HTT_TX_TQM_MAX_LIST_MPDU_CNT_HISTOGRAM_BINS 16 897 898 /* NOTE: Variable length TLV, use length spec to infer array size */ 899 struct htt_tx_tqm_gen_mpdu_stats_tlv_v { 900 /* HTT_TX_TQM_MAX_GEN_MPDU_END_REASON */ 901 DECLARE_FLEX_ARRAY(u32, gen_mpdu_end_reason); 902 }; 903 904 /* NOTE: Variable length TLV, use length spec to infer array size */ 905 struct htt_tx_tqm_list_mpdu_stats_tlv_v { 906 /* HTT_TX_TQM_MAX_LIST_MPDU_END_REASON */ 907 DECLARE_FLEX_ARRAY(u32, list_mpdu_end_reason); 908 }; 909 910 /* NOTE: Variable length TLV, use length spec to infer array size */ 911 struct htt_tx_tqm_list_mpdu_cnt_tlv_v { 912 /* HTT_TX_TQM_MAX_LIST_MPDU_CNT_HISTOGRAM_BINS */ 913 DECLARE_FLEX_ARRAY(u32, list_mpdu_cnt_hist); 914 }; 915 916 struct htt_tx_tqm_pdev_stats_tlv_v { 917 u32 msdu_count; 918 u32 mpdu_count; 919 u32 remove_msdu; 920 u32 remove_mpdu; 921 u32 remove_msdu_ttl; 922 u32 send_bar; 923 u32 bar_sync; 924 u32 notify_mpdu; 925 u32 sync_cmd; 926 u32 write_cmd; 927 u32 hwsch_trigger; 928 u32 ack_tlv_proc; 929 u32 gen_mpdu_cmd; 930 u32 gen_list_cmd; 931 u32 remove_mpdu_cmd; 932 u32 remove_mpdu_tried_cmd; 933 u32 mpdu_queue_stats_cmd; 934 u32 mpdu_head_info_cmd; 935 u32 msdu_flow_stats_cmd; 936 u32 remove_msdu_cmd; 937 u32 remove_msdu_ttl_cmd; 938 u32 flush_cache_cmd; 939 u32 update_mpduq_cmd; 940 u32 enqueue; 941 u32 enqueue_notify; 942 u32 notify_mpdu_at_head; 943 u32 notify_mpdu_state_valid; 944 /* 945 * On receiving TQM_FLOW_NOT_EMPTY_STATUS from TQM, (on MSDUs being enqueued 946 * the flow is non empty), if the number of MSDUs is greater than the threshold, 947 * notify is incremented. UDP_THRESH counters are for UDP MSDUs, and NONUDP are 948 * for non-UDP MSDUs. 949 * MSDUQ_SWNOTIFY_UDP_THRESH1 threshold - sched_udp_notify1 is incremented 950 * MSDUQ_SWNOTIFY_UDP_THRESH2 threshold - sched_udp_notify2 is incremented 951 * MSDUQ_SWNOTIFY_NONUDP_THRESH1 threshold - sched_nonudp_notify1 is incremented 952 * MSDUQ_SWNOTIFY_NONUDP_THRESH2 threshold - sched_nonudp_notify2 is incremented 953 * 954 * Notify signifies that we trigger the scheduler. 955 */ 956 u32 sched_udp_notify1; 957 u32 sched_udp_notify2; 958 u32 sched_nonudp_notify1; 959 u32 sched_nonudp_notify2; 960 }; 961 962 struct htt_tx_tqm_cmn_stats_tlv { 963 u32 mac_id__word; 964 u32 max_cmdq_id; 965 u32 list_mpdu_cnt_hist_intvl; 966 967 /* Global stats */ 968 u32 add_msdu; 969 u32 q_empty; 970 u32 q_not_empty; 971 u32 drop_notification; 972 u32 desc_threshold; 973 }; 974 975 struct htt_tx_tqm_error_stats_tlv { 976 /* Error stats */ 977 u32 q_empty_failure; 978 u32 q_not_empty_failure; 979 u32 add_msdu_failure; 980 }; 981 982 /* == TQM CMDQ stats == */ 983 #define HTT_TX_TQM_CMDQ_STATUS_MAC_ID GENMASK(7, 0) 984 #define HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID GENMASK(15, 8) 985 986 struct htt_tx_tqm_cmdq_status_tlv { 987 u32 mac_id__cmdq_id__word; 988 u32 sync_cmd; 989 u32 write_cmd; 990 u32 gen_mpdu_cmd; 991 u32 mpdu_queue_stats_cmd; 992 u32 mpdu_head_info_cmd; 993 u32 msdu_flow_stats_cmd; 994 u32 remove_mpdu_cmd; 995 u32 remove_msdu_cmd; 996 u32 flush_cache_cmd; 997 u32 update_mpduq_cmd; 998 u32 update_msduq_cmd; 999 }; 1000 1001 /* == TX-DE STATS == */ 1002 /* Structures for tx de stats */ 1003 struct htt_tx_de_eapol_packets_stats_tlv { 1004 u32 m1_packets; 1005 u32 m2_packets; 1006 u32 m3_packets; 1007 u32 m4_packets; 1008 u32 g1_packets; 1009 u32 g2_packets; 1010 }; 1011 1012 struct htt_tx_de_classify_failed_stats_tlv { 1013 u32 ap_bss_peer_not_found; 1014 u32 ap_bcast_mcast_no_peer; 1015 u32 sta_delete_in_progress; 1016 u32 ibss_no_bss_peer; 1017 u32 invalid_vdev_type; 1018 u32 invalid_ast_peer_entry; 1019 u32 peer_entry_invalid; 1020 u32 ethertype_not_ip; 1021 u32 eapol_lookup_failed; 1022 u32 qpeer_not_allow_data; 1023 u32 fse_tid_override; 1024 u32 ipv6_jumbogram_zero_length; 1025 u32 qos_to_non_qos_in_prog; 1026 }; 1027 1028 struct htt_tx_de_classify_stats_tlv { 1029 u32 arp_packets; 1030 u32 igmp_packets; 1031 u32 dhcp_packets; 1032 u32 host_inspected; 1033 u32 htt_included; 1034 u32 htt_valid_mcs; 1035 u32 htt_valid_nss; 1036 u32 htt_valid_preamble_type; 1037 u32 htt_valid_chainmask; 1038 u32 htt_valid_guard_interval; 1039 u32 htt_valid_retries; 1040 u32 htt_valid_bw_info; 1041 u32 htt_valid_power; 1042 u32 htt_valid_key_flags; 1043 u32 htt_valid_no_encryption; 1044 u32 fse_entry_count; 1045 u32 fse_priority_be; 1046 u32 fse_priority_high; 1047 u32 fse_priority_low; 1048 u32 fse_traffic_ptrn_be; 1049 u32 fse_traffic_ptrn_over_sub; 1050 u32 fse_traffic_ptrn_bursty; 1051 u32 fse_traffic_ptrn_interactive; 1052 u32 fse_traffic_ptrn_periodic; 1053 u32 fse_hwqueue_alloc; 1054 u32 fse_hwqueue_created; 1055 u32 fse_hwqueue_send_to_host; 1056 u32 mcast_entry; 1057 u32 bcast_entry; 1058 u32 htt_update_peer_cache; 1059 u32 htt_learning_frame; 1060 u32 fse_invalid_peer; 1061 /* 1062 * mec_notify is HTT TX WBM multicast echo check notification 1063 * from firmware to host. FW sends SA addresses to host for all 1064 * multicast/broadcast packets received on STA side. 1065 */ 1066 u32 mec_notify; 1067 }; 1068 1069 struct htt_tx_de_classify_status_stats_tlv { 1070 u32 eok; 1071 u32 classify_done; 1072 u32 lookup_failed; 1073 u32 send_host_dhcp; 1074 u32 send_host_mcast; 1075 u32 send_host_unknown_dest; 1076 u32 send_host; 1077 u32 status_invalid; 1078 }; 1079 1080 struct htt_tx_de_enqueue_packets_stats_tlv { 1081 u32 enqueued_pkts; 1082 u32 to_tqm; 1083 u32 to_tqm_bypass; 1084 }; 1085 1086 struct htt_tx_de_enqueue_discard_stats_tlv { 1087 u32 discarded_pkts; 1088 u32 local_frames; 1089 u32 is_ext_msdu; 1090 }; 1091 1092 struct htt_tx_de_compl_stats_tlv { 1093 u32 tcl_dummy_frame; 1094 u32 tqm_dummy_frame; 1095 u32 tqm_notify_frame; 1096 u32 fw2wbm_enq; 1097 u32 tqm_bypass_frame; 1098 }; 1099 1100 /* 1101 * The htt_tx_de_fw2wbm_ring_full_hist_tlv is a histogram of time we waited 1102 * for the fw2wbm ring buffer. we are requesting a buffer in FW2WBM release 1103 * ring,which may fail, due to non availability of buffer. Hence we sleep for 1104 * 200us & again request for it. This is a histogram of time we wait, with 1105 * bin of 200ms & there are 10 bin (2 seconds max) 1106 * They are defined by the following macros in FW 1107 * #define ENTRIES_PER_BIN_COUNT 1000 // per bin 1000 * 200us = 200ms 1108 * #define RING_FULL_BIN_ENTRIES (WAL_TX_DE_FW2WBM_ALLOC_TIMEOUT_COUNT / 1109 * ENTRIES_PER_BIN_COUNT) 1110 */ 1111 struct htt_tx_de_fw2wbm_ring_full_hist_tlv { 1112 DECLARE_FLEX_ARRAY(u32, fw2wbm_ring_full_hist); 1113 }; 1114 1115 struct htt_tx_de_cmn_stats_tlv { 1116 u32 mac_id__word; 1117 1118 /* Global Stats */ 1119 u32 tcl2fw_entry_count; 1120 u32 not_to_fw; 1121 u32 invalid_pdev_vdev_peer; 1122 u32 tcl_res_invalid_addrx; 1123 u32 wbm2fw_entry_count; 1124 u32 invalid_pdev; 1125 }; 1126 1127 /* == RING-IF STATS == */ 1128 #define HTT_STATS_LOW_WM_BINS 5 1129 #define HTT_STATS_HIGH_WM_BINS 5 1130 1131 #define HTT_RING_IF_STATS_NUM_ELEMS GENMASK(15, 0) 1132 #define HTT_RING_IF_STATS_PREFETCH_TAIL_INDEX GENMASK(31, 16) 1133 #define HTT_RING_IF_STATS_HEAD_IDX GENMASK(15, 0) 1134 #define HTT_RING_IF_STATS_TAIL_IDX GENMASK(31, 16) 1135 #define HTT_RING_IF_STATS_SHADOW_HEAD_IDX GENMASK(15, 0) 1136 #define HTT_RING_IF_STATS_SHADOW_TAIL_IDX GENMASK(31, 16) 1137 #define HTT_RING_IF_STATS_LWM_THRESH GENMASK(15, 0) 1138 #define HTT_RING_IF_STATS_HWM_THRESH GENMASK(31, 16) 1139 1140 struct htt_ring_if_stats_tlv { 1141 u32 base_addr; /* DWORD aligned base memory address of the ring */ 1142 u32 elem_size; 1143 u32 num_elems__prefetch_tail_idx; 1144 u32 head_idx__tail_idx; 1145 u32 shadow_head_idx__shadow_tail_idx; 1146 u32 num_tail_incr; 1147 u32 lwm_thresh__hwm_thresh; 1148 u32 overrun_hit_count; 1149 u32 underrun_hit_count; 1150 u32 prod_blockwait_count; 1151 u32 cons_blockwait_count; 1152 u32 low_wm_hit_count[HTT_STATS_LOW_WM_BINS]; 1153 u32 high_wm_hit_count[HTT_STATS_HIGH_WM_BINS]; 1154 }; 1155 1156 struct htt_ring_if_cmn_tlv { 1157 u32 mac_id__word; 1158 u32 num_records; 1159 }; 1160 1161 /* == SFM STATS == */ 1162 /* NOTE: Variable length TLV, use length spec to infer array size */ 1163 struct htt_sfm_client_user_tlv_v { 1164 /* Number of DWORDS used per user and per client */ 1165 DECLARE_FLEX_ARRAY(u32, dwords_used_by_user_n); 1166 }; 1167 1168 struct htt_sfm_client_tlv { 1169 /* Client ID */ 1170 u32 client_id; 1171 /* Minimum number of buffers */ 1172 u32 buf_min; 1173 /* Maximum number of buffers */ 1174 u32 buf_max; 1175 /* Number of Busy buffers */ 1176 u32 buf_busy; 1177 /* Number of Allocated buffers */ 1178 u32 buf_alloc; 1179 /* Number of Available/Usable buffers */ 1180 u32 buf_avail; 1181 /* Number of users */ 1182 u32 num_users; 1183 }; 1184 1185 struct htt_sfm_cmn_tlv { 1186 u32 mac_id__word; 1187 /* Indicates the total number of 128 byte buffers 1188 * in the CMEM that are available for buffer sharing 1189 */ 1190 u32 buf_total; 1191 /* Indicates for certain client or all the clients 1192 * there is no dowrd saved in SFM, refer to SFM_R1_MEM_EMPTY 1193 */ 1194 u32 mem_empty; 1195 /* DEALLOCATE_BUFFERS, refer to register SFM_R0_DEALLOCATE_BUFFERS */ 1196 u32 deallocate_bufs; 1197 /* Number of Records */ 1198 u32 num_records; 1199 }; 1200 1201 /* == SRNG STATS == */ 1202 #define HTT_SRING_STATS_MAC_ID GENMASK(7, 0) 1203 #define HTT_SRING_STATS_RING_ID GENMASK(15, 8) 1204 #define HTT_SRING_STATS_ARENA GENMASK(23, 16) 1205 #define HTT_SRING_STATS_EP BIT(24) 1206 #define HTT_SRING_STATS_NUM_AVAIL_WORDS GENMASK(15, 0) 1207 #define HTT_SRING_STATS_NUM_VALID_WORDS GENMASK(31, 16) 1208 #define HTT_SRING_STATS_HEAD_PTR GENMASK(15, 0) 1209 #define HTT_SRING_STATS_TAIL_PTR GENMASK(31, 16) 1210 #define HTT_SRING_STATS_CONSUMER_EMPTY GENMASK(15, 0) 1211 #define HTT_SRING_STATS_PRODUCER_FULL GENMASK(31, 16) 1212 #define HTT_SRING_STATS_PREFETCH_COUNT GENMASK(15, 0) 1213 #define HTT_SRING_STATS_INTERNAL_TAIL_PTR GENMASK(31, 16) 1214 1215 struct htt_sring_stats_tlv { 1216 u32 mac_id__ring_id__arena__ep; 1217 u32 base_addr_lsb; /* DWORD aligned base memory address of the ring */ 1218 u32 base_addr_msb; 1219 u32 ring_size; 1220 u32 elem_size; 1221 1222 u32 num_avail_words__num_valid_words; 1223 u32 head_ptr__tail_ptr; 1224 u32 consumer_empty__producer_full; 1225 u32 prefetch_count__internal_tail_ptr; 1226 }; 1227 1228 struct htt_sring_cmn_tlv { 1229 u32 num_records; 1230 }; 1231 1232 /* == PDEV TX RATE CTRL STATS == */ 1233 #define HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS 12 1234 #define HTT_TX_PDEV_STATS_NUM_GI_COUNTERS 4 1235 #define HTT_TX_PDEV_STATS_NUM_DCM_COUNTERS 5 1236 #define HTT_TX_PDEV_STATS_NUM_BW_COUNTERS 4 1237 #define HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS 8 1238 #define HTT_TX_PDEV_STATS_NUM_PREAMBLE_TYPES HTT_STATS_PREAM_COUNT 1239 #define HTT_TX_PDEV_STATS_NUM_LEGACY_CCK_STATS 4 1240 #define HTT_TX_PDEV_STATS_NUM_LEGACY_OFDM_STATS 8 1241 #define HTT_TX_PDEV_STATS_NUM_LTF 4 1242 1243 #define HTT_TX_NUM_OF_SOUNDING_STATS_WORDS \ 1244 (HTT_TX_PDEV_STATS_NUM_BW_COUNTERS * \ 1245 HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS) 1246 1247 struct htt_tx_pdev_rate_stats_tlv { 1248 u32 mac_id__word; 1249 u32 tx_ldpc; 1250 u32 rts_cnt; 1251 /* RSSI value of last ack packet (units = dB above noise floor) */ 1252 u32 ack_rssi; 1253 1254 u32 tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 1255 1256 u32 tx_su_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 1257 u32 tx_mu_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 1258 1259 /* element 0,1, ...7 -> NSS 1,2, ...8 */ 1260 u32 tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1261 /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */ 1262 u32 tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 1263 u32 tx_stbc[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 1264 u32 tx_pream[HTT_TX_PDEV_STATS_NUM_PREAMBLE_TYPES]; 1265 1266 /* Counters to track number of tx packets 1267 * in each GI (400us, 800us, 1600us & 3200us) in each mcs (0-11) 1268 */ 1269 u32 tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 1270 1271 /* Counters to track packets in dcm mcs (MCS 0, 1, 3, 4) */ 1272 u32 tx_dcm[HTT_TX_PDEV_STATS_NUM_DCM_COUNTERS]; 1273 /* Number of CTS-acknowledged RTS packets */ 1274 u32 rts_success; 1275 1276 /* 1277 * Counters for legacy 11a and 11b transmissions. 1278 * 1279 * The index corresponds to: 1280 * 1281 * CCK: 0: 1 Mbps, 1: 2 Mbps, 2: 5.5 Mbps, 3: 11 Mbps 1282 * 1283 * OFDM: 0: 6 Mbps, 1: 9 Mbps, 2: 12 Mbps, 3: 18 Mbps, 1284 * 4: 24 Mbps, 5: 36 Mbps, 6: 48 Mbps, 7: 54 Mbps 1285 */ 1286 u32 tx_legacy_cck_rate[HTT_TX_PDEV_STATS_NUM_LEGACY_CCK_STATS]; 1287 u32 tx_legacy_ofdm_rate[HTT_TX_PDEV_STATS_NUM_LEGACY_OFDM_STATS]; 1288 1289 u32 ac_mu_mimo_tx_ldpc; 1290 u32 ax_mu_mimo_tx_ldpc; 1291 u32 ofdma_tx_ldpc; 1292 1293 /* 1294 * Counters for 11ax HE LTF selection during TX. 1295 * 1296 * The index corresponds to: 1297 * 1298 * 0: unused, 1: 1x LTF, 2: 2x LTF, 3: 4x LTF 1299 */ 1300 u32 tx_he_ltf[HTT_TX_PDEV_STATS_NUM_LTF]; 1301 1302 u32 ac_mu_mimo_tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 1303 u32 ax_mu_mimo_tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 1304 u32 ofdma_tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 1305 1306 u32 ac_mu_mimo_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1307 u32 ax_mu_mimo_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1308 u32 ofdma_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1309 1310 u32 ac_mu_mimo_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 1311 u32 ax_mu_mimo_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 1312 u32 ofdma_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 1313 1314 u32 ac_mu_mimo_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] 1315 [HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 1316 u32 ax_mu_mimo_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] 1317 [HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 1318 u32 ofdma_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] 1319 [HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 1320 }; 1321 1322 /* == PDEV RX RATE CTRL STATS == */ 1323 #define HTT_RX_PDEV_STATS_NUM_LEGACY_CCK_STATS 4 1324 #define HTT_RX_PDEV_STATS_NUM_LEGACY_OFDM_STATS 8 1325 #define HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS 12 1326 #define HTT_RX_PDEV_STATS_NUM_GI_COUNTERS 4 1327 #define HTT_RX_PDEV_STATS_NUM_DCM_COUNTERS 5 1328 #define HTT_RX_PDEV_STATS_NUM_BW_COUNTERS 4 1329 #define HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS 8 1330 #define HTT_RX_PDEV_STATS_NUM_PREAMBLE_TYPES HTT_STATS_PREAM_COUNT 1331 #define HTT_RX_PDEV_MAX_OFDMA_NUM_USER 8 1332 #define HTT_RX_PDEV_STATS_RXEVM_MAX_PILOTS_PER_NSS 16 1333 #define HTT_RX_PDEV_STATS_NUM_RU_SIZE_COUNTERS 6 1334 #define HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER 8 1335 1336 struct htt_rx_pdev_rate_stats_tlv { 1337 u32 mac_id__word; 1338 u32 nsts; 1339 1340 u32 rx_ldpc; 1341 u32 rts_cnt; 1342 1343 u32 rssi_mgmt; /* units = dB above noise floor */ 1344 u32 rssi_data; /* units = dB above noise floor */ 1345 u32 rssi_comb; /* units = dB above noise floor */ 1346 u32 rx_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 1347 /* element 0,1, ...7 -> NSS 1,2, ...8 */ 1348 u32 rx_nss[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1349 u32 rx_dcm[HTT_RX_PDEV_STATS_NUM_DCM_COUNTERS]; 1350 u32 rx_stbc[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 1351 /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */ 1352 u32 rx_bw[HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; 1353 u32 rx_pream[HTT_RX_PDEV_STATS_NUM_PREAMBLE_TYPES]; 1354 u8 rssi_chain[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS] 1355 [HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; 1356 /* units = dB above noise floor */ 1357 1358 /* Counters to track number of rx packets 1359 * in each GI in each mcs (0-11) 1360 */ 1361 u32 rx_gi[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 1362 s32 rssi_in_dbm; /* rx Signal Strength value in dBm unit */ 1363 1364 u32 rx_11ax_su_ext; 1365 u32 rx_11ac_mumimo; 1366 u32 rx_11ax_mumimo; 1367 u32 rx_11ax_ofdma; 1368 u32 txbf; 1369 u32 rx_legacy_cck_rate[HTT_RX_PDEV_STATS_NUM_LEGACY_CCK_STATS]; 1370 u32 rx_legacy_ofdm_rate[HTT_RX_PDEV_STATS_NUM_LEGACY_OFDM_STATS]; 1371 u32 rx_active_dur_us_low; 1372 u32 rx_active_dur_us_high; 1373 1374 u32 rx_11ax_ul_ofdma; 1375 1376 u32 ul_ofdma_rx_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 1377 u32 ul_ofdma_rx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] 1378 [HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 1379 u32 ul_ofdma_rx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1380 u32 ul_ofdma_rx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 1381 u32 ul_ofdma_rx_stbc; 1382 u32 ul_ofdma_rx_ldpc; 1383 1384 /* record the stats for each user index */ 1385 u32 rx_ulofdma_non_data_ppdu[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; /* ppdu level */ 1386 u32 rx_ulofdma_data_ppdu[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; /* ppdu level */ 1387 u32 rx_ulofdma_mpdu_ok[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; /* mpdu level */ 1388 u32 rx_ulofdma_mpdu_fail[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; /* mpdu level */ 1389 1390 u32 nss_count; 1391 u32 pilot_count; 1392 /* RxEVM stats in dB */ 1393 s32 rx_pilot_evm_db[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS] 1394 [HTT_RX_PDEV_STATS_RXEVM_MAX_PILOTS_PER_NSS]; 1395 /* rx_pilot_evm_db_mean: 1396 * EVM mean across pilots, computed as 1397 * mean(10*log10(rx_pilot_evm_linear)) = mean(rx_pilot_evm_db) 1398 */ 1399 s32 rx_pilot_evm_db_mean[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1400 s8 rx_ul_fd_rssi[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS] 1401 [HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; /* dBm units */ 1402 /* per_chain_rssi_pkt_type: 1403 * This field shows what type of rx frame the per-chain RSSI was computed 1404 * on, by recording the frame type and sub-type as bit-fields within this 1405 * field: 1406 * BIT [3 : 0] :- IEEE80211_FC0_TYPE 1407 * BIT [7 : 4] :- IEEE80211_FC0_SUBTYPE 1408 * BIT [31 : 8] :- Reserved 1409 */ 1410 u32 per_chain_rssi_pkt_type; 1411 s8 rx_per_chain_rssi_in_dbm[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS] 1412 [HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; 1413 1414 u32 rx_su_ndpa; 1415 u32 rx_11ax_su_txbf_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 1416 u32 rx_mu_ndpa; 1417 u32 rx_11ax_mu_txbf_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 1418 u32 rx_br_poll; 1419 u32 rx_11ax_dl_ofdma_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 1420 u32 rx_11ax_dl_ofdma_ru[HTT_RX_PDEV_STATS_NUM_RU_SIZE_COUNTERS]; 1421 1422 u32 rx_ulmumimo_non_data_ppdu[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER]; 1423 u32 rx_ulmumimo_data_ppdu[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER]; 1424 u32 rx_ulmumimo_mpdu_ok[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER]; 1425 u32 rx_ulmumimo_mpdu_fail[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER]; 1426 u32 rx_ulofdma_non_data_nusers[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 1427 u32 rx_ulofdma_data_nusers[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 1428 }; 1429 1430 /* == RX PDEV/SOC STATS == */ 1431 struct htt_rx_soc_fw_stats_tlv { 1432 u32 fw_reo_ring_data_msdu; 1433 u32 fw_to_host_data_msdu_bcmc; 1434 u32 fw_to_host_data_msdu_uc; 1435 u32 ofld_remote_data_buf_recycle_cnt; 1436 u32 ofld_remote_free_buf_indication_cnt; 1437 1438 u32 ofld_buf_to_host_data_msdu_uc; 1439 u32 reo_fw_ring_to_host_data_msdu_uc; 1440 1441 u32 wbm_sw_ring_reap; 1442 u32 wbm_forward_to_host_cnt; 1443 u32 wbm_target_recycle_cnt; 1444 1445 u32 target_refill_ring_recycle_cnt; 1446 }; 1447 1448 /* NOTE: Variable length TLV, use length spec to infer array size */ 1449 struct htt_rx_soc_fw_refill_ring_empty_tlv_v { 1450 /* HTT_RX_STATS_REFILL_MAX_RING */ 1451 DECLARE_FLEX_ARRAY(u32, refill_ring_empty_cnt); 1452 }; 1453 1454 /* NOTE: Variable length TLV, use length spec to infer array size */ 1455 struct htt_rx_soc_fw_refill_ring_num_refill_tlv_v { 1456 /* HTT_RX_STATS_REFILL_MAX_RING */ 1457 DECLARE_FLEX_ARRAY(u32, refill_ring_num_refill); 1458 }; 1459 1460 /* RXDMA error code from WBM released packets */ 1461 enum htt_rx_rxdma_error_code_enum { 1462 HTT_RX_RXDMA_OVERFLOW_ERR = 0, 1463 HTT_RX_RXDMA_MPDU_LENGTH_ERR = 1, 1464 HTT_RX_RXDMA_FCS_ERR = 2, 1465 HTT_RX_RXDMA_DECRYPT_ERR = 3, 1466 HTT_RX_RXDMA_TKIP_MIC_ERR = 4, 1467 HTT_RX_RXDMA_UNECRYPTED_ERR = 5, 1468 HTT_RX_RXDMA_MSDU_LEN_ERR = 6, 1469 HTT_RX_RXDMA_MSDU_LIMIT_ERR = 7, 1470 HTT_RX_RXDMA_WIFI_PARSE_ERR = 8, 1471 HTT_RX_RXDMA_AMSDU_PARSE_ERR = 9, 1472 HTT_RX_RXDMA_SA_TIMEOUT_ERR = 10, 1473 HTT_RX_RXDMA_DA_TIMEOUT_ERR = 11, 1474 HTT_RX_RXDMA_FLOW_TIMEOUT_ERR = 12, 1475 HTT_RX_RXDMA_FLUSH_REQUEST = 13, 1476 HTT_RX_RXDMA_ERR_CODE_RVSD0 = 14, 1477 HTT_RX_RXDMA_ERR_CODE_RVSD1 = 15, 1478 1479 /* This MAX_ERR_CODE should not be used in any host/target messages, 1480 * so that even though it is defined within a host/target interface 1481 * definition header file, it isn't actually part of the host/target 1482 * interface, and thus can be modified. 1483 */ 1484 HTT_RX_RXDMA_MAX_ERR_CODE 1485 }; 1486 1487 /* NOTE: Variable length TLV, use length spec to infer array size */ 1488 struct htt_rx_soc_fw_refill_ring_num_rxdma_err_tlv_v { 1489 DECLARE_FLEX_ARRAY(u32, rxdma_err); /* HTT_RX_RXDMA_MAX_ERR_CODE */ 1490 }; 1491 1492 /* REO error code from WBM released packets */ 1493 enum htt_rx_reo_error_code_enum { 1494 HTT_RX_REO_QUEUE_DESC_ADDR_ZERO = 0, 1495 HTT_RX_REO_QUEUE_DESC_NOT_VALID = 1, 1496 HTT_RX_AMPDU_IN_NON_BA = 2, 1497 HTT_RX_NON_BA_DUPLICATE = 3, 1498 HTT_RX_BA_DUPLICATE = 4, 1499 HTT_RX_REGULAR_FRAME_2K_JUMP = 5, 1500 HTT_RX_BAR_FRAME_2K_JUMP = 6, 1501 HTT_RX_REGULAR_FRAME_OOR = 7, 1502 HTT_RX_BAR_FRAME_OOR = 8, 1503 HTT_RX_BAR_FRAME_NO_BA_SESSION = 9, 1504 HTT_RX_BAR_FRAME_SN_EQUALS_SSN = 10, 1505 HTT_RX_PN_CHECK_FAILED = 11, 1506 HTT_RX_2K_ERROR_HANDLING_FLAG_SET = 12, 1507 HTT_RX_PN_ERROR_HANDLING_FLAG_SET = 13, 1508 HTT_RX_QUEUE_DESCRIPTOR_BLOCKED_SET = 14, 1509 HTT_RX_REO_ERR_CODE_RVSD = 15, 1510 1511 /* This MAX_ERR_CODE should not be used in any host/target messages, 1512 * so that even though it is defined within a host/target interface 1513 * definition header file, it isn't actually part of the host/target 1514 * interface, and thus can be modified. 1515 */ 1516 HTT_RX_REO_MAX_ERR_CODE 1517 }; 1518 1519 /* NOTE: Variable length TLV, use length spec to infer array size */ 1520 struct htt_rx_soc_fw_refill_ring_num_reo_err_tlv_v { 1521 DECLARE_FLEX_ARRAY(u32, reo_err); /* HTT_RX_REO_MAX_ERR_CODE */ 1522 }; 1523 1524 /* == RX PDEV STATS == */ 1525 #define HTT_STATS_SUBTYPE_MAX 16 1526 1527 struct htt_rx_pdev_fw_stats_tlv { 1528 u32 mac_id__word; 1529 u32 ppdu_recvd; 1530 u32 mpdu_cnt_fcs_ok; 1531 u32 mpdu_cnt_fcs_err; 1532 u32 tcp_msdu_cnt; 1533 u32 tcp_ack_msdu_cnt; 1534 u32 udp_msdu_cnt; 1535 u32 other_msdu_cnt; 1536 u32 fw_ring_mpdu_ind; 1537 u32 fw_ring_mgmt_subtype[HTT_STATS_SUBTYPE_MAX]; 1538 u32 fw_ring_ctrl_subtype[HTT_STATS_SUBTYPE_MAX]; 1539 u32 fw_ring_mcast_data_msdu; 1540 u32 fw_ring_bcast_data_msdu; 1541 u32 fw_ring_ucast_data_msdu; 1542 u32 fw_ring_null_data_msdu; 1543 u32 fw_ring_mpdu_drop; 1544 u32 ofld_local_data_ind_cnt; 1545 u32 ofld_local_data_buf_recycle_cnt; 1546 u32 drx_local_data_ind_cnt; 1547 u32 drx_local_data_buf_recycle_cnt; 1548 u32 local_nondata_ind_cnt; 1549 u32 local_nondata_buf_recycle_cnt; 1550 1551 u32 fw_status_buf_ring_refill_cnt; 1552 u32 fw_status_buf_ring_empty_cnt; 1553 u32 fw_pkt_buf_ring_refill_cnt; 1554 u32 fw_pkt_buf_ring_empty_cnt; 1555 u32 fw_link_buf_ring_refill_cnt; 1556 u32 fw_link_buf_ring_empty_cnt; 1557 1558 u32 host_pkt_buf_ring_refill_cnt; 1559 u32 host_pkt_buf_ring_empty_cnt; 1560 u32 mon_pkt_buf_ring_refill_cnt; 1561 u32 mon_pkt_buf_ring_empty_cnt; 1562 u32 mon_status_buf_ring_refill_cnt; 1563 u32 mon_status_buf_ring_empty_cnt; 1564 u32 mon_desc_buf_ring_refill_cnt; 1565 u32 mon_desc_buf_ring_empty_cnt; 1566 u32 mon_dest_ring_update_cnt; 1567 u32 mon_dest_ring_full_cnt; 1568 1569 u32 rx_suspend_cnt; 1570 u32 rx_suspend_fail_cnt; 1571 u32 rx_resume_cnt; 1572 u32 rx_resume_fail_cnt; 1573 u32 rx_ring_switch_cnt; 1574 u32 rx_ring_restore_cnt; 1575 u32 rx_flush_cnt; 1576 u32 rx_recovery_reset_cnt; 1577 }; 1578 1579 #define HTT_STATS_PHY_ERR_MAX 43 1580 1581 struct htt_rx_pdev_fw_stats_phy_err_tlv { 1582 u32 mac_id__word; 1583 u32 total_phy_err_cnt; 1584 /* Counts of different types of phy errs 1585 * The mapping of PHY error types to phy_err array elements is HW dependent. 1586 * The only currently-supported mapping is shown below: 1587 * 1588 * 0 phyrx_err_phy_off Reception aborted due to receiving a PHY_OFF TLV 1589 * 1 phyrx_err_synth_off 1590 * 2 phyrx_err_ofdma_timing 1591 * 3 phyrx_err_ofdma_signal_parity 1592 * 4 phyrx_err_ofdma_rate_illegal 1593 * 5 phyrx_err_ofdma_length_illegal 1594 * 6 phyrx_err_ofdma_restart 1595 * 7 phyrx_err_ofdma_service 1596 * 8 phyrx_err_ppdu_ofdma_power_drop 1597 * 9 phyrx_err_cck_blokker 1598 * 10 phyrx_err_cck_timing 1599 * 11 phyrx_err_cck_header_crc 1600 * 12 phyrx_err_cck_rate_illegal 1601 * 13 phyrx_err_cck_length_illegal 1602 * 14 phyrx_err_cck_restart 1603 * 15 phyrx_err_cck_service 1604 * 16 phyrx_err_cck_power_drop 1605 * 17 phyrx_err_ht_crc_err 1606 * 18 phyrx_err_ht_length_illegal 1607 * 19 phyrx_err_ht_rate_illegal 1608 * 20 phyrx_err_ht_zlf 1609 * 21 phyrx_err_false_radar_ext 1610 * 22 phyrx_err_green_field 1611 * 23 phyrx_err_bw_gt_dyn_bw 1612 * 24 phyrx_err_leg_ht_mismatch 1613 * 25 phyrx_err_vht_crc_error 1614 * 26 phyrx_err_vht_siga_unsupported 1615 * 27 phyrx_err_vht_lsig_len_invalid 1616 * 28 phyrx_err_vht_ndp_or_zlf 1617 * 29 phyrx_err_vht_nsym_lt_zero 1618 * 30 phyrx_err_vht_rx_extra_symbol_mismatch 1619 * 31 phyrx_err_vht_rx_skip_group_id0 1620 * 32 phyrx_err_vht_rx_skip_group_id1to62 1621 * 33 phyrx_err_vht_rx_skip_group_id63 1622 * 34 phyrx_err_ofdm_ldpc_decoder_disabled 1623 * 35 phyrx_err_defer_nap 1624 * 36 phyrx_err_fdomain_timeout 1625 * 37 phyrx_err_lsig_rel_check 1626 * 38 phyrx_err_bt_collision 1627 * 39 phyrx_err_unsupported_mu_feedback 1628 * 40 phyrx_err_ppdu_tx_interrupt_rx 1629 * 41 phyrx_err_unsupported_cbf 1630 * 42 phyrx_err_other 1631 */ 1632 u32 phy_err[HTT_STATS_PHY_ERR_MAX]; 1633 }; 1634 1635 /* NOTE: Variable length TLV, use length spec to infer array size */ 1636 struct htt_rx_pdev_fw_ring_mpdu_err_tlv_v { 1637 /* Num error MPDU for each RxDMA error type */ 1638 DECLARE_FLEX_ARRAY(u32, fw_ring_mpdu_err); /* HTT_RX_STATS_RXDMA_MAX_ERR */ 1639 }; 1640 1641 /* NOTE: Variable length TLV, use length spec to infer array size */ 1642 struct htt_rx_pdev_fw_mpdu_drop_tlv_v { 1643 /* Num MPDU dropped */ 1644 DECLARE_FLEX_ARRAY(u32, fw_mpdu_drop); /* HTT_RX_STATS_FW_DROP_REASON_MAX */ 1645 }; 1646 1647 #define HTT_PDEV_CCA_STATS_TX_FRAME_INFO_PRESENT (0x1) 1648 #define HTT_PDEV_CCA_STATS_RX_FRAME_INFO_PRESENT (0x2) 1649 #define HTT_PDEV_CCA_STATS_RX_CLEAR_INFO_PRESENT (0x4) 1650 #define HTT_PDEV_CCA_STATS_MY_RX_FRAME_INFO_PRESENT (0x8) 1651 #define HTT_PDEV_CCA_STATS_USEC_CNT_INFO_PRESENT (0x10) 1652 #define HTT_PDEV_CCA_STATS_MED_RX_IDLE_INFO_PRESENT (0x20) 1653 #define HTT_PDEV_CCA_STATS_MED_TX_IDLE_GLOBAL_INFO_PRESENT (0x40) 1654 #define HTT_PDEV_CCA_STATS_CCA_OBBS_USEC_INFO_PRESENT (0x80) 1655 1656 struct htt_pdev_stats_cca_counters_tlv { 1657 /* Below values are obtained from the HW Cycles counter registers */ 1658 u32 tx_frame_usec; 1659 u32 rx_frame_usec; 1660 u32 rx_clear_usec; 1661 u32 my_rx_frame_usec; 1662 u32 usec_cnt; 1663 u32 med_rx_idle_usec; 1664 u32 med_tx_idle_global_usec; 1665 u32 cca_obss_usec; 1666 }; 1667 1668 struct htt_pdev_cca_stats_hist_v1_tlv { 1669 u32 chan_num; 1670 /* num of CCA records (Num of htt_pdev_stats_cca_counters_tlv)*/ 1671 u32 num_records; 1672 u32 valid_cca_counters_bitmap; 1673 u32 collection_interval; 1674 1675 /* This will be followed by an array which contains the CCA stats 1676 * collected in the last N intervals, 1677 * if the indication is for last N intervals CCA stats. 1678 * Then the pdev_cca_stats[0] element contains the oldest CCA stats 1679 * and pdev_cca_stats[N-1] will have the most recent CCA stats. 1680 * htt_pdev_stats_cca_counters_tlv cca_hist_tlv[1]; 1681 */ 1682 }; 1683 1684 struct htt_pdev_stats_twt_session_tlv { 1685 u32 vdev_id; 1686 struct htt_mac_addr peer_mac; 1687 u32 flow_id_flags; 1688 1689 /* TWT_DIALOG_ID_UNAVAILABLE is used 1690 * when TWT session is not initiated by host 1691 */ 1692 u32 dialog_id; 1693 u32 wake_dura_us; 1694 u32 wake_intvl_us; 1695 u32 sp_offset_us; 1696 }; 1697 1698 struct htt_pdev_stats_twt_sessions_tlv { 1699 u32 pdev_id; 1700 u32 num_sessions; 1701 struct htt_pdev_stats_twt_session_tlv twt_session[]; 1702 }; 1703 1704 enum htt_rx_reo_resource_sample_id_enum { 1705 /* Global link descriptor queued in REO */ 1706 HTT_RX_REO_RESOURCE_GLOBAL_LINK_DESC_COUNT_0 = 0, 1707 HTT_RX_REO_RESOURCE_GLOBAL_LINK_DESC_COUNT_1 = 1, 1708 HTT_RX_REO_RESOURCE_GLOBAL_LINK_DESC_COUNT_2 = 2, 1709 /*Number of queue descriptors of this aging group */ 1710 HTT_RX_REO_RESOURCE_BUFFERS_USED_AC0 = 3, 1711 HTT_RX_REO_RESOURCE_BUFFERS_USED_AC1 = 4, 1712 HTT_RX_REO_RESOURCE_BUFFERS_USED_AC2 = 5, 1713 HTT_RX_REO_RESOURCE_BUFFERS_USED_AC3 = 6, 1714 /* Total number of MSDUs buffered in AC */ 1715 HTT_RX_REO_RESOURCE_AGING_NUM_QUEUES_AC0 = 7, 1716 HTT_RX_REO_RESOURCE_AGING_NUM_QUEUES_AC1 = 8, 1717 HTT_RX_REO_RESOURCE_AGING_NUM_QUEUES_AC2 = 9, 1718 HTT_RX_REO_RESOURCE_AGING_NUM_QUEUES_AC3 = 10, 1719 1720 HTT_RX_REO_RESOURCE_STATS_MAX = 16 1721 }; 1722 1723 struct htt_rx_reo_resource_stats_tlv_v { 1724 /* Variable based on the Number of records. HTT_RX_REO_RESOURCE_STATS_MAX */ 1725 u32 sample_id; 1726 u32 total_max; 1727 u32 total_avg; 1728 u32 total_sample; 1729 u32 non_zeros_avg; 1730 u32 non_zeros_sample; 1731 u32 last_non_zeros_max; 1732 u32 last_non_zeros_min; 1733 u32 last_non_zeros_avg; 1734 u32 last_non_zeros_sample; 1735 }; 1736 1737 /* == TX SOUNDING STATS == */ 1738 1739 enum htt_txbf_sound_steer_modes { 1740 HTT_IMPLICIT_TXBF_STEER_STATS = 0, 1741 HTT_EXPLICIT_TXBF_SU_SIFS_STEER_STATS = 1, 1742 HTT_EXPLICIT_TXBF_SU_RBO_STEER_STATS = 2, 1743 HTT_EXPLICIT_TXBF_MU_SIFS_STEER_STATS = 3, 1744 HTT_EXPLICIT_TXBF_MU_RBO_STEER_STATS = 4, 1745 HTT_TXBF_MAX_NUM_OF_MODES = 5 1746 }; 1747 1748 enum htt_stats_sounding_tx_mode { 1749 HTT_TX_AC_SOUNDING_MODE = 0, 1750 HTT_TX_AX_SOUNDING_MODE = 1, 1751 }; 1752 1753 struct htt_tx_sounding_stats_tlv { 1754 u32 tx_sounding_mode; /* HTT_TX_XX_SOUNDING_MODE */ 1755 /* Counts number of soundings for all steering modes in each bw */ 1756 u32 cbf_20[HTT_TXBF_MAX_NUM_OF_MODES]; 1757 u32 cbf_40[HTT_TXBF_MAX_NUM_OF_MODES]; 1758 u32 cbf_80[HTT_TXBF_MAX_NUM_OF_MODES]; 1759 u32 cbf_160[HTT_TXBF_MAX_NUM_OF_MODES]; 1760 /* 1761 * The sounding array is a 2-D array stored as an 1-D array of 1762 * u32. The stats for a particular user/bw combination is 1763 * referenced with the following: 1764 * 1765 * sounding[(user* max_bw) + bw] 1766 * 1767 * ... where max_bw == 4 for 160mhz 1768 */ 1769 u32 sounding[HTT_TX_NUM_OF_SOUNDING_STATS_WORDS]; 1770 }; 1771 1772 struct htt_pdev_obss_pd_stats_tlv { 1773 u32 num_obss_tx_ppdu_success; 1774 u32 num_obss_tx_ppdu_failure; 1775 u32 num_sr_tx_transmissions; 1776 u32 num_spatial_reuse_opportunities; 1777 u32 num_non_srg_opportunities; 1778 u32 num_non_srg_ppdu_tried; 1779 u32 num_non_srg_ppdu_success; 1780 u32 num_srg_opportunities; 1781 u32 num_srg_ppdu_tried; 1782 u32 num_srg_ppdu_success; 1783 u32 num_psr_opportunities; 1784 u32 num_psr_ppdu_tried; 1785 u32 num_psr_ppdu_success; 1786 }; 1787 1788 struct htt_ring_backpressure_stats_tlv { 1789 u32 pdev_id; 1790 u32 current_head_idx; 1791 u32 current_tail_idx; 1792 u32 num_htt_msgs_sent; 1793 /* Time in milliseconds for which the ring has been in 1794 * its current backpressure condition 1795 */ 1796 u32 backpressure_time_ms; 1797 /* backpressure_hist - histogram showing how many times 1798 * different degrees of backpressure duration occurred: 1799 * Index 0 indicates the number of times ring was 1800 * continuously in backpressure state for 100 - 200ms. 1801 * Index 1 indicates the number of times ring was 1802 * continuously in backpressure state for 200 - 300ms. 1803 * Index 2 indicates the number of times ring was 1804 * continuously in backpressure state for 300 - 400ms. 1805 * Index 3 indicates the number of times ring was 1806 * continuously in backpressure state for 400 - 500ms. 1807 * Index 4 indicates the number of times ring was 1808 * continuously in backpressure state beyond 500ms. 1809 */ 1810 u32 backpressure_hist[5]; 1811 }; 1812 1813 #define HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS 14 1814 #define HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS 5 1815 #define HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS 8 1816 1817 struct htt_pdev_txrate_txbf_stats_tlv { 1818 /* SU TxBF TX MCS stats */ 1819 u32 tx_su_txbf_mcs[HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS]; 1820 /* Implicit BF TX MCS stats */ 1821 u32 tx_su_ibf_mcs[HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS]; 1822 /* Open loop TX MCS stats */ 1823 u32 tx_su_ol_mcs[HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS]; 1824 /* SU TxBF TX NSS stats */ 1825 u32 tx_su_txbf_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1826 /* Implicit BF TX NSS stats */ 1827 u32 tx_su_ibf_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1828 /* Open loop TX NSS stats */ 1829 u32 tx_su_ol_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1830 /* SU TxBF TX BW stats */ 1831 u32 tx_su_txbf_bw[HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS]; 1832 /* Implicit BF TX BW stats */ 1833 u32 tx_su_ibf_bw[HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS]; 1834 /* Open loop TX BW stats */ 1835 u32 tx_su_ol_bw[HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS]; 1836 }; 1837 1838 struct htt_txbf_ofdma_ndpa_stats_tlv { 1839 /* 11AX HE OFDMA NDPA frame queued to the HW */ 1840 u32 ax_ofdma_ndpa_queued[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1841 /* 11AX HE OFDMA NDPA frame sent over the air */ 1842 u32 ax_ofdma_ndpa_tried[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1843 /* 11AX HE OFDMA NDPA frame flushed by HW */ 1844 u32 ax_ofdma_ndpa_flushed[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1845 /* 11AX HE OFDMA NDPA frame completed with error(s) */ 1846 u32 ax_ofdma_ndpa_err[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1847 }; 1848 1849 struct htt_txbf_ofdma_ndp_stats_tlv { 1850 /* 11AX HE OFDMA NDP frame queued to the HW */ 1851 u32 ax_ofdma_ndp_queued[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1852 /* 11AX HE OFDMA NDPA frame sent over the air */ 1853 u32 ax_ofdma_ndp_tried[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1854 /* 11AX HE OFDMA NDPA frame flushed by HW */ 1855 u32 ax_ofdma_ndp_flushed[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1856 /* 11AX HE OFDMA NDPA frame completed with error(s) */ 1857 u32 ax_ofdma_ndp_err[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1858 }; 1859 1860 struct htt_txbf_ofdma_brp_stats_tlv { 1861 /* 11AX HE OFDMA MU BRPOLL frame queued to the HW */ 1862 u32 ax_ofdma_brpoll_queued[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1863 /* 11AX HE OFDMA MU BRPOLL frame sent over the air */ 1864 u32 ax_ofdma_brpoll_tried[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1865 /* 11AX HE OFDMA MU BRPOLL frame flushed by HW */ 1866 u32 ax_ofdma_brpoll_flushed[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1867 /* 11AX HE OFDMA MU BRPOLL frame completed with error(s) */ 1868 u32 ax_ofdma_brp_err[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1869 /* Number of CBF(s) received when 11AX HE OFDMA MU BRPOLL frame 1870 * completed with error(s). 1871 */ 1872 u32 ax_ofdma_brp_err_num_cbf_rcvd[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS + 1]; 1873 }; 1874 1875 struct htt_txbf_ofdma_steer_stats_tlv { 1876 /* 11AX HE OFDMA PPDUs that were sent over the air with steering (TXBF + OFDMA) */ 1877 u32 ax_ofdma_num_ppdu_steer[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1878 /* 11AX HE OFDMA PPDUs that were sent over the air in open loop */ 1879 u32 ax_ofdma_num_ppdu_ol[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1880 /* 11AX HE OFDMA number of users for which CBF prefetch was 1881 * initiated to PHY HW during TX. 1882 */ 1883 u32 ax_ofdma_num_usrs_prefetch[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1884 /* 11AX HE OFDMA number of users for which sounding was initiated during TX */ 1885 u32 ax_ofdma_num_usrs_sound[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1886 /* 11AX HE OFDMA number of users for which sounding was forced during TX */ 1887 u32 ax_ofdma_num_usrs_force_sound[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 1888 }; 1889 1890 #define HTT_MAX_RX_PKT_CNT 8 1891 #define HTT_MAX_RX_PKT_CRC_PASS_CNT 8 1892 #define HTT_MAX_PER_BLK_ERR_CNT 20 1893 #define HTT_MAX_RX_OTA_ERR_CNT 14 1894 #define HTT_STATS_MAX_CHAINS 8 1895 #define ATH11K_STATS_MGMT_FRM_TYPE_MAX 16 1896 1897 struct htt_phy_counters_tlv { 1898 /* number of RXTD OFDMA OTA error counts except power surge and drop */ 1899 u32 rx_ofdma_timing_err_cnt; 1900 /* rx_cck_fail_cnt: 1901 * number of cck error counts due to rx reception failure because of 1902 * timing error in cck 1903 */ 1904 u32 rx_cck_fail_cnt; 1905 /* number of times tx abort initiated by mac */ 1906 u32 mactx_abort_cnt; 1907 /* number of times rx abort initiated by mac */ 1908 u32 macrx_abort_cnt; 1909 /* number of times tx abort initiated by phy */ 1910 u32 phytx_abort_cnt; 1911 /* number of times rx abort initiated by phy */ 1912 u32 phyrx_abort_cnt; 1913 /* number of rx deferred count initiated by phy */ 1914 u32 phyrx_defer_abort_cnt; 1915 /* number of sizing events generated at LSTF */ 1916 u32 rx_gain_adj_lstf_event_cnt; 1917 /* number of sizing events generated at non-legacy LTF */ 1918 u32 rx_gain_adj_non_legacy_cnt; 1919 /* rx_pkt_cnt - 1920 * Received EOP (end-of-packet) count per packet type; 1921 * [0] = 11a; [1] = 11b; [2] = 11n; [3] = 11ac; [4] = 11ax; [5] = GF 1922 * [6-7]=RSVD 1923 */ 1924 u32 rx_pkt_cnt[HTT_MAX_RX_PKT_CNT]; 1925 /* rx_pkt_crc_pass_cnt - 1926 * Received EOP (end-of-packet) count per packet type; 1927 * [0] = 11a; [1] = 11b; [2] = 11n; [3] = 11ac; [4] = 11ax; [5] = GF 1928 * [6-7]=RSVD 1929 */ 1930 u32 rx_pkt_crc_pass_cnt[HTT_MAX_RX_PKT_CRC_PASS_CNT]; 1931 /* per_blk_err_cnt - 1932 * Error count per error source; 1933 * [0] = unknown; [1] = LSIG; [2] = HTSIG; [3] = VHTSIG; [4] = HESIG; 1934 * [5] = RXTD_OTA; [6] = RXTD_FATAL; [7] = DEMF; [8] = ROBE; 1935 * [9] = PMI; [10] = TXFD; [11] = TXTD; [12] = PHYRF 1936 * [13-19]=RSVD 1937 */ 1938 u32 per_blk_err_cnt[HTT_MAX_PER_BLK_ERR_CNT]; 1939 /* rx_ota_err_cnt - 1940 * RXTD OTA (over-the-air) error count per error reason; 1941 * [0] = voting fail; [1] = weak det fail; [2] = strong sig fail; 1942 * [3] = cck fail; [4] = power surge; [5] = power drop; 1943 * [6] = btcf timing timeout error; [7] = btcf packet detect error; 1944 * [8] = coarse timing timeout error 1945 * [9-13]=RSVD 1946 */ 1947 u32 rx_ota_err_cnt[HTT_MAX_RX_OTA_ERR_CNT]; 1948 }; 1949 1950 struct htt_phy_stats_tlv { 1951 /* per chain hw noise floor values in dBm */ 1952 s32 nf_chain[HTT_STATS_MAX_CHAINS]; 1953 /* number of false radars detected */ 1954 u32 false_radar_cnt; 1955 /* number of channel switches happened due to radar detection */ 1956 u32 radar_cs_cnt; 1957 /* ani_level - 1958 * ANI level (noise interference) corresponds to the channel 1959 * the desense levels range from -5 to 15 in dB units, 1960 * higher values indicating more noise interference. 1961 */ 1962 s32 ani_level; 1963 /* running time in minutes since FW boot */ 1964 u32 fw_run_time; 1965 }; 1966 1967 struct htt_peer_ctrl_path_txrx_stats_tlv { 1968 /* peer mac address */ 1969 u8 peer_mac_addr[ETH_ALEN]; 1970 u8 rsvd[2]; 1971 /* Num of tx mgmt frames with subtype on peer level */ 1972 u32 peer_tx_mgmt_subtype[ATH11K_STATS_MGMT_FRM_TYPE_MAX]; 1973 /* Num of rx mgmt frames with subtype on peer level */ 1974 u32 peer_rx_mgmt_subtype[ATH11K_STATS_MGMT_FRM_TYPE_MAX]; 1975 }; 1976 1977 #ifdef CONFIG_ATH11K_DEBUGFS 1978 1979 void ath11k_debugfs_htt_stats_init(struct ath11k *ar); 1980 void ath11k_debugfs_htt_ext_stats_handler(struct ath11k_base *ab, 1981 struct sk_buff *skb); 1982 int ath11k_debugfs_htt_stats_req(struct ath11k *ar); 1983 1984 #else /* CONFIG_ATH11K_DEBUGFS */ 1985 1986 static inline void ath11k_debugfs_htt_stats_init(struct ath11k *ar) 1987 { 1988 } 1989 1990 static inline void ath11k_debugfs_htt_ext_stats_handler(struct ath11k_base *ab, 1991 struct sk_buff *skb) 1992 { 1993 } 1994 1995 static inline int ath11k_debugfs_htt_stats_req(struct ath11k *ar) 1996 { 1997 return 0; 1998 } 1999 2000 #endif /* CONFIG_ATH11K_DEBUGFS */ 2001 2002 #endif 2003