1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef ATH11K_CORE_H 8 #define ATH11K_CORE_H 9 10 #include <linux/types.h> 11 #include <linux/interrupt.h> 12 #include <linux/irq.h> 13 #include <linux/bitfield.h> 14 #include <linux/dmi.h> 15 #include <linux/ctype.h> 16 #include <linux/rhashtable.h> 17 #include <linux/average.h> 18 #include <linux/firmware.h> 19 20 #include "qmi.h" 21 #include "htc.h" 22 #include "wmi.h" 23 #include "hal.h" 24 #include "dp.h" 25 #include "ce.h" 26 #include "mac.h" 27 #include "hw.h" 28 #include "hal_rx.h" 29 #include "reg.h" 30 #include "thermal.h" 31 #include "dbring.h" 32 #include "spectral.h" 33 #include "wow.h" 34 #include "fw.h" 35 36 #define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK) 37 38 #define ATH11K_TX_MGMT_NUM_PENDING_MAX 512 39 40 #define ATH11K_TX_MGMT_TARGET_MAX_SUPPORT_WMI 64 41 42 /* Pending management packets threshold for dropping probe responses */ 43 #define ATH11K_PRB_RSP_DROP_THRESHOLD ((ATH11K_TX_MGMT_TARGET_MAX_SUPPORT_WMI * 3) / 4) 44 45 #define ATH11K_INVALID_HW_MAC_ID 0xFF 46 #define ATH11K_CONNECTION_LOSS_HZ (3 * HZ) 47 48 /* SMBIOS type containing Board Data File Name Extension */ 49 #define ATH11K_SMBIOS_BDF_EXT_TYPE 0xF8 50 51 /* SMBIOS type structure length (excluding strings-set) */ 52 #define ATH11K_SMBIOS_BDF_EXT_LENGTH 0x9 53 54 /* The magic used by QCA spec */ 55 #define ATH11K_SMBIOS_BDF_EXT_MAGIC "BDF_" 56 57 extern unsigned int ath11k_frame_mode; 58 extern bool ath11k_ftm_mode; 59 60 #define ATH11K_SCAN_TIMEOUT_HZ (20 * HZ) 61 62 #define ATH11K_MON_TIMER_INTERVAL 10 63 #define ATH11K_RESET_TIMEOUT_HZ (20 * HZ) 64 #define ATH11K_RESET_MAX_FAIL_COUNT_FIRST 3 65 #define ATH11K_RESET_MAX_FAIL_COUNT_FINAL 5 66 #define ATH11K_RESET_FAIL_TIMEOUT_HZ (20 * HZ) 67 #define ATH11K_RECONFIGURE_TIMEOUT_HZ (10 * HZ) 68 #define ATH11K_RECOVER_START_TIMEOUT_HZ (20 * HZ) 69 70 enum ath11k_supported_bw { 71 ATH11K_BW_20 = 0, 72 ATH11K_BW_40 = 1, 73 ATH11K_BW_80 = 2, 74 ATH11K_BW_160 = 3, 75 }; 76 77 enum ath11k_bdf_search { 78 ATH11K_BDF_SEARCH_DEFAULT, 79 ATH11K_BDF_SEARCH_BUS_AND_BOARD, 80 }; 81 82 enum wme_ac { 83 WME_AC_BE, 84 WME_AC_BK, 85 WME_AC_VI, 86 WME_AC_VO, 87 WME_NUM_AC 88 }; 89 90 #define ATH11K_HT_MCS_MAX 7 91 #define ATH11K_VHT_MCS_MAX 9 92 #define ATH11K_HE_MCS_MAX 11 93 94 enum ath11k_crypt_mode { 95 /* Only use hardware crypto engine */ 96 ATH11K_CRYPT_MODE_HW, 97 /* Only use software crypto */ 98 ATH11K_CRYPT_MODE_SW, 99 }; 100 101 static inline enum wme_ac ath11k_tid_to_ac(u32 tid) 102 { 103 return (((tid == 0) || (tid == 3)) ? WME_AC_BE : 104 ((tid == 1) || (tid == 2)) ? WME_AC_BK : 105 ((tid == 4) || (tid == 5)) ? WME_AC_VI : 106 WME_AC_VO); 107 } 108 109 enum ath11k_skb_flags { 110 ATH11K_SKB_HW_80211_ENCAP = BIT(0), 111 ATH11K_SKB_CIPHER_SET = BIT(1), 112 }; 113 114 struct ath11k_skb_cb { 115 dma_addr_t paddr; 116 u8 eid; 117 u8 flags; 118 u32 cipher; 119 struct ath11k *ar; 120 struct ieee80211_vif *vif; 121 } __packed; 122 123 struct ath11k_skb_rxcb { 124 dma_addr_t paddr; 125 bool is_first_msdu; 126 bool is_last_msdu; 127 bool is_continuation; 128 bool is_mcbc; 129 bool is_eapol; 130 struct hal_rx_desc *rx_desc; 131 u8 err_rel_src; 132 u8 err_code; 133 u8 mac_id; 134 u8 unmapped; 135 u8 is_frag; 136 u8 tid; 137 u16 peer_id; 138 u16 seq_no; 139 }; 140 141 enum ath11k_hw_rev { 142 ATH11K_HW_IPQ8074, 143 ATH11K_HW_QCA6390_HW20, 144 ATH11K_HW_IPQ6018_HW10, 145 ATH11K_HW_QCN9074_HW10, 146 ATH11K_HW_WCN6855_HW20, 147 ATH11K_HW_WCN6855_HW21, 148 ATH11K_HW_WCN6750_HW10, 149 ATH11K_HW_IPQ5018_HW10, 150 }; 151 152 enum ath11k_firmware_mode { 153 /* the default mode, standard 802.11 functionality */ 154 ATH11K_FIRMWARE_MODE_NORMAL, 155 156 /* factory tests etc */ 157 ATH11K_FIRMWARE_MODE_FTM, 158 159 /* Cold boot calibration */ 160 ATH11K_FIRMWARE_MODE_COLD_BOOT = 7, 161 }; 162 163 extern bool ath11k_cold_boot_cal; 164 165 #define ATH11K_IRQ_NUM_MAX 52 166 #define ATH11K_EXT_IRQ_NUM_MAX 16 167 168 struct ath11k_ext_irq_grp { 169 struct ath11k_base *ab; 170 u32 irqs[ATH11K_EXT_IRQ_NUM_MAX]; 171 u32 num_irq; 172 u32 grp_id; 173 u64 timestamp; 174 bool napi_enabled; 175 struct napi_struct napi; 176 struct net_device napi_ndev; 177 }; 178 179 enum ath11k_smbios_cc_type { 180 /* disable country code setting from SMBIOS */ 181 ATH11K_SMBIOS_CC_DISABLE = 0, 182 183 /* set country code by ANSI country name, based on ISO3166-1 alpha2 */ 184 ATH11K_SMBIOS_CC_ISO = 1, 185 186 /* worldwide regdomain */ 187 ATH11K_SMBIOS_CC_WW = 2, 188 }; 189 190 struct ath11k_smbios_bdf { 191 struct dmi_header hdr; 192 193 u8 features_disabled; 194 195 /* enum ath11k_smbios_cc_type */ 196 u8 country_code_flag; 197 198 /* To set specific country, you need to set country code 199 * flag=ATH11K_SMBIOS_CC_ISO first, then if country is United 200 * States, then country code value = 0x5553 ("US",'U' = 0x55, 'S'= 201 * 0x53). To set country to INDONESIA, then country code value = 202 * 0x4944 ("IN", 'I'=0x49, 'D'=0x44). If country code flag = 203 * ATH11K_SMBIOS_CC_WW, then you can use worldwide regulatory 204 * setting. 205 */ 206 u16 cc_code; 207 208 u8 bdf_enabled; 209 u8 bdf_ext[]; 210 } __packed; 211 212 #define HEHANDLE_CAP_PHYINFO_SIZE 3 213 #define HECAP_PHYINFO_SIZE 9 214 #define HECAP_MACINFO_SIZE 5 215 #define HECAP_TXRX_MCS_NSS_SIZE 2 216 #define HECAP_PPET16_PPET8_MAX_SIZE 25 217 218 #define HE_PPET16_PPET8_SIZE 8 219 220 /* 802.11ax PPE (PPDU packet Extension) threshold */ 221 struct he_ppe_threshold { 222 u32 numss_m1; 223 u32 ru_mask; 224 u32 ppet16_ppet8_ru3_ru0[HE_PPET16_PPET8_SIZE]; 225 }; 226 227 struct ath11k_he { 228 u8 hecap_macinfo[HECAP_MACINFO_SIZE]; 229 u32 hecap_rxmcsnssmap; 230 u32 hecap_txmcsnssmap; 231 u32 hecap_phyinfo[HEHANDLE_CAP_PHYINFO_SIZE]; 232 struct he_ppe_threshold hecap_ppet; 233 u32 heop_param; 234 }; 235 236 #define MAX_RADIOS 3 237 238 /* ipq5018 hw param macros */ 239 #define MAX_RADIOS_5018 1 240 #define CE_CNT_5018 6 241 #define TARGET_CE_CNT_5018 9 242 #define SVC_CE_MAP_LEN_5018 17 243 #define RXDMA_PER_PDEV_5018 1 244 245 enum { 246 WMI_HOST_TP_SCALE_MAX = 0, 247 WMI_HOST_TP_SCALE_50 = 1, 248 WMI_HOST_TP_SCALE_25 = 2, 249 WMI_HOST_TP_SCALE_12 = 3, 250 WMI_HOST_TP_SCALE_MIN = 4, 251 WMI_HOST_TP_SCALE_SIZE = 5, 252 }; 253 254 enum ath11k_scan_state { 255 ATH11K_SCAN_IDLE, 256 ATH11K_SCAN_STARTING, 257 ATH11K_SCAN_RUNNING, 258 ATH11K_SCAN_ABORTING, 259 }; 260 261 enum ath11k_11d_state { 262 ATH11K_11D_IDLE, 263 ATH11K_11D_PREPARING, 264 ATH11K_11D_RUNNING, 265 }; 266 267 enum ath11k_dev_flags { 268 ATH11K_CAC_RUNNING, 269 ATH11K_FLAG_CORE_REGISTERED, 270 ATH11K_FLAG_CRASH_FLUSH, 271 ATH11K_FLAG_RAW_MODE, 272 ATH11K_FLAG_HW_CRYPTO_DISABLED, 273 ATH11K_FLAG_BTCOEX, 274 ATH11K_FLAG_RECOVERY, 275 ATH11K_FLAG_UNREGISTERING, 276 ATH11K_FLAG_REGISTERED, 277 ATH11K_FLAG_QMI_FAIL, 278 ATH11K_FLAG_HTC_SUSPEND_COMPLETE, 279 ATH11K_FLAG_CE_IRQ_ENABLED, 280 ATH11K_FLAG_EXT_IRQ_ENABLED, 281 ATH11K_FLAG_FIXED_MEM_RGN, 282 ATH11K_FLAG_DEVICE_INIT_DONE, 283 ATH11K_FLAG_MULTI_MSI_VECTORS, 284 ATH11K_FLAG_FTM_SEGMENTED, 285 }; 286 287 enum ath11k_monitor_flags { 288 ATH11K_FLAG_MONITOR_CONF_ENABLED, 289 ATH11K_FLAG_MONITOR_STARTED, 290 ATH11K_FLAG_MONITOR_VDEV_CREATED, 291 }; 292 293 #define ATH11K_IPV6_UC_TYPE 0 294 #define ATH11K_IPV6_AC_TYPE 1 295 296 #define ATH11K_IPV6_MAX_COUNT 16 297 #define ATH11K_IPV4_MAX_COUNT 2 298 299 struct ath11k_arp_ns_offload { 300 u8 ipv4_addr[ATH11K_IPV4_MAX_COUNT][4]; 301 u32 ipv4_count; 302 u32 ipv6_count; 303 u8 ipv6_addr[ATH11K_IPV6_MAX_COUNT][16]; 304 u8 self_ipv6_addr[ATH11K_IPV6_MAX_COUNT][16]; 305 u8 ipv6_type[ATH11K_IPV6_MAX_COUNT]; 306 bool ipv6_valid[ATH11K_IPV6_MAX_COUNT]; 307 u8 mac_addr[ETH_ALEN]; 308 }; 309 310 struct ath11k_rekey_data { 311 u8 kck[NL80211_KCK_LEN]; 312 u8 kek[NL80211_KCK_LEN]; 313 u64 replay_ctr; 314 bool enable_offload; 315 }; 316 317 /** 318 * struct ath11k_chan_power_info - TPE containing power info per channel chunk 319 * @chan_cfreq: channel center freq (MHz) 320 * e.g. 321 * channel 37/20 MHz, it is 6135 322 * channel 37/40 MHz, it is 6125 323 * channel 37/80 MHz, it is 6145 324 * channel 37/160 MHz, it is 6185 325 * @tx_power: transmit power (dBm) 326 */ 327 struct ath11k_chan_power_info { 328 u16 chan_cfreq; 329 s8 tx_power; 330 }; 331 332 /** 333 * struct ath11k_reg_tpc_power_info - regulatory TPC power info 334 * @is_psd_power: is PSD power or not 335 * @eirp_power: Maximum EIRP power (dBm), valid only if power is PSD 336 * @ap_power_type: type of power (SP/LPI/VLP) 337 * @num_pwr_levels: number of power levels 338 * @reg_max: Array of maximum TX power (dBm) per PSD value 339 * @ap_constraint_power: AP constraint power (dBm) 340 * @tpe: TPE values processed from TPE IE 341 * @chan_power_info: power info to send to firmware 342 */ 343 struct ath11k_reg_tpc_power_info { 344 bool is_psd_power; 345 u8 eirp_power; 346 enum wmi_reg_6ghz_ap_type ap_power_type; 347 u8 num_pwr_levels; 348 u8 reg_max[IEEE80211_MAX_NUM_PWR_LEVEL]; 349 u8 ap_constraint_power; 350 s8 tpe[IEEE80211_MAX_NUM_PWR_LEVEL]; 351 struct ath11k_chan_power_info chan_power_info[IEEE80211_MAX_NUM_PWR_LEVEL]; 352 }; 353 354 struct ath11k_vif { 355 u32 vdev_id; 356 enum wmi_vdev_type vdev_type; 357 enum wmi_vdev_subtype vdev_subtype; 358 u32 beacon_interval; 359 u32 dtim_period; 360 u16 ast_hash; 361 u16 ast_idx; 362 u16 tcl_metadata; 363 u8 hal_addr_search_flags; 364 u8 search_type; 365 366 struct ath11k *ar; 367 struct ieee80211_vif *vif; 368 369 u16 tx_seq_no; 370 struct wmi_wmm_params_all_arg wmm_params; 371 struct list_head list; 372 union { 373 struct { 374 u32 uapsd; 375 } sta; 376 struct { 377 /* 127 stations; wmi limit */ 378 u8 tim_bitmap[16]; 379 u8 tim_len; 380 u32 ssid_len; 381 u8 ssid[IEEE80211_MAX_SSID_LEN]; 382 bool hidden_ssid; 383 /* P2P_IE with NoA attribute for P2P_GO case */ 384 u32 noa_len; 385 u8 *noa_data; 386 } ap; 387 } u; 388 389 bool is_started; 390 bool is_up; 391 bool ftm_responder; 392 bool spectral_enabled; 393 bool ps; 394 u32 aid; 395 u8 bssid[ETH_ALEN]; 396 struct cfg80211_bitrate_mask bitrate_mask; 397 struct delayed_work connection_loss_work; 398 int num_legacy_stations; 399 int rtscts_prot_mode; 400 int txpower; 401 bool rsnie_present; 402 bool wpaie_present; 403 bool bcca_zero_sent; 404 bool do_not_send_tmpl; 405 struct ieee80211_chanctx_conf chanctx; 406 struct ath11k_arp_ns_offload arp_ns_offload; 407 struct ath11k_rekey_data rekey_data; 408 409 struct ath11k_reg_tpc_power_info reg_tpc_info; 410 }; 411 412 struct ath11k_vif_iter { 413 u32 vdev_id; 414 struct ath11k_vif *arvif; 415 }; 416 417 struct ath11k_rx_peer_stats { 418 u64 num_msdu; 419 u64 num_mpdu_fcs_ok; 420 u64 num_mpdu_fcs_err; 421 u64 tcp_msdu_count; 422 u64 udp_msdu_count; 423 u64 other_msdu_count; 424 u64 ampdu_msdu_count; 425 u64 non_ampdu_msdu_count; 426 u64 stbc_count; 427 u64 beamformed_count; 428 u64 mcs_count[HAL_RX_MAX_MCS + 1]; 429 u64 nss_count[HAL_RX_MAX_NSS]; 430 u64 bw_count[HAL_RX_BW_MAX]; 431 u64 gi_count[HAL_RX_GI_MAX]; 432 u64 coding_count[HAL_RX_SU_MU_CODING_MAX]; 433 u64 tid_count[IEEE80211_NUM_TIDS + 1]; 434 u64 pream_cnt[HAL_RX_PREAMBLE_MAX]; 435 u64 reception_type[HAL_RX_RECEPTION_TYPE_MAX]; 436 u64 rx_duration; 437 u64 dcm_count; 438 u64 ru_alloc_cnt[HAL_RX_RU_ALLOC_TYPE_MAX]; 439 }; 440 441 #define ATH11K_HE_MCS_NUM 12 442 #define ATH11K_VHT_MCS_NUM 10 443 #define ATH11K_BW_NUM 4 444 #define ATH11K_NSS_NUM 4 445 #define ATH11K_LEGACY_NUM 12 446 #define ATH11K_GI_NUM 4 447 #define ATH11K_HT_MCS_NUM 32 448 449 enum ath11k_pkt_rx_err { 450 ATH11K_PKT_RX_ERR_FCS, 451 ATH11K_PKT_RX_ERR_TKIP, 452 ATH11K_PKT_RX_ERR_CRYPT, 453 ATH11K_PKT_RX_ERR_PEER_IDX_INVAL, 454 ATH11K_PKT_RX_ERR_MAX, 455 }; 456 457 enum ath11k_ampdu_subfrm_num { 458 ATH11K_AMPDU_SUBFRM_NUM_10, 459 ATH11K_AMPDU_SUBFRM_NUM_20, 460 ATH11K_AMPDU_SUBFRM_NUM_30, 461 ATH11K_AMPDU_SUBFRM_NUM_40, 462 ATH11K_AMPDU_SUBFRM_NUM_50, 463 ATH11K_AMPDU_SUBFRM_NUM_60, 464 ATH11K_AMPDU_SUBFRM_NUM_MORE, 465 ATH11K_AMPDU_SUBFRM_NUM_MAX, 466 }; 467 468 enum ath11k_amsdu_subfrm_num { 469 ATH11K_AMSDU_SUBFRM_NUM_1, 470 ATH11K_AMSDU_SUBFRM_NUM_2, 471 ATH11K_AMSDU_SUBFRM_NUM_3, 472 ATH11K_AMSDU_SUBFRM_NUM_4, 473 ATH11K_AMSDU_SUBFRM_NUM_MORE, 474 ATH11K_AMSDU_SUBFRM_NUM_MAX, 475 }; 476 477 enum ath11k_counter_type { 478 ATH11K_COUNTER_TYPE_BYTES, 479 ATH11K_COUNTER_TYPE_PKTS, 480 ATH11K_COUNTER_TYPE_MAX, 481 }; 482 483 enum ath11k_stats_type { 484 ATH11K_STATS_TYPE_SUCC, 485 ATH11K_STATS_TYPE_FAIL, 486 ATH11K_STATS_TYPE_RETRY, 487 ATH11K_STATS_TYPE_AMPDU, 488 ATH11K_STATS_TYPE_MAX, 489 }; 490 491 struct ath11k_htt_data_stats { 492 u64 legacy[ATH11K_COUNTER_TYPE_MAX][ATH11K_LEGACY_NUM]; 493 u64 ht[ATH11K_COUNTER_TYPE_MAX][ATH11K_HT_MCS_NUM]; 494 u64 vht[ATH11K_COUNTER_TYPE_MAX][ATH11K_VHT_MCS_NUM]; 495 u64 he[ATH11K_COUNTER_TYPE_MAX][ATH11K_HE_MCS_NUM]; 496 u64 bw[ATH11K_COUNTER_TYPE_MAX][ATH11K_BW_NUM]; 497 u64 nss[ATH11K_COUNTER_TYPE_MAX][ATH11K_NSS_NUM]; 498 u64 gi[ATH11K_COUNTER_TYPE_MAX][ATH11K_GI_NUM]; 499 }; 500 501 struct ath11k_htt_tx_stats { 502 struct ath11k_htt_data_stats stats[ATH11K_STATS_TYPE_MAX]; 503 u64 tx_duration; 504 u64 ba_fails; 505 u64 ack_fails; 506 }; 507 508 struct ath11k_per_ppdu_tx_stats { 509 u16 succ_pkts; 510 u16 failed_pkts; 511 u16 retry_pkts; 512 u32 succ_bytes; 513 u32 failed_bytes; 514 u32 retry_bytes; 515 }; 516 517 DECLARE_EWMA(avg_rssi, 10, 8) 518 519 struct ath11k_sta { 520 struct ath11k_vif *arvif; 521 522 /* the following are protected by ar->data_lock */ 523 u32 changed; /* IEEE80211_RC_* */ 524 u32 bw; 525 u32 nss; 526 u32 smps; 527 enum hal_pn_type pn_type; 528 529 struct work_struct update_wk; 530 struct work_struct set_4addr_wk; 531 struct rate_info txrate; 532 u32 peer_nss; 533 struct rate_info last_txrate; 534 u64 rx_duration; 535 u64 tx_duration; 536 u8 rssi_comb; 537 struct ewma_avg_rssi avg_rssi; 538 s8 rssi_beacon; 539 s8 chain_signal[IEEE80211_MAX_CHAINS]; 540 struct ath11k_htt_tx_stats *tx_stats; 541 struct ath11k_rx_peer_stats *rx_stats; 542 543 #ifdef CONFIG_MAC80211_DEBUGFS 544 /* protected by conf_mutex */ 545 bool aggr_mode; 546 #endif 547 548 bool use_4addr_set; 549 u16 tcl_metadata; 550 551 /* Protected with ar->data_lock */ 552 enum ath11k_wmi_peer_ps_state peer_ps_state; 553 u64 ps_start_time; 554 u64 ps_start_jiffies; 555 u64 ps_total_duration; 556 bool peer_current_ps_valid; 557 558 u32 bw_prev; 559 }; 560 561 #define ATH11K_MIN_5G_FREQ 4150 562 #define ATH11K_MIN_6G_FREQ 5925 563 #define ATH11K_MAX_6G_FREQ 7115 564 #define ATH11K_NUM_CHANS 102 565 #define ATH11K_MAX_5G_CHAN 177 566 567 enum ath11k_state { 568 ATH11K_STATE_OFF, 569 ATH11K_STATE_ON, 570 ATH11K_STATE_RESTARTING, 571 ATH11K_STATE_RESTARTED, 572 ATH11K_STATE_WEDGED, 573 ATH11K_STATE_FTM, 574 /* Add other states as required */ 575 }; 576 577 /* Antenna noise floor */ 578 #define ATH11K_DEFAULT_NOISE_FLOOR -95 579 580 #define ATH11K_INVALID_RSSI_FULL -1 581 582 #define ATH11K_INVALID_RSSI_EMPTY -128 583 584 struct ath11k_fw_stats { 585 struct dentry *debugfs_fwstats; 586 u32 pdev_id; 587 u32 stats_id; 588 struct list_head pdevs; 589 struct list_head vdevs; 590 struct list_head bcn; 591 }; 592 593 struct ath11k_dbg_htt_stats { 594 u8 type; 595 u8 reset; 596 struct debug_htt_stats_req *stats_req; 597 /* protects shared stats req buffer */ 598 spinlock_t lock; 599 }; 600 601 #define MAX_MODULE_ID_BITMAP_WORDS 16 602 603 struct ath11k_debug { 604 struct dentry *debugfs_pdev; 605 struct ath11k_dbg_htt_stats htt_stats; 606 u32 extd_tx_stats; 607 u32 extd_rx_stats; 608 u32 pktlog_filter; 609 u32 pktlog_mode; 610 u32 pktlog_peer_valid; 611 u8 pktlog_peer_addr[ETH_ALEN]; 612 u32 rx_filter; 613 u32 mem_offset; 614 u32 module_id_bitmap[MAX_MODULE_ID_BITMAP_WORDS]; 615 struct ath11k_debug_dbr *dbr_debug[WMI_DIRECT_BUF_MAX]; 616 }; 617 618 struct ath11k_per_peer_tx_stats { 619 u32 succ_bytes; 620 u32 retry_bytes; 621 u32 failed_bytes; 622 u16 succ_pkts; 623 u16 retry_pkts; 624 u16 failed_pkts; 625 u32 duration; 626 u8 ba_fails; 627 bool is_ampdu; 628 }; 629 630 #define ATH11K_FLUSH_TIMEOUT (5 * HZ) 631 #define ATH11K_VDEV_DELETE_TIMEOUT_HZ (5 * HZ) 632 633 struct ath11k { 634 struct ath11k_base *ab; 635 struct ath11k_pdev *pdev; 636 struct ieee80211_hw *hw; 637 struct ath11k_pdev_wmi *wmi; 638 struct ath11k_pdev_dp dp; 639 u8 mac_addr[ETH_ALEN]; 640 struct ath11k_he ar_he; 641 enum ath11k_state state; 642 bool supports_6ghz; 643 struct { 644 struct completion started; 645 struct completion completed; 646 struct completion on_channel; 647 struct delayed_work timeout; 648 enum ath11k_scan_state state; 649 bool is_roc; 650 int vdev_id; 651 int roc_freq; 652 bool roc_notify; 653 } scan; 654 655 struct { 656 struct ieee80211_supported_band sbands[NUM_NL80211_BANDS]; 657 struct ieee80211_sband_iftype_data 658 iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES]; 659 } mac; 660 661 unsigned long dev_flags; 662 unsigned int filter_flags; 663 unsigned long monitor_flags; 664 u32 min_tx_power; 665 u32 max_tx_power; 666 u32 txpower_limit_2g; 667 u32 txpower_limit_5g; 668 u32 txpower_scale; 669 u32 power_scale; 670 u32 chan_tx_pwr; 671 u32 num_stations; 672 u32 max_num_stations; 673 /* To synchronize concurrent synchronous mac80211 callback operations, 674 * concurrent debugfs configuration and concurrent FW statistics events. 675 */ 676 struct mutex conf_mutex; 677 /* protects the radio specific data like debug stats, ppdu_stats_info stats, 678 * vdev_stop_status info, scan data, ath11k_sta info, ath11k_vif info, 679 * channel context data, survey info, test mode data. 680 */ 681 spinlock_t data_lock; 682 683 struct list_head arvifs; 684 /* should never be NULL; needed for regular htt rx */ 685 struct ieee80211_channel *rx_channel; 686 687 /* valid during scan; needed for mgmt rx during scan */ 688 struct ieee80211_channel *scan_channel; 689 690 u8 cfg_tx_chainmask; 691 u8 cfg_rx_chainmask; 692 u8 num_rx_chains; 693 u8 num_tx_chains; 694 /* pdev_idx starts from 0 whereas pdev->pdev_id starts with 1 */ 695 u8 pdev_idx; 696 u8 lmac_id; 697 698 struct completion peer_assoc_done; 699 struct completion peer_delete_done; 700 701 int install_key_status; 702 struct completion install_key_done; 703 704 int last_wmi_vdev_start_status; 705 struct completion vdev_setup_done; 706 struct completion vdev_delete_done; 707 708 int num_peers; 709 int max_num_peers; 710 u32 num_started_vdevs; 711 u32 num_created_vdevs; 712 unsigned long long allocated_vdev_map; 713 714 struct idr txmgmt_idr; 715 /* protects txmgmt_idr data */ 716 spinlock_t txmgmt_idr_lock; 717 atomic_t num_pending_mgmt_tx; 718 wait_queue_head_t txmgmt_empty_waitq; 719 720 /* cycle count is reported twice for each visited channel during scan. 721 * access protected by data_lock 722 */ 723 u32 survey_last_rx_clear_count; 724 u32 survey_last_cycle_count; 725 726 /* Channel info events are expected to come in pairs without and with 727 * COMPLETE flag set respectively for each channel visit during scan. 728 * 729 * However there are deviations from this rule. This flag is used to 730 * avoid reporting garbage data. 731 */ 732 bool ch_info_can_report_survey; 733 struct survey_info survey[ATH11K_NUM_CHANS]; 734 struct completion bss_survey_done; 735 736 struct work_struct regd_update_work; 737 738 struct work_struct wmi_mgmt_tx_work; 739 struct sk_buff_head wmi_mgmt_tx_queue; 740 741 struct ath11k_wow wow; 742 struct completion target_suspend; 743 bool target_suspend_ack; 744 struct ath11k_per_peer_tx_stats peer_tx_stats; 745 struct list_head ppdu_stats_info; 746 u32 ppdu_stat_list_depth; 747 748 struct ath11k_per_peer_tx_stats cached_stats; 749 u32 last_ppdu_id; 750 u32 cached_ppdu_id; 751 int monitor_vdev_id; 752 struct completion fw_mode_reset; 753 u8 ftm_msgref; 754 #ifdef CONFIG_ATH11K_DEBUGFS 755 struct ath11k_debug debug; 756 #endif 757 #ifdef CONFIG_ATH11K_SPECTRAL 758 struct ath11k_spectral spectral; 759 #endif 760 bool dfs_block_radar_events; 761 struct ath11k_thermal thermal; 762 u32 vdev_id_11d_scan; 763 struct completion completed_11d_scan; 764 enum ath11k_11d_state state_11d; 765 bool regdom_set_by_user; 766 int hw_rate_code; 767 u8 twt_enabled; 768 bool nlo_enabled; 769 u8 alpha2[REG_ALPHA2_LEN + 1]; 770 struct ath11k_fw_stats fw_stats; 771 struct completion fw_stats_complete; 772 bool fw_stats_done; 773 774 /* protected by conf_mutex */ 775 bool ps_state_enable; 776 bool ps_timekeeper_enable; 777 s8 max_allowed_tx_power; 778 }; 779 780 struct ath11k_band_cap { 781 u32 phy_id; 782 u32 max_bw_supported; 783 u32 ht_cap_info; 784 u32 he_cap_info[2]; 785 u32 he_mcs; 786 u32 he_cap_phy_info[PSOC_HOST_MAX_PHY_SIZE]; 787 struct ath11k_ppe_threshold he_ppet; 788 u16 he_6ghz_capa; 789 }; 790 791 struct ath11k_pdev_cap { 792 u32 supported_bands; 793 u32 ampdu_density; 794 u32 vht_cap; 795 u32 vht_mcs; 796 u32 he_mcs; 797 u32 tx_chain_mask; 798 u32 rx_chain_mask; 799 u32 tx_chain_mask_shift; 800 u32 rx_chain_mask_shift; 801 struct ath11k_band_cap band[NUM_NL80211_BANDS]; 802 bool nss_ratio_enabled; 803 u8 nss_ratio_info; 804 }; 805 806 struct ath11k_pdev { 807 struct ath11k *ar; 808 u32 pdev_id; 809 struct ath11k_pdev_cap cap; 810 u8 mac_addr[ETH_ALEN]; 811 }; 812 813 struct ath11k_board_data { 814 const struct firmware *fw; 815 const void *data; 816 size_t len; 817 }; 818 819 struct ath11k_pci_ops { 820 int (*wakeup)(struct ath11k_base *ab); 821 void (*release)(struct ath11k_base *ab); 822 int (*get_msi_irq)(struct ath11k_base *ab, unsigned int vector); 823 void (*window_write32)(struct ath11k_base *ab, u32 offset, u32 value); 824 u32 (*window_read32)(struct ath11k_base *ab, u32 offset); 825 }; 826 827 /* IPQ8074 HW channel counters frequency value in hertz */ 828 #define IPQ8074_CC_FREQ_HERTZ 320000 829 830 struct ath11k_bp_stats { 831 /* Head Pointer reported by the last HTT Backpressure event for the ring */ 832 u16 hp; 833 834 /* Tail Pointer reported by the last HTT Backpressure event for the ring */ 835 u16 tp; 836 837 /* Number of Backpressure events received for the ring */ 838 u32 count; 839 840 /* Last recorded event timestamp */ 841 unsigned long jiffies; 842 }; 843 844 struct ath11k_dp_ring_bp_stats { 845 struct ath11k_bp_stats umac_ring_bp_stats[HTT_SW_UMAC_RING_IDX_MAX]; 846 struct ath11k_bp_stats lmac_ring_bp_stats[HTT_SW_LMAC_RING_IDX_MAX][MAX_RADIOS]; 847 }; 848 849 struct ath11k_soc_dp_tx_err_stats { 850 /* TCL Ring Descriptor unavailable */ 851 u32 desc_na[DP_TCL_NUM_RING_MAX]; 852 /* Other failures during dp_tx due to mem allocation failure 853 * idr unavailable etc. 854 */ 855 atomic_t misc_fail; 856 }; 857 858 struct ath11k_soc_dp_stats { 859 u32 err_ring_pkts; 860 u32 invalid_rbm; 861 u32 rxdma_error[HAL_REO_ENTR_RING_RXDMA_ECODE_MAX]; 862 u32 reo_error[HAL_REO_DEST_RING_ERROR_CODE_MAX]; 863 u32 hal_reo_error[DP_REO_DST_RING_MAX]; 864 struct ath11k_soc_dp_tx_err_stats tx_err; 865 struct ath11k_dp_ring_bp_stats bp_stats; 866 }; 867 868 struct ath11k_msi_user { 869 char *name; 870 int num_vectors; 871 u32 base_vector; 872 }; 873 874 struct ath11k_msi_config { 875 int total_vectors; 876 int total_users; 877 struct ath11k_msi_user *users; 878 u16 hw_rev; 879 }; 880 881 /* Master structure to hold the hw data which may be used in core module */ 882 struct ath11k_base { 883 enum ath11k_hw_rev hw_rev; 884 enum ath11k_firmware_mode fw_mode; 885 struct platform_device *pdev; 886 struct device *dev; 887 struct ath11k_qmi qmi; 888 struct ath11k_wmi_base wmi_ab; 889 struct completion fw_ready; 890 int num_radios; 891 /* HW channel counters frequency value in hertz common to all MACs */ 892 u32 cc_freq_hz; 893 894 struct ath11k_htc htc; 895 896 struct ath11k_dp dp; 897 898 void __iomem *mem; 899 void __iomem *mem_ce; 900 unsigned long mem_len; 901 902 struct { 903 enum ath11k_bus bus; 904 const struct ath11k_hif_ops *ops; 905 } hif; 906 907 struct { 908 struct completion wakeup_completed; 909 } wow; 910 911 struct ath11k_ce ce; 912 struct timer_list rx_replenish_retry; 913 struct ath11k_hal hal; 914 /* To synchronize core_start/core_stop */ 915 struct mutex core_lock; 916 /* Protects data like peers */ 917 spinlock_t base_lock; 918 struct ath11k_pdev pdevs[MAX_RADIOS]; 919 struct { 920 enum WMI_HOST_WLAN_BAND supported_bands; 921 u32 pdev_id; 922 } target_pdev_ids[MAX_RADIOS]; 923 u8 target_pdev_count; 924 struct ath11k_pdev __rcu *pdevs_active[MAX_RADIOS]; 925 struct ath11k_hal_reg_capabilities_ext hal_reg_cap[MAX_RADIOS]; 926 unsigned long long free_vdev_map; 927 928 /* To synchronize rhash tbl write operation */ 929 struct mutex tbl_mtx_lock; 930 931 /* The rhashtable containing struct ath11k_peer keyed by mac addr */ 932 struct rhashtable *rhead_peer_addr; 933 struct rhashtable_params rhash_peer_addr_param; 934 935 /* The rhashtable containing struct ath11k_peer keyed by id */ 936 struct rhashtable *rhead_peer_id; 937 struct rhashtable_params rhash_peer_id_param; 938 939 struct list_head peers; 940 wait_queue_head_t peer_mapping_wq; 941 u8 mac_addr[ETH_ALEN]; 942 int irq_num[ATH11K_IRQ_NUM_MAX]; 943 struct ath11k_ext_irq_grp ext_irq_grp[ATH11K_EXT_IRQ_GRP_NUM_MAX]; 944 struct ath11k_targ_cap target_caps; 945 u32 ext_service_bitmap[WMI_SERVICE_EXT_BM_SIZE]; 946 bool pdevs_macaddr_valid; 947 948 struct ath11k_hw_params hw_params; 949 950 const struct firmware *cal_file; 951 952 /* Below regd's are protected by ab->data_lock */ 953 /* This is the regd set for every radio 954 * by the firmware during initialization 955 */ 956 struct ieee80211_regdomain *default_regd[MAX_RADIOS]; 957 /* This regd is set during dynamic country setting 958 * This may or may not be used during the runtime 959 */ 960 struct ieee80211_regdomain *new_regd[MAX_RADIOS]; 961 struct cur_regulatory_info *reg_info_store; 962 963 /* Current DFS Regulatory */ 964 enum ath11k_dfs_region dfs_region; 965 #ifdef CONFIG_ATH11K_DEBUGFS 966 struct dentry *debugfs_soc; 967 #endif 968 struct ath11k_soc_dp_stats soc_stats; 969 970 unsigned long dev_flags; 971 struct completion driver_recovery; 972 struct workqueue_struct *workqueue; 973 struct work_struct restart_work; 974 struct work_struct update_11d_work; 975 u8 new_alpha2[3]; 976 struct workqueue_struct *workqueue_aux; 977 struct work_struct reset_work; 978 atomic_t reset_count; 979 atomic_t recovery_count; 980 atomic_t recovery_start_count; 981 bool is_reset; 982 struct completion reset_complete; 983 struct completion reconfigure_complete; 984 struct completion recovery_start; 985 /* continuous recovery fail count */ 986 atomic_t fail_cont_count; 987 unsigned long reset_fail_timeout; 988 struct { 989 /* protected by data_lock */ 990 u32 fw_crash_counter; 991 } stats; 992 u32 pktlog_defs_checksum; 993 994 struct ath11k_dbring_cap *db_caps; 995 u32 num_db_cap; 996 997 /* To synchronize 11d scan vdev id */ 998 struct mutex vdev_id_11d_lock; 999 struct timer_list mon_reap_timer; 1000 1001 struct completion htc_suspend; 1002 1003 struct { 1004 enum ath11k_bdf_search bdf_search; 1005 u32 vendor; 1006 u32 device; 1007 u32 subsystem_vendor; 1008 u32 subsystem_device; 1009 } id; 1010 1011 struct { 1012 struct { 1013 const struct ath11k_msi_config *config; 1014 u32 ep_base_data; 1015 u32 irqs[32]; 1016 u32 addr_lo; 1017 u32 addr_hi; 1018 } msi; 1019 1020 const struct ath11k_pci_ops *ops; 1021 } pci; 1022 1023 struct { 1024 u32 api_version; 1025 1026 const struct firmware *fw; 1027 const u8 *amss_data; 1028 size_t amss_len; 1029 const u8 *m3_data; 1030 size_t m3_len; 1031 1032 DECLARE_BITMAP(fw_features, ATH11K_FW_FEATURE_COUNT); 1033 } fw; 1034 1035 #ifdef CONFIG_NL80211_TESTMODE 1036 struct { 1037 u32 data_pos; 1038 u32 expected_seq; 1039 u8 *eventdata; 1040 } testmode; 1041 #endif 1042 1043 /* must be last */ 1044 u8 drv_priv[] __aligned(sizeof(void *)); 1045 }; 1046 1047 struct ath11k_fw_stats_pdev { 1048 struct list_head list; 1049 1050 /* PDEV stats */ 1051 s32 ch_noise_floor; 1052 /* Cycles spent transmitting frames */ 1053 u32 tx_frame_count; 1054 /* Cycles spent receiving frames */ 1055 u32 rx_frame_count; 1056 /* Total channel busy time, evidently */ 1057 u32 rx_clear_count; 1058 /* Total on-channel time */ 1059 u32 cycle_count; 1060 u32 phy_err_count; 1061 u32 chan_tx_power; 1062 u32 ack_rx_bad; 1063 u32 rts_bad; 1064 u32 rts_good; 1065 u32 fcs_bad; 1066 u32 no_beacons; 1067 u32 mib_int_count; 1068 1069 /* PDEV TX stats */ 1070 /* Num HTT cookies queued to dispatch list */ 1071 s32 comp_queued; 1072 /* Num HTT cookies dispatched */ 1073 s32 comp_delivered; 1074 /* Num MSDU queued to WAL */ 1075 s32 msdu_enqued; 1076 /* Num MPDU queue to WAL */ 1077 s32 mpdu_enqued; 1078 /* Num MSDUs dropped by WMM limit */ 1079 s32 wmm_drop; 1080 /* Num Local frames queued */ 1081 s32 local_enqued; 1082 /* Num Local frames done */ 1083 s32 local_freed; 1084 /* Num queued to HW */ 1085 s32 hw_queued; 1086 /* Num PPDU reaped from HW */ 1087 s32 hw_reaped; 1088 /* Num underruns */ 1089 s32 underrun; 1090 /* Num hw paused */ 1091 u32 hw_paused; 1092 /* Num PPDUs cleaned up in TX abort */ 1093 s32 tx_abort; 1094 /* Num MPDUs requeued by SW */ 1095 s32 mpdus_requeued; 1096 /* excessive retries */ 1097 u32 tx_ko; 1098 u32 tx_xretry; 1099 /* data hw rate code */ 1100 u32 data_rc; 1101 /* Scheduler self triggers */ 1102 u32 self_triggers; 1103 /* frames dropped due to excessive sw retries */ 1104 u32 sw_retry_failure; 1105 /* illegal rate phy errors */ 1106 u32 illgl_rate_phy_err; 1107 /* wal pdev continuous xretry */ 1108 u32 pdev_cont_xretry; 1109 /* wal pdev tx timeouts */ 1110 u32 pdev_tx_timeout; 1111 /* wal pdev resets */ 1112 u32 pdev_resets; 1113 /* frames dropped due to non-availability of stateless TIDs */ 1114 u32 stateless_tid_alloc_failure; 1115 /* PhY/BB underrun */ 1116 u32 phy_underrun; 1117 /* MPDU is more than txop limit */ 1118 u32 txop_ovf; 1119 /* Num sequences posted */ 1120 u32 seq_posted; 1121 /* Num sequences failed in queueing */ 1122 u32 seq_failed_queueing; 1123 /* Num sequences completed */ 1124 u32 seq_completed; 1125 /* Num sequences restarted */ 1126 u32 seq_restarted; 1127 /* Num of MU sequences posted */ 1128 u32 mu_seq_posted; 1129 /* Num MPDUs flushed by SW, HWPAUSED, SW TXABORT 1130 * (Reset,channel change) 1131 */ 1132 s32 mpdus_sw_flush; 1133 /* Num MPDUs filtered by HW, all filter condition (TTL expired) */ 1134 s32 mpdus_hw_filter; 1135 /* Num MPDUs truncated by PDG (TXOP, TBTT, 1136 * PPDU_duration based on rate, dyn_bw) 1137 */ 1138 s32 mpdus_truncated; 1139 /* Num MPDUs that was tried but didn't receive ACK or BA */ 1140 s32 mpdus_ack_failed; 1141 /* Num MPDUs that was dropped du to expiry. */ 1142 s32 mpdus_expired; 1143 1144 /* PDEV RX stats */ 1145 /* Cnts any change in ring routing mid-ppdu */ 1146 s32 mid_ppdu_route_change; 1147 /* Total number of statuses processed */ 1148 s32 status_rcvd; 1149 /* Extra frags on rings 0-3 */ 1150 s32 r0_frags; 1151 s32 r1_frags; 1152 s32 r2_frags; 1153 s32 r3_frags; 1154 /* MSDUs / MPDUs delivered to HTT */ 1155 s32 htt_msdus; 1156 s32 htt_mpdus; 1157 /* MSDUs / MPDUs delivered to local stack */ 1158 s32 loc_msdus; 1159 s32 loc_mpdus; 1160 /* AMSDUs that have more MSDUs than the status ring size */ 1161 s32 oversize_amsdu; 1162 /* Number of PHY errors */ 1163 s32 phy_errs; 1164 /* Number of PHY errors drops */ 1165 s32 phy_err_drop; 1166 /* Number of mpdu errors - FCS, MIC, ENC etc. */ 1167 s32 mpdu_errs; 1168 /* Num overflow errors */ 1169 s32 rx_ovfl_errs; 1170 }; 1171 1172 struct ath11k_fw_stats_vdev { 1173 struct list_head list; 1174 1175 u32 vdev_id; 1176 u32 beacon_snr; 1177 u32 data_snr; 1178 u32 num_tx_frames[WLAN_MAX_AC]; 1179 u32 num_rx_frames; 1180 u32 num_tx_frames_retries[WLAN_MAX_AC]; 1181 u32 num_tx_frames_failures[WLAN_MAX_AC]; 1182 u32 num_rts_fail; 1183 u32 num_rts_success; 1184 u32 num_rx_err; 1185 u32 num_rx_discard; 1186 u32 num_tx_not_acked; 1187 u32 tx_rate_history[MAX_TX_RATE_VALUES]; 1188 u32 beacon_rssi_history[MAX_TX_RATE_VALUES]; 1189 }; 1190 1191 struct ath11k_fw_stats_bcn { 1192 struct list_head list; 1193 1194 u32 vdev_id; 1195 u32 tx_bcn_succ_cnt; 1196 u32 tx_bcn_outage_cnt; 1197 }; 1198 1199 void ath11k_fw_stats_init(struct ath11k *ar); 1200 void ath11k_fw_stats_pdevs_free(struct list_head *head); 1201 void ath11k_fw_stats_vdevs_free(struct list_head *head); 1202 void ath11k_fw_stats_bcn_free(struct list_head *head); 1203 void ath11k_fw_stats_free(struct ath11k_fw_stats *stats); 1204 1205 extern const struct ce_pipe_config ath11k_target_ce_config_wlan_ipq8074[]; 1206 extern const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq8074[]; 1207 extern const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq6018[]; 1208 1209 extern const struct ce_pipe_config ath11k_target_ce_config_wlan_qca6390[]; 1210 extern const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qca6390[]; 1211 1212 extern const struct ce_pipe_config ath11k_target_ce_config_wlan_ipq5018[]; 1213 extern const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq5018[]; 1214 1215 extern const struct ce_pipe_config ath11k_target_ce_config_wlan_qcn9074[]; 1216 extern const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qcn9074[]; 1217 int ath11k_core_qmi_firmware_ready(struct ath11k_base *ab); 1218 int ath11k_core_pre_init(struct ath11k_base *ab); 1219 int ath11k_core_init(struct ath11k_base *ath11k); 1220 void ath11k_core_deinit(struct ath11k_base *ath11k); 1221 struct ath11k_base *ath11k_core_alloc(struct device *dev, size_t priv_size, 1222 enum ath11k_bus bus); 1223 void ath11k_core_free(struct ath11k_base *ath11k); 1224 int ath11k_core_fetch_bdf(struct ath11k_base *ath11k, 1225 struct ath11k_board_data *bd); 1226 int ath11k_core_fetch_regdb(struct ath11k_base *ab, struct ath11k_board_data *bd); 1227 int ath11k_core_fetch_board_data_api_1(struct ath11k_base *ab, 1228 struct ath11k_board_data *bd, 1229 const char *name); 1230 void ath11k_core_free_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd); 1231 int ath11k_core_check_dt(struct ath11k_base *ath11k); 1232 int ath11k_core_check_smbios(struct ath11k_base *ab); 1233 void ath11k_core_halt(struct ath11k *ar); 1234 int ath11k_core_resume(struct ath11k_base *ab); 1235 int ath11k_core_suspend(struct ath11k_base *ab); 1236 void ath11k_core_pre_reconfigure_recovery(struct ath11k_base *ab); 1237 bool ath11k_core_coldboot_cal_support(struct ath11k_base *ab); 1238 1239 const struct firmware *ath11k_core_firmware_request(struct ath11k_base *ab, 1240 const char *filename); 1241 1242 static inline const char *ath11k_scan_state_str(enum ath11k_scan_state state) 1243 { 1244 switch (state) { 1245 case ATH11K_SCAN_IDLE: 1246 return "idle"; 1247 case ATH11K_SCAN_STARTING: 1248 return "starting"; 1249 case ATH11K_SCAN_RUNNING: 1250 return "running"; 1251 case ATH11K_SCAN_ABORTING: 1252 return "aborting"; 1253 } 1254 1255 return "unknown"; 1256 } 1257 1258 static inline struct ath11k_skb_cb *ATH11K_SKB_CB(struct sk_buff *skb) 1259 { 1260 BUILD_BUG_ON(sizeof(struct ath11k_skb_cb) > 1261 IEEE80211_TX_INFO_DRIVER_DATA_SIZE); 1262 return (struct ath11k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data; 1263 } 1264 1265 static inline struct ath11k_skb_rxcb *ATH11K_SKB_RXCB(struct sk_buff *skb) 1266 { 1267 BUILD_BUG_ON(sizeof(struct ath11k_skb_rxcb) > sizeof(skb->cb)); 1268 return (struct ath11k_skb_rxcb *)skb->cb; 1269 } 1270 1271 static inline struct ath11k_vif *ath11k_vif_to_arvif(struct ieee80211_vif *vif) 1272 { 1273 return (struct ath11k_vif *)vif->drv_priv; 1274 } 1275 1276 static inline struct ath11k_sta *ath11k_sta_to_arsta(struct ieee80211_sta *sta) 1277 { 1278 return (struct ath11k_sta *)sta->drv_priv; 1279 } 1280 1281 static inline struct ath11k *ath11k_ab_to_ar(struct ath11k_base *ab, 1282 int mac_id) 1283 { 1284 return ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar; 1285 } 1286 1287 static inline void ath11k_core_create_firmware_path(struct ath11k_base *ab, 1288 const char *filename, 1289 void *buf, size_t buf_len) 1290 { 1291 snprintf(buf, buf_len, "%s/%s/%s", ATH11K_FW_DIR, 1292 ab->hw_params.fw.dir, filename); 1293 } 1294 1295 static inline const char *ath11k_bus_str(enum ath11k_bus bus) 1296 { 1297 switch (bus) { 1298 case ATH11K_BUS_PCI: 1299 return "pci"; 1300 case ATH11K_BUS_AHB: 1301 return "ahb"; 1302 } 1303 1304 return "unknown"; 1305 } 1306 1307 #endif /* _CORE_H_ */ 1308