1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 5 */ 6 7 #include <linux/export.h> 8 #include <linux/module.h> 9 #include <linux/slab.h> 10 #include <linux/remoteproc.h> 11 #include <linux/firmware.h> 12 #include <linux/of.h> 13 14 #include "core.h" 15 #include "dp_tx.h" 16 #include "dp_rx.h" 17 #include "debug.h" 18 #include "hif.h" 19 #include "wow.h" 20 #include "fw.h" 21 22 unsigned int ath11k_debug_mask; 23 EXPORT_SYMBOL(ath11k_debug_mask); 24 module_param_named(debug_mask, ath11k_debug_mask, uint, 0644); 25 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 26 27 static unsigned int ath11k_crypto_mode; 28 module_param_named(crypto_mode, ath11k_crypto_mode, uint, 0644); 29 MODULE_PARM_DESC(crypto_mode, "crypto mode: 0-hardware, 1-software"); 30 31 /* frame mode values are mapped as per enum ath11k_hw_txrx_mode */ 32 unsigned int ath11k_frame_mode = ATH11K_HW_TXRX_NATIVE_WIFI; 33 module_param_named(frame_mode, ath11k_frame_mode, uint, 0644); 34 MODULE_PARM_DESC(frame_mode, 35 "Datapath frame mode (0: raw, 1: native wifi (default), 2: ethernet)"); 36 37 bool ath11k_ftm_mode; 38 module_param_named(ftm_mode, ath11k_ftm_mode, bool, 0444); 39 MODULE_PARM_DESC(ftm_mode, "Boots up in factory test mode"); 40 41 static const struct ath11k_hw_params ath11k_hw_params[] = { 42 { 43 .hw_rev = ATH11K_HW_IPQ8074, 44 .name = "ipq8074 hw2.0", 45 .fw = { 46 .dir = "IPQ8074/hw2.0", 47 .board_size = 256 * 1024, 48 .cal_offset = 128 * 1024, 49 }, 50 .max_radios = 3, 51 .bdf_addr = 0x4B0C0000, 52 .hw_ops = &ipq8074_ops, 53 .ring_mask = &ath11k_hw_ring_mask_ipq8074, 54 .internal_sleep_clock = false, 55 .regs = &ipq8074_regs, 56 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074, 57 .host_ce_config = ath11k_host_ce_config_ipq8074, 58 .ce_count = 12, 59 .target_ce_config = ath11k_target_ce_config_wlan_ipq8074, 60 .target_ce_count = 11, 61 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq8074, 62 .svc_to_ce_map_len = 21, 63 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 64 .single_pdev_only = false, 65 .rxdma1_enable = true, 66 .num_rxdma_per_pdev = 1, 67 .rx_mac_buf_ring = false, 68 .vdev_start_delay = false, 69 .htt_peer_map_v2 = true, 70 71 .spectral = { 72 .fft_sz = 2, 73 /* HW bug, expected BIN size is 2 bytes but HW report as 4 bytes. 74 * so added pad size as 2 bytes to compensate the BIN size 75 */ 76 .fft_pad_sz = 2, 77 .summary_pad_sz = 0, 78 .fft_hdr_len = 16, 79 .max_fft_bins = 512, 80 .fragment_160mhz = true, 81 }, 82 83 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 84 BIT(NL80211_IFTYPE_AP) | 85 BIT(NL80211_IFTYPE_MESH_POINT), 86 .supports_monitor = true, 87 .full_monitor_mode = false, 88 .supports_shadow_regs = false, 89 .idle_ps = false, 90 .supports_sta_ps = false, 91 .coldboot_cal_mm = true, 92 .coldboot_cal_ftm = true, 93 .cbcal_restart_fw = true, 94 .fw_mem_mode = 0, 95 .num_vdevs = 16 + 1, 96 .num_peers = 512, 97 .supports_suspend = false, 98 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074), 99 .supports_regdb = false, 100 .fix_l1ss = true, 101 .credit_flow = false, 102 .hal_params = &ath11k_hw_hal_params_ipq8074, 103 .supports_dynamic_smps_6ghz = false, 104 .alloc_cacheable_memory = true, 105 .supports_rssi_stats = false, 106 .fw_wmi_diag_event = false, 107 .current_cc_support = false, 108 .dbr_debug_support = true, 109 .global_reset = false, 110 .bios_sar_capa = NULL, 111 .m3_fw_support = false, 112 .fixed_bdf_addr = true, 113 .fixed_mem_region = true, 114 .static_window_map = false, 115 .hybrid_bus_type = false, 116 .fixed_fw_mem = false, 117 .support_off_channel_tx = false, 118 .supports_multi_bssid = false, 119 120 .sram_dump = {}, 121 122 .tcl_ring_retry = true, 123 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 124 .smp2p_wow_exit = false, 125 .support_dual_stations = false, 126 .pdev_suspend = false, 127 .cfr_support = true, 128 .cfr_num_stream_bufs = 255, 129 .cfr_stream_buf_size = 8200, 130 }, 131 { 132 .hw_rev = ATH11K_HW_IPQ6018_HW10, 133 .name = "ipq6018 hw1.0", 134 .fw = { 135 .dir = "IPQ6018/hw1.0", 136 .board_size = 256 * 1024, 137 .cal_offset = 128 * 1024, 138 }, 139 .max_radios = 2, 140 .bdf_addr = 0x4ABC0000, 141 .hw_ops = &ipq6018_ops, 142 .ring_mask = &ath11k_hw_ring_mask_ipq8074, 143 .internal_sleep_clock = false, 144 .regs = &ipq8074_regs, 145 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074, 146 .host_ce_config = ath11k_host_ce_config_ipq8074, 147 .ce_count = 12, 148 .target_ce_config = ath11k_target_ce_config_wlan_ipq8074, 149 .target_ce_count = 11, 150 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq6018, 151 .svc_to_ce_map_len = 19, 152 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 153 .single_pdev_only = false, 154 .rxdma1_enable = true, 155 .num_rxdma_per_pdev = 1, 156 .rx_mac_buf_ring = false, 157 .vdev_start_delay = false, 158 .htt_peer_map_v2 = true, 159 160 .spectral = { 161 .fft_sz = 4, 162 .fft_pad_sz = 0, 163 .summary_pad_sz = 0, 164 .fft_hdr_len = 16, 165 .max_fft_bins = 512, 166 .fragment_160mhz = true, 167 }, 168 169 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 170 BIT(NL80211_IFTYPE_AP) | 171 BIT(NL80211_IFTYPE_MESH_POINT), 172 .supports_monitor = true, 173 .full_monitor_mode = false, 174 .supports_shadow_regs = false, 175 .idle_ps = false, 176 .supports_sta_ps = false, 177 .coldboot_cal_mm = true, 178 .coldboot_cal_ftm = true, 179 .cbcal_restart_fw = true, 180 .fw_mem_mode = 0, 181 .num_vdevs = 16 + 1, 182 .num_peers = 512, 183 .supports_suspend = false, 184 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074), 185 .supports_regdb = false, 186 .fix_l1ss = true, 187 .credit_flow = false, 188 .hal_params = &ath11k_hw_hal_params_ipq8074, 189 .supports_dynamic_smps_6ghz = false, 190 .alloc_cacheable_memory = true, 191 .supports_rssi_stats = false, 192 .fw_wmi_diag_event = false, 193 .current_cc_support = false, 194 .dbr_debug_support = true, 195 .global_reset = false, 196 .bios_sar_capa = NULL, 197 .m3_fw_support = false, 198 .fixed_bdf_addr = true, 199 .fixed_mem_region = true, 200 .static_window_map = false, 201 .hybrid_bus_type = false, 202 .fixed_fw_mem = false, 203 .support_off_channel_tx = false, 204 .supports_multi_bssid = false, 205 206 .sram_dump = {}, 207 208 .tcl_ring_retry = true, 209 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 210 .smp2p_wow_exit = false, 211 .support_fw_mac_sequence = false, 212 .support_dual_stations = false, 213 .pdev_suspend = false, 214 .cfr_support = false, 215 .cfr_num_stream_bufs = 0, 216 .cfr_stream_buf_size = 0, 217 }, 218 { 219 .name = "qca6390 hw2.0", 220 .hw_rev = ATH11K_HW_QCA6390_HW20, 221 .fw = { 222 .dir = "QCA6390/hw2.0", 223 .board_size = 256 * 1024, 224 .cal_offset = 128 * 1024, 225 }, 226 .max_radios = 3, 227 .bdf_addr = 0x4B0C0000, 228 .hw_ops = &qca6390_ops, 229 .ring_mask = &ath11k_hw_ring_mask_qca6390, 230 .internal_sleep_clock = true, 231 .regs = &qca6390_regs, 232 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390, 233 .host_ce_config = ath11k_host_ce_config_qca6390, 234 .ce_count = 9, 235 .target_ce_config = ath11k_target_ce_config_wlan_qca6390, 236 .target_ce_count = 9, 237 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, 238 .svc_to_ce_map_len = 14, 239 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 240 .single_pdev_only = true, 241 .rxdma1_enable = false, 242 .num_rxdma_per_pdev = 2, 243 .rx_mac_buf_ring = true, 244 .vdev_start_delay = true, 245 .htt_peer_map_v2 = false, 246 247 .spectral = { 248 .fft_sz = 0, 249 .fft_pad_sz = 0, 250 .summary_pad_sz = 0, 251 .fft_hdr_len = 0, 252 .max_fft_bins = 0, 253 .fragment_160mhz = false, 254 }, 255 256 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 257 BIT(NL80211_IFTYPE_AP) | 258 BIT(NL80211_IFTYPE_P2P_DEVICE) | 259 BIT(NL80211_IFTYPE_P2P_CLIENT) | 260 BIT(NL80211_IFTYPE_P2P_GO), 261 .supports_monitor = false, 262 .full_monitor_mode = false, 263 .supports_shadow_regs = true, 264 .idle_ps = true, 265 .supports_sta_ps = true, 266 .coldboot_cal_mm = false, 267 .coldboot_cal_ftm = false, 268 .cbcal_restart_fw = false, 269 .fw_mem_mode = 0, 270 .num_vdevs = 4, 271 .num_peers = 512, 272 .supports_suspend = true, 273 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074), 274 .supports_regdb = false, 275 .fix_l1ss = true, 276 .credit_flow = true, 277 .hal_params = &ath11k_hw_hal_params_qca6390, 278 .supports_dynamic_smps_6ghz = false, 279 .alloc_cacheable_memory = false, 280 .supports_rssi_stats = true, 281 .fw_wmi_diag_event = true, 282 .current_cc_support = true, 283 .dbr_debug_support = false, 284 .global_reset = true, 285 .bios_sar_capa = NULL, 286 .m3_fw_support = true, 287 .fixed_bdf_addr = false, 288 .fixed_mem_region = false, 289 .static_window_map = false, 290 .hybrid_bus_type = false, 291 .fixed_fw_mem = false, 292 .support_off_channel_tx = true, 293 .supports_multi_bssid = true, 294 295 .sram_dump = { 296 .start = 0x01400000, 297 .end = 0x0171ffff, 298 }, 299 300 .tcl_ring_retry = true, 301 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 302 .smp2p_wow_exit = false, 303 .support_fw_mac_sequence = true, 304 .support_dual_stations = true, 305 .pdev_suspend = false, 306 .cfr_support = false, 307 .cfr_num_stream_bufs = 0, 308 .cfr_stream_buf_size = 0, 309 }, 310 { 311 .name = "qcn9074 hw1.0", 312 .hw_rev = ATH11K_HW_QCN9074_HW10, 313 .fw = { 314 .dir = "QCN9074/hw1.0", 315 .board_size = 256 * 1024, 316 .cal_offset = 128 * 1024, 317 }, 318 .max_radios = 1, 319 .single_pdev_only = false, 320 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9074, 321 .hw_ops = &qcn9074_ops, 322 .ring_mask = &ath11k_hw_ring_mask_qcn9074, 323 .internal_sleep_clock = false, 324 .regs = &qcn9074_regs, 325 .host_ce_config = ath11k_host_ce_config_qcn9074, 326 .ce_count = 6, 327 .target_ce_config = ath11k_target_ce_config_wlan_qcn9074, 328 .target_ce_count = 9, 329 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qcn9074, 330 .svc_to_ce_map_len = 18, 331 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 332 .rxdma1_enable = true, 333 .num_rxdma_per_pdev = 1, 334 .rx_mac_buf_ring = false, 335 .vdev_start_delay = false, 336 .htt_peer_map_v2 = true, 337 338 .spectral = { 339 .fft_sz = 2, 340 .fft_pad_sz = 0, 341 .summary_pad_sz = 16, 342 .fft_hdr_len = 24, 343 .max_fft_bins = 1024, 344 .fragment_160mhz = false, 345 }, 346 347 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 348 BIT(NL80211_IFTYPE_AP) | 349 BIT(NL80211_IFTYPE_MESH_POINT), 350 .supports_monitor = true, 351 .full_monitor_mode = true, 352 .supports_shadow_regs = false, 353 .idle_ps = false, 354 .supports_sta_ps = false, 355 .coldboot_cal_mm = false, 356 .coldboot_cal_ftm = true, 357 .cbcal_restart_fw = true, 358 .fw_mem_mode = 2, 359 .num_vdevs = 8, 360 .num_peers = 128, 361 .supports_suspend = false, 362 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074), 363 .supports_regdb = false, 364 .fix_l1ss = true, 365 .credit_flow = false, 366 .hal_params = &ath11k_hw_hal_params_ipq8074, 367 .supports_dynamic_smps_6ghz = true, 368 .alloc_cacheable_memory = true, 369 .supports_rssi_stats = false, 370 .fw_wmi_diag_event = false, 371 .current_cc_support = false, 372 .dbr_debug_support = true, 373 .global_reset = false, 374 .bios_sar_capa = NULL, 375 .m3_fw_support = true, 376 .fixed_bdf_addr = false, 377 .fixed_mem_region = false, 378 .static_window_map = true, 379 .hybrid_bus_type = false, 380 .fixed_fw_mem = false, 381 .support_off_channel_tx = false, 382 .supports_multi_bssid = false, 383 384 .sram_dump = {}, 385 386 .tcl_ring_retry = true, 387 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 388 .smp2p_wow_exit = false, 389 .support_fw_mac_sequence = false, 390 .support_dual_stations = false, 391 .pdev_suspend = false, 392 .cfr_support = false, 393 .cfr_num_stream_bufs = 0, 394 .cfr_stream_buf_size = 0, 395 }, 396 { 397 .name = "wcn6855 hw2.0", 398 .hw_rev = ATH11K_HW_WCN6855_HW20, 399 .fw = { 400 .dir = "WCN6855/hw2.0", 401 .board_size = 256 * 1024, 402 .cal_offset = 128 * 1024, 403 }, 404 .max_radios = 3, 405 .bdf_addr = 0x4B0C0000, 406 .hw_ops = &wcn6855_ops, 407 .ring_mask = &ath11k_hw_ring_mask_qca6390, 408 .internal_sleep_clock = true, 409 .regs = &wcn6855_regs, 410 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390, 411 .host_ce_config = ath11k_host_ce_config_qca6390, 412 .ce_count = 9, 413 .target_ce_config = ath11k_target_ce_config_wlan_qca6390, 414 .target_ce_count = 9, 415 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, 416 .svc_to_ce_map_len = 14, 417 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 418 .single_pdev_only = true, 419 .rxdma1_enable = false, 420 .num_rxdma_per_pdev = 2, 421 .rx_mac_buf_ring = true, 422 .vdev_start_delay = true, 423 .htt_peer_map_v2 = false, 424 425 .spectral = { 426 .fft_sz = 0, 427 .fft_pad_sz = 0, 428 .summary_pad_sz = 0, 429 .fft_hdr_len = 0, 430 .max_fft_bins = 0, 431 .fragment_160mhz = false, 432 }, 433 434 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 435 BIT(NL80211_IFTYPE_AP) | 436 BIT(NL80211_IFTYPE_P2P_DEVICE) | 437 BIT(NL80211_IFTYPE_P2P_CLIENT) | 438 BIT(NL80211_IFTYPE_P2P_GO), 439 .supports_monitor = false, 440 .full_monitor_mode = false, 441 .supports_shadow_regs = true, 442 .idle_ps = true, 443 .supports_sta_ps = true, 444 .coldboot_cal_mm = false, 445 .coldboot_cal_ftm = false, 446 .cbcal_restart_fw = false, 447 .fw_mem_mode = 0, 448 .num_vdevs = 4, 449 .num_peers = 512, 450 .supports_suspend = true, 451 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855), 452 .supports_regdb = true, 453 .fix_l1ss = false, 454 .credit_flow = true, 455 .hal_params = &ath11k_hw_hal_params_qca6390, 456 .supports_dynamic_smps_6ghz = false, 457 .alloc_cacheable_memory = false, 458 .supports_rssi_stats = true, 459 .fw_wmi_diag_event = true, 460 .current_cc_support = true, 461 .dbr_debug_support = false, 462 .global_reset = true, 463 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855, 464 .m3_fw_support = true, 465 .fixed_bdf_addr = false, 466 .fixed_mem_region = false, 467 .static_window_map = false, 468 .hybrid_bus_type = false, 469 .fixed_fw_mem = false, 470 .support_off_channel_tx = true, 471 .supports_multi_bssid = true, 472 473 .sram_dump = { 474 .start = 0x01400000, 475 .end = 0x0177ffff, 476 }, 477 478 .tcl_ring_retry = true, 479 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 480 .smp2p_wow_exit = false, 481 .support_fw_mac_sequence = true, 482 .support_dual_stations = true, 483 .pdev_suspend = false, 484 .cfr_support = false, 485 .cfr_num_stream_bufs = 0, 486 .cfr_stream_buf_size = 0, 487 }, 488 { 489 .name = "wcn6855 hw2.1", 490 .hw_rev = ATH11K_HW_WCN6855_HW21, 491 .fw = { 492 .dir = "WCN6855/hw2.1", 493 .board_size = 256 * 1024, 494 .cal_offset = 128 * 1024, 495 }, 496 .max_radios = 3, 497 .bdf_addr = 0x4B0C0000, 498 .hw_ops = &wcn6855_ops, 499 .ring_mask = &ath11k_hw_ring_mask_qca6390, 500 .internal_sleep_clock = true, 501 .regs = &wcn6855_regs, 502 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390, 503 .host_ce_config = ath11k_host_ce_config_qca6390, 504 .ce_count = 9, 505 .target_ce_config = ath11k_target_ce_config_wlan_qca6390, 506 .target_ce_count = 9, 507 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, 508 .svc_to_ce_map_len = 14, 509 .single_pdev_only = true, 510 .rxdma1_enable = false, 511 .num_rxdma_per_pdev = 2, 512 .rx_mac_buf_ring = true, 513 .vdev_start_delay = true, 514 .htt_peer_map_v2 = false, 515 516 .spectral = { 517 .fft_sz = 0, 518 .fft_pad_sz = 0, 519 .summary_pad_sz = 0, 520 .fft_hdr_len = 0, 521 .max_fft_bins = 0, 522 .fragment_160mhz = false, 523 }, 524 525 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 526 BIT(NL80211_IFTYPE_AP) | 527 BIT(NL80211_IFTYPE_P2P_DEVICE) | 528 BIT(NL80211_IFTYPE_P2P_CLIENT) | 529 BIT(NL80211_IFTYPE_P2P_GO), 530 .supports_monitor = false, 531 .supports_shadow_regs = true, 532 .idle_ps = true, 533 .supports_sta_ps = true, 534 .coldboot_cal_mm = false, 535 .coldboot_cal_ftm = false, 536 .cbcal_restart_fw = false, 537 .fw_mem_mode = 0, 538 .num_vdevs = 4, 539 .num_peers = 512, 540 .supports_suspend = true, 541 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855), 542 .supports_regdb = true, 543 .fix_l1ss = false, 544 .credit_flow = true, 545 .hal_params = &ath11k_hw_hal_params_qca6390, 546 .supports_dynamic_smps_6ghz = false, 547 .alloc_cacheable_memory = false, 548 .supports_rssi_stats = true, 549 .fw_wmi_diag_event = true, 550 .current_cc_support = true, 551 .dbr_debug_support = false, 552 .global_reset = true, 553 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855, 554 .m3_fw_support = true, 555 .fixed_bdf_addr = false, 556 .fixed_mem_region = false, 557 .static_window_map = false, 558 .hybrid_bus_type = false, 559 .fixed_fw_mem = false, 560 .support_off_channel_tx = true, 561 .supports_multi_bssid = true, 562 563 .sram_dump = { 564 .start = 0x01400000, 565 .end = 0x0177ffff, 566 }, 567 568 .tcl_ring_retry = true, 569 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 570 .smp2p_wow_exit = false, 571 .support_fw_mac_sequence = true, 572 .support_dual_stations = true, 573 .pdev_suspend = false, 574 .cfr_support = true, 575 .cfr_num_stream_bufs = 255, 576 .cfr_stream_buf_size = 8200, 577 }, 578 { 579 .name = "wcn6750 hw1.0", 580 .hw_rev = ATH11K_HW_WCN6750_HW10, 581 .fw = { 582 .dir = "WCN6750/hw1.0", 583 .board_size = 256 * 1024, 584 .cal_offset = 128 * 1024, 585 }, 586 .max_radios = 1, 587 .bdf_addr = 0x4B0C0000, 588 .hw_ops = &wcn6750_ops, 589 .ring_mask = &ath11k_hw_ring_mask_wcn6750, 590 .internal_sleep_clock = false, 591 .regs = &wcn6750_regs, 592 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_WCN6750, 593 .host_ce_config = ath11k_host_ce_config_qca6390, 594 .ce_count = 9, 595 .target_ce_config = ath11k_target_ce_config_wlan_qca6390, 596 .target_ce_count = 9, 597 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, 598 .svc_to_ce_map_len = 14, 599 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 600 .single_pdev_only = true, 601 .rxdma1_enable = false, 602 .num_rxdma_per_pdev = 1, 603 .rx_mac_buf_ring = true, 604 .vdev_start_delay = true, 605 .htt_peer_map_v2 = false, 606 607 .spectral = { 608 .fft_sz = 0, 609 .fft_pad_sz = 0, 610 .summary_pad_sz = 0, 611 .fft_hdr_len = 0, 612 .max_fft_bins = 0, 613 .fragment_160mhz = false, 614 }, 615 616 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 617 BIT(NL80211_IFTYPE_AP), 618 .supports_monitor = false, 619 .supports_shadow_regs = true, 620 .idle_ps = true, 621 .supports_sta_ps = true, 622 .coldboot_cal_mm = true, 623 .coldboot_cal_ftm = true, 624 .cbcal_restart_fw = false, 625 .fw_mem_mode = 0, 626 .num_vdevs = 3, 627 .num_peers = 512, 628 .supports_suspend = false, 629 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074), 630 .supports_regdb = true, 631 .fix_l1ss = false, 632 .credit_flow = true, 633 .hal_params = &ath11k_hw_hal_params_wcn6750, 634 .supports_dynamic_smps_6ghz = false, 635 .alloc_cacheable_memory = false, 636 .supports_rssi_stats = true, 637 .fw_wmi_diag_event = true, 638 .current_cc_support = true, 639 .dbr_debug_support = false, 640 .global_reset = false, 641 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855, 642 .m3_fw_support = false, 643 .fixed_bdf_addr = false, 644 .fixed_mem_region = false, 645 .static_window_map = true, 646 .hybrid_bus_type = true, 647 .fixed_fw_mem = true, 648 .support_off_channel_tx = true, 649 .supports_multi_bssid = true, 650 651 .sram_dump = {}, 652 653 .tcl_ring_retry = false, 654 .tx_ring_size = DP_TCL_DATA_RING_SIZE_WCN6750, 655 .smp2p_wow_exit = true, 656 .support_fw_mac_sequence = true, 657 .support_dual_stations = false, 658 .pdev_suspend = true, 659 .cfr_support = false, 660 .cfr_num_stream_bufs = 0, 661 .cfr_stream_buf_size = 0, 662 }, 663 { 664 .hw_rev = ATH11K_HW_IPQ5018_HW10, 665 .name = "ipq5018 hw1.0", 666 .fw = { 667 .dir = "IPQ5018/hw1.0", 668 .board_size = 256 * 1024, 669 .cal_offset = 128 * 1024, 670 }, 671 .max_radios = MAX_RADIOS_5018, 672 .bdf_addr = 0x4BA00000, 673 /* hal_desc_sz and hw ops are similar to qcn9074 */ 674 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074), 675 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074, 676 .ring_mask = &ath11k_hw_ring_mask_ipq8074, 677 .credit_flow = false, 678 .spectral = { 679 .fft_sz = 2, 680 .fft_pad_sz = 0, 681 .summary_pad_sz = 16, 682 .fft_hdr_len = 24, 683 .max_fft_bins = 1024, 684 }, 685 .internal_sleep_clock = false, 686 .regs = &ipq5018_regs, 687 .hw_ops = &ipq5018_ops, 688 .host_ce_config = ath11k_host_ce_config_qcn9074, 689 .ce_count = CE_CNT_5018, 690 .target_ce_config = ath11k_target_ce_config_wlan_ipq5018, 691 .target_ce_count = TARGET_CE_CNT_5018, 692 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq5018, 693 .svc_to_ce_map_len = SVC_CE_MAP_LEN_5018, 694 .ce_ie_addr = &ath11k_ce_ie_addr_ipq5018, 695 .ce_remap = &ath11k_ce_remap_ipq5018, 696 .rxdma1_enable = true, 697 .num_rxdma_per_pdev = RXDMA_PER_PDEV_5018, 698 .rx_mac_buf_ring = false, 699 .vdev_start_delay = false, 700 .htt_peer_map_v2 = true, 701 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 702 BIT(NL80211_IFTYPE_AP) | 703 BIT(NL80211_IFTYPE_MESH_POINT), 704 .supports_monitor = false, 705 .supports_sta_ps = false, 706 .supports_shadow_regs = false, 707 .fw_mem_mode = 0, 708 .num_vdevs = 16 + 1, 709 .num_peers = 512, 710 .supports_regdb = false, 711 .idle_ps = false, 712 .supports_suspend = false, 713 .hal_params = &ath11k_hw_hal_params_ipq5018, 714 .single_pdev_only = false, 715 .coldboot_cal_mm = true, 716 .coldboot_cal_ftm = true, 717 .cbcal_restart_fw = true, 718 .fix_l1ss = true, 719 .supports_dynamic_smps_6ghz = false, 720 .alloc_cacheable_memory = true, 721 .supports_rssi_stats = false, 722 .fw_wmi_diag_event = false, 723 .current_cc_support = false, 724 .dbr_debug_support = true, 725 .global_reset = false, 726 .bios_sar_capa = NULL, 727 .m3_fw_support = false, 728 .fixed_bdf_addr = true, 729 .fixed_mem_region = true, 730 .static_window_map = false, 731 .hybrid_bus_type = false, 732 .fixed_fw_mem = false, 733 .support_off_channel_tx = false, 734 .supports_multi_bssid = false, 735 736 .sram_dump = {}, 737 738 .tcl_ring_retry = true, 739 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 740 .smp2p_wow_exit = false, 741 .support_fw_mac_sequence = false, 742 .support_dual_stations = false, 743 .pdev_suspend = false, 744 .cfr_support = false, 745 .cfr_num_stream_bufs = 0, 746 .cfr_stream_buf_size = 0, 747 }, 748 { 749 .name = "qca2066 hw2.1", 750 .hw_rev = ATH11K_HW_QCA2066_HW21, 751 .fw = { 752 .dir = "QCA2066/hw2.1", 753 .board_size = 256 * 1024, 754 .cal_offset = 128 * 1024, 755 }, 756 .max_radios = 3, 757 .bdf_addr = 0x4B0C0000, 758 .hw_ops = &wcn6855_ops, 759 .ring_mask = &ath11k_hw_ring_mask_qca6390, 760 .internal_sleep_clock = true, 761 .regs = &wcn6855_regs, 762 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390, 763 .host_ce_config = ath11k_host_ce_config_qca6390, 764 .ce_count = 9, 765 .target_ce_config = ath11k_target_ce_config_wlan_qca6390, 766 .target_ce_count = 9, 767 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, 768 .svc_to_ce_map_len = 14, 769 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 770 .single_pdev_only = true, 771 .rxdma1_enable = false, 772 .num_rxdma_per_pdev = 2, 773 .rx_mac_buf_ring = true, 774 .vdev_start_delay = true, 775 .htt_peer_map_v2 = false, 776 777 .spectral = { 778 .fft_sz = 0, 779 .fft_pad_sz = 0, 780 .summary_pad_sz = 0, 781 .fft_hdr_len = 0, 782 .max_fft_bins = 0, 783 .fragment_160mhz = false, 784 }, 785 786 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 787 BIT(NL80211_IFTYPE_AP) | 788 BIT(NL80211_IFTYPE_P2P_DEVICE) | 789 BIT(NL80211_IFTYPE_P2P_CLIENT) | 790 BIT(NL80211_IFTYPE_P2P_GO), 791 .supports_monitor = false, 792 .full_monitor_mode = false, 793 .supports_shadow_regs = true, 794 .idle_ps = true, 795 .supports_sta_ps = true, 796 .coldboot_cal_mm = false, 797 .coldboot_cal_ftm = false, 798 .cbcal_restart_fw = false, 799 .fw_mem_mode = 0, 800 .num_vdevs = 4, 801 .num_peers = 512, 802 .supports_suspend = true, 803 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855), 804 .supports_regdb = true, 805 .fix_l1ss = false, 806 .credit_flow = true, 807 .hal_params = &ath11k_hw_hal_params_qca6390, 808 .supports_dynamic_smps_6ghz = false, 809 .alloc_cacheable_memory = false, 810 .supports_rssi_stats = true, 811 .fw_wmi_diag_event = true, 812 .current_cc_support = true, 813 .dbr_debug_support = false, 814 .global_reset = true, 815 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855, 816 .m3_fw_support = true, 817 .fixed_bdf_addr = false, 818 .fixed_mem_region = false, 819 .static_window_map = false, 820 .hybrid_bus_type = false, 821 .fixed_fw_mem = false, 822 .support_off_channel_tx = true, 823 .supports_multi_bssid = true, 824 825 .sram_dump = { 826 .start = 0x01400000, 827 .end = 0x0177ffff, 828 }, 829 830 .tcl_ring_retry = true, 831 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 832 .smp2p_wow_exit = false, 833 .support_fw_mac_sequence = true, 834 .support_dual_stations = true, 835 .cfr_support = false, 836 .cfr_num_stream_bufs = 0, 837 .cfr_stream_buf_size = 0, 838 }, 839 { 840 .name = "qca6698aq hw2.1", 841 .hw_rev = ATH11K_HW_QCA6698AQ_HW21, 842 .fw = { 843 .dir = "QCA6698AQ/hw2.1", 844 .board_size = 256 * 1024, 845 .cal_offset = 128 * 1024, 846 }, 847 .max_radios = 3, 848 .bdf_addr = 0x4B0C0000, 849 .hw_ops = &wcn6855_ops, 850 .ring_mask = &ath11k_hw_ring_mask_qca6390, 851 .internal_sleep_clock = true, 852 .regs = &wcn6855_regs, 853 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390, 854 .host_ce_config = ath11k_host_ce_config_qca6390, 855 .ce_count = 9, 856 .target_ce_config = ath11k_target_ce_config_wlan_qca6390, 857 .target_ce_count = 9, 858 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, 859 .svc_to_ce_map_len = 14, 860 .single_pdev_only = true, 861 .rxdma1_enable = false, 862 .num_rxdma_per_pdev = 2, 863 .rx_mac_buf_ring = true, 864 .vdev_start_delay = true, 865 .htt_peer_map_v2 = false, 866 867 .spectral = { 868 .fft_sz = 0, 869 .fft_pad_sz = 0, 870 .summary_pad_sz = 0, 871 .fft_hdr_len = 0, 872 .max_fft_bins = 0, 873 .fragment_160mhz = false, 874 }, 875 876 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 877 BIT(NL80211_IFTYPE_AP) | 878 BIT(NL80211_IFTYPE_P2P_DEVICE) | 879 BIT(NL80211_IFTYPE_P2P_CLIENT) | 880 BIT(NL80211_IFTYPE_P2P_GO), 881 .supports_monitor = false, 882 .supports_shadow_regs = true, 883 .idle_ps = true, 884 .supports_sta_ps = true, 885 .coldboot_cal_mm = false, 886 .coldboot_cal_ftm = false, 887 .cbcal_restart_fw = false, 888 .fw_mem_mode = 0, 889 .num_vdevs = 4, 890 .num_peers = 512, 891 .supports_suspend = true, 892 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855), 893 .supports_regdb = true, 894 .fix_l1ss = false, 895 .credit_flow = true, 896 .hal_params = &ath11k_hw_hal_params_qca6390, 897 .supports_dynamic_smps_6ghz = false, 898 .alloc_cacheable_memory = false, 899 .supports_rssi_stats = true, 900 .fw_wmi_diag_event = true, 901 .current_cc_support = true, 902 .dbr_debug_support = false, 903 .global_reset = true, 904 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855, 905 .m3_fw_support = true, 906 .fixed_bdf_addr = false, 907 .fixed_mem_region = false, 908 .static_window_map = false, 909 .hybrid_bus_type = false, 910 .fixed_fw_mem = false, 911 .support_off_channel_tx = true, 912 .supports_multi_bssid = true, 913 914 .sram_dump = { 915 .start = 0x01400000, 916 .end = 0x0177ffff, 917 }, 918 919 .tcl_ring_retry = true, 920 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 921 .smp2p_wow_exit = false, 922 .support_fw_mac_sequence = true, 923 .support_dual_stations = true, 924 .pdev_suspend = false, 925 .cfr_support = true, 926 .cfr_num_stream_bufs = 255, 927 .cfr_stream_buf_size = 8200, 928 }, 929 }; 930 931 static const struct dmi_system_id ath11k_pm_quirk_table[] = { 932 { 933 .driver_data = (void *)ATH11K_PM_WOW, 934 .matches = { /* X13 G4 AMD #1 */ 935 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"), 936 DMI_MATCH(DMI_PRODUCT_NAME, "21J3"), 937 }, 938 }, 939 { 940 .driver_data = (void *)ATH11K_PM_WOW, 941 .matches = { /* X13 G4 AMD #2 */ 942 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"), 943 DMI_MATCH(DMI_PRODUCT_NAME, "21J4"), 944 }, 945 }, 946 { 947 .driver_data = (void *)ATH11K_PM_WOW, 948 .matches = { /* T14 G4 AMD #1 */ 949 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"), 950 DMI_MATCH(DMI_PRODUCT_NAME, "21K3"), 951 }, 952 }, 953 { 954 .driver_data = (void *)ATH11K_PM_WOW, 955 .matches = { /* T14 G4 AMD #2 */ 956 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"), 957 DMI_MATCH(DMI_PRODUCT_NAME, "21K4"), 958 }, 959 }, 960 { 961 .driver_data = (void *)ATH11K_PM_WOW, 962 .matches = { /* P14s G4 AMD #1 */ 963 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"), 964 DMI_MATCH(DMI_PRODUCT_NAME, "21K5"), 965 }, 966 }, 967 { 968 .driver_data = (void *)ATH11K_PM_WOW, 969 .matches = { /* P14s G4 AMD #2 */ 970 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"), 971 DMI_MATCH(DMI_PRODUCT_NAME, "21K6"), 972 }, 973 }, 974 { 975 .driver_data = (void *)ATH11K_PM_WOW, 976 .matches = { /* T16 G2 AMD #1 */ 977 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"), 978 DMI_MATCH(DMI_PRODUCT_NAME, "21K7"), 979 }, 980 }, 981 { 982 .driver_data = (void *)ATH11K_PM_WOW, 983 .matches = { /* T16 G2 AMD #2 */ 984 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"), 985 DMI_MATCH(DMI_PRODUCT_NAME, "21K8"), 986 }, 987 }, 988 { 989 .driver_data = (void *)ATH11K_PM_WOW, 990 .matches = { /* P16s G2 AMD #1 */ 991 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"), 992 DMI_MATCH(DMI_PRODUCT_NAME, "21K9"), 993 }, 994 }, 995 { 996 .driver_data = (void *)ATH11K_PM_WOW, 997 .matches = { /* P16s G2 AMD #2 */ 998 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"), 999 DMI_MATCH(DMI_PRODUCT_NAME, "21KA"), 1000 }, 1001 }, 1002 { 1003 .driver_data = (void *)ATH11K_PM_WOW, 1004 .matches = { /* T14s G4 AMD #1 */ 1005 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"), 1006 DMI_MATCH(DMI_PRODUCT_NAME, "21F8"), 1007 }, 1008 }, 1009 { 1010 .driver_data = (void *)ATH11K_PM_WOW, 1011 .matches = { /* T14s G4 AMD #2 */ 1012 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"), 1013 DMI_MATCH(DMI_PRODUCT_NAME, "21F9"), 1014 }, 1015 }, 1016 { 1017 .driver_data = (void *)ATH11K_PM_WOW, 1018 .matches = { /* Z13 G1 */ 1019 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"), 1020 DMI_MATCH(DMI_PRODUCT_NAME, "21D2"), 1021 }, 1022 }, 1023 { 1024 .driver_data = (void *)ATH11K_PM_WOW, 1025 .matches = { /* Z13 G1 */ 1026 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"), 1027 DMI_MATCH(DMI_PRODUCT_NAME, "21D3"), 1028 }, 1029 }, 1030 { 1031 .driver_data = (void *)ATH11K_PM_WOW, 1032 .matches = { /* Z16 G1 */ 1033 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"), 1034 DMI_MATCH(DMI_PRODUCT_NAME, "21D4"), 1035 }, 1036 }, 1037 { 1038 .driver_data = (void *)ATH11K_PM_WOW, 1039 .matches = { /* Z16 G1 */ 1040 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"), 1041 DMI_MATCH(DMI_PRODUCT_NAME, "21D5"), 1042 }, 1043 }, 1044 {} 1045 }; 1046 1047 static const struct __ath11k_core_usecase_firmware_table { 1048 u32 hw_rev; 1049 const char *compatible; 1050 const char *firmware_name; 1051 } ath11k_core_usecase_firmware_table[] = { 1052 { ATH11K_HW_WCN6855_HW21, "qcom,hamoa-iot-evk", "nfa765"}, 1053 { ATH11K_HW_WCN6855_HW21, "qcom,lemans-evk", "nfa765"}, 1054 { ATH11K_HW_WCN6855_HW21, "qcom,monaco-evk", "nfa765"}, 1055 { ATH11K_HW_WCN6855_HW21, "qcom,purwa-iot-evk", "nfa765"}, 1056 { ATH11K_HW_WCN6855_HW21, "qcom,qcs6490-rb3gen2", "nfa765"}, 1057 { /* Sentinel */ } 1058 }; 1059 1060 const char *ath11k_core_get_usecase_firmware(struct ath11k_base *ab) 1061 { 1062 const struct __ath11k_core_usecase_firmware_table *entry = NULL; 1063 1064 entry = ath11k_core_usecase_firmware_table; 1065 while (entry->compatible) { 1066 if (ab->hw_rev == entry->hw_rev && 1067 of_machine_is_compatible(entry->compatible)) 1068 return entry->firmware_name; 1069 entry++; 1070 } 1071 1072 return NULL; 1073 } 1074 EXPORT_SYMBOL(ath11k_core_get_usecase_firmware); 1075 1076 void ath11k_fw_stats_pdevs_free(struct list_head *head) 1077 { 1078 struct ath11k_fw_stats_pdev *i, *tmp; 1079 1080 list_for_each_entry_safe(i, tmp, head, list) { 1081 list_del(&i->list); 1082 kfree(i); 1083 } 1084 } 1085 1086 void ath11k_fw_stats_vdevs_free(struct list_head *head) 1087 { 1088 struct ath11k_fw_stats_vdev *i, *tmp; 1089 1090 list_for_each_entry_safe(i, tmp, head, list) { 1091 list_del(&i->list); 1092 kfree(i); 1093 } 1094 } 1095 1096 void ath11k_fw_stats_bcn_free(struct list_head *head) 1097 { 1098 struct ath11k_fw_stats_bcn *i, *tmp; 1099 1100 list_for_each_entry_safe(i, tmp, head, list) { 1101 list_del(&i->list); 1102 kfree(i); 1103 } 1104 } 1105 1106 void ath11k_fw_stats_init(struct ath11k *ar) 1107 { 1108 INIT_LIST_HEAD(&ar->fw_stats.pdevs); 1109 INIT_LIST_HEAD(&ar->fw_stats.vdevs); 1110 INIT_LIST_HEAD(&ar->fw_stats.bcn); 1111 1112 init_completion(&ar->fw_stats_complete); 1113 init_completion(&ar->fw_stats_done); 1114 } 1115 1116 void ath11k_fw_stats_free(struct ath11k_fw_stats *stats) 1117 { 1118 ath11k_fw_stats_pdevs_free(&stats->pdevs); 1119 ath11k_fw_stats_vdevs_free(&stats->vdevs); 1120 ath11k_fw_stats_bcn_free(&stats->bcn); 1121 } 1122 1123 bool ath11k_core_coldboot_cal_support(struct ath11k_base *ab) 1124 { 1125 if (!ath11k_cold_boot_cal) 1126 return false; 1127 1128 if (ath11k_ftm_mode) 1129 return ab->hw_params.coldboot_cal_ftm; 1130 1131 else 1132 return ab->hw_params.coldboot_cal_mm; 1133 } 1134 1135 /* Check if we need to continue with suspend/resume operation. 1136 * Return: 1137 * a negative value: error happens and don't continue. 1138 * 0: no error but don't continue. 1139 * positive value: no error and do continue. 1140 */ 1141 static int ath11k_core_continue_suspend_resume(struct ath11k_base *ab) 1142 { 1143 struct ath11k *ar; 1144 1145 if (!ab->hw_params.supports_suspend) 1146 return -EOPNOTSUPP; 1147 1148 /* so far single_pdev_only chips have supports_suspend as true 1149 * so pass 0 as a dummy pdev_id here. 1150 */ 1151 ar = ab->pdevs[0].ar; 1152 if (!ar || ar->state != ATH11K_STATE_OFF) 1153 return 0; 1154 1155 return 1; 1156 } 1157 1158 static int ath11k_core_suspend_wow(struct ath11k_base *ab) 1159 { 1160 int ret; 1161 1162 ret = ath11k_dp_rx_pktlog_stop(ab, true); 1163 if (ret) { 1164 ath11k_warn(ab, "failed to stop dp rx (and timer) pktlog during suspend: %d\n", 1165 ret); 1166 return ret; 1167 } 1168 1169 /* So far only single_pdev_only devices can reach here, 1170 * so it is valid to handle the first, and the only, pdev. 1171 */ 1172 ret = ath11k_mac_wait_tx_complete(ab->pdevs[0].ar); 1173 if (ret) { 1174 ath11k_warn(ab, "failed to wait tx complete: %d\n", ret); 1175 return ret; 1176 } 1177 1178 ret = ath11k_wow_enable(ab); 1179 if (ret) { 1180 ath11k_warn(ab, "failed to enable wow during suspend: %d\n", ret); 1181 return ret; 1182 } 1183 1184 ret = ath11k_dp_rx_pktlog_stop(ab, false); 1185 if (ret) { 1186 ath11k_warn(ab, "failed to stop dp rx pktlog during suspend: %d\n", 1187 ret); 1188 return ret; 1189 } 1190 1191 ath11k_ce_stop_shadow_timers(ab); 1192 ath11k_dp_stop_shadow_timers(ab); 1193 1194 ath11k_hif_irq_disable(ab); 1195 ath11k_hif_ce_irq_disable(ab); 1196 1197 ret = ath11k_hif_suspend(ab); 1198 if (ret) { 1199 ath11k_warn(ab, "failed to suspend hif: %d\n", ret); 1200 return ret; 1201 } 1202 1203 return 0; 1204 } 1205 1206 static int ath11k_core_suspend_default(struct ath11k_base *ab) 1207 { 1208 int ret; 1209 1210 ret = ath11k_dp_rx_pktlog_stop(ab, true); 1211 if (ret) { 1212 ath11k_warn(ab, "failed to stop dp rx (and timer) pktlog during suspend: %d\n", 1213 ret); 1214 return ret; 1215 } 1216 1217 /* So far only single_pdev_only devices can reach here, 1218 * so it is valid to handle the first, and the only, pdev. 1219 */ 1220 ret = ath11k_mac_wait_tx_complete(ab->pdevs[0].ar); 1221 if (ret) { 1222 ath11k_warn(ab, "failed to wait tx complete: %d\n", ret); 1223 return ret; 1224 } 1225 1226 ret = ath11k_dp_rx_pktlog_stop(ab, false); 1227 if (ret) { 1228 ath11k_warn(ab, "failed to stop dp rx pktlog during suspend: %d\n", 1229 ret); 1230 return ret; 1231 } 1232 1233 ath11k_ce_stop_shadow_timers(ab); 1234 ath11k_dp_stop_shadow_timers(ab); 1235 1236 /* PM framework skips suspend_late/resume_early callbacks 1237 * if other devices report errors in their suspend callbacks. 1238 * However ath11k_core_resume() would still be called because 1239 * here we return success thus kernel put us on dpm_suspended_list. 1240 * Since we won't go through a power down/up cycle, there is 1241 * no chance to call complete(&ab->restart_completed) in 1242 * ath11k_core_restart(), making ath11k_core_resume() timeout. 1243 * So call it here to avoid this issue. This also works in case 1244 * no error happens thus suspend_late/resume_early get called, 1245 * because it will be reinitialized in ath11k_core_resume_early(). 1246 */ 1247 complete(&ab->restart_completed); 1248 1249 return 0; 1250 } 1251 1252 int ath11k_core_suspend(struct ath11k_base *ab) 1253 { 1254 int ret; 1255 1256 ret = ath11k_core_continue_suspend_resume(ab); 1257 if (ret <= 0) 1258 return ret; 1259 1260 if (ab->actual_pm_policy == ATH11K_PM_WOW) 1261 return ath11k_core_suspend_wow(ab); 1262 1263 return ath11k_core_suspend_default(ab); 1264 } 1265 EXPORT_SYMBOL(ath11k_core_suspend); 1266 1267 int ath11k_core_suspend_late(struct ath11k_base *ab) 1268 { 1269 int ret; 1270 1271 ret = ath11k_core_continue_suspend_resume(ab); 1272 if (ret <= 0) 1273 return ret; 1274 1275 if (ab->actual_pm_policy == ATH11K_PM_WOW) 1276 return 0; 1277 1278 ath11k_hif_power_down(ab, true); 1279 1280 return 0; 1281 } 1282 EXPORT_SYMBOL(ath11k_core_suspend_late); 1283 1284 int ath11k_core_resume_early(struct ath11k_base *ab) 1285 { 1286 int ret; 1287 1288 ret = ath11k_core_continue_suspend_resume(ab); 1289 if (ret <= 0) 1290 return ret; 1291 1292 if (ab->actual_pm_policy == ATH11K_PM_WOW) 1293 return 0; 1294 1295 reinit_completion(&ab->restart_completed); 1296 ret = ath11k_hif_power_up(ab); 1297 if (ret) 1298 ath11k_warn(ab, "failed to power up hif during resume: %d\n", ret); 1299 1300 return ret; 1301 } 1302 EXPORT_SYMBOL(ath11k_core_resume_early); 1303 1304 static int ath11k_core_resume_default(struct ath11k_base *ab) 1305 { 1306 struct ath11k *ar; 1307 long time_left; 1308 int ret; 1309 1310 time_left = wait_for_completion_timeout(&ab->restart_completed, 1311 ATH11K_RESET_TIMEOUT_HZ); 1312 if (time_left == 0) { 1313 ath11k_warn(ab, "timeout while waiting for restart complete"); 1314 return -ETIMEDOUT; 1315 } 1316 1317 /* So far only single_pdev_only devices can reach here, 1318 * so it is valid to handle the first, and the only, pdev. 1319 */ 1320 ar = ab->pdevs[0].ar; 1321 if (ab->hw_params.current_cc_support && 1322 ar->alpha2[0] != 0 && ar->alpha2[1] != 0) { 1323 ret = ath11k_reg_set_cc(ar); 1324 if (ret) { 1325 ath11k_warn(ab, "failed to set country code during resume: %d\n", 1326 ret); 1327 return ret; 1328 } 1329 } 1330 1331 ret = ath11k_dp_rx_pktlog_start(ab); 1332 if (ret) 1333 ath11k_warn(ab, "failed to start rx pktlog during resume: %d\n", 1334 ret); 1335 1336 return ret; 1337 } 1338 1339 static int ath11k_core_resume_wow(struct ath11k_base *ab) 1340 { 1341 int ret; 1342 1343 ret = ath11k_hif_resume(ab); 1344 if (ret) { 1345 ath11k_warn(ab, "failed to resume hif during resume: %d\n", ret); 1346 return ret; 1347 } 1348 1349 ath11k_hif_ce_irq_enable(ab); 1350 ath11k_hif_irq_enable(ab); 1351 1352 ret = ath11k_dp_rx_pktlog_start(ab); 1353 if (ret) { 1354 ath11k_warn(ab, "failed to start rx pktlog during resume: %d\n", 1355 ret); 1356 return ret; 1357 } 1358 1359 ret = ath11k_wow_wakeup(ab); 1360 if (ret) { 1361 ath11k_warn(ab, "failed to wakeup wow during resume: %d\n", ret); 1362 return ret; 1363 } 1364 1365 return 0; 1366 } 1367 1368 int ath11k_core_resume(struct ath11k_base *ab) 1369 { 1370 int ret; 1371 1372 ret = ath11k_core_continue_suspend_resume(ab); 1373 if (ret <= 0) 1374 return ret; 1375 1376 if (ab->actual_pm_policy == ATH11K_PM_WOW) 1377 return ath11k_core_resume_wow(ab); 1378 1379 return ath11k_core_resume_default(ab); 1380 } 1381 EXPORT_SYMBOL(ath11k_core_resume); 1382 1383 static void ath11k_core_check_cc_code_bdfext(const struct dmi_header *hdr, void *data) 1384 { 1385 struct ath11k_base *ab = data; 1386 const char *magic = ATH11K_SMBIOS_BDF_EXT_MAGIC; 1387 struct ath11k_smbios_bdf *smbios = (struct ath11k_smbios_bdf *)hdr; 1388 ssize_t copied; 1389 size_t len; 1390 int i; 1391 1392 if (ab->qmi.target.bdf_ext[0] != '\0') 1393 return; 1394 1395 if (hdr->type != ATH11K_SMBIOS_BDF_EXT_TYPE) 1396 return; 1397 1398 if (hdr->length != ATH11K_SMBIOS_BDF_EXT_LENGTH) { 1399 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1400 "wrong smbios bdf ext type length (%d).\n", 1401 hdr->length); 1402 return; 1403 } 1404 1405 spin_lock_bh(&ab->base_lock); 1406 1407 switch (smbios->country_code_flag) { 1408 case ATH11K_SMBIOS_CC_ISO: 1409 ab->new_alpha2[0] = (smbios->cc_code >> 8) & 0xff; 1410 ab->new_alpha2[1] = smbios->cc_code & 0xff; 1411 ath11k_dbg(ab, ATH11K_DBG_BOOT, "smbios cc_code %c%c\n", 1412 ab->new_alpha2[0], ab->new_alpha2[1]); 1413 break; 1414 case ATH11K_SMBIOS_CC_WW: 1415 ab->new_alpha2[0] = '0'; 1416 ab->new_alpha2[1] = '0'; 1417 ath11k_dbg(ab, ATH11K_DBG_BOOT, "smbios worldwide regdomain\n"); 1418 break; 1419 default: 1420 ath11k_dbg(ab, ATH11K_DBG_BOOT, "ignore smbios country code setting %d\n", 1421 smbios->country_code_flag); 1422 break; 1423 } 1424 1425 spin_unlock_bh(&ab->base_lock); 1426 1427 if (!smbios->bdf_enabled) { 1428 ath11k_dbg(ab, ATH11K_DBG_BOOT, "bdf variant name not found.\n"); 1429 return; 1430 } 1431 1432 /* Only one string exists (per spec) */ 1433 if (memcmp(smbios->bdf_ext, magic, strlen(magic)) != 0) { 1434 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1435 "bdf variant magic does not match.\n"); 1436 return; 1437 } 1438 1439 len = min_t(size_t, 1440 strlen(smbios->bdf_ext), sizeof(ab->qmi.target.bdf_ext)); 1441 for (i = 0; i < len; i++) { 1442 if (!isascii(smbios->bdf_ext[i]) || !isprint(smbios->bdf_ext[i])) { 1443 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1444 "bdf variant name contains non ascii chars.\n"); 1445 return; 1446 } 1447 } 1448 1449 /* Copy extension name without magic prefix */ 1450 copied = strscpy(ab->qmi.target.bdf_ext, smbios->bdf_ext + strlen(magic), 1451 sizeof(ab->qmi.target.bdf_ext)); 1452 if (copied < 0) { 1453 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1454 "bdf variant string is longer than the buffer can accommodate\n"); 1455 return; 1456 } 1457 1458 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1459 "found and validated bdf variant smbios_type 0x%x bdf %s\n", 1460 ATH11K_SMBIOS_BDF_EXT_TYPE, ab->qmi.target.bdf_ext); 1461 } 1462 1463 int ath11k_core_check_smbios(struct ath11k_base *ab) 1464 { 1465 ab->qmi.target.bdf_ext[0] = '\0'; 1466 dmi_walk(ath11k_core_check_cc_code_bdfext, ab); 1467 1468 if (ab->qmi.target.bdf_ext[0] == '\0') 1469 return -ENODATA; 1470 1471 return 0; 1472 } 1473 1474 int ath11k_core_check_dt(struct ath11k_base *ab) 1475 { 1476 size_t max_len = sizeof(ab->qmi.target.bdf_ext); 1477 const char *variant = NULL; 1478 struct device_node *node; 1479 1480 node = ab->dev->of_node; 1481 if (!node) 1482 return -ENOENT; 1483 1484 of_property_read_string(node, "qcom,calibration-variant", 1485 &variant); 1486 if (!variant) 1487 of_property_read_string(node, "qcom,ath11k-calibration-variant", 1488 &variant); 1489 if (!variant) 1490 return -ENODATA; 1491 1492 if (strscpy(ab->qmi.target.bdf_ext, variant, max_len) < 0) 1493 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1494 "bdf variant string is longer than the buffer can accommodate (variant: %s)\n", 1495 variant); 1496 1497 return 0; 1498 } 1499 1500 enum ath11k_bdf_name_type { 1501 ATH11K_BDF_NAME_FULL, 1502 ATH11K_BDF_NAME_BUS_NAME, 1503 ATH11K_BDF_NAME_CHIP_ID, 1504 }; 1505 1506 static int __ath11k_core_create_board_name(struct ath11k_base *ab, char *name, 1507 size_t name_len, bool with_variant, 1508 enum ath11k_bdf_name_type name_type) 1509 { 1510 /* strlen(',variant=') + strlen(ab->qmi.target.bdf_ext) */ 1511 char variant[9 + ATH11K_QMI_BDF_EXT_STR_LENGTH] = {}; 1512 1513 if (with_variant && ab->qmi.target.bdf_ext[0] != '\0') 1514 scnprintf(variant, sizeof(variant), ",variant=%s", 1515 ab->qmi.target.bdf_ext); 1516 1517 switch (ab->id.bdf_search) { 1518 case ATH11K_BDF_SEARCH_BUS_AND_BOARD: 1519 switch (name_type) { 1520 case ATH11K_BDF_NAME_FULL: 1521 scnprintf(name, name_len, 1522 "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x,qmi-chip-id=%d,qmi-board-id=%d%s", 1523 ath11k_bus_str(ab->hif.bus), 1524 ab->id.vendor, ab->id.device, 1525 ab->id.subsystem_vendor, 1526 ab->id.subsystem_device, 1527 ab->qmi.target.chip_id, 1528 ab->qmi.target.board_id, 1529 variant); 1530 break; 1531 case ATH11K_BDF_NAME_BUS_NAME: 1532 scnprintf(name, name_len, 1533 "bus=%s", 1534 ath11k_bus_str(ab->hif.bus)); 1535 break; 1536 case ATH11K_BDF_NAME_CHIP_ID: 1537 scnprintf(name, name_len, 1538 "bus=%s,qmi-chip-id=%d", 1539 ath11k_bus_str(ab->hif.bus), 1540 ab->qmi.target.chip_id); 1541 break; 1542 } 1543 break; 1544 default: 1545 scnprintf(name, name_len, 1546 "bus=%s,qmi-chip-id=%d,qmi-board-id=%d%s", 1547 ath11k_bus_str(ab->hif.bus), 1548 ab->qmi.target.chip_id, 1549 ab->qmi.target.board_id, variant); 1550 break; 1551 } 1552 1553 ath11k_dbg(ab, ATH11K_DBG_BOOT, "using board name '%s'\n", name); 1554 1555 return 0; 1556 } 1557 1558 static int ath11k_core_create_board_name(struct ath11k_base *ab, char *name, 1559 size_t name_len) 1560 { 1561 return __ath11k_core_create_board_name(ab, name, name_len, true, 1562 ATH11K_BDF_NAME_FULL); 1563 } 1564 1565 static int ath11k_core_create_fallback_board_name(struct ath11k_base *ab, char *name, 1566 size_t name_len) 1567 { 1568 return __ath11k_core_create_board_name(ab, name, name_len, false, 1569 ATH11K_BDF_NAME_FULL); 1570 } 1571 1572 static int ath11k_core_create_bus_type_board_name(struct ath11k_base *ab, char *name, 1573 size_t name_len) 1574 { 1575 return __ath11k_core_create_board_name(ab, name, name_len, false, 1576 ATH11K_BDF_NAME_BUS_NAME); 1577 } 1578 1579 static int ath11k_core_create_chip_id_board_name(struct ath11k_base *ab, char *name, 1580 size_t name_len) 1581 { 1582 return __ath11k_core_create_board_name(ab, name, name_len, false, 1583 ATH11K_BDF_NAME_CHIP_ID); 1584 } 1585 1586 const struct firmware *ath11k_core_firmware_request(struct ath11k_base *ab, 1587 const char *file) 1588 { 1589 const struct firmware *fw; 1590 char path[100]; 1591 int ret; 1592 1593 if (file == NULL) 1594 return ERR_PTR(-ENOENT); 1595 1596 ath11k_core_create_firmware_path(ab, file, path, sizeof(path)); 1597 1598 ret = firmware_request_nowarn(&fw, path, ab->dev); 1599 if (ret) 1600 return ERR_PTR(ret); 1601 1602 ath11k_dbg(ab, ATH11K_DBG_BOOT, "firmware request %s size %zu\n", 1603 path, fw->size); 1604 1605 return fw; 1606 } 1607 1608 void ath11k_core_free_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd) 1609 { 1610 if (!IS_ERR(bd->fw)) 1611 release_firmware(bd->fw); 1612 1613 memset(bd, 0, sizeof(*bd)); 1614 } 1615 1616 static int ath11k_core_parse_bd_ie_board(struct ath11k_base *ab, 1617 struct ath11k_board_data *bd, 1618 const void *buf, size_t buf_len, 1619 const char *boardname, 1620 int ie_id, 1621 int name_id, 1622 int data_id) 1623 { 1624 const struct ath11k_fw_ie *hdr; 1625 bool name_match_found; 1626 int ret, board_ie_id; 1627 size_t board_ie_len; 1628 const void *board_ie_data; 1629 1630 name_match_found = false; 1631 1632 /* go through ATH11K_BD_IE_BOARD_/ATH11K_BD_IE_REGDB_ elements */ 1633 while (buf_len > sizeof(struct ath11k_fw_ie)) { 1634 hdr = buf; 1635 board_ie_id = le32_to_cpu(hdr->id); 1636 board_ie_len = le32_to_cpu(hdr->len); 1637 board_ie_data = hdr->data; 1638 1639 buf_len -= sizeof(*hdr); 1640 buf += sizeof(*hdr); 1641 1642 if (buf_len < ALIGN(board_ie_len, 4)) { 1643 ath11k_err(ab, "invalid %s length: %zu < %zu\n", 1644 ath11k_bd_ie_type_str(ie_id), 1645 buf_len, ALIGN(board_ie_len, 4)); 1646 ret = -EINVAL; 1647 goto out; 1648 } 1649 1650 if (board_ie_id == name_id) { 1651 ath11k_dbg_dump(ab, ATH11K_DBG_BOOT, "board name", "", 1652 board_ie_data, board_ie_len); 1653 1654 if (board_ie_len != strlen(boardname)) 1655 goto next; 1656 1657 ret = memcmp(board_ie_data, boardname, strlen(boardname)); 1658 if (ret) 1659 goto next; 1660 1661 name_match_found = true; 1662 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1663 "found match %s for name '%s'", 1664 ath11k_bd_ie_type_str(ie_id), 1665 boardname); 1666 } else if (board_ie_id == data_id) { 1667 if (!name_match_found) 1668 /* no match found */ 1669 goto next; 1670 1671 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1672 "found %s for '%s'", 1673 ath11k_bd_ie_type_str(ie_id), 1674 boardname); 1675 1676 bd->data = board_ie_data; 1677 bd->len = board_ie_len; 1678 1679 ret = 0; 1680 goto out; 1681 } else { 1682 ath11k_warn(ab, "unknown %s id found: %d\n", 1683 ath11k_bd_ie_type_str(ie_id), 1684 board_ie_id); 1685 } 1686 next: 1687 /* jump over the padding */ 1688 board_ie_len = ALIGN(board_ie_len, 4); 1689 1690 buf_len -= board_ie_len; 1691 buf += board_ie_len; 1692 } 1693 1694 /* no match found */ 1695 ret = -ENOENT; 1696 1697 out: 1698 return ret; 1699 } 1700 1701 static int ath11k_core_fetch_board_data_api_n(struct ath11k_base *ab, 1702 struct ath11k_board_data *bd, 1703 const char *boardname, 1704 int ie_id_match, 1705 int name_id, 1706 int data_id) 1707 { 1708 size_t len, magic_len; 1709 const u8 *data; 1710 char *filename, filepath[100]; 1711 size_t ie_len; 1712 struct ath11k_fw_ie *hdr; 1713 int ret, ie_id; 1714 1715 filename = ATH11K_BOARD_API2_FILE; 1716 1717 if (!bd->fw) 1718 bd->fw = ath11k_core_firmware_request(ab, filename); 1719 1720 if (IS_ERR(bd->fw)) 1721 return PTR_ERR(bd->fw); 1722 1723 data = bd->fw->data; 1724 len = bd->fw->size; 1725 1726 ath11k_core_create_firmware_path(ab, filename, 1727 filepath, sizeof(filepath)); 1728 1729 /* magic has extra null byte padded */ 1730 magic_len = strlen(ATH11K_BOARD_MAGIC) + 1; 1731 if (len < magic_len) { 1732 ath11k_err(ab, "failed to find magic value in %s, file too short: %zu\n", 1733 filepath, len); 1734 ret = -EINVAL; 1735 goto err; 1736 } 1737 1738 if (memcmp(data, ATH11K_BOARD_MAGIC, magic_len)) { 1739 ath11k_err(ab, "found invalid board magic\n"); 1740 ret = -EINVAL; 1741 goto err; 1742 } 1743 1744 /* magic is padded to 4 bytes */ 1745 magic_len = ALIGN(magic_len, 4); 1746 if (len < magic_len) { 1747 ath11k_err(ab, "failed: %s too small to contain board data, len: %zu\n", 1748 filepath, len); 1749 ret = -EINVAL; 1750 goto err; 1751 } 1752 1753 data += magic_len; 1754 len -= magic_len; 1755 1756 while (len > sizeof(struct ath11k_fw_ie)) { 1757 hdr = (struct ath11k_fw_ie *)data; 1758 ie_id = le32_to_cpu(hdr->id); 1759 ie_len = le32_to_cpu(hdr->len); 1760 1761 len -= sizeof(*hdr); 1762 data = hdr->data; 1763 1764 if (len < ALIGN(ie_len, 4)) { 1765 ath11k_err(ab, "invalid length for board ie_id %d ie_len %zu len %zu\n", 1766 ie_id, ie_len, len); 1767 ret = -EINVAL; 1768 goto err; 1769 } 1770 1771 if (ie_id == ie_id_match) { 1772 ret = ath11k_core_parse_bd_ie_board(ab, bd, data, 1773 ie_len, 1774 boardname, 1775 ie_id_match, 1776 name_id, 1777 data_id); 1778 if (ret == -ENOENT) 1779 /* no match found, continue */ 1780 goto next; 1781 else if (ret) 1782 /* there was an error, bail out */ 1783 goto err; 1784 /* either found or error, so stop searching */ 1785 goto out; 1786 } 1787 next: 1788 /* jump over the padding */ 1789 ie_len = ALIGN(ie_len, 4); 1790 1791 len -= ie_len; 1792 data += ie_len; 1793 } 1794 1795 out: 1796 if (!bd->data || !bd->len) { 1797 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1798 "failed to fetch %s for %s from %s\n", 1799 ath11k_bd_ie_type_str(ie_id_match), 1800 boardname, filepath); 1801 ret = -ENODATA; 1802 goto err; 1803 } 1804 1805 return 0; 1806 1807 err: 1808 ath11k_core_free_bdf(ab, bd); 1809 return ret; 1810 } 1811 1812 int ath11k_core_fetch_board_data_api_1(struct ath11k_base *ab, 1813 struct ath11k_board_data *bd, 1814 const char *name) 1815 { 1816 bd->fw = ath11k_core_firmware_request(ab, name); 1817 1818 if (IS_ERR(bd->fw)) 1819 return PTR_ERR(bd->fw); 1820 1821 bd->data = bd->fw->data; 1822 bd->len = bd->fw->size; 1823 1824 return 0; 1825 } 1826 1827 #define BOARD_NAME_SIZE 200 1828 int ath11k_core_fetch_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd) 1829 { 1830 char *boardname = NULL, *fallback_boardname = NULL, *chip_id_boardname = NULL; 1831 char *filename, filepath[100]; 1832 int bd_api; 1833 int ret = 0; 1834 1835 filename = ATH11K_BOARD_API2_FILE; 1836 boardname = kzalloc(BOARD_NAME_SIZE, GFP_KERNEL); 1837 if (!boardname) { 1838 ret = -ENOMEM; 1839 goto exit; 1840 } 1841 1842 ret = ath11k_core_create_board_name(ab, boardname, BOARD_NAME_SIZE); 1843 if (ret) { 1844 ath11k_err(ab, "failed to create board name: %d", ret); 1845 goto exit; 1846 } 1847 1848 bd_api = 2; 1849 ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname, 1850 ATH11K_BD_IE_BOARD, 1851 ATH11K_BD_IE_BOARD_NAME, 1852 ATH11K_BD_IE_BOARD_DATA); 1853 if (!ret) 1854 goto exit; 1855 1856 fallback_boardname = kzalloc(BOARD_NAME_SIZE, GFP_KERNEL); 1857 if (!fallback_boardname) { 1858 ret = -ENOMEM; 1859 goto exit; 1860 } 1861 1862 ret = ath11k_core_create_fallback_board_name(ab, fallback_boardname, 1863 BOARD_NAME_SIZE); 1864 if (ret) { 1865 ath11k_err(ab, "failed to create fallback board name: %d", ret); 1866 goto exit; 1867 } 1868 1869 ret = ath11k_core_fetch_board_data_api_n(ab, bd, fallback_boardname, 1870 ATH11K_BD_IE_BOARD, 1871 ATH11K_BD_IE_BOARD_NAME, 1872 ATH11K_BD_IE_BOARD_DATA); 1873 if (!ret) 1874 goto exit; 1875 1876 chip_id_boardname = kzalloc(BOARD_NAME_SIZE, GFP_KERNEL); 1877 if (!chip_id_boardname) { 1878 ret = -ENOMEM; 1879 goto exit; 1880 } 1881 1882 ret = ath11k_core_create_chip_id_board_name(ab, chip_id_boardname, 1883 BOARD_NAME_SIZE); 1884 if (ret) { 1885 ath11k_err(ab, "failed to create chip id board name: %d", ret); 1886 goto exit; 1887 } 1888 1889 ret = ath11k_core_fetch_board_data_api_n(ab, bd, chip_id_boardname, 1890 ATH11K_BD_IE_BOARD, 1891 ATH11K_BD_IE_BOARD_NAME, 1892 ATH11K_BD_IE_BOARD_DATA); 1893 1894 if (!ret) 1895 goto exit; 1896 1897 bd_api = 1; 1898 ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_DEFAULT_BOARD_FILE); 1899 if (ret) { 1900 ath11k_core_create_firmware_path(ab, filename, 1901 filepath, sizeof(filepath)); 1902 ath11k_err(ab, "failed to fetch board data for %s from %s\n", 1903 boardname, filepath); 1904 if (memcmp(boardname, fallback_boardname, strlen(boardname))) 1905 ath11k_err(ab, "failed to fetch board data for %s from %s\n", 1906 fallback_boardname, filepath); 1907 1908 ath11k_err(ab, "failed to fetch board data for %s from %s\n", 1909 chip_id_boardname, filepath); 1910 1911 ath11k_err(ab, "failed to fetch board.bin from %s\n", 1912 ab->hw_params.fw.dir); 1913 } 1914 1915 exit: 1916 kfree(boardname); 1917 kfree(fallback_boardname); 1918 kfree(chip_id_boardname); 1919 1920 if (!ret) 1921 ath11k_dbg(ab, ATH11K_DBG_BOOT, "using board api %d\n", bd_api); 1922 1923 return ret; 1924 } 1925 1926 int ath11k_core_fetch_regdb(struct ath11k_base *ab, struct ath11k_board_data *bd) 1927 { 1928 char boardname[BOARD_NAME_SIZE], default_boardname[BOARD_NAME_SIZE]; 1929 int ret; 1930 1931 ret = ath11k_core_create_board_name(ab, boardname, BOARD_NAME_SIZE); 1932 if (ret) { 1933 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1934 "failed to create board name for regdb: %d", ret); 1935 goto exit; 1936 } 1937 1938 ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname, 1939 ATH11K_BD_IE_REGDB, 1940 ATH11K_BD_IE_REGDB_NAME, 1941 ATH11K_BD_IE_REGDB_DATA); 1942 if (!ret) 1943 goto exit; 1944 1945 ret = ath11k_core_create_bus_type_board_name(ab, default_boardname, 1946 BOARD_NAME_SIZE); 1947 if (ret) { 1948 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1949 "failed to create default board name for regdb: %d", ret); 1950 goto exit; 1951 } 1952 1953 ret = ath11k_core_fetch_board_data_api_n(ab, bd, default_boardname, 1954 ATH11K_BD_IE_REGDB, 1955 ATH11K_BD_IE_REGDB_NAME, 1956 ATH11K_BD_IE_REGDB_DATA); 1957 if (!ret) 1958 goto exit; 1959 1960 ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_REGDB_FILE_NAME); 1961 if (ret) 1962 ath11k_dbg(ab, ATH11K_DBG_BOOT, "failed to fetch %s from %s\n", 1963 ATH11K_REGDB_FILE_NAME, ab->hw_params.fw.dir); 1964 1965 exit: 1966 if (!ret) 1967 ath11k_dbg(ab, ATH11K_DBG_BOOT, "fetched regdb\n"); 1968 1969 return ret; 1970 } 1971 1972 static void ath11k_core_stop(struct ath11k_base *ab) 1973 { 1974 if (!test_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags)) 1975 ath11k_qmi_firmware_stop(ab); 1976 1977 ath11k_hif_stop(ab); 1978 ath11k_wmi_detach(ab); 1979 ath11k_dp_pdev_reo_cleanup(ab); 1980 1981 /* De-Init of components as needed */ 1982 } 1983 1984 static int ath11k_core_soc_create(struct ath11k_base *ab) 1985 { 1986 int ret; 1987 1988 if (ath11k_ftm_mode) { 1989 ab->fw_mode = ATH11K_FIRMWARE_MODE_FTM; 1990 ath11k_info(ab, "Booting in factory test mode\n"); 1991 } 1992 1993 ret = ath11k_qmi_init_service(ab); 1994 if (ret) { 1995 ath11k_err(ab, "failed to initialize qmi :%d\n", ret); 1996 return ret; 1997 } 1998 1999 ret = ath11k_debugfs_soc_create(ab); 2000 if (ret) { 2001 ath11k_err(ab, "failed to create ath11k debugfs\n"); 2002 goto err_qmi_deinit; 2003 } 2004 2005 ret = ath11k_hif_power_up(ab); 2006 if (ret) { 2007 ath11k_err(ab, "failed to power up :%d\n", ret); 2008 goto err_debugfs_reg; 2009 } 2010 2011 return 0; 2012 2013 err_debugfs_reg: 2014 ath11k_debugfs_soc_destroy(ab); 2015 err_qmi_deinit: 2016 ath11k_qmi_deinit_service(ab); 2017 return ret; 2018 } 2019 2020 static void ath11k_core_soc_destroy(struct ath11k_base *ab) 2021 { 2022 ath11k_debugfs_soc_destroy(ab); 2023 ath11k_dp_free(ab); 2024 ath11k_reg_free(ab); 2025 ath11k_qmi_deinit_service(ab); 2026 } 2027 2028 static int ath11k_core_pdev_create(struct ath11k_base *ab) 2029 { 2030 int ret; 2031 2032 ret = ath11k_debugfs_pdev_create(ab); 2033 if (ret) { 2034 ath11k_err(ab, "failed to create core pdev debugfs: %d\n", ret); 2035 return ret; 2036 } 2037 2038 ret = ath11k_dp_pdev_alloc(ab); 2039 if (ret) { 2040 ath11k_err(ab, "failed to attach DP pdev: %d\n", ret); 2041 goto err_pdev_debug; 2042 } 2043 2044 ret = ath11k_mac_register(ab); 2045 if (ret) { 2046 ath11k_err(ab, "failed register the radio with mac80211: %d\n", ret); 2047 goto err_dp_pdev_free; 2048 } 2049 2050 ret = ath11k_thermal_register(ab); 2051 if (ret) { 2052 ath11k_err(ab, "could not register thermal device: %d\n", 2053 ret); 2054 goto err_mac_unregister; 2055 } 2056 2057 ret = ath11k_spectral_init(ab); 2058 if (ret) { 2059 ath11k_err(ab, "failed to init spectral %d\n", ret); 2060 goto err_thermal_unregister; 2061 } 2062 2063 ret = ath11k_cfr_init(ab); 2064 if (ret) { 2065 ath11k_err(ab, "failed to init cfr %d\n", ret); 2066 goto err_spectral_unregister; 2067 } 2068 2069 return 0; 2070 2071 err_spectral_unregister: 2072 ath11k_spectral_deinit(ab); 2073 err_thermal_unregister: 2074 ath11k_thermal_unregister(ab); 2075 err_mac_unregister: 2076 ath11k_mac_unregister(ab); 2077 err_dp_pdev_free: 2078 ath11k_dp_pdev_free(ab); 2079 err_pdev_debug: 2080 ath11k_debugfs_pdev_destroy(ab); 2081 2082 return ret; 2083 } 2084 2085 static void ath11k_core_pdev_suspend_target(struct ath11k_base *ab) 2086 { 2087 struct ath11k *ar; 2088 struct ath11k_pdev *pdev; 2089 unsigned long time_left; 2090 int ret; 2091 int i; 2092 2093 if (!ab->hw_params.pdev_suspend) 2094 return; 2095 2096 for (i = 0; i < ab->num_radios; i++) { 2097 pdev = &ab->pdevs[i]; 2098 ar = pdev->ar; 2099 2100 reinit_completion(&ab->htc_suspend); 2101 2102 ret = ath11k_wmi_pdev_suspend(ar, WMI_PDEV_SUSPEND_AND_DISABLE_INTR, 2103 pdev->pdev_id); 2104 if (ret) { 2105 ath11k_warn(ab, "could not suspend target :%d\n", ret); 2106 /* pointless to try other pdevs */ 2107 return; 2108 } 2109 2110 time_left = wait_for_completion_timeout(&ab->htc_suspend, 3 * HZ); 2111 2112 if (!time_left) { 2113 ath11k_warn(ab, "suspend timed out - target pause event never came\n"); 2114 /* pointless to try other pdevs */ 2115 return; 2116 } 2117 } 2118 } 2119 2120 static void ath11k_core_pdev_destroy(struct ath11k_base *ab) 2121 { 2122 ath11k_cfr_deinit(ab); 2123 ath11k_spectral_deinit(ab); 2124 ath11k_thermal_unregister(ab); 2125 ath11k_mac_unregister(ab); 2126 ath11k_core_pdev_suspend_target(ab); 2127 ath11k_hif_irq_disable(ab); 2128 ath11k_dp_pdev_free(ab); 2129 ath11k_debugfs_pdev_destroy(ab); 2130 } 2131 2132 static int ath11k_core_start(struct ath11k_base *ab) 2133 { 2134 int ret; 2135 2136 ret = ath11k_wmi_attach(ab); 2137 if (ret) { 2138 ath11k_err(ab, "failed to attach wmi: %d\n", ret); 2139 return ret; 2140 } 2141 2142 ret = ath11k_htc_init(ab); 2143 if (ret) { 2144 ath11k_err(ab, "failed to init htc: %d\n", ret); 2145 goto err_wmi_detach; 2146 } 2147 2148 ret = ath11k_hif_start(ab); 2149 if (ret) { 2150 ath11k_err(ab, "failed to start HIF: %d\n", ret); 2151 goto err_wmi_detach; 2152 } 2153 2154 ret = ath11k_htc_wait_target(&ab->htc); 2155 if (ret) { 2156 ath11k_err(ab, "failed to connect to HTC: %d\n", ret); 2157 goto err_hif_stop; 2158 } 2159 2160 ret = ath11k_dp_htt_connect(&ab->dp); 2161 if (ret) { 2162 ath11k_err(ab, "failed to connect to HTT: %d\n", ret); 2163 goto err_hif_stop; 2164 } 2165 2166 ret = ath11k_wmi_connect(ab); 2167 if (ret) { 2168 ath11k_err(ab, "failed to connect wmi: %d\n", ret); 2169 goto err_hif_stop; 2170 } 2171 2172 ret = ath11k_htc_start(&ab->htc); 2173 if (ret) { 2174 ath11k_err(ab, "failed to start HTC: %d\n", ret); 2175 goto err_hif_stop; 2176 } 2177 2178 ret = ath11k_wmi_wait_for_service_ready(ab); 2179 if (ret) { 2180 ath11k_err(ab, "failed to receive wmi service ready event: %d\n", 2181 ret); 2182 goto err_hif_stop; 2183 } 2184 2185 ret = ath11k_mac_allocate(ab); 2186 if (ret) { 2187 ath11k_err(ab, "failed to create new hw device with mac80211 :%d\n", 2188 ret); 2189 goto err_hif_stop; 2190 } 2191 2192 ath11k_dp_pdev_pre_alloc(ab); 2193 2194 ret = ath11k_dp_pdev_reo_setup(ab); 2195 if (ret) { 2196 ath11k_err(ab, "failed to initialize reo destination rings: %d\n", ret); 2197 goto err_mac_destroy; 2198 } 2199 2200 ret = ath11k_wmi_cmd_init(ab); 2201 if (ret) { 2202 ath11k_err(ab, "failed to send wmi init cmd: %d\n", ret); 2203 goto err_reo_cleanup; 2204 } 2205 2206 ret = ath11k_wmi_wait_for_unified_ready(ab); 2207 if (ret) { 2208 ath11k_err(ab, "failed to receive wmi unified ready event: %d\n", 2209 ret); 2210 goto err_reo_cleanup; 2211 } 2212 2213 /* put hardware to DBS mode */ 2214 if (ab->hw_params.single_pdev_only && ab->hw_params.num_rxdma_per_pdev > 1) { 2215 ret = ath11k_wmi_set_hw_mode(ab, WMI_HOST_HW_MODE_DBS); 2216 if (ret) { 2217 ath11k_err(ab, "failed to send dbs mode: %d\n", ret); 2218 goto err_hif_stop; 2219 } 2220 } 2221 2222 ret = ath11k_dp_tx_htt_h2t_ver_req_msg(ab); 2223 if (ret) { 2224 ath11k_err(ab, "failed to send htt version request message: %d\n", 2225 ret); 2226 goto err_reo_cleanup; 2227 } 2228 2229 return 0; 2230 2231 err_reo_cleanup: 2232 ath11k_dp_pdev_reo_cleanup(ab); 2233 err_mac_destroy: 2234 ath11k_mac_destroy(ab); 2235 err_hif_stop: 2236 ath11k_hif_stop(ab); 2237 err_wmi_detach: 2238 ath11k_wmi_detach(ab); 2239 2240 return ret; 2241 } 2242 2243 static int ath11k_core_start_firmware(struct ath11k_base *ab, 2244 enum ath11k_firmware_mode mode) 2245 { 2246 int ret; 2247 2248 ath11k_ce_get_shadow_config(ab, &ab->qmi.ce_cfg.shadow_reg_v2, 2249 &ab->qmi.ce_cfg.shadow_reg_v2_len); 2250 2251 ret = ath11k_qmi_firmware_start(ab, mode); 2252 if (ret) { 2253 ath11k_err(ab, "failed to send firmware start: %d\n", ret); 2254 return ret; 2255 } 2256 2257 return ret; 2258 } 2259 2260 int ath11k_core_qmi_firmware_ready(struct ath11k_base *ab) 2261 { 2262 int ret; 2263 2264 switch (ath11k_crypto_mode) { 2265 case ATH11K_CRYPT_MODE_SW: 2266 set_bit(ATH11K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags); 2267 set_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags); 2268 break; 2269 case ATH11K_CRYPT_MODE_HW: 2270 clear_bit(ATH11K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags); 2271 clear_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags); 2272 break; 2273 default: 2274 ath11k_info(ab, "invalid crypto_mode: %d\n", ath11k_crypto_mode); 2275 return -EINVAL; 2276 } 2277 2278 ret = ath11k_core_start_firmware(ab, ab->fw_mode); 2279 if (ret) { 2280 ath11k_err(ab, "failed to start firmware: %d\n", ret); 2281 return ret; 2282 } 2283 2284 ret = ath11k_ce_init_pipes(ab); 2285 if (ret) { 2286 ath11k_err(ab, "failed to initialize CE: %d\n", ret); 2287 goto err_firmware_stop; 2288 } 2289 2290 ret = ath11k_dp_alloc(ab); 2291 if (ret) { 2292 ath11k_err(ab, "failed to init DP: %d\n", ret); 2293 goto err_firmware_stop; 2294 } 2295 2296 if (ath11k_frame_mode == ATH11K_HW_TXRX_RAW) 2297 set_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags); 2298 2299 mutex_lock(&ab->core_lock); 2300 ret = ath11k_core_start(ab); 2301 if (ret) { 2302 ath11k_err(ab, "failed to start core: %d\n", ret); 2303 goto err_dp_free; 2304 } 2305 2306 ret = ath11k_core_pdev_create(ab); 2307 if (ret) { 2308 ath11k_err(ab, "failed to create pdev core: %d\n", ret); 2309 goto err_core_stop; 2310 } 2311 ath11k_hif_irq_enable(ab); 2312 mutex_unlock(&ab->core_lock); 2313 2314 return 0; 2315 2316 err_core_stop: 2317 ath11k_core_stop(ab); 2318 ath11k_mac_destroy(ab); 2319 err_dp_free: 2320 ath11k_dp_free(ab); 2321 mutex_unlock(&ab->core_lock); 2322 err_firmware_stop: 2323 ath11k_qmi_firmware_stop(ab); 2324 2325 return ret; 2326 } 2327 2328 static int ath11k_core_reconfigure_on_crash(struct ath11k_base *ab) 2329 { 2330 int ret; 2331 2332 mutex_lock(&ab->core_lock); 2333 ath11k_hif_irq_disable(ab); 2334 ath11k_hif_ce_irq_disable(ab); 2335 ath11k_thermal_unregister(ab); 2336 ath11k_dp_pdev_free(ab); 2337 ath11k_cfr_deinit(ab); 2338 ath11k_spectral_deinit(ab); 2339 ath11k_ce_cleanup_pipes(ab); 2340 ath11k_wmi_detach(ab); 2341 ath11k_dp_pdev_reo_cleanup(ab); 2342 mutex_unlock(&ab->core_lock); 2343 2344 ath11k_dp_free(ab); 2345 ath11k_hal_srng_clear(ab); 2346 2347 ab->free_vdev_map = (1LL << (ab->num_radios * TARGET_NUM_VDEVS(ab))) - 1; 2348 2349 clear_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags); 2350 2351 ret = ath11k_core_qmi_firmware_ready(ab); 2352 if (ret) 2353 goto err_hal_srng_deinit; 2354 2355 clear_bit(ATH11K_FLAG_RECOVERY, &ab->dev_flags); 2356 2357 return 0; 2358 2359 err_hal_srng_deinit: 2360 ath11k_hal_srng_deinit(ab); 2361 return ret; 2362 } 2363 2364 void ath11k_core_halt(struct ath11k *ar) 2365 { 2366 struct ath11k_base *ab = ar->ab; 2367 struct list_head *pos, *n; 2368 2369 lockdep_assert_held(&ar->conf_mutex); 2370 2371 ar->num_created_vdevs = 0; 2372 ar->allocated_vdev_map = 0; 2373 2374 ath11k_mac_scan_finish(ar); 2375 ath11k_mac_peer_cleanup_all(ar); 2376 cancel_delayed_work_sync(&ar->scan.timeout); 2377 cancel_work_sync(&ar->channel_update_work); 2378 cancel_work_sync(&ar->regd_update_work); 2379 cancel_work_sync(&ab->update_11d_work); 2380 2381 rcu_assign_pointer(ab->pdevs_active[ar->pdev_idx], NULL); 2382 synchronize_rcu(); 2383 2384 spin_lock_bh(&ar->data_lock); 2385 list_for_each_safe(pos, n, &ar->arvifs) 2386 list_del_init(pos); 2387 spin_unlock_bh(&ar->data_lock); 2388 2389 idr_init(&ar->txmgmt_idr); 2390 } 2391 2392 static void ath11k_update_11d(struct work_struct *work) 2393 { 2394 struct ath11k_base *ab = container_of(work, struct ath11k_base, update_11d_work); 2395 struct ath11k *ar; 2396 struct ath11k_pdev *pdev; 2397 int ret, i; 2398 2399 for (i = 0; i < ab->num_radios; i++) { 2400 pdev = &ab->pdevs[i]; 2401 ar = pdev->ar; 2402 2403 spin_lock_bh(&ab->base_lock); 2404 memcpy(&ar->alpha2, &ab->new_alpha2, 2); 2405 spin_unlock_bh(&ab->base_lock); 2406 2407 ath11k_dbg(ab, ATH11K_DBG_WMI, "update 11d new cc %c%c for pdev %d\n", 2408 ar->alpha2[0], ar->alpha2[1], i); 2409 2410 ret = ath11k_reg_set_cc(ar); 2411 if (ret) 2412 ath11k_warn(ar->ab, 2413 "pdev id %d failed set current country code: %d\n", 2414 i, ret); 2415 } 2416 } 2417 2418 void ath11k_core_pre_reconfigure_recovery(struct ath11k_base *ab) 2419 { 2420 struct ath11k *ar; 2421 struct ath11k_pdev *pdev; 2422 int i; 2423 2424 spin_lock_bh(&ab->base_lock); 2425 ab->stats.fw_crash_counter++; 2426 spin_unlock_bh(&ab->base_lock); 2427 2428 for (i = 0; i < ab->num_radios; i++) { 2429 pdev = &ab->pdevs[i]; 2430 ar = pdev->ar; 2431 if (!ar || ar->state == ATH11K_STATE_OFF || 2432 ar->state == ATH11K_STATE_FTM) 2433 continue; 2434 2435 ieee80211_stop_queues(ar->hw); 2436 ath11k_mac_drain_tx(ar); 2437 ar->state_11d = ATH11K_11D_IDLE; 2438 complete(&ar->completed_11d_scan); 2439 complete(&ar->scan.started); 2440 complete_all(&ar->scan.completed); 2441 complete(&ar->scan.on_channel); 2442 complete(&ar->peer_assoc_done); 2443 complete(&ar->peer_delete_done); 2444 complete(&ar->install_key_done); 2445 complete(&ar->vdev_setup_done); 2446 complete(&ar->vdev_delete_done); 2447 complete(&ar->bss_survey_done); 2448 complete(&ar->thermal.wmi_sync); 2449 2450 wake_up(&ar->dp.tx_empty_waitq); 2451 ath11k_mac_tx_mgmt_pending_free(ar); 2452 idr_destroy(&ar->txmgmt_idr); 2453 wake_up(&ar->txmgmt_empty_waitq); 2454 2455 ar->monitor_vdev_id = -1; 2456 clear_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags); 2457 clear_bit(ATH11K_FLAG_MONITOR_VDEV_CREATED, &ar->monitor_flags); 2458 } 2459 2460 wake_up(&ab->wmi_ab.tx_credits_wq); 2461 wake_up(&ab->peer_mapping_wq); 2462 2463 reinit_completion(&ab->driver_recovery); 2464 } 2465 2466 static void ath11k_core_post_reconfigure_recovery(struct ath11k_base *ab) 2467 { 2468 struct ath11k *ar; 2469 struct ath11k_pdev *pdev; 2470 int i; 2471 2472 for (i = 0; i < ab->num_radios; i++) { 2473 pdev = &ab->pdevs[i]; 2474 ar = pdev->ar; 2475 if (!ar || ar->state == ATH11K_STATE_OFF) 2476 continue; 2477 2478 mutex_lock(&ar->conf_mutex); 2479 2480 switch (ar->state) { 2481 case ATH11K_STATE_ON: 2482 ar->state = ATH11K_STATE_RESTARTING; 2483 ath11k_core_halt(ar); 2484 ieee80211_restart_hw(ar->hw); 2485 break; 2486 case ATH11K_STATE_OFF: 2487 ath11k_warn(ab, 2488 "cannot restart radio %d that hasn't been started\n", 2489 i); 2490 break; 2491 case ATH11K_STATE_RESTARTING: 2492 break; 2493 case ATH11K_STATE_RESTARTED: 2494 ar->state = ATH11K_STATE_WEDGED; 2495 fallthrough; 2496 case ATH11K_STATE_WEDGED: 2497 ath11k_warn(ab, 2498 "device is wedged, will not restart radio %d\n", i); 2499 break; 2500 case ATH11K_STATE_FTM: 2501 ath11k_dbg(ab, ATH11K_DBG_TESTMODE, 2502 "fw mode reset done radio %d\n", i); 2503 break; 2504 } 2505 2506 mutex_unlock(&ar->conf_mutex); 2507 } 2508 complete(&ab->driver_recovery); 2509 } 2510 2511 static void ath11k_core_restart(struct work_struct *work) 2512 { 2513 struct ath11k_base *ab = container_of(work, struct ath11k_base, restart_work); 2514 int ret; 2515 2516 ret = ath11k_core_reconfigure_on_crash(ab); 2517 if (ret) { 2518 ath11k_err(ab, "failed to reconfigure driver on crash recovery\n"); 2519 return; 2520 } 2521 2522 if (ab->is_reset) 2523 complete_all(&ab->reconfigure_complete); 2524 2525 if (!ab->is_reset) 2526 ath11k_core_post_reconfigure_recovery(ab); 2527 2528 complete(&ab->restart_completed); 2529 } 2530 2531 static void ath11k_core_reset(struct work_struct *work) 2532 { 2533 struct ath11k_base *ab = container_of(work, struct ath11k_base, reset_work); 2534 int reset_count, fail_cont_count; 2535 long time_left; 2536 2537 if (!(test_bit(ATH11K_FLAG_REGISTERED, &ab->dev_flags))) { 2538 ath11k_warn(ab, "ignore reset dev flags 0x%lx\n", ab->dev_flags); 2539 return; 2540 } 2541 2542 /* Sometimes the recovery will fail and then the next all recovery fail, 2543 * this is to avoid infinite recovery since it can not recovery success. 2544 */ 2545 fail_cont_count = atomic_read(&ab->fail_cont_count); 2546 2547 if (fail_cont_count >= ATH11K_RESET_MAX_FAIL_COUNT_FINAL) 2548 return; 2549 2550 if (fail_cont_count >= ATH11K_RESET_MAX_FAIL_COUNT_FIRST && 2551 time_before(jiffies, ab->reset_fail_timeout)) 2552 return; 2553 2554 reset_count = atomic_inc_return(&ab->reset_count); 2555 2556 if (reset_count > 1) { 2557 /* Sometimes it happened another reset worker before the previous one 2558 * completed, then the second reset worker will destroy the previous one, 2559 * thus below is to avoid that. 2560 */ 2561 ath11k_warn(ab, "already resetting count %d\n", reset_count); 2562 2563 reinit_completion(&ab->reset_complete); 2564 time_left = wait_for_completion_timeout(&ab->reset_complete, 2565 ATH11K_RESET_TIMEOUT_HZ); 2566 2567 if (time_left) { 2568 ath11k_dbg(ab, ATH11K_DBG_BOOT, "to skip reset\n"); 2569 atomic_dec(&ab->reset_count); 2570 return; 2571 } 2572 2573 ab->reset_fail_timeout = jiffies + ATH11K_RESET_FAIL_TIMEOUT_HZ; 2574 /* Record the continuous recovery fail count when recovery failed*/ 2575 atomic_inc(&ab->fail_cont_count); 2576 } 2577 2578 ath11k_dbg(ab, ATH11K_DBG_BOOT, "reset starting\n"); 2579 2580 ab->is_reset = true; 2581 atomic_set(&ab->recovery_count, 0); 2582 reinit_completion(&ab->recovery_start); 2583 atomic_set(&ab->recovery_start_count, 0); 2584 2585 ath11k_coredump_collect(ab); 2586 ath11k_core_pre_reconfigure_recovery(ab); 2587 2588 reinit_completion(&ab->reconfigure_complete); 2589 ath11k_core_post_reconfigure_recovery(ab); 2590 2591 ath11k_dbg(ab, ATH11K_DBG_BOOT, "waiting recovery start...\n"); 2592 2593 time_left = wait_for_completion_timeout(&ab->recovery_start, 2594 ATH11K_RECOVER_START_TIMEOUT_HZ); 2595 2596 ath11k_hif_power_down(ab, false); 2597 ath11k_hif_power_up(ab); 2598 2599 ath11k_dbg(ab, ATH11K_DBG_BOOT, "reset started\n"); 2600 } 2601 2602 static int ath11k_init_hw_params(struct ath11k_base *ab) 2603 { 2604 const struct ath11k_hw_params *hw_params = NULL; 2605 int i; 2606 2607 for (i = 0; i < ARRAY_SIZE(ath11k_hw_params); i++) { 2608 hw_params = &ath11k_hw_params[i]; 2609 2610 if (hw_params->hw_rev == ab->hw_rev) 2611 break; 2612 } 2613 2614 if (i == ARRAY_SIZE(ath11k_hw_params)) { 2615 ath11k_err(ab, "Unsupported hardware version: 0x%x\n", ab->hw_rev); 2616 return -EINVAL; 2617 } 2618 2619 ab->hw_params = *hw_params; 2620 2621 ath11k_info(ab, "%s\n", ab->hw_params.name); 2622 2623 return 0; 2624 } 2625 2626 int ath11k_core_pre_init(struct ath11k_base *ab) 2627 { 2628 int ret; 2629 2630 ret = ath11k_init_hw_params(ab); 2631 if (ret) { 2632 ath11k_err(ab, "failed to get hw params: %d\n", ret); 2633 return ret; 2634 } 2635 2636 ret = ath11k_fw_pre_init(ab); 2637 if (ret) { 2638 ath11k_err(ab, "failed to pre init firmware: %d", ret); 2639 return ret; 2640 } 2641 2642 return 0; 2643 } 2644 EXPORT_SYMBOL(ath11k_core_pre_init); 2645 2646 static int ath11k_core_pm_notify(struct notifier_block *nb, 2647 unsigned long action, void *nouse) 2648 { 2649 struct ath11k_base *ab = container_of(nb, struct ath11k_base, 2650 pm_nb); 2651 2652 switch (action) { 2653 case PM_SUSPEND_PREPARE: 2654 ab->actual_pm_policy = ab->pm_policy; 2655 break; 2656 case PM_HIBERNATION_PREPARE: 2657 ab->actual_pm_policy = ATH11K_PM_DEFAULT; 2658 break; 2659 default: 2660 break; 2661 } 2662 2663 return NOTIFY_OK; 2664 } 2665 2666 static int ath11k_core_pm_notifier_register(struct ath11k_base *ab) 2667 { 2668 ab->pm_nb.notifier_call = ath11k_core_pm_notify; 2669 return register_pm_notifier(&ab->pm_nb); 2670 } 2671 2672 void ath11k_core_pm_notifier_unregister(struct ath11k_base *ab) 2673 { 2674 int ret; 2675 2676 ret = unregister_pm_notifier(&ab->pm_nb); 2677 if (ret) 2678 /* just warn here, there is nothing can be done in fail case */ 2679 ath11k_warn(ab, "failed to unregister PM notifier %d\n", ret); 2680 } 2681 EXPORT_SYMBOL(ath11k_core_pm_notifier_unregister); 2682 2683 int ath11k_core_init(struct ath11k_base *ab) 2684 { 2685 const struct dmi_system_id *dmi_id; 2686 int ret; 2687 2688 dmi_id = dmi_first_match(ath11k_pm_quirk_table); 2689 if (dmi_id) 2690 ab->pm_policy = (kernel_ulong_t)dmi_id->driver_data; 2691 else 2692 ab->pm_policy = ATH11K_PM_DEFAULT; 2693 2694 ath11k_dbg(ab, ATH11K_DBG_BOOT, "pm policy %u\n", ab->pm_policy); 2695 2696 ret = ath11k_core_pm_notifier_register(ab); 2697 if (ret) { 2698 ath11k_err(ab, "failed to register PM notifier: %d\n", ret); 2699 return ret; 2700 } 2701 2702 ret = ath11k_core_soc_create(ab); 2703 if (ret) { 2704 ath11k_err(ab, "failed to create soc core: %d\n", ret); 2705 goto err_unregister_pm_notifier; 2706 } 2707 2708 return 0; 2709 2710 err_unregister_pm_notifier: 2711 ath11k_core_pm_notifier_unregister(ab); 2712 2713 return ret; 2714 } 2715 EXPORT_SYMBOL(ath11k_core_init); 2716 2717 void ath11k_core_deinit(struct ath11k_base *ab) 2718 { 2719 mutex_lock(&ab->core_lock); 2720 2721 ath11k_core_pdev_destroy(ab); 2722 ath11k_core_stop(ab); 2723 2724 mutex_unlock(&ab->core_lock); 2725 2726 ath11k_hif_power_down(ab, false); 2727 ath11k_mac_destroy(ab); 2728 ath11k_core_soc_destroy(ab); 2729 ath11k_core_pm_notifier_unregister(ab); 2730 } 2731 EXPORT_SYMBOL(ath11k_core_deinit); 2732 2733 void ath11k_core_free(struct ath11k_base *ab) 2734 { 2735 destroy_workqueue(ab->workqueue_aux); 2736 destroy_workqueue(ab->workqueue); 2737 2738 kfree(ab); 2739 } 2740 EXPORT_SYMBOL(ath11k_core_free); 2741 2742 struct ath11k_base *ath11k_core_alloc(struct device *dev, size_t priv_size, 2743 enum ath11k_bus bus) 2744 { 2745 struct ath11k_base *ab; 2746 2747 ab = kzalloc(sizeof(*ab) + priv_size, GFP_KERNEL); 2748 if (!ab) 2749 return NULL; 2750 2751 init_completion(&ab->driver_recovery); 2752 2753 ab->workqueue = create_singlethread_workqueue("ath11k_wq"); 2754 if (!ab->workqueue) 2755 goto err_sc_free; 2756 2757 ab->workqueue_aux = create_singlethread_workqueue("ath11k_aux_wq"); 2758 if (!ab->workqueue_aux) 2759 goto err_free_wq; 2760 2761 mutex_init(&ab->core_lock); 2762 mutex_init(&ab->tbl_mtx_lock); 2763 spin_lock_init(&ab->base_lock); 2764 mutex_init(&ab->vdev_id_11d_lock); 2765 init_completion(&ab->reset_complete); 2766 init_completion(&ab->reconfigure_complete); 2767 init_completion(&ab->recovery_start); 2768 2769 INIT_LIST_HEAD(&ab->peers); 2770 init_waitqueue_head(&ab->peer_mapping_wq); 2771 init_waitqueue_head(&ab->wmi_ab.tx_credits_wq); 2772 init_waitqueue_head(&ab->qmi.cold_boot_waitq); 2773 INIT_WORK(&ab->restart_work, ath11k_core_restart); 2774 INIT_WORK(&ab->update_11d_work, ath11k_update_11d); 2775 INIT_WORK(&ab->reset_work, ath11k_core_reset); 2776 INIT_WORK(&ab->dump_work, ath11k_coredump_upload); 2777 timer_setup(&ab->rx_replenish_retry, ath11k_ce_rx_replenish_retry, 0); 2778 init_completion(&ab->htc_suspend); 2779 init_completion(&ab->wow.wakeup_completed); 2780 init_completion(&ab->restart_completed); 2781 2782 ab->dev = dev; 2783 ab->hif.bus = bus; 2784 2785 return ab; 2786 2787 err_free_wq: 2788 destroy_workqueue(ab->workqueue); 2789 err_sc_free: 2790 kfree(ab); 2791 return NULL; 2792 } 2793 EXPORT_SYMBOL(ath11k_core_alloc); 2794 2795 MODULE_DESCRIPTION("Core module for Qualcomm Atheros 802.11ax wireless LAN cards."); 2796 MODULE_LICENSE("Dual BSD/GPL"); 2797