1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include <linux/module.h> 8 #include <linux/slab.h> 9 #include <linux/remoteproc.h> 10 #include <linux/firmware.h> 11 #include <linux/of.h> 12 13 #include "core.h" 14 #include "dp_tx.h" 15 #include "dp_rx.h" 16 #include "debug.h" 17 #include "hif.h" 18 #include "wow.h" 19 #include "fw.h" 20 21 unsigned int ath11k_debug_mask; 22 EXPORT_SYMBOL(ath11k_debug_mask); 23 module_param_named(debug_mask, ath11k_debug_mask, uint, 0644); 24 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 25 26 static unsigned int ath11k_crypto_mode; 27 module_param_named(crypto_mode, ath11k_crypto_mode, uint, 0644); 28 MODULE_PARM_DESC(crypto_mode, "crypto mode: 0-hardware, 1-software"); 29 30 /* frame mode values are mapped as per enum ath11k_hw_txrx_mode */ 31 unsigned int ath11k_frame_mode = ATH11K_HW_TXRX_NATIVE_WIFI; 32 module_param_named(frame_mode, ath11k_frame_mode, uint, 0644); 33 MODULE_PARM_DESC(frame_mode, 34 "Datapath frame mode (0: raw, 1: native wifi (default), 2: ethernet)"); 35 36 bool ath11k_ftm_mode; 37 module_param_named(ftm_mode, ath11k_ftm_mode, bool, 0444); 38 MODULE_PARM_DESC(ftm_mode, "Boots up in factory test mode"); 39 40 static const struct ath11k_hw_params ath11k_hw_params[] = { 41 { 42 .hw_rev = ATH11K_HW_IPQ8074, 43 .name = "ipq8074 hw2.0", 44 .fw = { 45 .dir = "IPQ8074/hw2.0", 46 .board_size = 256 * 1024, 47 .cal_offset = 128 * 1024, 48 }, 49 .max_radios = 3, 50 .bdf_addr = 0x4B0C0000, 51 .hw_ops = &ipq8074_ops, 52 .ring_mask = &ath11k_hw_ring_mask_ipq8074, 53 .internal_sleep_clock = false, 54 .regs = &ipq8074_regs, 55 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074, 56 .host_ce_config = ath11k_host_ce_config_ipq8074, 57 .ce_count = 12, 58 .target_ce_config = ath11k_target_ce_config_wlan_ipq8074, 59 .target_ce_count = 11, 60 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq8074, 61 .svc_to_ce_map_len = 21, 62 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 63 .single_pdev_only = false, 64 .rxdma1_enable = true, 65 .num_rxmda_per_pdev = 1, 66 .rx_mac_buf_ring = false, 67 .vdev_start_delay = false, 68 .htt_peer_map_v2 = true, 69 70 .spectral = { 71 .fft_sz = 2, 72 /* HW bug, expected BIN size is 2 bytes but HW report as 4 bytes. 73 * so added pad size as 2 bytes to compensate the BIN size 74 */ 75 .fft_pad_sz = 2, 76 .summary_pad_sz = 0, 77 .fft_hdr_len = 16, 78 .max_fft_bins = 512, 79 .fragment_160mhz = true, 80 }, 81 82 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 83 BIT(NL80211_IFTYPE_AP) | 84 BIT(NL80211_IFTYPE_MESH_POINT), 85 .supports_monitor = true, 86 .full_monitor_mode = false, 87 .supports_shadow_regs = false, 88 .idle_ps = false, 89 .supports_sta_ps = false, 90 .coldboot_cal_mm = true, 91 .coldboot_cal_ftm = true, 92 .cbcal_restart_fw = true, 93 .fw_mem_mode = 0, 94 .num_vdevs = 16 + 1, 95 .num_peers = 512, 96 .supports_suspend = false, 97 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074), 98 .supports_regdb = false, 99 .fix_l1ss = true, 100 .credit_flow = false, 101 .max_tx_ring = DP_TCL_NUM_RING_MAX, 102 .hal_params = &ath11k_hw_hal_params_ipq8074, 103 .supports_dynamic_smps_6ghz = false, 104 .alloc_cacheable_memory = true, 105 .supports_rssi_stats = false, 106 .fw_wmi_diag_event = false, 107 .current_cc_support = false, 108 .dbr_debug_support = true, 109 .global_reset = false, 110 .bios_sar_capa = NULL, 111 .m3_fw_support = false, 112 .fixed_bdf_addr = true, 113 .fixed_mem_region = true, 114 .static_window_map = false, 115 .hybrid_bus_type = false, 116 .fixed_fw_mem = false, 117 .support_off_channel_tx = false, 118 .supports_multi_bssid = false, 119 120 .sram_dump = {}, 121 122 .tcl_ring_retry = true, 123 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 124 .smp2p_wow_exit = false, 125 .support_dual_stations = false, 126 }, 127 { 128 .hw_rev = ATH11K_HW_IPQ6018_HW10, 129 .name = "ipq6018 hw1.0", 130 .fw = { 131 .dir = "IPQ6018/hw1.0", 132 .board_size = 256 * 1024, 133 .cal_offset = 128 * 1024, 134 }, 135 .max_radios = 2, 136 .bdf_addr = 0x4ABC0000, 137 .hw_ops = &ipq6018_ops, 138 .ring_mask = &ath11k_hw_ring_mask_ipq8074, 139 .internal_sleep_clock = false, 140 .regs = &ipq8074_regs, 141 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074, 142 .host_ce_config = ath11k_host_ce_config_ipq8074, 143 .ce_count = 12, 144 .target_ce_config = ath11k_target_ce_config_wlan_ipq8074, 145 .target_ce_count = 11, 146 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq6018, 147 .svc_to_ce_map_len = 19, 148 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 149 .single_pdev_only = false, 150 .rxdma1_enable = true, 151 .num_rxmda_per_pdev = 1, 152 .rx_mac_buf_ring = false, 153 .vdev_start_delay = false, 154 .htt_peer_map_v2 = true, 155 156 .spectral = { 157 .fft_sz = 4, 158 .fft_pad_sz = 0, 159 .summary_pad_sz = 0, 160 .fft_hdr_len = 16, 161 .max_fft_bins = 512, 162 .fragment_160mhz = true, 163 }, 164 165 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 166 BIT(NL80211_IFTYPE_AP) | 167 BIT(NL80211_IFTYPE_MESH_POINT), 168 .supports_monitor = true, 169 .full_monitor_mode = false, 170 .supports_shadow_regs = false, 171 .idle_ps = false, 172 .supports_sta_ps = false, 173 .coldboot_cal_mm = true, 174 .coldboot_cal_ftm = true, 175 .cbcal_restart_fw = true, 176 .fw_mem_mode = 0, 177 .num_vdevs = 16 + 1, 178 .num_peers = 512, 179 .supports_suspend = false, 180 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074), 181 .supports_regdb = false, 182 .fix_l1ss = true, 183 .credit_flow = false, 184 .max_tx_ring = DP_TCL_NUM_RING_MAX, 185 .hal_params = &ath11k_hw_hal_params_ipq8074, 186 .supports_dynamic_smps_6ghz = false, 187 .alloc_cacheable_memory = true, 188 .supports_rssi_stats = false, 189 .fw_wmi_diag_event = false, 190 .current_cc_support = false, 191 .dbr_debug_support = true, 192 .global_reset = false, 193 .bios_sar_capa = NULL, 194 .m3_fw_support = false, 195 .fixed_bdf_addr = true, 196 .fixed_mem_region = true, 197 .static_window_map = false, 198 .hybrid_bus_type = false, 199 .fixed_fw_mem = false, 200 .support_off_channel_tx = false, 201 .supports_multi_bssid = false, 202 203 .sram_dump = {}, 204 205 .tcl_ring_retry = true, 206 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 207 .smp2p_wow_exit = false, 208 .support_fw_mac_sequence = false, 209 .support_dual_stations = false, 210 }, 211 { 212 .name = "qca6390 hw2.0", 213 .hw_rev = ATH11K_HW_QCA6390_HW20, 214 .fw = { 215 .dir = "QCA6390/hw2.0", 216 .board_size = 256 * 1024, 217 .cal_offset = 128 * 1024, 218 }, 219 .max_radios = 3, 220 .bdf_addr = 0x4B0C0000, 221 .hw_ops = &qca6390_ops, 222 .ring_mask = &ath11k_hw_ring_mask_qca6390, 223 .internal_sleep_clock = true, 224 .regs = &qca6390_regs, 225 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390, 226 .host_ce_config = ath11k_host_ce_config_qca6390, 227 .ce_count = 9, 228 .target_ce_config = ath11k_target_ce_config_wlan_qca6390, 229 .target_ce_count = 9, 230 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, 231 .svc_to_ce_map_len = 14, 232 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 233 .single_pdev_only = true, 234 .rxdma1_enable = false, 235 .num_rxmda_per_pdev = 2, 236 .rx_mac_buf_ring = true, 237 .vdev_start_delay = true, 238 .htt_peer_map_v2 = false, 239 240 .spectral = { 241 .fft_sz = 0, 242 .fft_pad_sz = 0, 243 .summary_pad_sz = 0, 244 .fft_hdr_len = 0, 245 .max_fft_bins = 0, 246 .fragment_160mhz = false, 247 }, 248 249 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 250 BIT(NL80211_IFTYPE_AP) | 251 BIT(NL80211_IFTYPE_P2P_DEVICE) | 252 BIT(NL80211_IFTYPE_P2P_CLIENT) | 253 BIT(NL80211_IFTYPE_P2P_GO), 254 .supports_monitor = false, 255 .full_monitor_mode = false, 256 .supports_shadow_regs = true, 257 .idle_ps = true, 258 .supports_sta_ps = true, 259 .coldboot_cal_mm = false, 260 .coldboot_cal_ftm = false, 261 .cbcal_restart_fw = false, 262 .fw_mem_mode = 0, 263 .num_vdevs = 2 + 1, 264 .num_peers = 512, 265 .supports_suspend = true, 266 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074), 267 .supports_regdb = false, 268 .fix_l1ss = true, 269 .credit_flow = true, 270 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390, 271 .hal_params = &ath11k_hw_hal_params_qca6390, 272 .supports_dynamic_smps_6ghz = false, 273 .alloc_cacheable_memory = false, 274 .supports_rssi_stats = true, 275 .fw_wmi_diag_event = true, 276 .current_cc_support = true, 277 .dbr_debug_support = false, 278 .global_reset = true, 279 .bios_sar_capa = NULL, 280 .m3_fw_support = true, 281 .fixed_bdf_addr = false, 282 .fixed_mem_region = false, 283 .static_window_map = false, 284 .hybrid_bus_type = false, 285 .fixed_fw_mem = false, 286 .support_off_channel_tx = true, 287 .supports_multi_bssid = true, 288 289 .sram_dump = { 290 .start = 0x01400000, 291 .end = 0x0171ffff, 292 }, 293 294 .tcl_ring_retry = true, 295 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 296 .smp2p_wow_exit = false, 297 .support_fw_mac_sequence = true, 298 .support_dual_stations = true, 299 }, 300 { 301 .name = "qcn9074 hw1.0", 302 .hw_rev = ATH11K_HW_QCN9074_HW10, 303 .fw = { 304 .dir = "QCN9074/hw1.0", 305 .board_size = 256 * 1024, 306 .cal_offset = 128 * 1024, 307 }, 308 .max_radios = 1, 309 .single_pdev_only = false, 310 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9074, 311 .hw_ops = &qcn9074_ops, 312 .ring_mask = &ath11k_hw_ring_mask_qcn9074, 313 .internal_sleep_clock = false, 314 .regs = &qcn9074_regs, 315 .host_ce_config = ath11k_host_ce_config_qcn9074, 316 .ce_count = 6, 317 .target_ce_config = ath11k_target_ce_config_wlan_qcn9074, 318 .target_ce_count = 9, 319 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qcn9074, 320 .svc_to_ce_map_len = 18, 321 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 322 .rxdma1_enable = true, 323 .num_rxmda_per_pdev = 1, 324 .rx_mac_buf_ring = false, 325 .vdev_start_delay = false, 326 .htt_peer_map_v2 = true, 327 328 .spectral = { 329 .fft_sz = 2, 330 .fft_pad_sz = 0, 331 .summary_pad_sz = 16, 332 .fft_hdr_len = 24, 333 .max_fft_bins = 1024, 334 .fragment_160mhz = false, 335 }, 336 337 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 338 BIT(NL80211_IFTYPE_AP) | 339 BIT(NL80211_IFTYPE_MESH_POINT), 340 .supports_monitor = true, 341 .full_monitor_mode = true, 342 .supports_shadow_regs = false, 343 .idle_ps = false, 344 .supports_sta_ps = false, 345 .coldboot_cal_mm = false, 346 .coldboot_cal_ftm = true, 347 .cbcal_restart_fw = true, 348 .fw_mem_mode = 2, 349 .num_vdevs = 8, 350 .num_peers = 128, 351 .supports_suspend = false, 352 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074), 353 .supports_regdb = false, 354 .fix_l1ss = true, 355 .credit_flow = false, 356 .max_tx_ring = DP_TCL_NUM_RING_MAX, 357 .hal_params = &ath11k_hw_hal_params_ipq8074, 358 .supports_dynamic_smps_6ghz = true, 359 .alloc_cacheable_memory = true, 360 .supports_rssi_stats = false, 361 .fw_wmi_diag_event = false, 362 .current_cc_support = false, 363 .dbr_debug_support = true, 364 .global_reset = false, 365 .bios_sar_capa = NULL, 366 .m3_fw_support = true, 367 .fixed_bdf_addr = false, 368 .fixed_mem_region = false, 369 .static_window_map = true, 370 .hybrid_bus_type = false, 371 .fixed_fw_mem = false, 372 .support_off_channel_tx = false, 373 .supports_multi_bssid = false, 374 375 .sram_dump = {}, 376 377 .tcl_ring_retry = true, 378 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 379 .smp2p_wow_exit = false, 380 .support_fw_mac_sequence = false, 381 .support_dual_stations = false, 382 }, 383 { 384 .name = "wcn6855 hw2.0", 385 .hw_rev = ATH11K_HW_WCN6855_HW20, 386 .fw = { 387 .dir = "WCN6855/hw2.0", 388 .board_size = 256 * 1024, 389 .cal_offset = 128 * 1024, 390 }, 391 .max_radios = 3, 392 .bdf_addr = 0x4B0C0000, 393 .hw_ops = &wcn6855_ops, 394 .ring_mask = &ath11k_hw_ring_mask_qca6390, 395 .internal_sleep_clock = true, 396 .regs = &wcn6855_regs, 397 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390, 398 .host_ce_config = ath11k_host_ce_config_qca6390, 399 .ce_count = 9, 400 .target_ce_config = ath11k_target_ce_config_wlan_qca6390, 401 .target_ce_count = 9, 402 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, 403 .svc_to_ce_map_len = 14, 404 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 405 .single_pdev_only = true, 406 .rxdma1_enable = false, 407 .num_rxmda_per_pdev = 2, 408 .rx_mac_buf_ring = true, 409 .vdev_start_delay = true, 410 .htt_peer_map_v2 = false, 411 412 .spectral = { 413 .fft_sz = 0, 414 .fft_pad_sz = 0, 415 .summary_pad_sz = 0, 416 .fft_hdr_len = 0, 417 .max_fft_bins = 0, 418 .fragment_160mhz = false, 419 }, 420 421 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 422 BIT(NL80211_IFTYPE_AP) | 423 BIT(NL80211_IFTYPE_P2P_DEVICE) | 424 BIT(NL80211_IFTYPE_P2P_CLIENT) | 425 BIT(NL80211_IFTYPE_P2P_GO), 426 .supports_monitor = false, 427 .full_monitor_mode = false, 428 .supports_shadow_regs = true, 429 .idle_ps = true, 430 .supports_sta_ps = true, 431 .coldboot_cal_mm = false, 432 .coldboot_cal_ftm = false, 433 .cbcal_restart_fw = false, 434 .fw_mem_mode = 0, 435 .num_vdevs = 2 + 1, 436 .num_peers = 512, 437 .supports_suspend = true, 438 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855), 439 .supports_regdb = true, 440 .fix_l1ss = false, 441 .credit_flow = true, 442 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390, 443 .hal_params = &ath11k_hw_hal_params_qca6390, 444 .supports_dynamic_smps_6ghz = false, 445 .alloc_cacheable_memory = false, 446 .supports_rssi_stats = true, 447 .fw_wmi_diag_event = true, 448 .current_cc_support = true, 449 .dbr_debug_support = false, 450 .global_reset = true, 451 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855, 452 .m3_fw_support = true, 453 .fixed_bdf_addr = false, 454 .fixed_mem_region = false, 455 .static_window_map = false, 456 .hybrid_bus_type = false, 457 .fixed_fw_mem = false, 458 .support_off_channel_tx = true, 459 .supports_multi_bssid = true, 460 461 .sram_dump = { 462 .start = 0x01400000, 463 .end = 0x0177ffff, 464 }, 465 466 .tcl_ring_retry = true, 467 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 468 .smp2p_wow_exit = false, 469 .support_fw_mac_sequence = true, 470 .support_dual_stations = true, 471 }, 472 { 473 .name = "wcn6855 hw2.1", 474 .hw_rev = ATH11K_HW_WCN6855_HW21, 475 .fw = { 476 .dir = "WCN6855/hw2.1", 477 .board_size = 256 * 1024, 478 .cal_offset = 128 * 1024, 479 }, 480 .max_radios = 3, 481 .bdf_addr = 0x4B0C0000, 482 .hw_ops = &wcn6855_ops, 483 .ring_mask = &ath11k_hw_ring_mask_qca6390, 484 .internal_sleep_clock = true, 485 .regs = &wcn6855_regs, 486 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390, 487 .host_ce_config = ath11k_host_ce_config_qca6390, 488 .ce_count = 9, 489 .target_ce_config = ath11k_target_ce_config_wlan_qca6390, 490 .target_ce_count = 9, 491 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, 492 .svc_to_ce_map_len = 14, 493 .single_pdev_only = true, 494 .rxdma1_enable = false, 495 .num_rxmda_per_pdev = 2, 496 .rx_mac_buf_ring = true, 497 .vdev_start_delay = true, 498 .htt_peer_map_v2 = false, 499 500 .spectral = { 501 .fft_sz = 0, 502 .fft_pad_sz = 0, 503 .summary_pad_sz = 0, 504 .fft_hdr_len = 0, 505 .max_fft_bins = 0, 506 .fragment_160mhz = false, 507 }, 508 509 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 510 BIT(NL80211_IFTYPE_AP) | 511 BIT(NL80211_IFTYPE_P2P_DEVICE) | 512 BIT(NL80211_IFTYPE_P2P_CLIENT) | 513 BIT(NL80211_IFTYPE_P2P_GO), 514 .supports_monitor = false, 515 .supports_shadow_regs = true, 516 .idle_ps = true, 517 .supports_sta_ps = true, 518 .coldboot_cal_mm = false, 519 .coldboot_cal_ftm = false, 520 .cbcal_restart_fw = false, 521 .fw_mem_mode = 0, 522 .num_vdevs = 2 + 1, 523 .num_peers = 512, 524 .supports_suspend = true, 525 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855), 526 .supports_regdb = true, 527 .fix_l1ss = false, 528 .credit_flow = true, 529 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390, 530 .hal_params = &ath11k_hw_hal_params_qca6390, 531 .supports_dynamic_smps_6ghz = false, 532 .alloc_cacheable_memory = false, 533 .supports_rssi_stats = true, 534 .fw_wmi_diag_event = true, 535 .current_cc_support = true, 536 .dbr_debug_support = false, 537 .global_reset = true, 538 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855, 539 .m3_fw_support = true, 540 .fixed_bdf_addr = false, 541 .fixed_mem_region = false, 542 .static_window_map = false, 543 .hybrid_bus_type = false, 544 .fixed_fw_mem = false, 545 .support_off_channel_tx = true, 546 .supports_multi_bssid = true, 547 548 .sram_dump = { 549 .start = 0x01400000, 550 .end = 0x0177ffff, 551 }, 552 553 .tcl_ring_retry = true, 554 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 555 .smp2p_wow_exit = false, 556 .support_fw_mac_sequence = true, 557 .support_dual_stations = true, 558 }, 559 { 560 .name = "wcn6750 hw1.0", 561 .hw_rev = ATH11K_HW_WCN6750_HW10, 562 .fw = { 563 .dir = "WCN6750/hw1.0", 564 .board_size = 256 * 1024, 565 .cal_offset = 128 * 1024, 566 }, 567 .max_radios = 1, 568 .bdf_addr = 0x4B0C0000, 569 .hw_ops = &wcn6750_ops, 570 .ring_mask = &ath11k_hw_ring_mask_wcn6750, 571 .internal_sleep_clock = false, 572 .regs = &wcn6750_regs, 573 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_WCN6750, 574 .host_ce_config = ath11k_host_ce_config_qca6390, 575 .ce_count = 9, 576 .target_ce_config = ath11k_target_ce_config_wlan_qca6390, 577 .target_ce_count = 9, 578 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, 579 .svc_to_ce_map_len = 14, 580 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 581 .single_pdev_only = true, 582 .rxdma1_enable = false, 583 .num_rxmda_per_pdev = 1, 584 .rx_mac_buf_ring = true, 585 .vdev_start_delay = true, 586 .htt_peer_map_v2 = false, 587 588 .spectral = { 589 .fft_sz = 0, 590 .fft_pad_sz = 0, 591 .summary_pad_sz = 0, 592 .fft_hdr_len = 0, 593 .max_fft_bins = 0, 594 .fragment_160mhz = false, 595 }, 596 597 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 598 BIT(NL80211_IFTYPE_AP), 599 .supports_monitor = false, 600 .supports_shadow_regs = true, 601 .idle_ps = true, 602 .supports_sta_ps = true, 603 .coldboot_cal_mm = true, 604 .coldboot_cal_ftm = true, 605 .cbcal_restart_fw = false, 606 .fw_mem_mode = 0, 607 .num_vdevs = 16 + 1, 608 .num_peers = 512, 609 .supports_suspend = false, 610 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074), 611 .supports_regdb = true, 612 .fix_l1ss = false, 613 .credit_flow = true, 614 .max_tx_ring = DP_TCL_NUM_RING_MAX, 615 .hal_params = &ath11k_hw_hal_params_wcn6750, 616 .supports_dynamic_smps_6ghz = false, 617 .alloc_cacheable_memory = false, 618 .supports_rssi_stats = true, 619 .fw_wmi_diag_event = false, 620 .current_cc_support = true, 621 .dbr_debug_support = false, 622 .global_reset = false, 623 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855, 624 .m3_fw_support = false, 625 .fixed_bdf_addr = false, 626 .fixed_mem_region = false, 627 .static_window_map = true, 628 .hybrid_bus_type = true, 629 .fixed_fw_mem = true, 630 .support_off_channel_tx = true, 631 .supports_multi_bssid = true, 632 633 .sram_dump = {}, 634 635 .tcl_ring_retry = false, 636 .tx_ring_size = DP_TCL_DATA_RING_SIZE_WCN6750, 637 .smp2p_wow_exit = true, 638 .support_fw_mac_sequence = true, 639 .support_dual_stations = false, 640 }, 641 { 642 .hw_rev = ATH11K_HW_IPQ5018_HW10, 643 .name = "ipq5018 hw1.0", 644 .fw = { 645 .dir = "IPQ5018/hw1.0", 646 .board_size = 256 * 1024, 647 .cal_offset = 128 * 1024, 648 }, 649 .max_radios = MAX_RADIOS_5018, 650 .bdf_addr = 0x4BA00000, 651 /* hal_desc_sz and hw ops are similar to qcn9074 */ 652 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074), 653 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074, 654 .ring_mask = &ath11k_hw_ring_mask_ipq8074, 655 .credit_flow = false, 656 .max_tx_ring = 1, 657 .spectral = { 658 .fft_sz = 2, 659 .fft_pad_sz = 0, 660 .summary_pad_sz = 16, 661 .fft_hdr_len = 24, 662 .max_fft_bins = 1024, 663 }, 664 .internal_sleep_clock = false, 665 .regs = &ipq5018_regs, 666 .hw_ops = &ipq5018_ops, 667 .host_ce_config = ath11k_host_ce_config_qcn9074, 668 .ce_count = CE_CNT_5018, 669 .target_ce_config = ath11k_target_ce_config_wlan_ipq5018, 670 .target_ce_count = TARGET_CE_CNT_5018, 671 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq5018, 672 .svc_to_ce_map_len = SVC_CE_MAP_LEN_5018, 673 .ce_ie_addr = &ath11k_ce_ie_addr_ipq5018, 674 .ce_remap = &ath11k_ce_remap_ipq5018, 675 .rxdma1_enable = true, 676 .num_rxmda_per_pdev = RXDMA_PER_PDEV_5018, 677 .rx_mac_buf_ring = false, 678 .vdev_start_delay = false, 679 .htt_peer_map_v2 = true, 680 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 681 BIT(NL80211_IFTYPE_AP) | 682 BIT(NL80211_IFTYPE_MESH_POINT), 683 .supports_monitor = false, 684 .supports_sta_ps = false, 685 .supports_shadow_regs = false, 686 .fw_mem_mode = 0, 687 .num_vdevs = 16 + 1, 688 .num_peers = 512, 689 .supports_regdb = false, 690 .idle_ps = false, 691 .supports_suspend = false, 692 .hal_params = &ath11k_hw_hal_params_ipq8074, 693 .single_pdev_only = false, 694 .coldboot_cal_mm = true, 695 .coldboot_cal_ftm = true, 696 .cbcal_restart_fw = true, 697 .fix_l1ss = true, 698 .supports_dynamic_smps_6ghz = false, 699 .alloc_cacheable_memory = true, 700 .supports_rssi_stats = false, 701 .fw_wmi_diag_event = false, 702 .current_cc_support = false, 703 .dbr_debug_support = true, 704 .global_reset = false, 705 .bios_sar_capa = NULL, 706 .m3_fw_support = false, 707 .fixed_bdf_addr = true, 708 .fixed_mem_region = true, 709 .static_window_map = false, 710 .hybrid_bus_type = false, 711 .fixed_fw_mem = false, 712 .support_off_channel_tx = false, 713 .supports_multi_bssid = false, 714 715 .sram_dump = {}, 716 717 .tcl_ring_retry = true, 718 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 719 .smp2p_wow_exit = false, 720 .support_fw_mac_sequence = false, 721 .support_dual_stations = false, 722 }, 723 { 724 .name = "qca2066 hw2.1", 725 .hw_rev = ATH11K_HW_QCA2066_HW21, 726 .fw = { 727 .dir = "QCA2066/hw2.1", 728 .board_size = 256 * 1024, 729 .cal_offset = 128 * 1024, 730 }, 731 .max_radios = 3, 732 .bdf_addr = 0x4B0C0000, 733 .hw_ops = &wcn6855_ops, 734 .ring_mask = &ath11k_hw_ring_mask_qca6390, 735 .internal_sleep_clock = true, 736 .regs = &wcn6855_regs, 737 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390, 738 .host_ce_config = ath11k_host_ce_config_qca6390, 739 .ce_count = 9, 740 .target_ce_config = ath11k_target_ce_config_wlan_qca6390, 741 .target_ce_count = 9, 742 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, 743 .svc_to_ce_map_len = 14, 744 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 745 .single_pdev_only = true, 746 .rxdma1_enable = false, 747 .num_rxmda_per_pdev = 2, 748 .rx_mac_buf_ring = true, 749 .vdev_start_delay = true, 750 .htt_peer_map_v2 = false, 751 752 .spectral = { 753 .fft_sz = 0, 754 .fft_pad_sz = 0, 755 .summary_pad_sz = 0, 756 .fft_hdr_len = 0, 757 .max_fft_bins = 0, 758 .fragment_160mhz = false, 759 }, 760 761 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 762 BIT(NL80211_IFTYPE_AP) | 763 BIT(NL80211_IFTYPE_P2P_DEVICE) | 764 BIT(NL80211_IFTYPE_P2P_CLIENT) | 765 BIT(NL80211_IFTYPE_P2P_GO), 766 .supports_monitor = false, 767 .full_monitor_mode = false, 768 .supports_shadow_regs = true, 769 .idle_ps = true, 770 .supports_sta_ps = true, 771 .coldboot_cal_mm = false, 772 .coldboot_cal_ftm = false, 773 .cbcal_restart_fw = false, 774 .fw_mem_mode = 0, 775 .num_vdevs = 2 + 1, 776 .num_peers = 512, 777 .supports_suspend = true, 778 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855), 779 .supports_regdb = true, 780 .fix_l1ss = false, 781 .credit_flow = true, 782 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390, 783 .hal_params = &ath11k_hw_hal_params_qca6390, 784 .supports_dynamic_smps_6ghz = false, 785 .alloc_cacheable_memory = false, 786 .supports_rssi_stats = true, 787 .fw_wmi_diag_event = true, 788 .current_cc_support = true, 789 .dbr_debug_support = false, 790 .global_reset = true, 791 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855, 792 .m3_fw_support = true, 793 .fixed_bdf_addr = false, 794 .fixed_mem_region = false, 795 .static_window_map = false, 796 .hybrid_bus_type = false, 797 .fixed_fw_mem = false, 798 .support_off_channel_tx = true, 799 .supports_multi_bssid = true, 800 801 .sram_dump = { 802 .start = 0x01400000, 803 .end = 0x0177ffff, 804 }, 805 806 .tcl_ring_retry = true, 807 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 808 .smp2p_wow_exit = false, 809 .support_fw_mac_sequence = true, 810 .support_dual_stations = true, 811 }, 812 }; 813 814 static inline struct ath11k_pdev *ath11k_core_get_single_pdev(struct ath11k_base *ab) 815 { 816 WARN_ON(!ab->hw_params.single_pdev_only); 817 818 return &ab->pdevs[0]; 819 } 820 821 void ath11k_fw_stats_pdevs_free(struct list_head *head) 822 { 823 struct ath11k_fw_stats_pdev *i, *tmp; 824 825 list_for_each_entry_safe(i, tmp, head, list) { 826 list_del(&i->list); 827 kfree(i); 828 } 829 } 830 831 void ath11k_fw_stats_vdevs_free(struct list_head *head) 832 { 833 struct ath11k_fw_stats_vdev *i, *tmp; 834 835 list_for_each_entry_safe(i, tmp, head, list) { 836 list_del(&i->list); 837 kfree(i); 838 } 839 } 840 841 void ath11k_fw_stats_bcn_free(struct list_head *head) 842 { 843 struct ath11k_fw_stats_bcn *i, *tmp; 844 845 list_for_each_entry_safe(i, tmp, head, list) { 846 list_del(&i->list); 847 kfree(i); 848 } 849 } 850 851 void ath11k_fw_stats_init(struct ath11k *ar) 852 { 853 INIT_LIST_HEAD(&ar->fw_stats.pdevs); 854 INIT_LIST_HEAD(&ar->fw_stats.vdevs); 855 INIT_LIST_HEAD(&ar->fw_stats.bcn); 856 857 init_completion(&ar->fw_stats_complete); 858 } 859 860 void ath11k_fw_stats_free(struct ath11k_fw_stats *stats) 861 { 862 ath11k_fw_stats_pdevs_free(&stats->pdevs); 863 ath11k_fw_stats_vdevs_free(&stats->vdevs); 864 ath11k_fw_stats_bcn_free(&stats->bcn); 865 } 866 867 bool ath11k_core_coldboot_cal_support(struct ath11k_base *ab) 868 { 869 if (!ath11k_cold_boot_cal) 870 return false; 871 872 if (ath11k_ftm_mode) 873 return ab->hw_params.coldboot_cal_ftm; 874 875 else 876 return ab->hw_params.coldboot_cal_mm; 877 } 878 879 int ath11k_core_suspend(struct ath11k_base *ab) 880 { 881 int ret; 882 struct ath11k_pdev *pdev; 883 struct ath11k *ar; 884 885 if (!ab->hw_params.supports_suspend) 886 return -EOPNOTSUPP; 887 888 /* so far single_pdev_only chips have supports_suspend as true 889 * and only the first pdev is valid. 890 */ 891 pdev = ath11k_core_get_single_pdev(ab); 892 ar = pdev->ar; 893 if (!ar || ar->state != ATH11K_STATE_OFF) 894 return 0; 895 896 ret = ath11k_dp_rx_pktlog_stop(ab, true); 897 if (ret) { 898 ath11k_warn(ab, "failed to stop dp rx (and timer) pktlog during suspend: %d\n", 899 ret); 900 return ret; 901 } 902 903 ret = ath11k_mac_wait_tx_complete(ar); 904 if (ret) { 905 ath11k_warn(ab, "failed to wait tx complete: %d\n", ret); 906 return ret; 907 } 908 909 ret = ath11k_dp_rx_pktlog_stop(ab, false); 910 if (ret) { 911 ath11k_warn(ab, "failed to stop dp rx pktlog during suspend: %d\n", 912 ret); 913 return ret; 914 } 915 916 ath11k_ce_stop_shadow_timers(ab); 917 ath11k_dp_stop_shadow_timers(ab); 918 919 /* PM framework skips suspend_late/resume_early callbacks 920 * if other devices report errors in their suspend callbacks. 921 * However ath11k_core_resume() would still be called because 922 * here we return success thus kernel put us on dpm_suspended_list. 923 * Since we won't go through a power down/up cycle, there is 924 * no chance to call complete(&ab->restart_completed) in 925 * ath11k_core_restart(), making ath11k_core_resume() timeout. 926 * So call it here to avoid this issue. This also works in case 927 * no error happens thus suspend_late/resume_early get called, 928 * because it will be reinitialized in ath11k_core_resume_early(). 929 */ 930 complete(&ab->restart_completed); 931 932 return 0; 933 } 934 EXPORT_SYMBOL(ath11k_core_suspend); 935 936 int ath11k_core_suspend_late(struct ath11k_base *ab) 937 { 938 struct ath11k_pdev *pdev; 939 struct ath11k *ar; 940 941 if (!ab->hw_params.supports_suspend) 942 return -EOPNOTSUPP; 943 944 /* so far single_pdev_only chips have supports_suspend as true 945 * and only the first pdev is valid. 946 */ 947 pdev = ath11k_core_get_single_pdev(ab); 948 ar = pdev->ar; 949 if (!ar || ar->state != ATH11K_STATE_OFF) 950 return 0; 951 952 ath11k_hif_irq_disable(ab); 953 ath11k_hif_ce_irq_disable(ab); 954 955 ath11k_hif_power_down(ab, true); 956 957 return 0; 958 } 959 EXPORT_SYMBOL(ath11k_core_suspend_late); 960 961 int ath11k_core_resume_early(struct ath11k_base *ab) 962 { 963 int ret; 964 struct ath11k_pdev *pdev; 965 struct ath11k *ar; 966 967 if (!ab->hw_params.supports_suspend) 968 return -EOPNOTSUPP; 969 970 /* so far single_pdev_only chips have supports_suspend as true 971 * and only the first pdev is valid. 972 */ 973 pdev = ath11k_core_get_single_pdev(ab); 974 ar = pdev->ar; 975 if (!ar || ar->state != ATH11K_STATE_OFF) 976 return 0; 977 978 reinit_completion(&ab->restart_completed); 979 ret = ath11k_hif_power_up(ab); 980 if (ret) 981 ath11k_warn(ab, "failed to power up hif during resume: %d\n", ret); 982 983 return ret; 984 } 985 EXPORT_SYMBOL(ath11k_core_resume_early); 986 987 int ath11k_core_resume(struct ath11k_base *ab) 988 { 989 int ret; 990 struct ath11k_pdev *pdev; 991 struct ath11k *ar; 992 long time_left; 993 994 if (!ab->hw_params.supports_suspend) 995 return -EOPNOTSUPP; 996 997 /* so far single_pdev_only chips have supports_suspend as true 998 * and only the first pdev is valid. 999 */ 1000 pdev = ath11k_core_get_single_pdev(ab); 1001 ar = pdev->ar; 1002 if (!ar || ar->state != ATH11K_STATE_OFF) 1003 return 0; 1004 1005 time_left = wait_for_completion_timeout(&ab->restart_completed, 1006 ATH11K_RESET_TIMEOUT_HZ); 1007 if (time_left == 0) { 1008 ath11k_warn(ab, "timeout while waiting for restart complete"); 1009 return -ETIMEDOUT; 1010 } 1011 1012 ret = ath11k_dp_rx_pktlog_start(ab); 1013 if (ret) 1014 ath11k_warn(ab, "failed to start rx pktlog during resume: %d\n", 1015 ret); 1016 1017 return ret; 1018 } 1019 EXPORT_SYMBOL(ath11k_core_resume); 1020 1021 static void ath11k_core_check_cc_code_bdfext(const struct dmi_header *hdr, void *data) 1022 { 1023 struct ath11k_base *ab = data; 1024 const char *magic = ATH11K_SMBIOS_BDF_EXT_MAGIC; 1025 struct ath11k_smbios_bdf *smbios = (struct ath11k_smbios_bdf *)hdr; 1026 ssize_t copied; 1027 size_t len; 1028 int i; 1029 1030 if (ab->qmi.target.bdf_ext[0] != '\0') 1031 return; 1032 1033 if (hdr->type != ATH11K_SMBIOS_BDF_EXT_TYPE) 1034 return; 1035 1036 if (hdr->length != ATH11K_SMBIOS_BDF_EXT_LENGTH) { 1037 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1038 "wrong smbios bdf ext type length (%d).\n", 1039 hdr->length); 1040 return; 1041 } 1042 1043 spin_lock_bh(&ab->base_lock); 1044 1045 switch (smbios->country_code_flag) { 1046 case ATH11K_SMBIOS_CC_ISO: 1047 ab->new_alpha2[0] = (smbios->cc_code >> 8) & 0xff; 1048 ab->new_alpha2[1] = smbios->cc_code & 0xff; 1049 ath11k_dbg(ab, ATH11K_DBG_BOOT, "smbios cc_code %c%c\n", 1050 ab->new_alpha2[0], ab->new_alpha2[1]); 1051 break; 1052 case ATH11K_SMBIOS_CC_WW: 1053 ab->new_alpha2[0] = '0'; 1054 ab->new_alpha2[1] = '0'; 1055 ath11k_dbg(ab, ATH11K_DBG_BOOT, "smbios worldwide regdomain\n"); 1056 break; 1057 default: 1058 ath11k_dbg(ab, ATH11K_DBG_BOOT, "ignore smbios country code setting %d\n", 1059 smbios->country_code_flag); 1060 break; 1061 } 1062 1063 spin_unlock_bh(&ab->base_lock); 1064 1065 if (!smbios->bdf_enabled) { 1066 ath11k_dbg(ab, ATH11K_DBG_BOOT, "bdf variant name not found.\n"); 1067 return; 1068 } 1069 1070 /* Only one string exists (per spec) */ 1071 if (memcmp(smbios->bdf_ext, magic, strlen(magic)) != 0) { 1072 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1073 "bdf variant magic does not match.\n"); 1074 return; 1075 } 1076 1077 len = min_t(size_t, 1078 strlen(smbios->bdf_ext), sizeof(ab->qmi.target.bdf_ext)); 1079 for (i = 0; i < len; i++) { 1080 if (!isascii(smbios->bdf_ext[i]) || !isprint(smbios->bdf_ext[i])) { 1081 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1082 "bdf variant name contains non ascii chars.\n"); 1083 return; 1084 } 1085 } 1086 1087 /* Copy extension name without magic prefix */ 1088 copied = strscpy(ab->qmi.target.bdf_ext, smbios->bdf_ext + strlen(magic), 1089 sizeof(ab->qmi.target.bdf_ext)); 1090 if (copied < 0) { 1091 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1092 "bdf variant string is longer than the buffer can accommodate\n"); 1093 return; 1094 } 1095 1096 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1097 "found and validated bdf variant smbios_type 0x%x bdf %s\n", 1098 ATH11K_SMBIOS_BDF_EXT_TYPE, ab->qmi.target.bdf_ext); 1099 } 1100 1101 int ath11k_core_check_smbios(struct ath11k_base *ab) 1102 { 1103 ab->qmi.target.bdf_ext[0] = '\0'; 1104 dmi_walk(ath11k_core_check_cc_code_bdfext, ab); 1105 1106 if (ab->qmi.target.bdf_ext[0] == '\0') 1107 return -ENODATA; 1108 1109 return 0; 1110 } 1111 1112 int ath11k_core_check_dt(struct ath11k_base *ab) 1113 { 1114 size_t max_len = sizeof(ab->qmi.target.bdf_ext); 1115 const char *variant = NULL; 1116 struct device_node *node; 1117 1118 node = ab->dev->of_node; 1119 if (!node) 1120 return -ENOENT; 1121 1122 of_property_read_string(node, "qcom,ath11k-calibration-variant", 1123 &variant); 1124 if (!variant) 1125 return -ENODATA; 1126 1127 if (strscpy(ab->qmi.target.bdf_ext, variant, max_len) < 0) 1128 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1129 "bdf variant string is longer than the buffer can accommodate (variant: %s)\n", 1130 variant); 1131 1132 return 0; 1133 } 1134 1135 enum ath11k_bdf_name_type { 1136 ATH11K_BDF_NAME_FULL, 1137 ATH11K_BDF_NAME_BUS_NAME, 1138 ATH11K_BDF_NAME_CHIP_ID, 1139 }; 1140 1141 static int __ath11k_core_create_board_name(struct ath11k_base *ab, char *name, 1142 size_t name_len, bool with_variant, 1143 enum ath11k_bdf_name_type name_type) 1144 { 1145 /* strlen(',variant=') + strlen(ab->qmi.target.bdf_ext) */ 1146 char variant[9 + ATH11K_QMI_BDF_EXT_STR_LENGTH] = { 0 }; 1147 1148 if (with_variant && ab->qmi.target.bdf_ext[0] != '\0') 1149 scnprintf(variant, sizeof(variant), ",variant=%s", 1150 ab->qmi.target.bdf_ext); 1151 1152 switch (ab->id.bdf_search) { 1153 case ATH11K_BDF_SEARCH_BUS_AND_BOARD: 1154 switch (name_type) { 1155 case ATH11K_BDF_NAME_FULL: 1156 scnprintf(name, name_len, 1157 "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x,qmi-chip-id=%d,qmi-board-id=%d%s", 1158 ath11k_bus_str(ab->hif.bus), 1159 ab->id.vendor, ab->id.device, 1160 ab->id.subsystem_vendor, 1161 ab->id.subsystem_device, 1162 ab->qmi.target.chip_id, 1163 ab->qmi.target.board_id, 1164 variant); 1165 break; 1166 case ATH11K_BDF_NAME_BUS_NAME: 1167 scnprintf(name, name_len, 1168 "bus=%s", 1169 ath11k_bus_str(ab->hif.bus)); 1170 break; 1171 case ATH11K_BDF_NAME_CHIP_ID: 1172 scnprintf(name, name_len, 1173 "bus=%s,qmi-chip-id=%d", 1174 ath11k_bus_str(ab->hif.bus), 1175 ab->qmi.target.chip_id); 1176 break; 1177 } 1178 break; 1179 default: 1180 scnprintf(name, name_len, 1181 "bus=%s,qmi-chip-id=%d,qmi-board-id=%d%s", 1182 ath11k_bus_str(ab->hif.bus), 1183 ab->qmi.target.chip_id, 1184 ab->qmi.target.board_id, variant); 1185 break; 1186 } 1187 1188 ath11k_dbg(ab, ATH11K_DBG_BOOT, "using board name '%s'\n", name); 1189 1190 return 0; 1191 } 1192 1193 static int ath11k_core_create_board_name(struct ath11k_base *ab, char *name, 1194 size_t name_len) 1195 { 1196 return __ath11k_core_create_board_name(ab, name, name_len, true, 1197 ATH11K_BDF_NAME_FULL); 1198 } 1199 1200 static int ath11k_core_create_fallback_board_name(struct ath11k_base *ab, char *name, 1201 size_t name_len) 1202 { 1203 return __ath11k_core_create_board_name(ab, name, name_len, false, 1204 ATH11K_BDF_NAME_FULL); 1205 } 1206 1207 static int ath11k_core_create_bus_type_board_name(struct ath11k_base *ab, char *name, 1208 size_t name_len) 1209 { 1210 return __ath11k_core_create_board_name(ab, name, name_len, false, 1211 ATH11K_BDF_NAME_BUS_NAME); 1212 } 1213 1214 static int ath11k_core_create_chip_id_board_name(struct ath11k_base *ab, char *name, 1215 size_t name_len) 1216 { 1217 return __ath11k_core_create_board_name(ab, name, name_len, false, 1218 ATH11K_BDF_NAME_CHIP_ID); 1219 } 1220 1221 const struct firmware *ath11k_core_firmware_request(struct ath11k_base *ab, 1222 const char *file) 1223 { 1224 const struct firmware *fw; 1225 char path[100]; 1226 int ret; 1227 1228 if (file == NULL) 1229 return ERR_PTR(-ENOENT); 1230 1231 ath11k_core_create_firmware_path(ab, file, path, sizeof(path)); 1232 1233 ret = firmware_request_nowarn(&fw, path, ab->dev); 1234 if (ret) 1235 return ERR_PTR(ret); 1236 1237 ath11k_dbg(ab, ATH11K_DBG_BOOT, "firmware request %s size %zu\n", 1238 path, fw->size); 1239 1240 return fw; 1241 } 1242 1243 void ath11k_core_free_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd) 1244 { 1245 if (!IS_ERR(bd->fw)) 1246 release_firmware(bd->fw); 1247 1248 memset(bd, 0, sizeof(*bd)); 1249 } 1250 1251 static int ath11k_core_parse_bd_ie_board(struct ath11k_base *ab, 1252 struct ath11k_board_data *bd, 1253 const void *buf, size_t buf_len, 1254 const char *boardname, 1255 int ie_id, 1256 int name_id, 1257 int data_id) 1258 { 1259 const struct ath11k_fw_ie *hdr; 1260 bool name_match_found; 1261 int ret, board_ie_id; 1262 size_t board_ie_len; 1263 const void *board_ie_data; 1264 1265 name_match_found = false; 1266 1267 /* go through ATH11K_BD_IE_BOARD_/ATH11K_BD_IE_REGDB_ elements */ 1268 while (buf_len > sizeof(struct ath11k_fw_ie)) { 1269 hdr = buf; 1270 board_ie_id = le32_to_cpu(hdr->id); 1271 board_ie_len = le32_to_cpu(hdr->len); 1272 board_ie_data = hdr->data; 1273 1274 buf_len -= sizeof(*hdr); 1275 buf += sizeof(*hdr); 1276 1277 if (buf_len < ALIGN(board_ie_len, 4)) { 1278 ath11k_err(ab, "invalid %s length: %zu < %zu\n", 1279 ath11k_bd_ie_type_str(ie_id), 1280 buf_len, ALIGN(board_ie_len, 4)); 1281 ret = -EINVAL; 1282 goto out; 1283 } 1284 1285 if (board_ie_id == name_id) { 1286 ath11k_dbg_dump(ab, ATH11K_DBG_BOOT, "board name", "", 1287 board_ie_data, board_ie_len); 1288 1289 if (board_ie_len != strlen(boardname)) 1290 goto next; 1291 1292 ret = memcmp(board_ie_data, boardname, strlen(boardname)); 1293 if (ret) 1294 goto next; 1295 1296 name_match_found = true; 1297 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1298 "found match %s for name '%s'", 1299 ath11k_bd_ie_type_str(ie_id), 1300 boardname); 1301 } else if (board_ie_id == data_id) { 1302 if (!name_match_found) 1303 /* no match found */ 1304 goto next; 1305 1306 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1307 "found %s for '%s'", 1308 ath11k_bd_ie_type_str(ie_id), 1309 boardname); 1310 1311 bd->data = board_ie_data; 1312 bd->len = board_ie_len; 1313 1314 ret = 0; 1315 goto out; 1316 } else { 1317 ath11k_warn(ab, "unknown %s id found: %d\n", 1318 ath11k_bd_ie_type_str(ie_id), 1319 board_ie_id); 1320 } 1321 next: 1322 /* jump over the padding */ 1323 board_ie_len = ALIGN(board_ie_len, 4); 1324 1325 buf_len -= board_ie_len; 1326 buf += board_ie_len; 1327 } 1328 1329 /* no match found */ 1330 ret = -ENOENT; 1331 1332 out: 1333 return ret; 1334 } 1335 1336 static int ath11k_core_fetch_board_data_api_n(struct ath11k_base *ab, 1337 struct ath11k_board_data *bd, 1338 const char *boardname, 1339 int ie_id_match, 1340 int name_id, 1341 int data_id) 1342 { 1343 size_t len, magic_len; 1344 const u8 *data; 1345 char *filename, filepath[100]; 1346 size_t ie_len; 1347 struct ath11k_fw_ie *hdr; 1348 int ret, ie_id; 1349 1350 filename = ATH11K_BOARD_API2_FILE; 1351 1352 if (!bd->fw) 1353 bd->fw = ath11k_core_firmware_request(ab, filename); 1354 1355 if (IS_ERR(bd->fw)) 1356 return PTR_ERR(bd->fw); 1357 1358 data = bd->fw->data; 1359 len = bd->fw->size; 1360 1361 ath11k_core_create_firmware_path(ab, filename, 1362 filepath, sizeof(filepath)); 1363 1364 /* magic has extra null byte padded */ 1365 magic_len = strlen(ATH11K_BOARD_MAGIC) + 1; 1366 if (len < magic_len) { 1367 ath11k_err(ab, "failed to find magic value in %s, file too short: %zu\n", 1368 filepath, len); 1369 ret = -EINVAL; 1370 goto err; 1371 } 1372 1373 if (memcmp(data, ATH11K_BOARD_MAGIC, magic_len)) { 1374 ath11k_err(ab, "found invalid board magic\n"); 1375 ret = -EINVAL; 1376 goto err; 1377 } 1378 1379 /* magic is padded to 4 bytes */ 1380 magic_len = ALIGN(magic_len, 4); 1381 if (len < magic_len) { 1382 ath11k_err(ab, "failed: %s too small to contain board data, len: %zu\n", 1383 filepath, len); 1384 ret = -EINVAL; 1385 goto err; 1386 } 1387 1388 data += magic_len; 1389 len -= magic_len; 1390 1391 while (len > sizeof(struct ath11k_fw_ie)) { 1392 hdr = (struct ath11k_fw_ie *)data; 1393 ie_id = le32_to_cpu(hdr->id); 1394 ie_len = le32_to_cpu(hdr->len); 1395 1396 len -= sizeof(*hdr); 1397 data = hdr->data; 1398 1399 if (len < ALIGN(ie_len, 4)) { 1400 ath11k_err(ab, "invalid length for board ie_id %d ie_len %zu len %zu\n", 1401 ie_id, ie_len, len); 1402 ret = -EINVAL; 1403 goto err; 1404 } 1405 1406 if (ie_id == ie_id_match) { 1407 ret = ath11k_core_parse_bd_ie_board(ab, bd, data, 1408 ie_len, 1409 boardname, 1410 ie_id_match, 1411 name_id, 1412 data_id); 1413 if (ret == -ENOENT) 1414 /* no match found, continue */ 1415 goto next; 1416 else if (ret) 1417 /* there was an error, bail out */ 1418 goto err; 1419 /* either found or error, so stop searching */ 1420 goto out; 1421 } 1422 next: 1423 /* jump over the padding */ 1424 ie_len = ALIGN(ie_len, 4); 1425 1426 len -= ie_len; 1427 data += ie_len; 1428 } 1429 1430 out: 1431 if (!bd->data || !bd->len) { 1432 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1433 "failed to fetch %s for %s from %s\n", 1434 ath11k_bd_ie_type_str(ie_id_match), 1435 boardname, filepath); 1436 ret = -ENODATA; 1437 goto err; 1438 } 1439 1440 return 0; 1441 1442 err: 1443 ath11k_core_free_bdf(ab, bd); 1444 return ret; 1445 } 1446 1447 int ath11k_core_fetch_board_data_api_1(struct ath11k_base *ab, 1448 struct ath11k_board_data *bd, 1449 const char *name) 1450 { 1451 bd->fw = ath11k_core_firmware_request(ab, name); 1452 1453 if (IS_ERR(bd->fw)) 1454 return PTR_ERR(bd->fw); 1455 1456 bd->data = bd->fw->data; 1457 bd->len = bd->fw->size; 1458 1459 return 0; 1460 } 1461 1462 #define BOARD_NAME_SIZE 200 1463 int ath11k_core_fetch_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd) 1464 { 1465 char *boardname = NULL, *fallback_boardname = NULL, *chip_id_boardname = NULL; 1466 char *filename, filepath[100]; 1467 int bd_api; 1468 int ret = 0; 1469 1470 filename = ATH11K_BOARD_API2_FILE; 1471 boardname = kzalloc(BOARD_NAME_SIZE, GFP_KERNEL); 1472 if (!boardname) { 1473 ret = -ENOMEM; 1474 goto exit; 1475 } 1476 1477 ret = ath11k_core_create_board_name(ab, boardname, BOARD_NAME_SIZE); 1478 if (ret) { 1479 ath11k_err(ab, "failed to create board name: %d", ret); 1480 goto exit; 1481 } 1482 1483 bd_api = 2; 1484 ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname, 1485 ATH11K_BD_IE_BOARD, 1486 ATH11K_BD_IE_BOARD_NAME, 1487 ATH11K_BD_IE_BOARD_DATA); 1488 if (!ret) 1489 goto exit; 1490 1491 fallback_boardname = kzalloc(BOARD_NAME_SIZE, GFP_KERNEL); 1492 if (!fallback_boardname) { 1493 ret = -ENOMEM; 1494 goto exit; 1495 } 1496 1497 ret = ath11k_core_create_fallback_board_name(ab, fallback_boardname, 1498 BOARD_NAME_SIZE); 1499 if (ret) { 1500 ath11k_err(ab, "failed to create fallback board name: %d", ret); 1501 goto exit; 1502 } 1503 1504 ret = ath11k_core_fetch_board_data_api_n(ab, bd, fallback_boardname, 1505 ATH11K_BD_IE_BOARD, 1506 ATH11K_BD_IE_BOARD_NAME, 1507 ATH11K_BD_IE_BOARD_DATA); 1508 if (!ret) 1509 goto exit; 1510 1511 chip_id_boardname = kzalloc(BOARD_NAME_SIZE, GFP_KERNEL); 1512 if (!chip_id_boardname) { 1513 ret = -ENOMEM; 1514 goto exit; 1515 } 1516 1517 ret = ath11k_core_create_chip_id_board_name(ab, chip_id_boardname, 1518 BOARD_NAME_SIZE); 1519 if (ret) { 1520 ath11k_err(ab, "failed to create chip id board name: %d", ret); 1521 goto exit; 1522 } 1523 1524 ret = ath11k_core_fetch_board_data_api_n(ab, bd, chip_id_boardname, 1525 ATH11K_BD_IE_BOARD, 1526 ATH11K_BD_IE_BOARD_NAME, 1527 ATH11K_BD_IE_BOARD_DATA); 1528 1529 if (!ret) 1530 goto exit; 1531 1532 bd_api = 1; 1533 ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_DEFAULT_BOARD_FILE); 1534 if (ret) { 1535 ath11k_core_create_firmware_path(ab, filename, 1536 filepath, sizeof(filepath)); 1537 ath11k_err(ab, "failed to fetch board data for %s from %s\n", 1538 boardname, filepath); 1539 if (memcmp(boardname, fallback_boardname, strlen(boardname))) 1540 ath11k_err(ab, "failed to fetch board data for %s from %s\n", 1541 fallback_boardname, filepath); 1542 1543 ath11k_err(ab, "failed to fetch board data for %s from %s\n", 1544 chip_id_boardname, filepath); 1545 1546 ath11k_err(ab, "failed to fetch board.bin from %s\n", 1547 ab->hw_params.fw.dir); 1548 } 1549 1550 exit: 1551 kfree(boardname); 1552 kfree(fallback_boardname); 1553 kfree(chip_id_boardname); 1554 1555 if (!ret) 1556 ath11k_dbg(ab, ATH11K_DBG_BOOT, "using board api %d\n", bd_api); 1557 1558 return ret; 1559 } 1560 1561 int ath11k_core_fetch_regdb(struct ath11k_base *ab, struct ath11k_board_data *bd) 1562 { 1563 char boardname[BOARD_NAME_SIZE], default_boardname[BOARD_NAME_SIZE]; 1564 int ret; 1565 1566 ret = ath11k_core_create_board_name(ab, boardname, BOARD_NAME_SIZE); 1567 if (ret) { 1568 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1569 "failed to create board name for regdb: %d", ret); 1570 goto exit; 1571 } 1572 1573 ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname, 1574 ATH11K_BD_IE_REGDB, 1575 ATH11K_BD_IE_REGDB_NAME, 1576 ATH11K_BD_IE_REGDB_DATA); 1577 if (!ret) 1578 goto exit; 1579 1580 ret = ath11k_core_create_bus_type_board_name(ab, default_boardname, 1581 BOARD_NAME_SIZE); 1582 if (ret) { 1583 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1584 "failed to create default board name for regdb: %d", ret); 1585 goto exit; 1586 } 1587 1588 ret = ath11k_core_fetch_board_data_api_n(ab, bd, default_boardname, 1589 ATH11K_BD_IE_REGDB, 1590 ATH11K_BD_IE_REGDB_NAME, 1591 ATH11K_BD_IE_REGDB_DATA); 1592 if (!ret) 1593 goto exit; 1594 1595 ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_REGDB_FILE_NAME); 1596 if (ret) 1597 ath11k_dbg(ab, ATH11K_DBG_BOOT, "failed to fetch %s from %s\n", 1598 ATH11K_REGDB_FILE_NAME, ab->hw_params.fw.dir); 1599 1600 exit: 1601 if (!ret) 1602 ath11k_dbg(ab, ATH11K_DBG_BOOT, "fetched regdb\n"); 1603 1604 return ret; 1605 } 1606 1607 static void ath11k_core_stop(struct ath11k_base *ab) 1608 { 1609 if (!test_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags)) 1610 ath11k_qmi_firmware_stop(ab); 1611 1612 ath11k_hif_stop(ab); 1613 ath11k_wmi_detach(ab); 1614 ath11k_dp_pdev_reo_cleanup(ab); 1615 1616 /* De-Init of components as needed */ 1617 } 1618 1619 static int ath11k_core_soc_create(struct ath11k_base *ab) 1620 { 1621 int ret; 1622 1623 if (ath11k_ftm_mode) { 1624 ab->fw_mode = ATH11K_FIRMWARE_MODE_FTM; 1625 ath11k_info(ab, "Booting in factory test mode\n"); 1626 } 1627 1628 ret = ath11k_qmi_init_service(ab); 1629 if (ret) { 1630 ath11k_err(ab, "failed to initialize qmi :%d\n", ret); 1631 return ret; 1632 } 1633 1634 ret = ath11k_debugfs_soc_create(ab); 1635 if (ret) { 1636 ath11k_err(ab, "failed to create ath11k debugfs\n"); 1637 goto err_qmi_deinit; 1638 } 1639 1640 ret = ath11k_hif_power_up(ab); 1641 if (ret) { 1642 ath11k_err(ab, "failed to power up :%d\n", ret); 1643 goto err_debugfs_reg; 1644 } 1645 1646 return 0; 1647 1648 err_debugfs_reg: 1649 ath11k_debugfs_soc_destroy(ab); 1650 err_qmi_deinit: 1651 ath11k_qmi_deinit_service(ab); 1652 return ret; 1653 } 1654 1655 static void ath11k_core_soc_destroy(struct ath11k_base *ab) 1656 { 1657 ath11k_debugfs_soc_destroy(ab); 1658 ath11k_dp_free(ab); 1659 ath11k_reg_free(ab); 1660 ath11k_qmi_deinit_service(ab); 1661 } 1662 1663 static int ath11k_core_pdev_create(struct ath11k_base *ab) 1664 { 1665 int ret; 1666 1667 ret = ath11k_debugfs_pdev_create(ab); 1668 if (ret) { 1669 ath11k_err(ab, "failed to create core pdev debugfs: %d\n", ret); 1670 return ret; 1671 } 1672 1673 ret = ath11k_dp_pdev_alloc(ab); 1674 if (ret) { 1675 ath11k_err(ab, "failed to attach DP pdev: %d\n", ret); 1676 goto err_pdev_debug; 1677 } 1678 1679 ret = ath11k_mac_register(ab); 1680 if (ret) { 1681 ath11k_err(ab, "failed register the radio with mac80211: %d\n", ret); 1682 goto err_dp_pdev_free; 1683 } 1684 1685 ret = ath11k_thermal_register(ab); 1686 if (ret) { 1687 ath11k_err(ab, "could not register thermal device: %d\n", 1688 ret); 1689 goto err_mac_unregister; 1690 } 1691 1692 ret = ath11k_spectral_init(ab); 1693 if (ret) { 1694 ath11k_err(ab, "failed to init spectral %d\n", ret); 1695 goto err_thermal_unregister; 1696 } 1697 1698 return 0; 1699 1700 err_thermal_unregister: 1701 ath11k_thermal_unregister(ab); 1702 err_mac_unregister: 1703 ath11k_mac_unregister(ab); 1704 err_dp_pdev_free: 1705 ath11k_dp_pdev_free(ab); 1706 err_pdev_debug: 1707 ath11k_debugfs_pdev_destroy(ab); 1708 1709 return ret; 1710 } 1711 1712 static void ath11k_core_pdev_destroy(struct ath11k_base *ab) 1713 { 1714 ath11k_spectral_deinit(ab); 1715 ath11k_thermal_unregister(ab); 1716 ath11k_mac_unregister(ab); 1717 ath11k_hif_irq_disable(ab); 1718 ath11k_dp_pdev_free(ab); 1719 ath11k_debugfs_pdev_destroy(ab); 1720 } 1721 1722 static int ath11k_core_start(struct ath11k_base *ab) 1723 { 1724 int ret; 1725 1726 ret = ath11k_wmi_attach(ab); 1727 if (ret) { 1728 ath11k_err(ab, "failed to attach wmi: %d\n", ret); 1729 return ret; 1730 } 1731 1732 ret = ath11k_htc_init(ab); 1733 if (ret) { 1734 ath11k_err(ab, "failed to init htc: %d\n", ret); 1735 goto err_wmi_detach; 1736 } 1737 1738 ret = ath11k_hif_start(ab); 1739 if (ret) { 1740 ath11k_err(ab, "failed to start HIF: %d\n", ret); 1741 goto err_wmi_detach; 1742 } 1743 1744 ret = ath11k_htc_wait_target(&ab->htc); 1745 if (ret) { 1746 ath11k_err(ab, "failed to connect to HTC: %d\n", ret); 1747 goto err_hif_stop; 1748 } 1749 1750 ret = ath11k_dp_htt_connect(&ab->dp); 1751 if (ret) { 1752 ath11k_err(ab, "failed to connect to HTT: %d\n", ret); 1753 goto err_hif_stop; 1754 } 1755 1756 ret = ath11k_wmi_connect(ab); 1757 if (ret) { 1758 ath11k_err(ab, "failed to connect wmi: %d\n", ret); 1759 goto err_hif_stop; 1760 } 1761 1762 ret = ath11k_htc_start(&ab->htc); 1763 if (ret) { 1764 ath11k_err(ab, "failed to start HTC: %d\n", ret); 1765 goto err_hif_stop; 1766 } 1767 1768 ret = ath11k_wmi_wait_for_service_ready(ab); 1769 if (ret) { 1770 ath11k_err(ab, "failed to receive wmi service ready event: %d\n", 1771 ret); 1772 goto err_hif_stop; 1773 } 1774 1775 ret = ath11k_mac_allocate(ab); 1776 if (ret) { 1777 ath11k_err(ab, "failed to create new hw device with mac80211 :%d\n", 1778 ret); 1779 goto err_hif_stop; 1780 } 1781 1782 ath11k_dp_pdev_pre_alloc(ab); 1783 1784 ret = ath11k_dp_pdev_reo_setup(ab); 1785 if (ret) { 1786 ath11k_err(ab, "failed to initialize reo destination rings: %d\n", ret); 1787 goto err_mac_destroy; 1788 } 1789 1790 ret = ath11k_wmi_cmd_init(ab); 1791 if (ret) { 1792 ath11k_err(ab, "failed to send wmi init cmd: %d\n", ret); 1793 goto err_reo_cleanup; 1794 } 1795 1796 ret = ath11k_wmi_wait_for_unified_ready(ab); 1797 if (ret) { 1798 ath11k_err(ab, "failed to receive wmi unified ready event: %d\n", 1799 ret); 1800 goto err_reo_cleanup; 1801 } 1802 1803 /* put hardware to DBS mode */ 1804 if (ab->hw_params.single_pdev_only && ab->hw_params.num_rxmda_per_pdev > 1) { 1805 ret = ath11k_wmi_set_hw_mode(ab, WMI_HOST_HW_MODE_DBS); 1806 if (ret) { 1807 ath11k_err(ab, "failed to send dbs mode: %d\n", ret); 1808 goto err_hif_stop; 1809 } 1810 } 1811 1812 ret = ath11k_dp_tx_htt_h2t_ver_req_msg(ab); 1813 if (ret) { 1814 ath11k_err(ab, "failed to send htt version request message: %d\n", 1815 ret); 1816 goto err_reo_cleanup; 1817 } 1818 1819 return 0; 1820 1821 err_reo_cleanup: 1822 ath11k_dp_pdev_reo_cleanup(ab); 1823 err_mac_destroy: 1824 ath11k_mac_destroy(ab); 1825 err_hif_stop: 1826 ath11k_hif_stop(ab); 1827 err_wmi_detach: 1828 ath11k_wmi_detach(ab); 1829 1830 return ret; 1831 } 1832 1833 static int ath11k_core_start_firmware(struct ath11k_base *ab, 1834 enum ath11k_firmware_mode mode) 1835 { 1836 int ret; 1837 1838 ath11k_ce_get_shadow_config(ab, &ab->qmi.ce_cfg.shadow_reg_v2, 1839 &ab->qmi.ce_cfg.shadow_reg_v2_len); 1840 1841 ret = ath11k_qmi_firmware_start(ab, mode); 1842 if (ret) { 1843 ath11k_err(ab, "failed to send firmware start: %d\n", ret); 1844 return ret; 1845 } 1846 1847 return ret; 1848 } 1849 1850 int ath11k_core_qmi_firmware_ready(struct ath11k_base *ab) 1851 { 1852 int ret; 1853 1854 ret = ath11k_core_start_firmware(ab, ab->fw_mode); 1855 if (ret) { 1856 ath11k_err(ab, "failed to start firmware: %d\n", ret); 1857 return ret; 1858 } 1859 1860 ret = ath11k_ce_init_pipes(ab); 1861 if (ret) { 1862 ath11k_err(ab, "failed to initialize CE: %d\n", ret); 1863 goto err_firmware_stop; 1864 } 1865 1866 ret = ath11k_dp_alloc(ab); 1867 if (ret) { 1868 ath11k_err(ab, "failed to init DP: %d\n", ret); 1869 goto err_firmware_stop; 1870 } 1871 1872 switch (ath11k_crypto_mode) { 1873 case ATH11K_CRYPT_MODE_SW: 1874 set_bit(ATH11K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags); 1875 set_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags); 1876 break; 1877 case ATH11K_CRYPT_MODE_HW: 1878 clear_bit(ATH11K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags); 1879 clear_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags); 1880 break; 1881 default: 1882 ath11k_info(ab, "invalid crypto_mode: %d\n", ath11k_crypto_mode); 1883 return -EINVAL; 1884 } 1885 1886 if (ath11k_frame_mode == ATH11K_HW_TXRX_RAW) 1887 set_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags); 1888 1889 mutex_lock(&ab->core_lock); 1890 ret = ath11k_core_start(ab); 1891 if (ret) { 1892 ath11k_err(ab, "failed to start core: %d\n", ret); 1893 goto err_dp_free; 1894 } 1895 1896 ret = ath11k_core_pdev_create(ab); 1897 if (ret) { 1898 ath11k_err(ab, "failed to create pdev core: %d\n", ret); 1899 goto err_core_stop; 1900 } 1901 ath11k_hif_irq_enable(ab); 1902 mutex_unlock(&ab->core_lock); 1903 1904 return 0; 1905 1906 err_core_stop: 1907 ath11k_core_stop(ab); 1908 ath11k_mac_destroy(ab); 1909 err_dp_free: 1910 ath11k_dp_free(ab); 1911 mutex_unlock(&ab->core_lock); 1912 err_firmware_stop: 1913 ath11k_qmi_firmware_stop(ab); 1914 1915 return ret; 1916 } 1917 1918 static int ath11k_core_reconfigure_on_crash(struct ath11k_base *ab) 1919 { 1920 int ret; 1921 1922 mutex_lock(&ab->core_lock); 1923 ath11k_thermal_unregister(ab); 1924 ath11k_dp_pdev_free(ab); 1925 ath11k_spectral_deinit(ab); 1926 ath11k_ce_cleanup_pipes(ab); 1927 ath11k_wmi_detach(ab); 1928 ath11k_dp_pdev_reo_cleanup(ab); 1929 mutex_unlock(&ab->core_lock); 1930 1931 ath11k_dp_free(ab); 1932 ath11k_hal_srng_deinit(ab); 1933 1934 ab->free_vdev_map = (1LL << (ab->num_radios * TARGET_NUM_VDEVS(ab))) - 1; 1935 1936 ret = ath11k_hal_srng_init(ab); 1937 if (ret) 1938 return ret; 1939 1940 clear_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags); 1941 1942 ret = ath11k_core_qmi_firmware_ready(ab); 1943 if (ret) 1944 goto err_hal_srng_deinit; 1945 1946 clear_bit(ATH11K_FLAG_RECOVERY, &ab->dev_flags); 1947 1948 return 0; 1949 1950 err_hal_srng_deinit: 1951 ath11k_hal_srng_deinit(ab); 1952 return ret; 1953 } 1954 1955 void ath11k_core_halt(struct ath11k *ar) 1956 { 1957 struct ath11k_base *ab = ar->ab; 1958 1959 lockdep_assert_held(&ar->conf_mutex); 1960 1961 ar->num_created_vdevs = 0; 1962 ar->allocated_vdev_map = 0; 1963 1964 ath11k_mac_scan_finish(ar); 1965 ath11k_mac_peer_cleanup_all(ar); 1966 cancel_delayed_work_sync(&ar->scan.timeout); 1967 cancel_work_sync(&ar->regd_update_work); 1968 cancel_work_sync(&ab->update_11d_work); 1969 1970 rcu_assign_pointer(ab->pdevs_active[ar->pdev_idx], NULL); 1971 synchronize_rcu(); 1972 INIT_LIST_HEAD(&ar->arvifs); 1973 idr_init(&ar->txmgmt_idr); 1974 } 1975 1976 static void ath11k_update_11d(struct work_struct *work) 1977 { 1978 struct ath11k_base *ab = container_of(work, struct ath11k_base, update_11d_work); 1979 struct ath11k *ar; 1980 struct ath11k_pdev *pdev; 1981 struct wmi_set_current_country_params set_current_param = {}; 1982 int ret, i; 1983 1984 spin_lock_bh(&ab->base_lock); 1985 memcpy(&set_current_param.alpha2, &ab->new_alpha2, 2); 1986 spin_unlock_bh(&ab->base_lock); 1987 1988 ath11k_dbg(ab, ATH11K_DBG_WMI, "update 11d new cc %c%c\n", 1989 set_current_param.alpha2[0], 1990 set_current_param.alpha2[1]); 1991 1992 for (i = 0; i < ab->num_radios; i++) { 1993 pdev = &ab->pdevs[i]; 1994 ar = pdev->ar; 1995 1996 memcpy(&ar->alpha2, &set_current_param.alpha2, 2); 1997 ret = ath11k_wmi_send_set_current_country_cmd(ar, &set_current_param); 1998 if (ret) 1999 ath11k_warn(ar->ab, 2000 "pdev id %d failed set current country code: %d\n", 2001 i, ret); 2002 } 2003 } 2004 2005 void ath11k_core_pre_reconfigure_recovery(struct ath11k_base *ab) 2006 { 2007 struct ath11k *ar; 2008 struct ath11k_pdev *pdev; 2009 int i; 2010 2011 spin_lock_bh(&ab->base_lock); 2012 ab->stats.fw_crash_counter++; 2013 spin_unlock_bh(&ab->base_lock); 2014 2015 for (i = 0; i < ab->num_radios; i++) { 2016 pdev = &ab->pdevs[i]; 2017 ar = pdev->ar; 2018 if (!ar || ar->state == ATH11K_STATE_OFF || 2019 ar->state == ATH11K_STATE_FTM) 2020 continue; 2021 2022 ieee80211_stop_queues(ar->hw); 2023 ath11k_mac_drain_tx(ar); 2024 ar->state_11d = ATH11K_11D_IDLE; 2025 complete(&ar->completed_11d_scan); 2026 complete(&ar->scan.started); 2027 complete_all(&ar->scan.completed); 2028 complete(&ar->scan.on_channel); 2029 complete(&ar->peer_assoc_done); 2030 complete(&ar->peer_delete_done); 2031 complete(&ar->install_key_done); 2032 complete(&ar->vdev_setup_done); 2033 complete(&ar->vdev_delete_done); 2034 complete(&ar->bss_survey_done); 2035 complete(&ar->thermal.wmi_sync); 2036 2037 wake_up(&ar->dp.tx_empty_waitq); 2038 idr_for_each(&ar->txmgmt_idr, 2039 ath11k_mac_tx_mgmt_pending_free, ar); 2040 idr_destroy(&ar->txmgmt_idr); 2041 wake_up(&ar->txmgmt_empty_waitq); 2042 2043 ar->monitor_vdev_id = -1; 2044 clear_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags); 2045 clear_bit(ATH11K_FLAG_MONITOR_VDEV_CREATED, &ar->monitor_flags); 2046 } 2047 2048 wake_up(&ab->wmi_ab.tx_credits_wq); 2049 wake_up(&ab->peer_mapping_wq); 2050 2051 reinit_completion(&ab->driver_recovery); 2052 } 2053 2054 static void ath11k_core_post_reconfigure_recovery(struct ath11k_base *ab) 2055 { 2056 struct ath11k *ar; 2057 struct ath11k_pdev *pdev; 2058 int i; 2059 2060 for (i = 0; i < ab->num_radios; i++) { 2061 pdev = &ab->pdevs[i]; 2062 ar = pdev->ar; 2063 if (!ar || ar->state == ATH11K_STATE_OFF) 2064 continue; 2065 2066 mutex_lock(&ar->conf_mutex); 2067 2068 switch (ar->state) { 2069 case ATH11K_STATE_ON: 2070 ar->state = ATH11K_STATE_RESTARTING; 2071 ath11k_core_halt(ar); 2072 ieee80211_restart_hw(ar->hw); 2073 break; 2074 case ATH11K_STATE_OFF: 2075 ath11k_warn(ab, 2076 "cannot restart radio %d that hasn't been started\n", 2077 i); 2078 break; 2079 case ATH11K_STATE_RESTARTING: 2080 break; 2081 case ATH11K_STATE_RESTARTED: 2082 ar->state = ATH11K_STATE_WEDGED; 2083 fallthrough; 2084 case ATH11K_STATE_WEDGED: 2085 ath11k_warn(ab, 2086 "device is wedged, will not restart radio %d\n", i); 2087 break; 2088 case ATH11K_STATE_FTM: 2089 ath11k_dbg(ab, ATH11K_DBG_TESTMODE, 2090 "fw mode reset done radio %d\n", i); 2091 break; 2092 } 2093 2094 mutex_unlock(&ar->conf_mutex); 2095 } 2096 complete(&ab->driver_recovery); 2097 } 2098 2099 static void ath11k_core_restart(struct work_struct *work) 2100 { 2101 struct ath11k_base *ab = container_of(work, struct ath11k_base, restart_work); 2102 int ret; 2103 2104 ret = ath11k_core_reconfigure_on_crash(ab); 2105 if (ret) { 2106 ath11k_err(ab, "failed to reconfigure driver on crash recovery\n"); 2107 return; 2108 } 2109 2110 if (ab->is_reset) 2111 complete_all(&ab->reconfigure_complete); 2112 2113 if (!ab->is_reset) 2114 ath11k_core_post_reconfigure_recovery(ab); 2115 2116 complete(&ab->restart_completed); 2117 } 2118 2119 static void ath11k_core_reset(struct work_struct *work) 2120 { 2121 struct ath11k_base *ab = container_of(work, struct ath11k_base, reset_work); 2122 int reset_count, fail_cont_count; 2123 long time_left; 2124 2125 if (!(test_bit(ATH11K_FLAG_REGISTERED, &ab->dev_flags))) { 2126 ath11k_warn(ab, "ignore reset dev flags 0x%lx\n", ab->dev_flags); 2127 return; 2128 } 2129 2130 /* Sometimes the recovery will fail and then the next all recovery fail, 2131 * this is to avoid infinite recovery since it can not recovery success. 2132 */ 2133 fail_cont_count = atomic_read(&ab->fail_cont_count); 2134 2135 if (fail_cont_count >= ATH11K_RESET_MAX_FAIL_COUNT_FINAL) 2136 return; 2137 2138 if (fail_cont_count >= ATH11K_RESET_MAX_FAIL_COUNT_FIRST && 2139 time_before(jiffies, ab->reset_fail_timeout)) 2140 return; 2141 2142 reset_count = atomic_inc_return(&ab->reset_count); 2143 2144 if (reset_count > 1) { 2145 /* Sometimes it happened another reset worker before the previous one 2146 * completed, then the second reset worker will destroy the previous one, 2147 * thus below is to avoid that. 2148 */ 2149 ath11k_warn(ab, "already resetting count %d\n", reset_count); 2150 2151 reinit_completion(&ab->reset_complete); 2152 time_left = wait_for_completion_timeout(&ab->reset_complete, 2153 ATH11K_RESET_TIMEOUT_HZ); 2154 2155 if (time_left) { 2156 ath11k_dbg(ab, ATH11K_DBG_BOOT, "to skip reset\n"); 2157 atomic_dec(&ab->reset_count); 2158 return; 2159 } 2160 2161 ab->reset_fail_timeout = jiffies + ATH11K_RESET_FAIL_TIMEOUT_HZ; 2162 /* Record the continuous recovery fail count when recovery failed*/ 2163 atomic_inc(&ab->fail_cont_count); 2164 } 2165 2166 ath11k_dbg(ab, ATH11K_DBG_BOOT, "reset starting\n"); 2167 2168 ab->is_reset = true; 2169 atomic_set(&ab->recovery_count, 0); 2170 reinit_completion(&ab->recovery_start); 2171 atomic_set(&ab->recovery_start_count, 0); 2172 2173 ath11k_core_pre_reconfigure_recovery(ab); 2174 2175 reinit_completion(&ab->reconfigure_complete); 2176 ath11k_core_post_reconfigure_recovery(ab); 2177 2178 ath11k_dbg(ab, ATH11K_DBG_BOOT, "waiting recovery start...\n"); 2179 2180 time_left = wait_for_completion_timeout(&ab->recovery_start, 2181 ATH11K_RECOVER_START_TIMEOUT_HZ); 2182 2183 ath11k_hif_irq_disable(ab); 2184 ath11k_hif_ce_irq_disable(ab); 2185 2186 ath11k_hif_power_down(ab, false); 2187 ath11k_hif_power_up(ab); 2188 2189 ath11k_dbg(ab, ATH11K_DBG_BOOT, "reset started\n"); 2190 } 2191 2192 static int ath11k_init_hw_params(struct ath11k_base *ab) 2193 { 2194 const struct ath11k_hw_params *hw_params = NULL; 2195 int i; 2196 2197 for (i = 0; i < ARRAY_SIZE(ath11k_hw_params); i++) { 2198 hw_params = &ath11k_hw_params[i]; 2199 2200 if (hw_params->hw_rev == ab->hw_rev) 2201 break; 2202 } 2203 2204 if (i == ARRAY_SIZE(ath11k_hw_params)) { 2205 ath11k_err(ab, "Unsupported hardware version: 0x%x\n", ab->hw_rev); 2206 return -EINVAL; 2207 } 2208 2209 ab->hw_params = *hw_params; 2210 2211 ath11k_info(ab, "%s\n", ab->hw_params.name); 2212 2213 return 0; 2214 } 2215 2216 int ath11k_core_pre_init(struct ath11k_base *ab) 2217 { 2218 int ret; 2219 2220 ret = ath11k_init_hw_params(ab); 2221 if (ret) { 2222 ath11k_err(ab, "failed to get hw params: %d\n", ret); 2223 return ret; 2224 } 2225 2226 ret = ath11k_fw_pre_init(ab); 2227 if (ret) { 2228 ath11k_err(ab, "failed to pre init firmware: %d", ret); 2229 return ret; 2230 } 2231 2232 return 0; 2233 } 2234 EXPORT_SYMBOL(ath11k_core_pre_init); 2235 2236 int ath11k_core_init(struct ath11k_base *ab) 2237 { 2238 int ret; 2239 2240 ret = ath11k_core_soc_create(ab); 2241 if (ret) { 2242 ath11k_err(ab, "failed to create soc core: %d\n", ret); 2243 return ret; 2244 } 2245 2246 return 0; 2247 } 2248 EXPORT_SYMBOL(ath11k_core_init); 2249 2250 void ath11k_core_deinit(struct ath11k_base *ab) 2251 { 2252 mutex_lock(&ab->core_lock); 2253 2254 ath11k_core_pdev_destroy(ab); 2255 ath11k_core_stop(ab); 2256 2257 mutex_unlock(&ab->core_lock); 2258 2259 ath11k_hif_power_down(ab, false); 2260 ath11k_mac_destroy(ab); 2261 ath11k_core_soc_destroy(ab); 2262 ath11k_fw_destroy(ab); 2263 } 2264 EXPORT_SYMBOL(ath11k_core_deinit); 2265 2266 void ath11k_core_free(struct ath11k_base *ab) 2267 { 2268 destroy_workqueue(ab->workqueue_aux); 2269 destroy_workqueue(ab->workqueue); 2270 2271 kfree(ab); 2272 } 2273 EXPORT_SYMBOL(ath11k_core_free); 2274 2275 struct ath11k_base *ath11k_core_alloc(struct device *dev, size_t priv_size, 2276 enum ath11k_bus bus) 2277 { 2278 struct ath11k_base *ab; 2279 2280 ab = kzalloc(sizeof(*ab) + priv_size, GFP_KERNEL); 2281 if (!ab) 2282 return NULL; 2283 2284 init_completion(&ab->driver_recovery); 2285 2286 ab->workqueue = create_singlethread_workqueue("ath11k_wq"); 2287 if (!ab->workqueue) 2288 goto err_sc_free; 2289 2290 ab->workqueue_aux = create_singlethread_workqueue("ath11k_aux_wq"); 2291 if (!ab->workqueue_aux) 2292 goto err_free_wq; 2293 2294 mutex_init(&ab->core_lock); 2295 mutex_init(&ab->tbl_mtx_lock); 2296 spin_lock_init(&ab->base_lock); 2297 mutex_init(&ab->vdev_id_11d_lock); 2298 init_completion(&ab->reset_complete); 2299 init_completion(&ab->reconfigure_complete); 2300 init_completion(&ab->recovery_start); 2301 2302 INIT_LIST_HEAD(&ab->peers); 2303 init_waitqueue_head(&ab->peer_mapping_wq); 2304 init_waitqueue_head(&ab->wmi_ab.tx_credits_wq); 2305 init_waitqueue_head(&ab->qmi.cold_boot_waitq); 2306 INIT_WORK(&ab->restart_work, ath11k_core_restart); 2307 INIT_WORK(&ab->update_11d_work, ath11k_update_11d); 2308 INIT_WORK(&ab->reset_work, ath11k_core_reset); 2309 timer_setup(&ab->rx_replenish_retry, ath11k_ce_rx_replenish_retry, 0); 2310 init_completion(&ab->htc_suspend); 2311 init_completion(&ab->wow.wakeup_completed); 2312 init_completion(&ab->restart_completed); 2313 2314 ab->dev = dev; 2315 ab->hif.bus = bus; 2316 2317 return ab; 2318 2319 err_free_wq: 2320 destroy_workqueue(ab->workqueue); 2321 err_sc_free: 2322 kfree(ab); 2323 return NULL; 2324 } 2325 EXPORT_SYMBOL(ath11k_core_alloc); 2326 2327 MODULE_DESCRIPTION("Core module for Qualcomm Atheros 802.11ax wireless LAN cards."); 2328 MODULE_LICENSE("Dual BSD/GPL"); 2329