1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 5 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 6 */ 7 8 #include <linux/export.h> 9 #include "dp_rx.h" 10 #include "debug.h" 11 #include "hif.h" 12 13 const struct ce_attr ath11k_host_ce_config_ipq8074[] = { 14 /* CE0: host->target HTC control and raw streams */ 15 { 16 .flags = CE_ATTR_FLAGS, 17 .src_nentries = 16, 18 .src_sz_max = 2048, 19 .dest_nentries = 0, 20 .send_cb = ath11k_htc_tx_completion_handler, 21 }, 22 23 /* CE1: target->host HTT + HTC control */ 24 { 25 .flags = CE_ATTR_FLAGS, 26 .src_nentries = 0, 27 .src_sz_max = 2048, 28 .dest_nentries = 512, 29 .recv_cb = ath11k_htc_rx_completion_handler, 30 }, 31 32 /* CE2: target->host WMI */ 33 { 34 .flags = CE_ATTR_FLAGS, 35 .src_nentries = 0, 36 .src_sz_max = 2048, 37 .dest_nentries = 512, 38 .recv_cb = ath11k_htc_rx_completion_handler, 39 }, 40 41 /* CE3: host->target WMI (mac0) */ 42 { 43 .flags = CE_ATTR_FLAGS, 44 .src_nentries = 32, 45 .src_sz_max = 2048, 46 .dest_nentries = 0, 47 .send_cb = ath11k_htc_tx_completion_handler, 48 }, 49 50 /* CE4: host->target HTT */ 51 { 52 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, 53 .src_nentries = 2048, 54 .src_sz_max = 256, 55 .dest_nentries = 0, 56 }, 57 58 /* CE5: target->host pktlog */ 59 { 60 .flags = CE_ATTR_FLAGS, 61 .src_nentries = 0, 62 .src_sz_max = 2048, 63 .dest_nentries = 512, 64 .recv_cb = ath11k_dp_htt_htc_t2h_msg_handler, 65 }, 66 67 /* CE6: target autonomous hif_memcpy */ 68 { 69 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, 70 .src_nentries = 0, 71 .src_sz_max = 0, 72 .dest_nentries = 0, 73 }, 74 75 /* CE7: host->target WMI (mac1) */ 76 { 77 .flags = CE_ATTR_FLAGS, 78 .src_nentries = 32, 79 .src_sz_max = 2048, 80 .dest_nentries = 0, 81 .send_cb = ath11k_htc_tx_completion_handler, 82 }, 83 84 /* CE8: target autonomous hif_memcpy */ 85 { 86 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, 87 .src_nentries = 0, 88 .src_sz_max = 0, 89 .dest_nentries = 0, 90 }, 91 92 /* CE9: host->target WMI (mac2) */ 93 { 94 .flags = CE_ATTR_FLAGS, 95 .src_nentries = 32, 96 .src_sz_max = 2048, 97 .dest_nentries = 0, 98 .send_cb = ath11k_htc_tx_completion_handler, 99 }, 100 101 /* CE10: target->host HTT */ 102 { 103 .flags = CE_ATTR_FLAGS, 104 .src_nentries = 0, 105 .src_sz_max = 2048, 106 .dest_nentries = 512, 107 .recv_cb = ath11k_htc_rx_completion_handler, 108 }, 109 110 /* CE11: Not used */ 111 { 112 .flags = CE_ATTR_FLAGS, 113 .src_nentries = 0, 114 .src_sz_max = 0, 115 .dest_nentries = 0, 116 }, 117 }; 118 119 const struct ce_attr ath11k_host_ce_config_qca6390[] = { 120 /* CE0: host->target HTC control and raw streams */ 121 { 122 .flags = CE_ATTR_FLAGS, 123 .src_nentries = 16, 124 .src_sz_max = 2048, 125 .dest_nentries = 0, 126 }, 127 128 /* CE1: target->host HTT + HTC control */ 129 { 130 .flags = CE_ATTR_FLAGS, 131 .src_nentries = 0, 132 .src_sz_max = 2048, 133 .dest_nentries = 512, 134 .recv_cb = ath11k_htc_rx_completion_handler, 135 }, 136 137 /* CE2: target->host WMI */ 138 { 139 .flags = CE_ATTR_FLAGS, 140 .src_nentries = 0, 141 .src_sz_max = 2048, 142 .dest_nentries = 512, 143 .recv_cb = ath11k_htc_rx_completion_handler, 144 }, 145 146 /* CE3: host->target WMI (mac0) */ 147 { 148 .flags = CE_ATTR_FLAGS, 149 .src_nentries = 32, 150 .src_sz_max = 2048, 151 .dest_nentries = 0, 152 .send_cb = ath11k_htc_tx_completion_handler, 153 }, 154 155 /* CE4: host->target HTT */ 156 { 157 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, 158 .src_nentries = 2048, 159 .src_sz_max = 256, 160 .dest_nentries = 0, 161 }, 162 163 /* CE5: target->host pktlog */ 164 { 165 .flags = CE_ATTR_FLAGS, 166 .src_nentries = 0, 167 .src_sz_max = 2048, 168 .dest_nentries = 512, 169 .recv_cb = ath11k_dp_htt_htc_t2h_msg_handler, 170 }, 171 172 /* CE6: target autonomous hif_memcpy */ 173 { 174 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, 175 .src_nentries = 0, 176 .src_sz_max = 0, 177 .dest_nentries = 0, 178 }, 179 180 /* CE7: host->target WMI (mac1) */ 181 { 182 .flags = CE_ATTR_FLAGS, 183 .src_nentries = 32, 184 .src_sz_max = 2048, 185 .dest_nentries = 0, 186 .send_cb = ath11k_htc_tx_completion_handler, 187 }, 188 189 /* CE8: target autonomous hif_memcpy */ 190 { 191 .flags = CE_ATTR_FLAGS, 192 .src_nentries = 0, 193 .src_sz_max = 0, 194 .dest_nentries = 0, 195 }, 196 197 }; 198 199 const struct ce_attr ath11k_host_ce_config_qcn9074[] = { 200 /* CE0: host->target HTC control and raw streams */ 201 { 202 .flags = CE_ATTR_FLAGS, 203 .src_nentries = 16, 204 .src_sz_max = 2048, 205 .dest_nentries = 0, 206 }, 207 208 /* CE1: target->host HTT + HTC control */ 209 { 210 .flags = CE_ATTR_FLAGS, 211 .src_nentries = 0, 212 .src_sz_max = 2048, 213 .dest_nentries = 512, 214 .recv_cb = ath11k_htc_rx_completion_handler, 215 }, 216 217 /* CE2: target->host WMI */ 218 { 219 .flags = CE_ATTR_FLAGS, 220 .src_nentries = 0, 221 .src_sz_max = 2048, 222 .dest_nentries = 32, 223 .recv_cb = ath11k_htc_rx_completion_handler, 224 }, 225 226 /* CE3: host->target WMI (mac0) */ 227 { 228 .flags = CE_ATTR_FLAGS, 229 .src_nentries = 32, 230 .src_sz_max = 2048, 231 .dest_nentries = 0, 232 .send_cb = ath11k_htc_tx_completion_handler, 233 }, 234 235 /* CE4: host->target HTT */ 236 { 237 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, 238 .src_nentries = 2048, 239 .src_sz_max = 256, 240 .dest_nentries = 0, 241 }, 242 243 /* CE5: target->host pktlog */ 244 { 245 .flags = CE_ATTR_FLAGS, 246 .src_nentries = 0, 247 .src_sz_max = 2048, 248 .dest_nentries = 512, 249 .recv_cb = ath11k_dp_htt_htc_t2h_msg_handler, 250 }, 251 }; 252 253 static bool ath11k_ce_need_shadow_fix(int ce_id) 254 { 255 /* only ce4 needs shadow workaround */ 256 if (ce_id == 4) 257 return true; 258 return false; 259 } 260 261 void ath11k_ce_stop_shadow_timers(struct ath11k_base *ab) 262 { 263 int i; 264 265 if (!ab->hw_params.supports_shadow_regs) 266 return; 267 268 for (i = 0; i < ab->hw_params.ce_count; i++) 269 if (ath11k_ce_need_shadow_fix(i)) 270 ath11k_dp_shadow_stop_timer(ab, &ab->ce.hp_timer[i]); 271 } 272 273 static int ath11k_ce_rx_buf_enqueue_pipe(struct ath11k_ce_pipe *pipe, 274 struct sk_buff *skb, dma_addr_t paddr) 275 { 276 struct ath11k_base *ab = pipe->ab; 277 struct ath11k_ce_ring *ring = pipe->dest_ring; 278 struct hal_srng *srng; 279 unsigned int write_index; 280 unsigned int nentries_mask = ring->nentries_mask; 281 u32 *desc; 282 int ret; 283 284 lockdep_assert_held(&ab->ce.ce_lock); 285 286 write_index = ring->write_index; 287 288 srng = &ab->hal.srng_list[ring->hal_ring_id]; 289 290 spin_lock_bh(&srng->lock); 291 292 ath11k_hal_srng_access_begin(ab, srng); 293 294 if (unlikely(ath11k_hal_srng_src_num_free(ab, srng, false) < 1)) { 295 ret = -ENOSPC; 296 goto exit; 297 } 298 299 desc = ath11k_hal_srng_src_get_next_entry(ab, srng); 300 if (!desc) { 301 ret = -ENOSPC; 302 goto exit; 303 } 304 305 ath11k_hal_ce_dst_set_desc(desc, paddr); 306 307 ring->skb[write_index] = skb; 308 write_index = CE_RING_IDX_INCR(nentries_mask, write_index); 309 ring->write_index = write_index; 310 311 pipe->rx_buf_needed--; 312 313 ret = 0; 314 exit: 315 ath11k_hal_srng_access_end(ab, srng); 316 317 spin_unlock_bh(&srng->lock); 318 319 return ret; 320 } 321 322 static int ath11k_ce_rx_post_pipe(struct ath11k_ce_pipe *pipe) 323 { 324 struct ath11k_base *ab = pipe->ab; 325 struct sk_buff *skb; 326 dma_addr_t paddr; 327 int ret = 0; 328 329 if (!(pipe->dest_ring || pipe->status_ring)) 330 return 0; 331 332 spin_lock_bh(&ab->ce.ce_lock); 333 while (pipe->rx_buf_needed) { 334 skb = dev_alloc_skb(pipe->buf_sz); 335 if (!skb) { 336 ret = -ENOMEM; 337 goto exit; 338 } 339 340 WARN_ON_ONCE(!IS_ALIGNED((unsigned long)skb->data, 4)); 341 342 paddr = dma_map_single(ab->dev, skb->data, 343 skb->len + skb_tailroom(skb), 344 DMA_FROM_DEVICE); 345 if (unlikely(dma_mapping_error(ab->dev, paddr))) { 346 ath11k_warn(ab, "failed to dma map ce rx buf\n"); 347 dev_kfree_skb_any(skb); 348 ret = -EIO; 349 goto exit; 350 } 351 352 ATH11K_SKB_RXCB(skb)->paddr = paddr; 353 354 ret = ath11k_ce_rx_buf_enqueue_pipe(pipe, skb, paddr); 355 356 if (ret) { 357 ath11k_warn(ab, "failed to enqueue rx buf: %d\n", ret); 358 dma_unmap_single(ab->dev, paddr, 359 skb->len + skb_tailroom(skb), 360 DMA_FROM_DEVICE); 361 dev_kfree_skb_any(skb); 362 goto exit; 363 } 364 } 365 366 exit: 367 spin_unlock_bh(&ab->ce.ce_lock); 368 return ret; 369 } 370 371 static int ath11k_ce_completed_recv_next(struct ath11k_ce_pipe *pipe, 372 struct sk_buff **skb, int *nbytes) 373 { 374 struct ath11k_base *ab = pipe->ab; 375 struct hal_srng *srng; 376 unsigned int sw_index; 377 unsigned int nentries_mask; 378 u32 *desc; 379 int ret = 0; 380 381 spin_lock_bh(&ab->ce.ce_lock); 382 383 sw_index = pipe->dest_ring->sw_index; 384 nentries_mask = pipe->dest_ring->nentries_mask; 385 386 srng = &ab->hal.srng_list[pipe->status_ring->hal_ring_id]; 387 388 spin_lock_bh(&srng->lock); 389 390 ath11k_hal_srng_access_begin(ab, srng); 391 392 desc = ath11k_hal_srng_dst_get_next_entry(ab, srng); 393 if (!desc) { 394 ret = -EIO; 395 goto err; 396 } 397 398 /* Make sure descriptor is read after the head pointer. */ 399 dma_rmb(); 400 401 *nbytes = ath11k_hal_ce_dst_status_get_length(desc); 402 403 *skb = pipe->dest_ring->skb[sw_index]; 404 pipe->dest_ring->skb[sw_index] = NULL; 405 406 sw_index = CE_RING_IDX_INCR(nentries_mask, sw_index); 407 pipe->dest_ring->sw_index = sw_index; 408 409 pipe->rx_buf_needed++; 410 err: 411 ath11k_hal_srng_access_end(ab, srng); 412 413 spin_unlock_bh(&srng->lock); 414 415 spin_unlock_bh(&ab->ce.ce_lock); 416 417 return ret; 418 } 419 420 static void ath11k_ce_recv_process_cb(struct ath11k_ce_pipe *pipe) 421 { 422 struct ath11k_base *ab = pipe->ab; 423 struct sk_buff *skb; 424 struct sk_buff_head list; 425 unsigned int nbytes, max_nbytes; 426 int ret; 427 428 __skb_queue_head_init(&list); 429 while (ath11k_ce_completed_recv_next(pipe, &skb, &nbytes) == 0) { 430 max_nbytes = skb->len + skb_tailroom(skb); 431 dma_unmap_single(ab->dev, ATH11K_SKB_RXCB(skb)->paddr, 432 max_nbytes, DMA_FROM_DEVICE); 433 434 if (unlikely(max_nbytes < nbytes || nbytes == 0)) { 435 ath11k_warn(ab, "unexpected rx length (nbytes %d, max %d)", 436 nbytes, max_nbytes); 437 dev_kfree_skb_any(skb); 438 continue; 439 } 440 441 skb_put(skb, nbytes); 442 __skb_queue_tail(&list, skb); 443 } 444 445 while ((skb = __skb_dequeue(&list))) { 446 ath11k_dbg(ab, ATH11K_DBG_CE, "rx ce pipe %d len %d\n", 447 pipe->pipe_num, skb->len); 448 pipe->recv_cb(ab, skb); 449 } 450 451 ret = ath11k_ce_rx_post_pipe(pipe); 452 if (ret && ret != -ENOSPC) { 453 ath11k_warn(ab, "failed to post rx buf to pipe: %d err: %d\n", 454 pipe->pipe_num, ret); 455 mod_timer(&ab->rx_replenish_retry, 456 jiffies + ATH11K_CE_RX_POST_RETRY_JIFFIES); 457 } 458 } 459 460 static struct sk_buff *ath11k_ce_completed_send_next(struct ath11k_ce_pipe *pipe) 461 { 462 struct ath11k_base *ab = pipe->ab; 463 struct hal_srng *srng; 464 unsigned int sw_index; 465 unsigned int nentries_mask; 466 struct sk_buff *skb; 467 u32 *desc; 468 469 spin_lock_bh(&ab->ce.ce_lock); 470 471 sw_index = pipe->src_ring->sw_index; 472 nentries_mask = pipe->src_ring->nentries_mask; 473 474 srng = &ab->hal.srng_list[pipe->src_ring->hal_ring_id]; 475 476 spin_lock_bh(&srng->lock); 477 478 ath11k_hal_srng_access_begin(ab, srng); 479 480 desc = ath11k_hal_srng_src_reap_next(ab, srng); 481 if (!desc) { 482 skb = ERR_PTR(-EIO); 483 goto err_unlock; 484 } 485 486 skb = pipe->src_ring->skb[sw_index]; 487 488 pipe->src_ring->skb[sw_index] = NULL; 489 490 sw_index = CE_RING_IDX_INCR(nentries_mask, sw_index); 491 pipe->src_ring->sw_index = sw_index; 492 493 err_unlock: 494 spin_unlock_bh(&srng->lock); 495 496 spin_unlock_bh(&ab->ce.ce_lock); 497 498 return skb; 499 } 500 501 static void ath11k_ce_tx_process_cb(struct ath11k_ce_pipe *pipe) 502 { 503 struct ath11k_base *ab = pipe->ab; 504 struct sk_buff *skb; 505 struct sk_buff_head list; 506 507 __skb_queue_head_init(&list); 508 while (!IS_ERR(skb = ath11k_ce_completed_send_next(pipe))) { 509 if (!skb) 510 continue; 511 512 dma_unmap_single(ab->dev, ATH11K_SKB_CB(skb)->paddr, skb->len, 513 DMA_TO_DEVICE); 514 515 if ((!pipe->send_cb) || ab->hw_params.credit_flow) { 516 dev_kfree_skb_any(skb); 517 continue; 518 } 519 520 __skb_queue_tail(&list, skb); 521 } 522 523 while ((skb = __skb_dequeue(&list))) { 524 ath11k_dbg(ab, ATH11K_DBG_CE, "tx ce pipe %d len %d\n", 525 pipe->pipe_num, skb->len); 526 pipe->send_cb(ab, skb); 527 } 528 } 529 530 static void ath11k_ce_srng_msi_ring_params_setup(struct ath11k_base *ab, u32 ce_id, 531 struct hal_srng_params *ring_params) 532 { 533 u32 msi_data_start; 534 u32 msi_data_count, msi_data_idx; 535 u32 msi_irq_start; 536 u32 addr_lo; 537 u32 addr_hi; 538 int ret; 539 540 ret = ath11k_get_user_msi_vector(ab, "CE", 541 &msi_data_count, &msi_data_start, 542 &msi_irq_start); 543 544 if (ret) 545 return; 546 547 ath11k_get_msi_address(ab, &addr_lo, &addr_hi); 548 ath11k_get_ce_msi_idx(ab, ce_id, &msi_data_idx); 549 550 ring_params->msi_addr = addr_lo; 551 ring_params->msi_addr |= (dma_addr_t)(((uint64_t)addr_hi) << 32); 552 ring_params->msi_data = (msi_data_idx % msi_data_count) + msi_data_start; 553 ring_params->flags |= HAL_SRNG_FLAGS_MSI_INTR; 554 } 555 556 static int ath11k_ce_init_ring(struct ath11k_base *ab, 557 struct ath11k_ce_ring *ce_ring, 558 int ce_id, enum hal_ring_type type) 559 { 560 struct hal_srng_params params = { 0 }; 561 int ret; 562 563 params.ring_base_paddr = ce_ring->base_addr_ce_space; 564 params.ring_base_vaddr = ce_ring->base_addr_owner_space; 565 params.num_entries = ce_ring->nentries; 566 567 if (!(CE_ATTR_DIS_INTR & ab->hw_params.host_ce_config[ce_id].flags)) 568 ath11k_ce_srng_msi_ring_params_setup(ab, ce_id, ¶ms); 569 570 switch (type) { 571 case HAL_CE_SRC: 572 if (!(CE_ATTR_DIS_INTR & ab->hw_params.host_ce_config[ce_id].flags)) 573 params.intr_batch_cntr_thres_entries = 1; 574 break; 575 case HAL_CE_DST: 576 params.max_buffer_len = ab->hw_params.host_ce_config[ce_id].src_sz_max; 577 if (!(ab->hw_params.host_ce_config[ce_id].flags & CE_ATTR_DIS_INTR)) { 578 params.intr_timer_thres_us = 1024; 579 params.flags |= HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN; 580 params.low_threshold = ce_ring->nentries - 3; 581 } 582 break; 583 case HAL_CE_DST_STATUS: 584 if (!(ab->hw_params.host_ce_config[ce_id].flags & CE_ATTR_DIS_INTR)) { 585 params.intr_batch_cntr_thres_entries = 1; 586 params.intr_timer_thres_us = 0x1000; 587 } 588 break; 589 default: 590 ath11k_warn(ab, "Invalid CE ring type %d\n", type); 591 return -EINVAL; 592 } 593 594 /* TODO: Init other params needed by HAL to init the ring */ 595 596 ret = ath11k_hal_srng_setup(ab, type, ce_id, 0, ¶ms); 597 if (ret < 0) { 598 ath11k_warn(ab, "failed to setup srng: %d ring_id %d\n", 599 ret, ce_id); 600 return ret; 601 } 602 603 ce_ring->hal_ring_id = ret; 604 605 if (ab->hw_params.supports_shadow_regs && 606 ath11k_ce_need_shadow_fix(ce_id)) 607 ath11k_dp_shadow_init_timer(ab, &ab->ce.hp_timer[ce_id], 608 ATH11K_SHADOW_CTRL_TIMER_INTERVAL, 609 ce_ring->hal_ring_id); 610 611 return 0; 612 } 613 614 static struct ath11k_ce_ring * 615 ath11k_ce_alloc_ring(struct ath11k_base *ab, int nentries, int desc_sz) 616 { 617 struct ath11k_ce_ring *ce_ring; 618 dma_addr_t base_addr; 619 620 ce_ring = kzalloc(struct_size(ce_ring, skb, nentries), GFP_KERNEL); 621 if (ce_ring == NULL) 622 return ERR_PTR(-ENOMEM); 623 624 ce_ring->nentries = nentries; 625 ce_ring->nentries_mask = nentries - 1; 626 627 /* Legacy platforms that do not support cache 628 * coherent DMA are unsupported 629 */ 630 ce_ring->base_addr_owner_space_unaligned = 631 dma_alloc_coherent(ab->dev, 632 nentries * desc_sz + CE_DESC_RING_ALIGN, 633 &base_addr, GFP_KERNEL); 634 if (!ce_ring->base_addr_owner_space_unaligned) { 635 kfree(ce_ring); 636 return ERR_PTR(-ENOMEM); 637 } 638 639 ce_ring->base_addr_ce_space_unaligned = base_addr; 640 641 ce_ring->base_addr_owner_space = PTR_ALIGN( 642 ce_ring->base_addr_owner_space_unaligned, 643 CE_DESC_RING_ALIGN); 644 ce_ring->base_addr_ce_space = ALIGN( 645 ce_ring->base_addr_ce_space_unaligned, 646 CE_DESC_RING_ALIGN); 647 648 return ce_ring; 649 } 650 651 static int ath11k_ce_alloc_pipe(struct ath11k_base *ab, int ce_id) 652 { 653 struct ath11k_ce_pipe *pipe = &ab->ce.ce_pipe[ce_id]; 654 const struct ce_attr *attr = &ab->hw_params.host_ce_config[ce_id]; 655 struct ath11k_ce_ring *ring; 656 int nentries; 657 int desc_sz; 658 659 pipe->attr_flags = attr->flags; 660 661 if (attr->src_nentries) { 662 pipe->send_cb = attr->send_cb; 663 nentries = roundup_pow_of_two(attr->src_nentries); 664 desc_sz = ath11k_hal_ce_get_desc_size(HAL_CE_DESC_SRC); 665 ring = ath11k_ce_alloc_ring(ab, nentries, desc_sz); 666 if (IS_ERR(ring)) 667 return PTR_ERR(ring); 668 pipe->src_ring = ring; 669 } 670 671 if (attr->dest_nentries) { 672 pipe->recv_cb = attr->recv_cb; 673 nentries = roundup_pow_of_two(attr->dest_nentries); 674 desc_sz = ath11k_hal_ce_get_desc_size(HAL_CE_DESC_DST); 675 ring = ath11k_ce_alloc_ring(ab, nentries, desc_sz); 676 if (IS_ERR(ring)) 677 return PTR_ERR(ring); 678 pipe->dest_ring = ring; 679 680 desc_sz = ath11k_hal_ce_get_desc_size(HAL_CE_DESC_DST_STATUS); 681 ring = ath11k_ce_alloc_ring(ab, nentries, desc_sz); 682 if (IS_ERR(ring)) 683 return PTR_ERR(ring); 684 pipe->status_ring = ring; 685 } 686 687 return 0; 688 } 689 690 void ath11k_ce_per_engine_service(struct ath11k_base *ab, u16 ce_id) 691 { 692 struct ath11k_ce_pipe *pipe = &ab->ce.ce_pipe[ce_id]; 693 const struct ce_attr *attr = &ab->hw_params.host_ce_config[ce_id]; 694 695 if (attr->src_nentries) 696 ath11k_ce_tx_process_cb(pipe); 697 698 if (pipe->recv_cb) 699 ath11k_ce_recv_process_cb(pipe); 700 } 701 702 void ath11k_ce_poll_send_completed(struct ath11k_base *ab, u8 pipe_id) 703 { 704 struct ath11k_ce_pipe *pipe = &ab->ce.ce_pipe[pipe_id]; 705 const struct ce_attr *attr = &ab->hw_params.host_ce_config[pipe_id]; 706 707 if ((pipe->attr_flags & CE_ATTR_DIS_INTR) && attr->src_nentries) 708 ath11k_ce_tx_process_cb(pipe); 709 } 710 EXPORT_SYMBOL(ath11k_ce_per_engine_service); 711 712 int ath11k_ce_send(struct ath11k_base *ab, struct sk_buff *skb, u8 pipe_id, 713 u16 transfer_id) 714 { 715 struct ath11k_ce_pipe *pipe = &ab->ce.ce_pipe[pipe_id]; 716 struct hal_srng *srng; 717 u32 *desc; 718 unsigned int write_index, sw_index; 719 unsigned int nentries_mask; 720 int ret = 0; 721 u8 byte_swap_data = 0; 722 int num_used; 723 724 /* Check if some entries could be regained by handling tx completion if 725 * the CE has interrupts disabled and the used entries is more than the 726 * defined usage threshold. 727 */ 728 if (pipe->attr_flags & CE_ATTR_DIS_INTR) { 729 spin_lock_bh(&ab->ce.ce_lock); 730 write_index = pipe->src_ring->write_index; 731 732 sw_index = pipe->src_ring->sw_index; 733 734 if (write_index >= sw_index) 735 num_used = write_index - sw_index; 736 else 737 num_used = pipe->src_ring->nentries - sw_index + 738 write_index; 739 740 spin_unlock_bh(&ab->ce.ce_lock); 741 742 if (num_used > ATH11K_CE_USAGE_THRESHOLD) 743 ath11k_ce_poll_send_completed(ab, pipe->pipe_num); 744 } 745 746 if (test_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags)) 747 return -ESHUTDOWN; 748 749 spin_lock_bh(&ab->ce.ce_lock); 750 751 write_index = pipe->src_ring->write_index; 752 nentries_mask = pipe->src_ring->nentries_mask; 753 754 srng = &ab->hal.srng_list[pipe->src_ring->hal_ring_id]; 755 756 spin_lock_bh(&srng->lock); 757 758 ath11k_hal_srng_access_begin(ab, srng); 759 760 if (unlikely(ath11k_hal_srng_src_num_free(ab, srng, false) < 1)) { 761 ath11k_hal_srng_access_end(ab, srng); 762 ret = -ENOBUFS; 763 goto err_unlock; 764 } 765 766 desc = ath11k_hal_srng_src_get_next_reaped(ab, srng); 767 if (!desc) { 768 ath11k_hal_srng_access_end(ab, srng); 769 ret = -ENOBUFS; 770 goto err_unlock; 771 } 772 773 if (pipe->attr_flags & CE_ATTR_BYTE_SWAP_DATA) 774 byte_swap_data = 1; 775 776 ath11k_hal_ce_src_set_desc(desc, ATH11K_SKB_CB(skb)->paddr, 777 skb->len, transfer_id, byte_swap_data); 778 779 pipe->src_ring->skb[write_index] = skb; 780 pipe->src_ring->write_index = CE_RING_IDX_INCR(nentries_mask, 781 write_index); 782 783 ath11k_hal_srng_access_end(ab, srng); 784 785 if (ath11k_ce_need_shadow_fix(pipe_id)) 786 ath11k_dp_shadow_start_timer(ab, srng, &ab->ce.hp_timer[pipe_id]); 787 788 spin_unlock_bh(&srng->lock); 789 790 spin_unlock_bh(&ab->ce.ce_lock); 791 792 return 0; 793 794 err_unlock: 795 spin_unlock_bh(&srng->lock); 796 797 spin_unlock_bh(&ab->ce.ce_lock); 798 799 return ret; 800 } 801 802 static void ath11k_ce_rx_pipe_cleanup(struct ath11k_ce_pipe *pipe) 803 { 804 struct ath11k_base *ab = pipe->ab; 805 struct ath11k_ce_ring *ring = pipe->dest_ring; 806 struct sk_buff *skb; 807 int i; 808 809 if (!(ring && pipe->buf_sz)) 810 return; 811 812 for (i = 0; i < ring->nentries; i++) { 813 skb = ring->skb[i]; 814 if (!skb) 815 continue; 816 817 ring->skb[i] = NULL; 818 dma_unmap_single(ab->dev, ATH11K_SKB_RXCB(skb)->paddr, 819 skb->len + skb_tailroom(skb), DMA_FROM_DEVICE); 820 dev_kfree_skb_any(skb); 821 } 822 } 823 824 static void ath11k_ce_shadow_config(struct ath11k_base *ab) 825 { 826 int i; 827 828 for (i = 0; i < ab->hw_params.ce_count; i++) { 829 if (ab->hw_params.host_ce_config[i].src_nentries) 830 ath11k_hal_srng_update_shadow_config(ab, 831 HAL_CE_SRC, i); 832 833 if (ab->hw_params.host_ce_config[i].dest_nentries) { 834 ath11k_hal_srng_update_shadow_config(ab, 835 HAL_CE_DST, i); 836 837 ath11k_hal_srng_update_shadow_config(ab, 838 HAL_CE_DST_STATUS, i); 839 } 840 } 841 } 842 843 void ath11k_ce_get_shadow_config(struct ath11k_base *ab, 844 u32 **shadow_cfg, u32 *shadow_cfg_len) 845 { 846 if (!ab->hw_params.supports_shadow_regs) 847 return; 848 849 ath11k_hal_srng_get_shadow_config(ab, shadow_cfg, shadow_cfg_len); 850 851 /* shadow is already configured */ 852 if (*shadow_cfg_len) 853 return; 854 855 /* shadow isn't configured yet, configure now. 856 * non-CE srngs are configured firstly, then 857 * all CE srngs. 858 */ 859 ath11k_hal_srng_shadow_config(ab); 860 ath11k_ce_shadow_config(ab); 861 862 /* get the shadow configuration */ 863 ath11k_hal_srng_get_shadow_config(ab, shadow_cfg, shadow_cfg_len); 864 } 865 EXPORT_SYMBOL(ath11k_ce_get_shadow_config); 866 867 void ath11k_ce_cleanup_pipes(struct ath11k_base *ab) 868 { 869 struct ath11k_ce_pipe *pipe; 870 int pipe_num; 871 872 ath11k_ce_stop_shadow_timers(ab); 873 874 for (pipe_num = 0; pipe_num < ab->hw_params.ce_count; pipe_num++) { 875 pipe = &ab->ce.ce_pipe[pipe_num]; 876 ath11k_ce_rx_pipe_cleanup(pipe); 877 878 /* Cleanup any src CE's which have interrupts disabled */ 879 ath11k_ce_poll_send_completed(ab, pipe_num); 880 881 /* NOTE: Should we also clean up tx buffer in all pipes? */ 882 } 883 } 884 EXPORT_SYMBOL(ath11k_ce_cleanup_pipes); 885 886 void ath11k_ce_rx_post_buf(struct ath11k_base *ab) 887 { 888 struct ath11k_ce_pipe *pipe; 889 int i; 890 int ret; 891 892 for (i = 0; i < ab->hw_params.ce_count; i++) { 893 pipe = &ab->ce.ce_pipe[i]; 894 ret = ath11k_ce_rx_post_pipe(pipe); 895 if (ret) { 896 if (ret == -ENOSPC) 897 continue; 898 899 ath11k_warn(ab, "failed to post rx buf to pipe: %d err: %d\n", 900 i, ret); 901 mod_timer(&ab->rx_replenish_retry, 902 jiffies + ATH11K_CE_RX_POST_RETRY_JIFFIES); 903 904 return; 905 } 906 } 907 } 908 EXPORT_SYMBOL(ath11k_ce_rx_post_buf); 909 910 void ath11k_ce_rx_replenish_retry(struct timer_list *t) 911 { 912 struct ath11k_base *ab = timer_container_of(ab, t, rx_replenish_retry); 913 914 ath11k_ce_rx_post_buf(ab); 915 } 916 917 int ath11k_ce_init_pipes(struct ath11k_base *ab) 918 { 919 struct ath11k_ce_pipe *pipe; 920 int i; 921 int ret; 922 923 for (i = 0; i < ab->hw_params.ce_count; i++) { 924 pipe = &ab->ce.ce_pipe[i]; 925 926 if (pipe->src_ring) { 927 ret = ath11k_ce_init_ring(ab, pipe->src_ring, i, 928 HAL_CE_SRC); 929 if (ret) { 930 ath11k_warn(ab, "failed to init src ring: %d\n", 931 ret); 932 /* Should we clear any partial init */ 933 return ret; 934 } 935 936 pipe->src_ring->write_index = 0; 937 pipe->src_ring->sw_index = 0; 938 } 939 940 if (pipe->dest_ring) { 941 ret = ath11k_ce_init_ring(ab, pipe->dest_ring, i, 942 HAL_CE_DST); 943 if (ret) { 944 ath11k_warn(ab, "failed to init dest ring: %d\n", 945 ret); 946 /* Should we clear any partial init */ 947 return ret; 948 } 949 950 pipe->rx_buf_needed = pipe->dest_ring->nentries ? 951 pipe->dest_ring->nentries - 2 : 0; 952 953 pipe->dest_ring->write_index = 0; 954 pipe->dest_ring->sw_index = 0; 955 } 956 957 if (pipe->status_ring) { 958 ret = ath11k_ce_init_ring(ab, pipe->status_ring, i, 959 HAL_CE_DST_STATUS); 960 if (ret) { 961 ath11k_warn(ab, "failed to init dest status ing: %d\n", 962 ret); 963 /* Should we clear any partial init */ 964 return ret; 965 } 966 967 pipe->status_ring->write_index = 0; 968 pipe->status_ring->sw_index = 0; 969 } 970 } 971 972 return 0; 973 } 974 975 void ath11k_ce_free_pipes(struct ath11k_base *ab) 976 { 977 struct ath11k_ce_pipe *pipe; 978 struct ath11k_ce_ring *ce_ring; 979 int desc_sz; 980 int i; 981 982 for (i = 0; i < ab->hw_params.ce_count; i++) { 983 pipe = &ab->ce.ce_pipe[i]; 984 985 if (ath11k_ce_need_shadow_fix(i)) 986 ath11k_dp_shadow_stop_timer(ab, &ab->ce.hp_timer[i]); 987 988 if (pipe->src_ring) { 989 desc_sz = ath11k_hal_ce_get_desc_size(HAL_CE_DESC_SRC); 990 ce_ring = pipe->src_ring; 991 dma_free_coherent(ab->dev, 992 pipe->src_ring->nentries * desc_sz + 993 CE_DESC_RING_ALIGN, 994 ce_ring->base_addr_owner_space_unaligned, 995 ce_ring->base_addr_ce_space_unaligned); 996 kfree(pipe->src_ring); 997 pipe->src_ring = NULL; 998 } 999 1000 if (pipe->dest_ring) { 1001 desc_sz = ath11k_hal_ce_get_desc_size(HAL_CE_DESC_DST); 1002 ce_ring = pipe->dest_ring; 1003 dma_free_coherent(ab->dev, 1004 pipe->dest_ring->nentries * desc_sz + 1005 CE_DESC_RING_ALIGN, 1006 ce_ring->base_addr_owner_space_unaligned, 1007 ce_ring->base_addr_ce_space_unaligned); 1008 kfree(pipe->dest_ring); 1009 pipe->dest_ring = NULL; 1010 } 1011 1012 if (pipe->status_ring) { 1013 desc_sz = 1014 ath11k_hal_ce_get_desc_size(HAL_CE_DESC_DST_STATUS); 1015 ce_ring = pipe->status_ring; 1016 dma_free_coherent(ab->dev, 1017 pipe->status_ring->nentries * desc_sz + 1018 CE_DESC_RING_ALIGN, 1019 ce_ring->base_addr_owner_space_unaligned, 1020 ce_ring->base_addr_ce_space_unaligned); 1021 kfree(pipe->status_ring); 1022 pipe->status_ring = NULL; 1023 } 1024 } 1025 } 1026 EXPORT_SYMBOL(ath11k_ce_free_pipes); 1027 1028 int ath11k_ce_alloc_pipes(struct ath11k_base *ab) 1029 { 1030 struct ath11k_ce_pipe *pipe; 1031 int i; 1032 int ret; 1033 const struct ce_attr *attr; 1034 1035 spin_lock_init(&ab->ce.ce_lock); 1036 1037 for (i = 0; i < ab->hw_params.ce_count; i++) { 1038 attr = &ab->hw_params.host_ce_config[i]; 1039 pipe = &ab->ce.ce_pipe[i]; 1040 pipe->pipe_num = i; 1041 pipe->ab = ab; 1042 pipe->buf_sz = attr->src_sz_max; 1043 1044 ret = ath11k_ce_alloc_pipe(ab, i); 1045 if (ret) { 1046 /* Free any partial successful allocation */ 1047 ath11k_ce_free_pipes(ab); 1048 return ret; 1049 } 1050 } 1051 1052 return 0; 1053 } 1054 EXPORT_SYMBOL(ath11k_ce_alloc_pipes); 1055 1056 /* For Big Endian Host, Copy Engine byte_swap is enabled 1057 * When Copy Engine does byte_swap, need to byte swap again for the 1058 * Host to get/put buffer content in the correct byte order 1059 */ 1060 void ath11k_ce_byte_swap(void *mem, u32 len) 1061 { 1062 int i; 1063 1064 if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) { 1065 if (!mem) 1066 return; 1067 1068 for (i = 0; i < (len / 4); i++) { 1069 *(u32 *)mem = swab32(*(u32 *)mem); 1070 mem += 4; 1071 } 1072 } 1073 } 1074 1075 int ath11k_ce_get_attr_flags(struct ath11k_base *ab, int ce_id) 1076 { 1077 if (ce_id >= ab->hw_params.ce_count) 1078 return -EINVAL; 1079 1080 return ab->hw_params.host_ce_config[ce_id].flags; 1081 } 1082 EXPORT_SYMBOL(ath11k_ce_get_attr_flags); 1083