1 /* SPDX-License-Identifier: ISC */ 2 /* 3 * Copyright (c) 2004-2011 Atheros Communications Inc. 4 * Copyright (c) 2011-2012 Qualcomm Atheros, Inc. 5 * Copyright (c) 2016-2017 Erik Stromdahl <erik.stromdahl@gmail.com> 6 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 7 */ 8 9 #ifndef _USB_H_ 10 #define _USB_H_ 11 12 /* constants */ 13 #define TX_URB_COUNT 32 14 #define RX_URB_COUNT 32 15 #define ATH10K_USB_RX_BUFFER_SIZE 4096 16 17 #define ATH10K_USB_PIPE_INVALID ATH10K_USB_PIPE_MAX 18 19 /* USB endpoint definitions */ 20 #define ATH10K_USB_EP_ADDR_APP_CTRL_IN 0x81 21 #define ATH10K_USB_EP_ADDR_APP_DATA_IN 0x82 22 #define ATH10K_USB_EP_ADDR_APP_DATA2_IN 0x83 23 #define ATH10K_USB_EP_ADDR_APP_INT_IN 0x84 24 25 #define ATH10K_USB_EP_ADDR_APP_CTRL_OUT 0x01 26 #define ATH10K_USB_EP_ADDR_APP_DATA_LP_OUT 0x02 27 #define ATH10K_USB_EP_ADDR_APP_DATA_MP_OUT 0x03 28 #define ATH10K_USB_EP_ADDR_APP_DATA_HP_OUT 0x04 29 30 /* diagnostic command definitions */ 31 #define ATH10K_USB_CONTROL_REQ_SEND_BMI_CMD 1 32 #define ATH10K_USB_CONTROL_REQ_RECV_BMI_RESP 2 33 #define ATH10K_USB_CONTROL_REQ_DIAG_CMD 3 34 #define ATH10K_USB_CONTROL_REQ_DIAG_RESP 4 35 36 #define ATH10K_USB_CTRL_DIAG_CC_READ 0 37 #define ATH10K_USB_CTRL_DIAG_CC_WRITE 1 38 39 #define ATH10K_USB_IS_BULK_EP(attr) (((attr) & 3) == 0x02) 40 #define ATH10K_USB_IS_INT_EP(attr) (((attr) & 3) == 0x03) 41 #define ATH10K_USB_IS_ISOC_EP(attr) (((attr) & 3) == 0x01) 42 #define ATH10K_USB_IS_DIR_IN(addr) ((addr) & 0x80) 43 44 struct ath10k_usb_ctrl_diag_cmd_write { 45 __le32 cmd; 46 __le32 address; 47 __le32 value; 48 __le32 padding; 49 } __packed; 50 51 struct ath10k_usb_ctrl_diag_cmd_read { 52 __le32 cmd; 53 __le32 address; 54 } __packed; 55 56 struct ath10k_usb_ctrl_diag_resp_read { 57 u8 value[4]; 58 } __packed; 59 60 /* tx/rx pipes for usb */ 61 enum ath10k_usb_pipe_id { 62 ATH10K_USB_PIPE_TX_CTRL = 0, 63 ATH10K_USB_PIPE_TX_DATA_LP, 64 ATH10K_USB_PIPE_TX_DATA_MP, 65 ATH10K_USB_PIPE_TX_DATA_HP, 66 ATH10K_USB_PIPE_RX_CTRL, 67 ATH10K_USB_PIPE_RX_DATA, 68 ATH10K_USB_PIPE_RX_DATA2, 69 ATH10K_USB_PIPE_RX_INT, 70 ATH10K_USB_PIPE_MAX 71 }; 72 73 struct ath10k_usb_pipe { 74 struct list_head urb_list_head; 75 struct usb_anchor urb_submitted; 76 u32 urb_alloc; 77 u32 urb_cnt; 78 u32 urb_cnt_thresh; 79 unsigned int usb_pipe_handle; 80 u32 flags; 81 u8 ep_address; 82 u8 logical_pipe_num; 83 struct ath10k_usb *ar_usb; 84 u16 max_packet_size; 85 struct work_struct io_complete_work; 86 struct sk_buff_head io_comp_queue; 87 struct usb_endpoint_descriptor *ep_desc; 88 }; 89 90 #define ATH10K_USB_PIPE_FLAG_TX BIT(0) 91 92 /* usb device object */ 93 struct ath10k_usb { 94 /* protects pipe->urb_list_head and pipe->urb_cnt */ 95 spinlock_t cs_lock; 96 97 struct usb_device *udev; 98 struct usb_interface *interface; 99 struct ath10k_usb_pipe pipes[ATH10K_USB_PIPE_MAX]; 100 u8 *diag_cmd_buffer; 101 u8 *diag_resp_buffer; 102 struct ath10k *ar; 103 }; 104 105 /* usb urb object */ 106 struct ath10k_urb_context { 107 struct list_head link; 108 struct ath10k_usb_pipe *pipe; 109 struct sk_buff *skb; 110 struct ath10k *ar; 111 }; 112 113 static inline struct ath10k_usb *ath10k_usb_priv(struct ath10k *ar) 114 { 115 return (struct ath10k_usb *)ar->drv_priv; 116 } 117 118 #endif 119