1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (c) 2018 The Linux Foundation. All rights reserved. 4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 5 */ 6 7 #include <linux/bits.h> 8 #include <linux/clk.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_device.h> 13 #include <linux/platform_device.h> 14 #include <linux/property.h> 15 #include <linux/pwrseq/consumer.h> 16 #include <linux/regulator/consumer.h> 17 #include <linux/remoteproc/qcom_rproc.h> 18 #include <linux/of_reserved_mem.h> 19 #include <linux/iommu.h> 20 21 #include "ce.h" 22 #include "coredump.h" 23 #include "debug.h" 24 #include "hif.h" 25 #include "htc.h" 26 #include "snoc.h" 27 28 #define ATH10K_SNOC_RX_POST_RETRY_MS 50 29 #define CE_POLL_PIPE 4 30 #define ATH10K_SNOC_WAKE_IRQ 2 31 32 static char *const ce_name[] = { 33 "WLAN_CE_0", 34 "WLAN_CE_1", 35 "WLAN_CE_2", 36 "WLAN_CE_3", 37 "WLAN_CE_4", 38 "WLAN_CE_5", 39 "WLAN_CE_6", 40 "WLAN_CE_7", 41 "WLAN_CE_8", 42 "WLAN_CE_9", 43 "WLAN_CE_10", 44 "WLAN_CE_11", 45 }; 46 47 static const char * const ath10k_regulators[] = { 48 "vdd-0.8-cx-mx", 49 "vdd-1.8-xo", 50 "vdd-1.3-rfa", 51 "vdd-3.3-ch0", 52 "vdd-3.3-ch1", 53 }; 54 55 static const char * const ath10k_clocks[] = { 56 "cxo_ref_clk_pin", "qdss", 57 }; 58 59 static void ath10k_snoc_htc_tx_cb(struct ath10k_ce_pipe *ce_state); 60 static void ath10k_snoc_htt_tx_cb(struct ath10k_ce_pipe *ce_state); 61 static void ath10k_snoc_htc_rx_cb(struct ath10k_ce_pipe *ce_state); 62 static void ath10k_snoc_htt_rx_cb(struct ath10k_ce_pipe *ce_state); 63 static void ath10k_snoc_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state); 64 static void ath10k_snoc_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state); 65 66 static const struct ath10k_snoc_drv_priv drv_priv = { 67 .hw_rev = ATH10K_HW_WCN3990, 68 .dma_mask = DMA_BIT_MASK(35), 69 .msa_size = 0x100000, 70 }; 71 72 #define WCN3990_SRC_WR_IDX_OFFSET 0x3C 73 #define WCN3990_DST_WR_IDX_OFFSET 0x40 74 75 static struct ath10k_shadow_reg_cfg target_shadow_reg_cfg_map[] = { 76 { 77 .ce_id = __cpu_to_le16(0), 78 .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET), 79 }, 80 81 { 82 .ce_id = __cpu_to_le16(3), 83 .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET), 84 }, 85 86 { 87 .ce_id = __cpu_to_le16(4), 88 .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET), 89 }, 90 91 { 92 .ce_id = __cpu_to_le16(5), 93 .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET), 94 }, 95 96 { 97 .ce_id = __cpu_to_le16(7), 98 .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET), 99 }, 100 101 { 102 .ce_id = __cpu_to_le16(1), 103 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET), 104 }, 105 106 { 107 .ce_id = __cpu_to_le16(2), 108 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET), 109 }, 110 111 { 112 .ce_id = __cpu_to_le16(7), 113 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET), 114 }, 115 116 { 117 .ce_id = __cpu_to_le16(8), 118 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET), 119 }, 120 121 { 122 .ce_id = __cpu_to_le16(9), 123 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET), 124 }, 125 126 { 127 .ce_id = __cpu_to_le16(10), 128 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET), 129 }, 130 131 { 132 .ce_id = __cpu_to_le16(11), 133 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET), 134 }, 135 }; 136 137 static struct ce_attr host_ce_config_wlan[] = { 138 /* CE0: host->target HTC control streams */ 139 { 140 .flags = CE_ATTR_FLAGS, 141 .src_nentries = 16, 142 .src_sz_max = 2048, 143 .dest_nentries = 0, 144 .send_cb = ath10k_snoc_htc_tx_cb, 145 }, 146 147 /* CE1: target->host HTT + HTC control */ 148 { 149 .flags = CE_ATTR_FLAGS, 150 .src_nentries = 0, 151 .src_sz_max = 2048, 152 .dest_nentries = 512, 153 .recv_cb = ath10k_snoc_htt_htc_rx_cb, 154 }, 155 156 /* CE2: target->host WMI */ 157 { 158 .flags = CE_ATTR_FLAGS, 159 .src_nentries = 0, 160 .src_sz_max = 2048, 161 .dest_nentries = 64, 162 .recv_cb = ath10k_snoc_htc_rx_cb, 163 }, 164 165 /* CE3: host->target WMI */ 166 { 167 .flags = CE_ATTR_FLAGS, 168 .src_nentries = 32, 169 .src_sz_max = 2048, 170 .dest_nentries = 0, 171 .send_cb = ath10k_snoc_htc_tx_cb, 172 }, 173 174 /* CE4: host->target HTT */ 175 { 176 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, 177 .src_nentries = 2048, 178 .src_sz_max = 256, 179 .dest_nentries = 0, 180 .send_cb = ath10k_snoc_htt_tx_cb, 181 }, 182 183 /* CE5: target->host HTT (ipa_uc->target ) */ 184 { 185 .flags = CE_ATTR_FLAGS, 186 .src_nentries = 0, 187 .src_sz_max = 512, 188 .dest_nentries = 512, 189 .recv_cb = ath10k_snoc_htt_rx_cb, 190 }, 191 192 /* CE6: target autonomous hif_memcpy */ 193 { 194 .flags = CE_ATTR_FLAGS, 195 .src_nentries = 0, 196 .src_sz_max = 0, 197 .dest_nentries = 0, 198 }, 199 200 /* CE7: ce_diag, the Diagnostic Window */ 201 { 202 .flags = CE_ATTR_FLAGS, 203 .src_nentries = 2, 204 .src_sz_max = 2048, 205 .dest_nentries = 2, 206 }, 207 208 /* CE8: Target to uMC */ 209 { 210 .flags = CE_ATTR_FLAGS, 211 .src_nentries = 0, 212 .src_sz_max = 2048, 213 .dest_nentries = 128, 214 }, 215 216 /* CE9 target->host HTT */ 217 { 218 .flags = CE_ATTR_FLAGS, 219 .src_nentries = 0, 220 .src_sz_max = 2048, 221 .dest_nentries = 512, 222 .recv_cb = ath10k_snoc_htt_htc_rx_cb, 223 }, 224 225 /* CE10: target->host HTT */ 226 { 227 .flags = CE_ATTR_FLAGS, 228 .src_nentries = 0, 229 .src_sz_max = 2048, 230 .dest_nentries = 512, 231 .recv_cb = ath10k_snoc_htt_htc_rx_cb, 232 }, 233 234 /* CE11: target -> host PKTLOG */ 235 { 236 .flags = CE_ATTR_FLAGS, 237 .src_nentries = 0, 238 .src_sz_max = 2048, 239 .dest_nentries = 512, 240 .recv_cb = ath10k_snoc_pktlog_rx_cb, 241 }, 242 }; 243 244 static struct ce_pipe_config target_ce_config_wlan[] = { 245 /* CE0: host->target HTC control and raw streams */ 246 { 247 .pipenum = __cpu_to_le32(0), 248 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 249 .nentries = __cpu_to_le32(32), 250 .nbytes_max = __cpu_to_le32(2048), 251 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 252 .reserved = __cpu_to_le32(0), 253 }, 254 255 /* CE1: target->host HTT + HTC control */ 256 { 257 .pipenum = __cpu_to_le32(1), 258 .pipedir = __cpu_to_le32(PIPEDIR_IN), 259 .nentries = __cpu_to_le32(32), 260 .nbytes_max = __cpu_to_le32(2048), 261 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 262 .reserved = __cpu_to_le32(0), 263 }, 264 265 /* CE2: target->host WMI */ 266 { 267 .pipenum = __cpu_to_le32(2), 268 .pipedir = __cpu_to_le32(PIPEDIR_IN), 269 .nentries = __cpu_to_le32(64), 270 .nbytes_max = __cpu_to_le32(2048), 271 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 272 .reserved = __cpu_to_le32(0), 273 }, 274 275 /* CE3: host->target WMI */ 276 { 277 .pipenum = __cpu_to_le32(3), 278 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 279 .nentries = __cpu_to_le32(32), 280 .nbytes_max = __cpu_to_le32(2048), 281 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 282 .reserved = __cpu_to_le32(0), 283 }, 284 285 /* CE4: host->target HTT */ 286 { 287 .pipenum = __cpu_to_le32(4), 288 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 289 .nentries = __cpu_to_le32(256), 290 .nbytes_max = __cpu_to_le32(256), 291 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 292 .reserved = __cpu_to_le32(0), 293 }, 294 295 /* CE5: target->host HTT (HIF->HTT) */ 296 { 297 .pipenum = __cpu_to_le32(5), 298 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 299 .nentries = __cpu_to_le32(1024), 300 .nbytes_max = __cpu_to_le32(64), 301 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 302 .reserved = __cpu_to_le32(0), 303 }, 304 305 /* CE6: Reserved for target autonomous hif_memcpy */ 306 { 307 .pipenum = __cpu_to_le32(6), 308 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 309 .nentries = __cpu_to_le32(32), 310 .nbytes_max = __cpu_to_le32(16384), 311 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 312 .reserved = __cpu_to_le32(0), 313 }, 314 315 /* CE7 used only by Host */ 316 { 317 .pipenum = __cpu_to_le32(7), 318 .pipedir = __cpu_to_le32(4), 319 .nentries = __cpu_to_le32(0), 320 .nbytes_max = __cpu_to_le32(0), 321 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 322 .reserved = __cpu_to_le32(0), 323 }, 324 325 /* CE8 Target to uMC */ 326 { 327 .pipenum = __cpu_to_le32(8), 328 .pipedir = __cpu_to_le32(PIPEDIR_IN), 329 .nentries = __cpu_to_le32(32), 330 .nbytes_max = __cpu_to_le32(2048), 331 .flags = __cpu_to_le32(0), 332 .reserved = __cpu_to_le32(0), 333 }, 334 335 /* CE9 target->host HTT */ 336 { 337 .pipenum = __cpu_to_le32(9), 338 .pipedir = __cpu_to_le32(PIPEDIR_IN), 339 .nentries = __cpu_to_le32(32), 340 .nbytes_max = __cpu_to_le32(2048), 341 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 342 .reserved = __cpu_to_le32(0), 343 }, 344 345 /* CE10 target->host HTT */ 346 { 347 .pipenum = __cpu_to_le32(10), 348 .pipedir = __cpu_to_le32(PIPEDIR_IN), 349 .nentries = __cpu_to_le32(32), 350 .nbytes_max = __cpu_to_le32(2048), 351 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 352 .reserved = __cpu_to_le32(0), 353 }, 354 355 /* CE11 target autonomous qcache memcpy */ 356 { 357 .pipenum = __cpu_to_le32(11), 358 .pipedir = __cpu_to_le32(PIPEDIR_IN), 359 .nentries = __cpu_to_le32(32), 360 .nbytes_max = __cpu_to_le32(2048), 361 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 362 .reserved = __cpu_to_le32(0), 363 }, 364 }; 365 366 static struct ce_service_to_pipe target_service_to_ce_map_wlan[] = { 367 { 368 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO), 369 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 370 __cpu_to_le32(3), 371 }, 372 { 373 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO), 374 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 375 __cpu_to_le32(2), 376 }, 377 { 378 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK), 379 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 380 __cpu_to_le32(3), 381 }, 382 { 383 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK), 384 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 385 __cpu_to_le32(2), 386 }, 387 { 388 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE), 389 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 390 __cpu_to_le32(3), 391 }, 392 { 393 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE), 394 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 395 __cpu_to_le32(2), 396 }, 397 { 398 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI), 399 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 400 __cpu_to_le32(3), 401 }, 402 { 403 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI), 404 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 405 __cpu_to_le32(2), 406 }, 407 { 408 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL), 409 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 410 __cpu_to_le32(3), 411 }, 412 { 413 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL), 414 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 415 __cpu_to_le32(2), 416 }, 417 { 418 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL), 419 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 420 __cpu_to_le32(0), 421 }, 422 { 423 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL), 424 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 425 __cpu_to_le32(2), 426 }, 427 { /* not used */ 428 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS), 429 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 430 __cpu_to_le32(0), 431 }, 432 { /* not used */ 433 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS), 434 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 435 __cpu_to_le32(2), 436 }, 437 { 438 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG), 439 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 440 __cpu_to_le32(4), 441 }, 442 { 443 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG), 444 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 445 __cpu_to_le32(1), 446 }, 447 { /* not used */ 448 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS), 449 __cpu_to_le32(PIPEDIR_OUT), 450 __cpu_to_le32(5), 451 }, 452 { /* in = DL = target -> host */ 453 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA2_MSG), 454 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 455 __cpu_to_le32(9), 456 }, 457 { /* in = DL = target -> host */ 458 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA3_MSG), 459 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 460 __cpu_to_le32(10), 461 }, 462 { /* in = DL = target -> host pktlog */ 463 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_LOG_MSG), 464 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 465 __cpu_to_le32(11), 466 }, 467 /* (Additions here) */ 468 469 { /* must be last */ 470 __cpu_to_le32(0), 471 __cpu_to_le32(0), 472 __cpu_to_le32(0), 473 }, 474 }; 475 476 static void ath10k_snoc_write32(struct ath10k *ar, u32 offset, u32 value) 477 { 478 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 479 480 iowrite32(value, ar_snoc->mem + offset); 481 } 482 483 static u32 ath10k_snoc_read32(struct ath10k *ar, u32 offset) 484 { 485 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 486 u32 val; 487 488 val = ioread32(ar_snoc->mem + offset); 489 490 return val; 491 } 492 493 static int __ath10k_snoc_rx_post_buf(struct ath10k_snoc_pipe *pipe) 494 { 495 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl; 496 struct ath10k *ar = pipe->hif_ce_state; 497 struct ath10k_ce *ce = ath10k_ce_priv(ar); 498 struct sk_buff *skb; 499 dma_addr_t paddr; 500 int ret; 501 502 skb = dev_alloc_skb(pipe->buf_sz); 503 if (!skb) 504 return -ENOMEM; 505 506 WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb"); 507 508 paddr = dma_map_single(ar->dev, skb->data, 509 skb->len + skb_tailroom(skb), 510 DMA_FROM_DEVICE); 511 if (unlikely(dma_mapping_error(ar->dev, paddr))) { 512 ath10k_warn(ar, "failed to dma map snoc rx buf\n"); 513 dev_kfree_skb_any(skb); 514 return -EIO; 515 } 516 517 ATH10K_SKB_RXCB(skb)->paddr = paddr; 518 519 spin_lock_bh(&ce->ce_lock); 520 ret = ce_pipe->ops->ce_rx_post_buf(ce_pipe, skb, paddr); 521 spin_unlock_bh(&ce->ce_lock); 522 if (ret) { 523 dma_unmap_single(ar->dev, paddr, skb->len + skb_tailroom(skb), 524 DMA_FROM_DEVICE); 525 dev_kfree_skb_any(skb); 526 return ret; 527 } 528 529 return 0; 530 } 531 532 static void ath10k_snoc_rx_post_pipe(struct ath10k_snoc_pipe *pipe) 533 { 534 struct ath10k *ar = pipe->hif_ce_state; 535 struct ath10k_ce *ce = ath10k_ce_priv(ar); 536 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 537 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl; 538 int ret, num; 539 540 if (pipe->buf_sz == 0) 541 return; 542 543 if (!ce_pipe->dest_ring) 544 return; 545 546 spin_lock_bh(&ce->ce_lock); 547 num = __ath10k_ce_rx_num_free_bufs(ce_pipe); 548 spin_unlock_bh(&ce->ce_lock); 549 while (num--) { 550 ret = __ath10k_snoc_rx_post_buf(pipe); 551 if (ret) { 552 if (ret == -ENOSPC) 553 break; 554 ath10k_warn(ar, "failed to post rx buf: %d\n", ret); 555 mod_timer(&ar_snoc->rx_post_retry, jiffies + 556 ATH10K_SNOC_RX_POST_RETRY_MS); 557 break; 558 } 559 } 560 } 561 562 static void ath10k_snoc_rx_post(struct ath10k *ar) 563 { 564 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 565 int i; 566 567 for (i = 0; i < CE_COUNT; i++) 568 ath10k_snoc_rx_post_pipe(&ar_snoc->pipe_info[i]); 569 } 570 571 static void ath10k_snoc_process_rx_cb(struct ath10k_ce_pipe *ce_state, 572 void (*callback)(struct ath10k *ar, 573 struct sk_buff *skb)) 574 { 575 struct ath10k *ar = ce_state->ar; 576 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 577 struct ath10k_snoc_pipe *pipe_info = &ar_snoc->pipe_info[ce_state->id]; 578 struct sk_buff *skb; 579 struct sk_buff_head list; 580 void *transfer_context; 581 unsigned int nbytes, max_nbytes; 582 583 __skb_queue_head_init(&list); 584 while (ath10k_ce_completed_recv_next(ce_state, &transfer_context, 585 &nbytes) == 0) { 586 skb = transfer_context; 587 max_nbytes = skb->len + skb_tailroom(skb); 588 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, 589 max_nbytes, DMA_FROM_DEVICE); 590 591 if (unlikely(max_nbytes < nbytes)) { 592 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)\n", 593 nbytes, max_nbytes); 594 dev_kfree_skb_any(skb); 595 continue; 596 } 597 598 skb_put(skb, nbytes); 599 __skb_queue_tail(&list, skb); 600 } 601 602 while ((skb = __skb_dequeue(&list))) { 603 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc rx ce pipe %d len %d\n", 604 ce_state->id, skb->len); 605 606 callback(ar, skb); 607 } 608 609 ath10k_snoc_rx_post_pipe(pipe_info); 610 } 611 612 static void ath10k_snoc_htc_rx_cb(struct ath10k_ce_pipe *ce_state) 613 { 614 ath10k_snoc_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler); 615 } 616 617 static void ath10k_snoc_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state) 618 { 619 /* CE4 polling needs to be done whenever CE pipe which transports 620 * HTT Rx (target->host) is processed. 621 */ 622 ath10k_ce_per_engine_service(ce_state->ar, CE_POLL_PIPE); 623 624 ath10k_snoc_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler); 625 } 626 627 /* Called by lower (CE) layer when data is received from the Target. 628 * WCN3990 firmware uses separate CE(CE11) to transfer pktlog data. 629 */ 630 static void ath10k_snoc_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state) 631 { 632 ath10k_snoc_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler); 633 } 634 635 static void ath10k_snoc_htt_rx_deliver(struct ath10k *ar, struct sk_buff *skb) 636 { 637 skb_pull(skb, sizeof(struct ath10k_htc_hdr)); 638 ath10k_htt_t2h_msg_handler(ar, skb); 639 } 640 641 static void ath10k_snoc_htt_rx_cb(struct ath10k_ce_pipe *ce_state) 642 { 643 ath10k_ce_per_engine_service(ce_state->ar, CE_POLL_PIPE); 644 ath10k_snoc_process_rx_cb(ce_state, ath10k_snoc_htt_rx_deliver); 645 } 646 647 static void ath10k_snoc_rx_replenish_retry(struct timer_list *t) 648 { 649 struct ath10k_snoc *ar_snoc = timer_container_of(ar_snoc, t, 650 rx_post_retry); 651 struct ath10k *ar = ar_snoc->ar; 652 653 ath10k_snoc_rx_post(ar); 654 } 655 656 static void ath10k_snoc_htc_tx_cb(struct ath10k_ce_pipe *ce_state) 657 { 658 struct ath10k *ar = ce_state->ar; 659 struct sk_buff_head list; 660 struct sk_buff *skb; 661 662 __skb_queue_head_init(&list); 663 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) { 664 if (!skb) 665 continue; 666 667 __skb_queue_tail(&list, skb); 668 } 669 670 while ((skb = __skb_dequeue(&list))) 671 ath10k_htc_tx_completion_handler(ar, skb); 672 } 673 674 static void ath10k_snoc_htt_tx_cb(struct ath10k_ce_pipe *ce_state) 675 { 676 struct ath10k *ar = ce_state->ar; 677 struct sk_buff *skb; 678 679 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) { 680 if (!skb) 681 continue; 682 683 dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr, 684 skb->len, DMA_TO_DEVICE); 685 ath10k_htt_hif_tx_complete(ar, skb); 686 } 687 } 688 689 static int ath10k_snoc_hif_tx_sg(struct ath10k *ar, u8 pipe_id, 690 struct ath10k_hif_sg_item *items, int n_items) 691 { 692 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 693 struct ath10k_ce *ce = ath10k_ce_priv(ar); 694 struct ath10k_snoc_pipe *snoc_pipe; 695 struct ath10k_ce_pipe *ce_pipe; 696 int err, i = 0; 697 698 snoc_pipe = &ar_snoc->pipe_info[pipe_id]; 699 ce_pipe = snoc_pipe->ce_hdl; 700 spin_lock_bh(&ce->ce_lock); 701 702 for (i = 0; i < n_items - 1; i++) { 703 ath10k_dbg(ar, ATH10K_DBG_SNOC, 704 "snoc tx item %d paddr %pad len %d n_items %d\n", 705 i, &items[i].paddr, items[i].len, n_items); 706 707 err = ath10k_ce_send_nolock(ce_pipe, 708 items[i].transfer_context, 709 items[i].paddr, 710 items[i].len, 711 items[i].transfer_id, 712 CE_SEND_FLAG_GATHER); 713 if (err) 714 goto err; 715 } 716 717 ath10k_dbg(ar, ATH10K_DBG_SNOC, 718 "snoc tx item %d paddr %pad len %d n_items %d\n", 719 i, &items[i].paddr, items[i].len, n_items); 720 721 err = ath10k_ce_send_nolock(ce_pipe, 722 items[i].transfer_context, 723 items[i].paddr, 724 items[i].len, 725 items[i].transfer_id, 726 0); 727 if (err) 728 goto err; 729 730 spin_unlock_bh(&ce->ce_lock); 731 732 return 0; 733 734 err: 735 for (; i > 0; i--) 736 __ath10k_ce_send_revert(ce_pipe); 737 738 spin_unlock_bh(&ce->ce_lock); 739 return err; 740 } 741 742 static int ath10k_snoc_hif_get_target_info(struct ath10k *ar, 743 struct bmi_target_info *target_info) 744 { 745 target_info->version = ATH10K_HW_WCN3990; 746 target_info->type = ATH10K_HW_WCN3990; 747 748 return 0; 749 } 750 751 static u16 ath10k_snoc_hif_get_free_queue_number(struct ath10k *ar, u8 pipe) 752 { 753 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 754 755 ath10k_dbg(ar, ATH10K_DBG_SNOC, "hif get free queue number\n"); 756 757 return ath10k_ce_num_free_src_entries(ar_snoc->pipe_info[pipe].ce_hdl); 758 } 759 760 static void ath10k_snoc_hif_send_complete_check(struct ath10k *ar, u8 pipe, 761 int force) 762 { 763 int resources; 764 765 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc hif send complete check\n"); 766 767 if (!force) { 768 resources = ath10k_snoc_hif_get_free_queue_number(ar, pipe); 769 770 if (resources > (host_ce_config_wlan[pipe].src_nentries >> 1)) 771 return; 772 } 773 ath10k_ce_per_engine_service(ar, pipe); 774 } 775 776 static int ath10k_snoc_hif_map_service_to_pipe(struct ath10k *ar, 777 u16 service_id, 778 u8 *ul_pipe, u8 *dl_pipe) 779 { 780 const struct ce_service_to_pipe *entry; 781 bool ul_set = false, dl_set = false; 782 int i; 783 784 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc hif map service\n"); 785 786 for (i = 0; i < ARRAY_SIZE(target_service_to_ce_map_wlan); i++) { 787 entry = &target_service_to_ce_map_wlan[i]; 788 789 if (__le32_to_cpu(entry->service_id) != service_id) 790 continue; 791 792 switch (__le32_to_cpu(entry->pipedir)) { 793 case PIPEDIR_NONE: 794 break; 795 case PIPEDIR_IN: 796 WARN_ON(dl_set); 797 *dl_pipe = __le32_to_cpu(entry->pipenum); 798 dl_set = true; 799 break; 800 case PIPEDIR_OUT: 801 WARN_ON(ul_set); 802 *ul_pipe = __le32_to_cpu(entry->pipenum); 803 ul_set = true; 804 break; 805 case PIPEDIR_INOUT: 806 WARN_ON(dl_set); 807 WARN_ON(ul_set); 808 *dl_pipe = __le32_to_cpu(entry->pipenum); 809 *ul_pipe = __le32_to_cpu(entry->pipenum); 810 dl_set = true; 811 ul_set = true; 812 break; 813 } 814 } 815 816 if (!ul_set || !dl_set) 817 return -ENOENT; 818 819 return 0; 820 } 821 822 static void ath10k_snoc_hif_get_default_pipe(struct ath10k *ar, 823 u8 *ul_pipe, u8 *dl_pipe) 824 { 825 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc hif get default pipe\n"); 826 827 (void)ath10k_snoc_hif_map_service_to_pipe(ar, 828 ATH10K_HTC_SVC_ID_RSVD_CTRL, 829 ul_pipe, dl_pipe); 830 } 831 832 static inline void ath10k_snoc_irq_disable(struct ath10k *ar) 833 { 834 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 835 int id; 836 837 for (id = 0; id < CE_COUNT_MAX; id++) 838 disable_irq(ar_snoc->ce_irqs[id].irq_line); 839 } 840 841 static inline void ath10k_snoc_irq_enable(struct ath10k *ar) 842 { 843 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 844 int id; 845 846 for (id = 0; id < CE_COUNT_MAX; id++) 847 enable_irq(ar_snoc->ce_irqs[id].irq_line); 848 } 849 850 static void ath10k_snoc_rx_pipe_cleanup(struct ath10k_snoc_pipe *snoc_pipe) 851 { 852 struct ath10k_ce_pipe *ce_pipe; 853 struct ath10k_ce_ring *ce_ring; 854 struct sk_buff *skb; 855 struct ath10k *ar; 856 int i; 857 858 ar = snoc_pipe->hif_ce_state; 859 ce_pipe = snoc_pipe->ce_hdl; 860 ce_ring = ce_pipe->dest_ring; 861 862 if (!ce_ring) 863 return; 864 865 if (!snoc_pipe->buf_sz) 866 return; 867 868 for (i = 0; i < ce_ring->nentries; i++) { 869 skb = ce_ring->per_transfer_context[i]; 870 if (!skb) 871 continue; 872 873 ce_ring->per_transfer_context[i] = NULL; 874 875 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, 876 skb->len + skb_tailroom(skb), 877 DMA_FROM_DEVICE); 878 dev_kfree_skb_any(skb); 879 } 880 } 881 882 static void ath10k_snoc_tx_pipe_cleanup(struct ath10k_snoc_pipe *snoc_pipe) 883 { 884 struct ath10k_ce_pipe *ce_pipe; 885 struct ath10k_ce_ring *ce_ring; 886 struct sk_buff *skb; 887 struct ath10k *ar; 888 int i; 889 890 ar = snoc_pipe->hif_ce_state; 891 ce_pipe = snoc_pipe->ce_hdl; 892 ce_ring = ce_pipe->src_ring; 893 894 if (!ce_ring) 895 return; 896 897 if (!snoc_pipe->buf_sz) 898 return; 899 900 for (i = 0; i < ce_ring->nentries; i++) { 901 skb = ce_ring->per_transfer_context[i]; 902 if (!skb) 903 continue; 904 905 ce_ring->per_transfer_context[i] = NULL; 906 907 ath10k_htc_tx_completion_handler(ar, skb); 908 } 909 } 910 911 static void ath10k_snoc_buffer_cleanup(struct ath10k *ar) 912 { 913 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 914 struct ath10k_snoc_pipe *pipe_info; 915 int pipe_num; 916 917 timer_delete_sync(&ar_snoc->rx_post_retry); 918 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) { 919 pipe_info = &ar_snoc->pipe_info[pipe_num]; 920 ath10k_snoc_rx_pipe_cleanup(pipe_info); 921 ath10k_snoc_tx_pipe_cleanup(pipe_info); 922 } 923 } 924 925 static void ath10k_snoc_hif_stop(struct ath10k *ar) 926 { 927 if (!test_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags)) 928 ath10k_snoc_irq_disable(ar); 929 930 ath10k_core_napi_sync_disable(ar); 931 ath10k_snoc_buffer_cleanup(ar); 932 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif stop\n"); 933 } 934 935 static int ath10k_snoc_hif_start(struct ath10k *ar) 936 { 937 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 938 939 bitmap_clear(ar_snoc->pending_ce_irqs, 0, CE_COUNT_MAX); 940 941 netif_threaded_enable(ar->napi_dev); 942 ath10k_core_napi_enable(ar); 943 /* IRQs are left enabled when we restart due to a firmware crash */ 944 if (!test_bit(ATH10K_SNOC_FLAG_RECOVERY, &ar_snoc->flags)) 945 ath10k_snoc_irq_enable(ar); 946 ath10k_snoc_rx_post(ar); 947 948 clear_bit(ATH10K_SNOC_FLAG_RECOVERY, &ar_snoc->flags); 949 950 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif start\n"); 951 952 return 0; 953 } 954 955 static int ath10k_snoc_init_pipes(struct ath10k *ar) 956 { 957 int i, ret; 958 959 for (i = 0; i < CE_COUNT; i++) { 960 ret = ath10k_ce_init_pipe(ar, i, &host_ce_config_wlan[i]); 961 if (ret) { 962 ath10k_err(ar, "failed to initialize copy engine pipe %d: %d\n", 963 i, ret); 964 return ret; 965 } 966 } 967 968 return 0; 969 } 970 971 static int ath10k_snoc_wlan_enable(struct ath10k *ar, 972 enum ath10k_firmware_mode fw_mode) 973 { 974 struct ath10k_tgt_pipe_cfg tgt_cfg[CE_COUNT_MAX]; 975 struct ath10k_qmi_wlan_enable_cfg cfg; 976 enum wlfw_driver_mode_enum_v01 mode; 977 int pipe_num; 978 979 for (pipe_num = 0; pipe_num < CE_COUNT_MAX; pipe_num++) { 980 tgt_cfg[pipe_num].pipe_num = 981 target_ce_config_wlan[pipe_num].pipenum; 982 tgt_cfg[pipe_num].pipe_dir = 983 target_ce_config_wlan[pipe_num].pipedir; 984 tgt_cfg[pipe_num].nentries = 985 target_ce_config_wlan[pipe_num].nentries; 986 tgt_cfg[pipe_num].nbytes_max = 987 target_ce_config_wlan[pipe_num].nbytes_max; 988 tgt_cfg[pipe_num].flags = 989 target_ce_config_wlan[pipe_num].flags; 990 tgt_cfg[pipe_num].reserved = 0; 991 } 992 993 cfg.num_ce_tgt_cfg = sizeof(target_ce_config_wlan) / 994 sizeof(struct ath10k_tgt_pipe_cfg); 995 cfg.ce_tgt_cfg = (struct ath10k_tgt_pipe_cfg *) 996 &tgt_cfg; 997 cfg.num_ce_svc_pipe_cfg = sizeof(target_service_to_ce_map_wlan) / 998 sizeof(struct ath10k_svc_pipe_cfg); 999 cfg.ce_svc_cfg = (struct ath10k_svc_pipe_cfg *) 1000 &target_service_to_ce_map_wlan; 1001 cfg.num_shadow_reg_cfg = ARRAY_SIZE(target_shadow_reg_cfg_map); 1002 cfg.shadow_reg_cfg = (struct ath10k_shadow_reg_cfg *) 1003 &target_shadow_reg_cfg_map; 1004 1005 switch (fw_mode) { 1006 case ATH10K_FIRMWARE_MODE_NORMAL: 1007 mode = QMI_WLFW_MISSION_V01; 1008 break; 1009 case ATH10K_FIRMWARE_MODE_UTF: 1010 mode = QMI_WLFW_FTM_V01; 1011 break; 1012 default: 1013 ath10k_err(ar, "invalid firmware mode %d\n", fw_mode); 1014 return -EINVAL; 1015 } 1016 1017 return ath10k_qmi_wlan_enable(ar, &cfg, mode, 1018 NULL); 1019 } 1020 1021 static int ath10k_hw_power_on(struct ath10k *ar) 1022 { 1023 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1024 int ret; 1025 1026 ath10k_dbg(ar, ATH10K_DBG_SNOC, "soc power on\n"); 1027 1028 ret = pwrseq_power_on(ar_snoc->pwrseq); 1029 if (ret) 1030 return ret; 1031 1032 ret = regulator_bulk_enable(ar_snoc->num_vregs, ar_snoc->vregs); 1033 if (ret) 1034 goto pwrseq_off; 1035 1036 ret = clk_bulk_prepare_enable(ar_snoc->num_clks, ar_snoc->clks); 1037 if (ret) 1038 goto vreg_off; 1039 1040 return ret; 1041 1042 vreg_off: 1043 regulator_bulk_disable(ar_snoc->num_vregs, ar_snoc->vregs); 1044 pwrseq_off: 1045 pwrseq_power_off(ar_snoc->pwrseq); 1046 1047 return ret; 1048 } 1049 1050 static int ath10k_hw_power_off(struct ath10k *ar) 1051 { 1052 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1053 int ret_seq = 0; 1054 int ret_vreg; 1055 1056 ath10k_dbg(ar, ATH10K_DBG_SNOC, "soc power off\n"); 1057 1058 clk_bulk_disable_unprepare(ar_snoc->num_clks, ar_snoc->clks); 1059 1060 ret_vreg = regulator_bulk_disable(ar_snoc->num_vregs, ar_snoc->vregs); 1061 1062 if (ar_snoc->pwrseq) 1063 ret_seq = pwrseq_power_off(ar_snoc->pwrseq); 1064 1065 return ret_vreg ? : ret_seq; 1066 } 1067 1068 static void ath10k_snoc_wlan_disable(struct ath10k *ar) 1069 { 1070 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1071 1072 /* If both ATH10K_FLAG_CRASH_FLUSH and ATH10K_SNOC_FLAG_RECOVERY 1073 * flags are not set, it means that the driver has restarted 1074 * due to a crash inject via debugfs. In this case, the driver 1075 * needs to restart the firmware and hence send qmi wlan disable, 1076 * during the driver restart sequence. 1077 */ 1078 if (!test_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags) || 1079 !test_bit(ATH10K_SNOC_FLAG_RECOVERY, &ar_snoc->flags)) 1080 ath10k_qmi_wlan_disable(ar); 1081 } 1082 1083 static void ath10k_snoc_hif_power_down(struct ath10k *ar) 1084 { 1085 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power down\n"); 1086 1087 ath10k_snoc_wlan_disable(ar); 1088 ath10k_ce_free_rri(ar); 1089 ath10k_hw_power_off(ar); 1090 } 1091 1092 static int ath10k_snoc_hif_power_up(struct ath10k *ar, 1093 enum ath10k_firmware_mode fw_mode) 1094 { 1095 int ret; 1096 1097 ath10k_dbg(ar, ATH10K_DBG_SNOC, "%s:WCN3990 driver state = %d\n", 1098 __func__, ar->state); 1099 1100 ret = ath10k_hw_power_on(ar); 1101 if (ret) { 1102 ath10k_err(ar, "failed to power on device: %d\n", ret); 1103 return ret; 1104 } 1105 1106 ret = ath10k_snoc_wlan_enable(ar, fw_mode); 1107 if (ret) { 1108 ath10k_err(ar, "failed to enable wcn3990: %d\n", ret); 1109 goto err_hw_power_off; 1110 } 1111 1112 ath10k_ce_alloc_rri(ar); 1113 1114 ret = ath10k_snoc_init_pipes(ar); 1115 if (ret) { 1116 ath10k_err(ar, "failed to initialize CE: %d\n", ret); 1117 goto err_free_rri; 1118 } 1119 1120 ath10k_ce_enable_interrupts(ar); 1121 1122 return 0; 1123 1124 err_free_rri: 1125 ath10k_ce_free_rri(ar); 1126 ath10k_snoc_wlan_disable(ar); 1127 1128 err_hw_power_off: 1129 ath10k_hw_power_off(ar); 1130 1131 return ret; 1132 } 1133 1134 static int ath10k_snoc_hif_set_target_log_mode(struct ath10k *ar, 1135 u8 fw_log_mode) 1136 { 1137 u8 fw_dbg_mode; 1138 1139 if (fw_log_mode) 1140 fw_dbg_mode = ATH10K_ENABLE_FW_LOG_CE; 1141 else 1142 fw_dbg_mode = ATH10K_ENABLE_FW_LOG_DIAG; 1143 1144 return ath10k_qmi_set_fw_log_mode(ar, fw_dbg_mode); 1145 } 1146 1147 #ifdef CONFIG_PM 1148 static int ath10k_snoc_hif_suspend(struct ath10k *ar) 1149 { 1150 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1151 int ret; 1152 1153 if (!device_may_wakeup(ar->dev)) 1154 return -EPERM; 1155 1156 ret = enable_irq_wake(ar_snoc->ce_irqs[ATH10K_SNOC_WAKE_IRQ].irq_line); 1157 if (ret) { 1158 ath10k_err(ar, "failed to enable wakeup irq :%d\n", ret); 1159 return ret; 1160 } 1161 1162 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc device suspended\n"); 1163 1164 return ret; 1165 } 1166 1167 static int ath10k_snoc_hif_resume(struct ath10k *ar) 1168 { 1169 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1170 int ret; 1171 1172 if (!device_may_wakeup(ar->dev)) 1173 return -EPERM; 1174 1175 ret = disable_irq_wake(ar_snoc->ce_irqs[ATH10K_SNOC_WAKE_IRQ].irq_line); 1176 if (ret) { 1177 ath10k_err(ar, "failed to disable wakeup irq: %d\n", ret); 1178 return ret; 1179 } 1180 1181 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc device resumed\n"); 1182 1183 return ret; 1184 } 1185 #endif 1186 1187 static const struct ath10k_hif_ops ath10k_snoc_hif_ops = { 1188 .read32 = ath10k_snoc_read32, 1189 .write32 = ath10k_snoc_write32, 1190 .start = ath10k_snoc_hif_start, 1191 .stop = ath10k_snoc_hif_stop, 1192 .map_service_to_pipe = ath10k_snoc_hif_map_service_to_pipe, 1193 .get_default_pipe = ath10k_snoc_hif_get_default_pipe, 1194 .power_up = ath10k_snoc_hif_power_up, 1195 .power_down = ath10k_snoc_hif_power_down, 1196 .tx_sg = ath10k_snoc_hif_tx_sg, 1197 .send_complete_check = ath10k_snoc_hif_send_complete_check, 1198 .get_free_queue_number = ath10k_snoc_hif_get_free_queue_number, 1199 .get_target_info = ath10k_snoc_hif_get_target_info, 1200 .set_target_log_mode = ath10k_snoc_hif_set_target_log_mode, 1201 1202 #ifdef CONFIG_PM 1203 .suspend = ath10k_snoc_hif_suspend, 1204 .resume = ath10k_snoc_hif_resume, 1205 #endif 1206 }; 1207 1208 static const struct ath10k_bus_ops ath10k_snoc_bus_ops = { 1209 .read32 = ath10k_snoc_read32, 1210 .write32 = ath10k_snoc_write32, 1211 }; 1212 1213 static int ath10k_snoc_get_ce_id_from_irq(struct ath10k *ar, int irq) 1214 { 1215 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1216 int i; 1217 1218 for (i = 0; i < CE_COUNT_MAX; i++) { 1219 if (ar_snoc->ce_irqs[i].irq_line == irq) 1220 return i; 1221 } 1222 ath10k_err(ar, "No matching CE id for irq %d\n", irq); 1223 1224 return -EINVAL; 1225 } 1226 1227 static irqreturn_t ath10k_snoc_per_engine_handler(int irq, void *arg) 1228 { 1229 struct ath10k *ar = arg; 1230 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1231 int ce_id = ath10k_snoc_get_ce_id_from_irq(ar, irq); 1232 1233 if (ce_id < 0 || ce_id >= ARRAY_SIZE(ar_snoc->pipe_info)) { 1234 ath10k_warn(ar, "unexpected/invalid irq %d ce_id %d\n", irq, 1235 ce_id); 1236 return IRQ_HANDLED; 1237 } 1238 1239 ath10k_ce_disable_interrupt(ar, ce_id); 1240 set_bit(ce_id, ar_snoc->pending_ce_irqs); 1241 1242 napi_schedule(&ar->napi); 1243 1244 return IRQ_HANDLED; 1245 } 1246 1247 static int ath10k_snoc_napi_poll(struct napi_struct *ctx, int budget) 1248 { 1249 struct ath10k *ar = container_of(ctx, struct ath10k, napi); 1250 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1251 int done = 0; 1252 int ce_id; 1253 1254 if (test_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags)) { 1255 napi_complete(ctx); 1256 return done; 1257 } 1258 1259 for (ce_id = 0; ce_id < CE_COUNT; ce_id++) 1260 if (test_and_clear_bit(ce_id, ar_snoc->pending_ce_irqs)) { 1261 ath10k_ce_per_engine_service(ar, ce_id); 1262 ath10k_ce_enable_interrupt(ar, ce_id); 1263 } 1264 1265 done = ath10k_htt_txrx_compl_task(ar, budget); 1266 1267 if (done < budget) 1268 napi_complete(ctx); 1269 1270 return done; 1271 } 1272 1273 static void ath10k_snoc_init_napi(struct ath10k *ar) 1274 { 1275 netif_napi_add(ar->napi_dev, &ar->napi, ath10k_snoc_napi_poll); 1276 } 1277 1278 static int ath10k_snoc_request_irq(struct ath10k *ar) 1279 { 1280 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1281 int ret, id; 1282 1283 for (id = 0; id < CE_COUNT_MAX; id++) { 1284 ret = request_irq(ar_snoc->ce_irqs[id].irq_line, 1285 ath10k_snoc_per_engine_handler, 1286 IRQF_NO_AUTOEN, ce_name[id], ar); 1287 if (ret) { 1288 ath10k_err(ar, 1289 "failed to register IRQ handler for CE %d: %d\n", 1290 id, ret); 1291 goto err_irq; 1292 } 1293 } 1294 1295 return 0; 1296 1297 err_irq: 1298 for (id -= 1; id >= 0; id--) 1299 free_irq(ar_snoc->ce_irqs[id].irq_line, ar); 1300 1301 return ret; 1302 } 1303 1304 static void ath10k_snoc_free_irq(struct ath10k *ar) 1305 { 1306 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1307 int id; 1308 1309 for (id = 0; id < CE_COUNT_MAX; id++) 1310 free_irq(ar_snoc->ce_irqs[id].irq_line, ar); 1311 } 1312 1313 static int ath10k_snoc_resource_init(struct ath10k *ar) 1314 { 1315 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1316 struct platform_device *pdev; 1317 struct resource *res; 1318 int i, ret = 0; 1319 1320 pdev = ar_snoc->dev; 1321 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "membase"); 1322 if (!res) { 1323 ath10k_err(ar, "Memory base not found in DT\n"); 1324 return -EINVAL; 1325 } 1326 1327 ar_snoc->mem_pa = res->start; 1328 ar_snoc->mem = devm_ioremap(&pdev->dev, ar_snoc->mem_pa, 1329 resource_size(res)); 1330 if (!ar_snoc->mem) { 1331 ath10k_err(ar, "Memory base ioremap failed with physical address %pa\n", 1332 &ar_snoc->mem_pa); 1333 return -EINVAL; 1334 } 1335 1336 for (i = 0; i < CE_COUNT; i++) { 1337 ret = platform_get_irq(ar_snoc->dev, i); 1338 if (ret < 0) 1339 return ret; 1340 ar_snoc->ce_irqs[i].irq_line = ret; 1341 } 1342 1343 ret = device_property_read_u32(&pdev->dev, "qcom,xo-cal-data", 1344 &ar_snoc->xo_cal_data); 1345 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc xo-cal-data return %d\n", ret); 1346 if (ret == 0) { 1347 ar_snoc->xo_cal_supported = true; 1348 ath10k_dbg(ar, ATH10K_DBG_SNOC, "xo cal data %x\n", 1349 ar_snoc->xo_cal_data); 1350 } 1351 1352 return 0; 1353 } 1354 1355 static void ath10k_snoc_quirks_init(struct ath10k *ar) 1356 { 1357 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1358 struct device *dev = &ar_snoc->dev->dev; 1359 1360 /* ignore errors, keep NULL if there is no property */ 1361 of_property_read_string(dev->of_node, "firmware-name", &ar->board_name); 1362 1363 if (of_property_read_bool(dev->of_node, "qcom,snoc-host-cap-8bit-quirk")) 1364 set_bit(ATH10K_SNOC_FLAG_8BIT_HOST_CAP_QUIRK, &ar_snoc->flags); 1365 } 1366 1367 int ath10k_snoc_fw_indication(struct ath10k *ar, u64 type) 1368 { 1369 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1370 struct ath10k_bus_params bus_params = {}; 1371 int ret; 1372 1373 if (test_bit(ATH10K_SNOC_FLAG_UNREGISTERING, &ar_snoc->flags)) 1374 return 0; 1375 1376 switch (type) { 1377 case ATH10K_QMI_EVENT_FW_READY_IND: 1378 if (test_bit(ATH10K_SNOC_FLAG_REGISTERED, &ar_snoc->flags)) { 1379 ath10k_core_start_recovery(ar); 1380 break; 1381 } 1382 1383 bus_params.dev_type = ATH10K_DEV_TYPE_LL; 1384 bus_params.chip_id = ar_snoc->target_info.soc_version; 1385 ret = ath10k_core_register(ar, &bus_params); 1386 if (ret) { 1387 ath10k_err(ar, "Failed to register driver core: %d\n", 1388 ret); 1389 return ret; 1390 } 1391 set_bit(ATH10K_SNOC_FLAG_REGISTERED, &ar_snoc->flags); 1392 break; 1393 case ATH10K_QMI_EVENT_FW_DOWN_IND: 1394 set_bit(ATH10K_SNOC_FLAG_RECOVERY, &ar_snoc->flags); 1395 set_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags); 1396 break; 1397 default: 1398 ath10k_err(ar, "invalid fw indication: %llx\n", type); 1399 return -EINVAL; 1400 } 1401 1402 return 0; 1403 } 1404 1405 static int ath10k_snoc_setup_resource(struct ath10k *ar) 1406 { 1407 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1408 struct ath10k_ce *ce = ath10k_ce_priv(ar); 1409 struct ath10k_snoc_pipe *pipe; 1410 int i, ret; 1411 1412 timer_setup(&ar_snoc->rx_post_retry, ath10k_snoc_rx_replenish_retry, 0); 1413 spin_lock_init(&ce->ce_lock); 1414 for (i = 0; i < CE_COUNT; i++) { 1415 pipe = &ar_snoc->pipe_info[i]; 1416 pipe->ce_hdl = &ce->ce_states[i]; 1417 pipe->pipe_num = i; 1418 pipe->hif_ce_state = ar; 1419 1420 ret = ath10k_ce_alloc_pipe(ar, i, &host_ce_config_wlan[i]); 1421 if (ret) { 1422 ath10k_err(ar, "failed to allocate copy engine pipe %d: %d\n", 1423 i, ret); 1424 return ret; 1425 } 1426 1427 pipe->buf_sz = host_ce_config_wlan[i].src_sz_max; 1428 } 1429 ath10k_snoc_init_napi(ar); 1430 1431 return 0; 1432 } 1433 1434 static void ath10k_snoc_release_resource(struct ath10k *ar) 1435 { 1436 int i; 1437 1438 netif_napi_del(&ar->napi); 1439 for (i = 0; i < CE_COUNT; i++) 1440 ath10k_ce_free_pipe(ar, i); 1441 } 1442 1443 static void ath10k_msa_dump_memory(struct ath10k *ar, 1444 struct ath10k_fw_crash_data *crash_data) 1445 { 1446 const struct ath10k_hw_mem_layout *mem_layout; 1447 const struct ath10k_mem_region *current_region; 1448 struct ath10k_dump_ram_data_hdr *hdr; 1449 size_t buf_len; 1450 u8 *buf; 1451 1452 if (!crash_data || !crash_data->ramdump_buf) 1453 return; 1454 1455 mem_layout = ath10k_coredump_get_mem_layout(ar); 1456 if (!mem_layout) 1457 return; 1458 1459 current_region = &mem_layout->region_table.regions[0]; 1460 1461 buf = crash_data->ramdump_buf; 1462 buf_len = crash_data->ramdump_buf_len; 1463 memset(buf, 0, buf_len); 1464 1465 /* Reserve space for the header. */ 1466 hdr = (void *)buf; 1467 buf += sizeof(*hdr); 1468 buf_len -= sizeof(*hdr); 1469 1470 hdr->region_type = cpu_to_le32(current_region->type); 1471 hdr->start = cpu_to_le32((unsigned long)ar->msa.vaddr); 1472 hdr->length = cpu_to_le32(ar->msa.mem_size); 1473 1474 if (current_region->len < ar->msa.mem_size) { 1475 memcpy(buf, ar->msa.vaddr, current_region->len); 1476 ath10k_warn(ar, "msa dump length is less than msa size %x, %x\n", 1477 current_region->len, ar->msa.mem_size); 1478 } else { 1479 memcpy(buf, ar->msa.vaddr, ar->msa.mem_size); 1480 } 1481 } 1482 1483 void ath10k_snoc_fw_crashed_dump(struct ath10k *ar) 1484 { 1485 struct ath10k_fw_crash_data *crash_data; 1486 char guid[UUID_STRING_LEN + 1]; 1487 1488 mutex_lock(&ar->dump_mutex); 1489 1490 spin_lock_bh(&ar->data_lock); 1491 ar->stats.fw_crash_counter++; 1492 spin_unlock_bh(&ar->data_lock); 1493 1494 crash_data = ath10k_coredump_new(ar); 1495 1496 if (crash_data) 1497 scnprintf(guid, sizeof(guid), "%pUl", &crash_data->guid); 1498 else 1499 scnprintf(guid, sizeof(guid), "n/a"); 1500 1501 ath10k_err(ar, "firmware crashed! (guid %s)\n", guid); 1502 ath10k_print_driver_info(ar); 1503 ath10k_msa_dump_memory(ar, crash_data); 1504 mutex_unlock(&ar->dump_mutex); 1505 } 1506 1507 static int ath10k_snoc_modem_notify(struct notifier_block *nb, unsigned long action, 1508 void *data) 1509 { 1510 struct ath10k_snoc *ar_snoc = container_of(nb, struct ath10k_snoc, nb); 1511 struct ath10k *ar = ar_snoc->ar; 1512 struct qcom_ssr_notify_data *notify_data = data; 1513 1514 switch (action) { 1515 case QCOM_SSR_BEFORE_POWERUP: 1516 ath10k_dbg(ar, ATH10K_DBG_SNOC, "received modem starting event\n"); 1517 clear_bit(ATH10K_SNOC_FLAG_MODEM_STOPPED, &ar_snoc->flags); 1518 break; 1519 1520 case QCOM_SSR_AFTER_POWERUP: 1521 ath10k_dbg(ar, ATH10K_DBG_SNOC, "received modem running event\n"); 1522 break; 1523 1524 case QCOM_SSR_BEFORE_SHUTDOWN: 1525 ath10k_dbg(ar, ATH10K_DBG_SNOC, "received modem %s event\n", 1526 notify_data->crashed ? "crashed" : "stopping"); 1527 if (!notify_data->crashed) 1528 set_bit(ATH10K_SNOC_FLAG_MODEM_STOPPED, &ar_snoc->flags); 1529 else 1530 clear_bit(ATH10K_SNOC_FLAG_MODEM_STOPPED, &ar_snoc->flags); 1531 break; 1532 1533 case QCOM_SSR_AFTER_SHUTDOWN: 1534 ath10k_dbg(ar, ATH10K_DBG_SNOC, "received modem offline event\n"); 1535 break; 1536 1537 default: 1538 ath10k_err(ar, "received unrecognized event %lu\n", action); 1539 break; 1540 } 1541 1542 return NOTIFY_OK; 1543 } 1544 1545 static int ath10k_modem_init(struct ath10k *ar) 1546 { 1547 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1548 void *notifier; 1549 int ret; 1550 1551 ar_snoc->nb.notifier_call = ath10k_snoc_modem_notify; 1552 1553 notifier = qcom_register_ssr_notifier("mpss", &ar_snoc->nb); 1554 if (IS_ERR(notifier)) { 1555 ret = PTR_ERR(notifier); 1556 ath10k_err(ar, "failed to initialize modem notifier: %d\n", ret); 1557 return ret; 1558 } 1559 1560 ar_snoc->notifier = notifier; 1561 1562 return 0; 1563 } 1564 1565 static void ath10k_modem_deinit(struct ath10k *ar) 1566 { 1567 int ret; 1568 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1569 1570 ret = qcom_unregister_ssr_notifier(ar_snoc->notifier, &ar_snoc->nb); 1571 if (ret) 1572 ath10k_err(ar, "error %d unregistering notifier\n", ret); 1573 } 1574 1575 static int ath10k_setup_msa_resources(struct ath10k *ar, u32 msa_size) 1576 { 1577 struct device *dev = ar->dev; 1578 struct resource r; 1579 int ret; 1580 1581 ret = of_reserved_mem_region_to_resource(dev->of_node, 0, &r); 1582 if (!ret) { 1583 ar->msa.paddr = r.start; 1584 ar->msa.mem_size = resource_size(&r); 1585 ar->msa.vaddr = devm_memremap(dev, ar->msa.paddr, 1586 ar->msa.mem_size, 1587 MEMREMAP_WT); 1588 if (IS_ERR(ar->msa.vaddr)) { 1589 dev_err(dev, "failed to map memory region: %pa\n", 1590 &r.start); 1591 return PTR_ERR(ar->msa.vaddr); 1592 } 1593 } else { 1594 ar->msa.vaddr = dmam_alloc_coherent(dev, msa_size, 1595 &ar->msa.paddr, 1596 GFP_KERNEL); 1597 if (!ar->msa.vaddr) { 1598 ath10k_err(ar, "failed to allocate dma memory for msa region\n"); 1599 return -ENOMEM; 1600 } 1601 ar->msa.mem_size = msa_size; 1602 } 1603 1604 ath10k_dbg(ar, ATH10K_DBG_QMI, "qmi msa.paddr: %pad , msa.vaddr: 0x%p\n", 1605 &ar->msa.paddr, 1606 ar->msa.vaddr); 1607 1608 return 0; 1609 } 1610 1611 static int ath10k_fw_init(struct ath10k *ar) 1612 { 1613 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1614 struct device *host_dev = &ar_snoc->dev->dev; 1615 struct platform_device_info info; 1616 struct iommu_domain *iommu_dom; 1617 struct platform_device *pdev; 1618 struct device_node *node; 1619 int ret; 1620 1621 node = of_get_child_by_name(host_dev->of_node, "wifi-firmware"); 1622 if (!node) { 1623 ar_snoc->use_tz = true; 1624 return 0; 1625 } 1626 1627 memset(&info, 0, sizeof(info)); 1628 info.fwnode = &node->fwnode; 1629 info.parent = host_dev; 1630 info.name = node->name; 1631 info.dma_mask = DMA_BIT_MASK(32); 1632 1633 pdev = platform_device_register_full(&info); 1634 if (IS_ERR(pdev)) { 1635 of_node_put(node); 1636 return PTR_ERR(pdev); 1637 } 1638 1639 pdev->dev.of_node = node; 1640 1641 ret = of_dma_configure(&pdev->dev, node, true); 1642 if (ret) { 1643 ath10k_err(ar, "dma configure fail: %d\n", ret); 1644 goto err_unregister; 1645 } 1646 1647 ar_snoc->fw.dev = &pdev->dev; 1648 1649 iommu_dom = iommu_paging_domain_alloc(ar_snoc->fw.dev); 1650 if (IS_ERR(iommu_dom)) { 1651 ath10k_err(ar, "failed to allocate iommu domain\n"); 1652 ret = PTR_ERR(iommu_dom); 1653 goto err_unregister; 1654 } 1655 1656 ret = iommu_attach_device(iommu_dom, ar_snoc->fw.dev); 1657 if (ret) { 1658 ath10k_err(ar, "could not attach device: %d\n", ret); 1659 goto err_iommu_free; 1660 } 1661 1662 ar_snoc->fw.iommu_domain = iommu_dom; 1663 ar_snoc->fw.fw_start_addr = ar->msa.paddr; 1664 1665 ret = iommu_map(iommu_dom, ar_snoc->fw.fw_start_addr, 1666 ar->msa.paddr, ar->msa.mem_size, 1667 IOMMU_READ | IOMMU_WRITE, GFP_KERNEL); 1668 if (ret) { 1669 ath10k_err(ar, "failed to map firmware region: %d\n", ret); 1670 goto err_iommu_detach; 1671 } 1672 1673 of_node_put(node); 1674 1675 return 0; 1676 1677 err_iommu_detach: 1678 iommu_detach_device(iommu_dom, ar_snoc->fw.dev); 1679 1680 err_iommu_free: 1681 iommu_domain_free(iommu_dom); 1682 1683 err_unregister: 1684 platform_device_unregister(pdev); 1685 of_node_put(node); 1686 1687 return ret; 1688 } 1689 1690 static int ath10k_fw_deinit(struct ath10k *ar) 1691 { 1692 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1693 const size_t mapped_size = ar_snoc->fw.mapped_mem_size; 1694 struct iommu_domain *iommu; 1695 size_t unmapped_size; 1696 1697 if (ar_snoc->use_tz) 1698 return 0; 1699 1700 iommu = ar_snoc->fw.iommu_domain; 1701 1702 unmapped_size = iommu_unmap(iommu, ar_snoc->fw.fw_start_addr, 1703 mapped_size); 1704 if (unmapped_size != mapped_size) 1705 ath10k_err(ar, "failed to unmap firmware: %zu\n", 1706 unmapped_size); 1707 1708 iommu_detach_device(iommu, ar_snoc->fw.dev); 1709 iommu_domain_free(iommu); 1710 1711 platform_device_unregister(to_platform_device(ar_snoc->fw.dev)); 1712 1713 return 0; 1714 } 1715 1716 static const struct of_device_id ath10k_snoc_dt_match[] = { 1717 { .compatible = "qcom,wcn3990-wifi", 1718 .data = &drv_priv, 1719 }, 1720 { } 1721 }; 1722 MODULE_DEVICE_TABLE(of, ath10k_snoc_dt_match); 1723 1724 static int ath10k_snoc_probe(struct platform_device *pdev) 1725 { 1726 const struct ath10k_snoc_drv_priv *drv_data; 1727 struct ath10k_snoc *ar_snoc; 1728 struct device *dev; 1729 struct ath10k *ar; 1730 u32 msa_size; 1731 int ret; 1732 u32 i; 1733 1734 dev = &pdev->dev; 1735 drv_data = device_get_match_data(dev); 1736 if (!drv_data) { 1737 dev_err(dev, "failed to find matching device tree id\n"); 1738 return -EINVAL; 1739 } 1740 1741 ret = dma_set_mask_and_coherent(dev, drv_data->dma_mask); 1742 if (ret) { 1743 dev_err(dev, "failed to set dma mask: %d\n", ret); 1744 return ret; 1745 } 1746 1747 ar = ath10k_core_create(sizeof(*ar_snoc), dev, ATH10K_BUS_SNOC, 1748 drv_data->hw_rev, &ath10k_snoc_hif_ops); 1749 if (!ar) { 1750 dev_err(dev, "failed to allocate core\n"); 1751 return -ENOMEM; 1752 } 1753 1754 ar_snoc = ath10k_snoc_priv(ar); 1755 ar_snoc->dev = pdev; 1756 platform_set_drvdata(pdev, ar); 1757 ar_snoc->ar = ar; 1758 ar_snoc->ce.bus_ops = &ath10k_snoc_bus_ops; 1759 ar->ce_priv = &ar_snoc->ce; 1760 msa_size = drv_data->msa_size; 1761 1762 ath10k_snoc_quirks_init(ar); 1763 1764 ret = ath10k_snoc_resource_init(ar); 1765 if (ret) { 1766 ath10k_warn(ar, "failed to initialize resource: %d\n", ret); 1767 goto err_core_destroy; 1768 } 1769 1770 ret = ath10k_snoc_setup_resource(ar); 1771 if (ret) { 1772 ath10k_warn(ar, "failed to setup resource: %d\n", ret); 1773 goto err_core_destroy; 1774 } 1775 ret = ath10k_snoc_request_irq(ar); 1776 if (ret) { 1777 ath10k_warn(ar, "failed to request irqs: %d\n", ret); 1778 goto err_release_resource; 1779 } 1780 1781 /* 1782 * devm_pwrseq_get() can return -EPROBE_DEFER in two cases: 1783 * - it is not supposed to be used 1784 * - it is supposed to be used, but the driver hasn't probed yet. 1785 * 1786 * There is no simple way to distinguish between these two cases, but: 1787 * - if it is not supposed to be used, then regulator_bulk_get() will 1788 * return all regulators as expected, continuing the probe 1789 * - if it is supposed to be used, but wasn't probed yet, we will get 1790 * -EPROBE_DEFER from regulator_bulk_get() too. 1791 * 1792 * For backwards compatibility with DTs specifying regulators directly 1793 * rather than using the PMU device, ignore the defer error from 1794 * pwrseq. 1795 */ 1796 ar_snoc->pwrseq = devm_pwrseq_get(&pdev->dev, "wlan"); 1797 if (IS_ERR(ar_snoc->pwrseq)) { 1798 ret = PTR_ERR(ar_snoc->pwrseq); 1799 ar_snoc->pwrseq = NULL; 1800 if (ret != -EPROBE_DEFER) 1801 goto err_free_irq; 1802 1803 ar_snoc->num_vregs = ARRAY_SIZE(ath10k_regulators); 1804 } else { 1805 /* 1806 * The first regulator (vdd-0.8-cx-mx) is used to power on part 1807 * of the SoC rather than the PMU on WCN399x, the rest are 1808 * handled via pwrseq. 1809 */ 1810 ar_snoc->num_vregs = 1; 1811 } 1812 1813 ar_snoc->vregs = devm_kcalloc(&pdev->dev, ar_snoc->num_vregs, 1814 sizeof(*ar_snoc->vregs), GFP_KERNEL); 1815 if (!ar_snoc->vregs) { 1816 ret = -ENOMEM; 1817 goto err_free_irq; 1818 } 1819 for (i = 0; i < ar_snoc->num_vregs; i++) 1820 ar_snoc->vregs[i].supply = ath10k_regulators[i]; 1821 1822 ret = devm_regulator_bulk_get(&pdev->dev, ar_snoc->num_vregs, 1823 ar_snoc->vregs); 1824 if (ret < 0) 1825 goto err_free_irq; 1826 1827 ar_snoc->num_clks = ARRAY_SIZE(ath10k_clocks); 1828 ar_snoc->clks = devm_kcalloc(&pdev->dev, ar_snoc->num_clks, 1829 sizeof(*ar_snoc->clks), GFP_KERNEL); 1830 if (!ar_snoc->clks) { 1831 ret = -ENOMEM; 1832 goto err_free_irq; 1833 } 1834 1835 for (i = 0; i < ar_snoc->num_clks; i++) 1836 ar_snoc->clks[i].id = ath10k_clocks[i]; 1837 1838 ret = devm_clk_bulk_get_optional(&pdev->dev, ar_snoc->num_clks, 1839 ar_snoc->clks); 1840 if (ret) 1841 goto err_free_irq; 1842 1843 ret = ath10k_setup_msa_resources(ar, msa_size); 1844 if (ret) { 1845 ath10k_warn(ar, "failed to setup msa resources: %d\n", ret); 1846 goto err_free_irq; 1847 } 1848 1849 ret = ath10k_fw_init(ar); 1850 if (ret) { 1851 ath10k_err(ar, "failed to initialize firmware: %d\n", ret); 1852 goto err_free_irq; 1853 } 1854 1855 ret = ath10k_qmi_init(ar, msa_size); 1856 if (ret) { 1857 ath10k_warn(ar, "failed to register wlfw qmi client: %d\n", ret); 1858 goto err_fw_deinit; 1859 } 1860 1861 ret = ath10k_modem_init(ar); 1862 if (ret) 1863 goto err_qmi_deinit; 1864 1865 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc probe\n"); 1866 1867 return 0; 1868 1869 err_qmi_deinit: 1870 ath10k_qmi_deinit(ar); 1871 1872 err_fw_deinit: 1873 ath10k_fw_deinit(ar); 1874 1875 err_free_irq: 1876 ath10k_snoc_free_irq(ar); 1877 1878 err_release_resource: 1879 ath10k_snoc_release_resource(ar); 1880 1881 err_core_destroy: 1882 ath10k_core_destroy(ar); 1883 1884 return ret; 1885 } 1886 1887 static int ath10k_snoc_free_resources(struct ath10k *ar) 1888 { 1889 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1890 1891 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc free resources\n"); 1892 1893 set_bit(ATH10K_SNOC_FLAG_UNREGISTERING, &ar_snoc->flags); 1894 1895 ath10k_core_unregister(ar); 1896 ath10k_fw_deinit(ar); 1897 ath10k_snoc_free_irq(ar); 1898 ath10k_snoc_release_resource(ar); 1899 ath10k_modem_deinit(ar); 1900 ath10k_qmi_deinit(ar); 1901 ath10k_core_destroy(ar); 1902 1903 return 0; 1904 } 1905 1906 static void ath10k_snoc_remove(struct platform_device *pdev) 1907 { 1908 struct ath10k *ar = platform_get_drvdata(pdev); 1909 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1910 1911 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc remove\n"); 1912 1913 reinit_completion(&ar->driver_recovery); 1914 1915 if (test_bit(ATH10K_SNOC_FLAG_RECOVERY, &ar_snoc->flags)) 1916 wait_for_completion_timeout(&ar->driver_recovery, 3 * HZ); 1917 1918 ath10k_snoc_free_resources(ar); 1919 } 1920 1921 static void ath10k_snoc_shutdown(struct platform_device *pdev) 1922 { 1923 struct ath10k *ar = platform_get_drvdata(pdev); 1924 1925 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc shutdown\n"); 1926 ath10k_snoc_free_resources(ar); 1927 } 1928 1929 static struct platform_driver ath10k_snoc_driver = { 1930 .probe = ath10k_snoc_probe, 1931 .remove = ath10k_snoc_remove, 1932 .shutdown = ath10k_snoc_shutdown, 1933 .driver = { 1934 .name = "ath10k_snoc", 1935 .of_match_table = ath10k_snoc_dt_match, 1936 }, 1937 }; 1938 module_platform_driver(ath10k_snoc_driver); 1939 1940 MODULE_AUTHOR("Qualcomm"); 1941 MODULE_LICENSE("Dual BSD/GPL"); 1942 MODULE_DESCRIPTION("Driver support for Atheros WCN3990 SNOC devices"); 1943