xref: /linux/drivers/net/wireless/ath/ath10k/sdio.h (revision bd628c1bed7902ec1f24ba0fe70758949146abbe)
1 /*
2  * Copyright (c) 2004-2011 Atheros Communications Inc.
3  * Copyright (c) 2011-2012 Qualcomm Atheros, Inc.
4  * Copyright (c) 2016-2017 Erik Stromdahl <erik.stromdahl@gmail.com>
5  *
6  * Permission to use, copy, modify, and/or distribute this software for any
7  * purpose with or without fee is hereby granted, provided that the above
8  * copyright notice and this permission notice appear in all copies.
9  *
10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17  */
18 
19 #ifndef _SDIO_H_
20 #define _SDIO_H_
21 
22 #define ATH10K_HIF_MBOX_BLOCK_SIZE              256
23 
24 #define QCA_MANUFACTURER_ID_BASE                GENMASK(11, 8)
25 #define QCA_MANUFACTURER_ID_AR6005_BASE         0x5
26 #define QCA_MANUFACTURER_ID_QCA9377_BASE        0x7
27 #define QCA_SDIO_ID_AR6005_BASE                 0x500
28 #define QCA_SDIO_ID_QCA9377_BASE                0x700
29 #define QCA_MANUFACTURER_ID_REV_MASK            0x00FF
30 #define QCA_MANUFACTURER_CODE                   0x271 /* Qualcomm/Atheros */
31 
32 #define ATH10K_SDIO_MAX_BUFFER_SIZE             4096 /*Unsure of this constant*/
33 
34 /* Mailbox address in SDIO address space */
35 #define ATH10K_HIF_MBOX_BASE_ADDR               0x1000
36 #define ATH10K_HIF_MBOX_WIDTH                   0x800
37 
38 #define ATH10K_HIF_MBOX_TOT_WIDTH \
39 	(ATH10K_HIF_MBOX_NUM_MAX * ATH10K_HIF_MBOX_WIDTH)
40 
41 #define ATH10K_HIF_MBOX0_EXT_BASE_ADDR          0x5000
42 #define ATH10K_HIF_MBOX0_EXT_WIDTH              (36 * 1024)
43 #define ATH10K_HIF_MBOX0_EXT_WIDTH_ROME_2_0     (56 * 1024)
44 #define ATH10K_HIF_MBOX1_EXT_WIDTH              (36 * 1024)
45 #define ATH10K_HIF_MBOX_DUMMY_SPACE_SIZE        (2 * 1024)
46 
47 #define ATH10K_HTC_MBOX_MAX_PAYLOAD_LENGTH \
48 	(ATH10K_SDIO_MAX_BUFFER_SIZE - sizeof(struct ath10k_htc_hdr))
49 
50 #define ATH10K_HIF_MBOX_NUM_MAX                 4
51 #define ATH10K_SDIO_BUS_REQUEST_MAX_NUM         64
52 
53 #define ATH10K_SDIO_HIF_COMMUNICATION_TIMEOUT_HZ (100 * HZ)
54 
55 /* HTC runs over mailbox 0 */
56 #define ATH10K_HTC_MAILBOX                      0
57 #define ATH10K_HTC_MAILBOX_MASK                 BIT(ATH10K_HTC_MAILBOX)
58 
59 /* GMBOX addresses */
60 #define ATH10K_HIF_GMBOX_BASE_ADDR              0x7000
61 #define ATH10K_HIF_GMBOX_WIDTH                  0x4000
62 
63 /* Modified versions of the sdio.h macros.
64  * The macros in sdio.h can't be used easily with the FIELD_{PREP|GET}
65  * macros in bitfield.h, so we define our own macros here.
66  */
67 #define ATH10K_SDIO_DRIVE_DTSX_MASK \
68 	(SDIO_DRIVE_DTSx_MASK << SDIO_DRIVE_DTSx_SHIFT)
69 
70 #define ATH10K_SDIO_DRIVE_DTSX_TYPE_B           0
71 #define ATH10K_SDIO_DRIVE_DTSX_TYPE_A           1
72 #define ATH10K_SDIO_DRIVE_DTSX_TYPE_C           2
73 #define ATH10K_SDIO_DRIVE_DTSX_TYPE_D           3
74 
75 /* SDIO CCCR register definitions */
76 #define CCCR_SDIO_IRQ_MODE_REG                  0xF0
77 #define CCCR_SDIO_IRQ_MODE_REG_SDIO3            0x16
78 
79 #define CCCR_SDIO_DRIVER_STRENGTH_ENABLE_ADDR   0xF2
80 
81 #define CCCR_SDIO_DRIVER_STRENGTH_ENABLE_A      0x02
82 #define CCCR_SDIO_DRIVER_STRENGTH_ENABLE_C      0x04
83 #define CCCR_SDIO_DRIVER_STRENGTH_ENABLE_D      0x08
84 
85 #define CCCR_SDIO_ASYNC_INT_DELAY_ADDRESS       0xF0
86 #define CCCR_SDIO_ASYNC_INT_DELAY_MASK          0xC0
87 
88 /* mode to enable special 4-bit interrupt assertion without clock */
89 #define SDIO_IRQ_MODE_ASYNC_4BIT_IRQ            BIT(0)
90 #define SDIO_IRQ_MODE_ASYNC_4BIT_IRQ_SDIO3      BIT(1)
91 
92 #define ATH10K_SDIO_TARGET_DEBUG_INTR_MASK      0x01
93 
94 /* The theoretical maximum number of RX messages that can be fetched
95  * from the mbox interrupt handler in one loop is derived in the following
96  * way:
97  *
98  * Let's assume that each packet in a bundle of the maximum bundle size
99  * (HTC_HOST_MAX_MSG_PER_RX_BUNDLE) has the HTC header bundle count set
100  * to the maximum value (HTC_HOST_MAX_MSG_PER_RX_BUNDLE).
101  *
102  * in this case the driver must allocate
103  * (HTC_HOST_MAX_MSG_PER_RX_BUNDLE * HTC_HOST_MAX_MSG_PER_RX_BUNDLE) skb's.
104  */
105 #define ATH10K_SDIO_MAX_RX_MSGS \
106 	(HTC_HOST_MAX_MSG_PER_RX_BUNDLE * HTC_HOST_MAX_MSG_PER_RX_BUNDLE)
107 
108 #define ATH10K_FIFO_TIMEOUT_AND_CHIP_CONTROL   0x00000868u
109 #define ATH10K_FIFO_TIMEOUT_AND_CHIP_CONTROL_DISABLE_SLEEP_OFF 0xFFFEFFFF
110 #define ATH10K_FIFO_TIMEOUT_AND_CHIP_CONTROL_DISABLE_SLEEP_ON 0x10000
111 
112 struct ath10k_sdio_bus_request {
113 	struct list_head list;
114 
115 	/* sdio address */
116 	u32 address;
117 
118 	struct sk_buff *skb;
119 	enum ath10k_htc_ep_id eid;
120 	int status;
121 	/* Specifies if the current request is an HTC message.
122 	 * If not, the eid is not applicable an the TX completion handler
123 	 * associated with the endpoint will not be invoked.
124 	 */
125 	bool htc_msg;
126 	/* Completion that (if set) will be invoked for non HTC requests
127 	 * (htc_msg == false) when the request has been processed.
128 	 */
129 	struct completion *comp;
130 };
131 
132 struct ath10k_sdio_rx_data {
133 	struct sk_buff *skb;
134 	size_t alloc_len;
135 	size_t act_len;
136 	enum ath10k_htc_ep_id eid;
137 	bool part_of_bundle;
138 	bool last_in_bundle;
139 	bool trailer_only;
140 	int status;
141 };
142 
143 struct ath10k_sdio_irq_proc_regs {
144 	u8 host_int_status;
145 	u8 cpu_int_status;
146 	u8 error_int_status;
147 	u8 counter_int_status;
148 	u8 mbox_frame;
149 	u8 rx_lookahead_valid;
150 	u8 host_int_status2;
151 	u8 gmbox_rx_avail;
152 	__le32 rx_lookahead[2];
153 	__le32 rx_gmbox_lookahead_alias[2];
154 };
155 
156 struct ath10k_sdio_irq_enable_regs {
157 	u8 int_status_en;
158 	u8 cpu_int_status_en;
159 	u8 err_int_status_en;
160 	u8 cntr_int_status_en;
161 };
162 
163 struct ath10k_sdio_irq_data {
164 	/* protects irq_proc_reg and irq_en_reg below.
165 	 * We use a mutex here and not a spinlock since we will have the
166 	 * mutex locked while calling the sdio_memcpy_ functions.
167 	 * These function require non atomic context, and hence, spinlocks
168 	 * can be held while calling these functions.
169 	 */
170 	struct mutex mtx;
171 	struct ath10k_sdio_irq_proc_regs *irq_proc_reg;
172 	struct ath10k_sdio_irq_enable_regs *irq_en_reg;
173 };
174 
175 struct ath10k_mbox_ext_info {
176 	u32 htc_ext_addr;
177 	u32 htc_ext_sz;
178 };
179 
180 struct ath10k_mbox_info {
181 	u32 htc_addr;
182 	struct ath10k_mbox_ext_info ext_info[2];
183 	u32 block_size;
184 	u32 block_mask;
185 	u32 gmbox_addr;
186 	u32 gmbox_sz;
187 };
188 
189 struct ath10k_sdio {
190 	struct sdio_func *func;
191 
192 	struct ath10k_mbox_info mbox_info;
193 	bool swap_mbox;
194 	u32 mbox_addr[ATH10K_HTC_EP_COUNT];
195 	u32 mbox_size[ATH10K_HTC_EP_COUNT];
196 
197 	/* available bus requests */
198 	struct ath10k_sdio_bus_request bus_req[ATH10K_SDIO_BUS_REQUEST_MAX_NUM];
199 	/* free list of bus requests */
200 	struct list_head bus_req_freeq;
201 	/* protects access to bus_req_freeq */
202 	spinlock_t lock;
203 
204 	struct ath10k_sdio_rx_data rx_pkts[ATH10K_SDIO_MAX_RX_MSGS];
205 	size_t n_rx_pkts;
206 
207 	struct ath10k *ar;
208 	struct ath10k_sdio_irq_data irq_data;
209 
210 	/* temporary buffer for BMI requests */
211 	u8 *bmi_buf;
212 
213 	bool is_disabled;
214 
215 	struct workqueue_struct *workqueue;
216 	struct work_struct wr_async_work;
217 	struct list_head wr_asyncq;
218 	/* protects access to wr_asyncq */
219 	spinlock_t wr_async_lock;
220 };
221 
222 static inline struct ath10k_sdio *ath10k_sdio_priv(struct ath10k *ar)
223 {
224 	return (struct ath10k_sdio *)ar->drv_priv;
225 }
226 
227 #endif
228