xref: /linux/drivers/net/wireless/ath/ath10k/pci.h (revision 55d0969c451159cff86949b38c39171cab962069)
1 /* SPDX-License-Identifier: ISC */
2 /*
3  * Copyright (c) 2005-2011 Atheros Communications Inc.
4  * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
5  * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
6  */
7 
8 #ifndef _PCI_H_
9 #define _PCI_H_
10 
11 #include <linux/interrupt.h>
12 #include <linux/mutex.h>
13 
14 #include "hw.h"
15 #include "ce.h"
16 #include "ahb.h"
17 
18 /*
19  * maximum number of bytes that can be
20  * handled atomically by DiagRead/DiagWrite
21  */
22 #define DIAG_TRANSFER_LIMIT 2048
23 
24 struct bmi_xfer {
25 	bool tx_done;
26 	bool rx_done;
27 	bool wait_for_resp;
28 	u32 resp_len;
29 };
30 
31 /*
32  * PCI-specific Target state
33  *
34  * NOTE: Structure is shared between Host software and Target firmware!
35  *
36  * Much of this may be of interest to the Host so
37  * HOST_INTEREST->hi_interconnect_state points here
38  * (and all members are 32-bit quantities in order to
39  * facilitate Host access). In particular, Host software is
40  * required to initialize pipe_cfg_addr and svc_to_pipe_map.
41  */
42 struct pcie_state {
43 	/* Pipe configuration Target address */
44 	/* NB: ce_pipe_config[CE_COUNT] */
45 	u32 pipe_cfg_addr;
46 
47 	/* Service to pipe map Target address */
48 	/* NB: service_to_pipe[PIPE_TO_CE_MAP_CN] */
49 	u32 svc_to_pipe_map;
50 
51 	/* number of MSI interrupts requested */
52 	u32 msi_requested;
53 
54 	/* number of MSI interrupts granted */
55 	u32 msi_granted;
56 
57 	/* Message Signalled Interrupt address */
58 	u32 msi_addr;
59 
60 	/* Base data */
61 	u32 msi_data;
62 
63 	/*
64 	 * Data for firmware interrupt;
65 	 * MSI data for other interrupts are
66 	 * in various SoC registers
67 	 */
68 	u32 msi_fw_intr_data;
69 
70 	/* PCIE_PWR_METHOD_* */
71 	u32 power_mgmt_method;
72 
73 	/* PCIE_CONFIG_FLAG_* */
74 	u32 config_flags;
75 };
76 
77 /* PCIE_CONFIG_FLAG definitions */
78 #define PCIE_CONFIG_FLAG_ENABLE_L1  0x0000001
79 
80 /* Per-pipe state. */
81 struct ath10k_pci_pipe {
82 	/* Handle of underlying Copy Engine */
83 	struct ath10k_ce_pipe *ce_hdl;
84 
85 	/* Our pipe number; facilitates use of pipe_info ptrs. */
86 	u8 pipe_num;
87 
88 	/* Convenience back pointer to hif_ce_state. */
89 	struct ath10k *hif_ce_state;
90 
91 	size_t buf_sz;
92 
93 	/* protects compl_free and num_send_allowed */
94 	spinlock_t pipe_lock;
95 };
96 
97 struct ath10k_pci_supp_chip {
98 	u32 dev_id;
99 	u32 rev_id;
100 };
101 
102 enum ath10k_pci_irq_mode {
103 	ATH10K_PCI_IRQ_AUTO = 0,
104 	ATH10K_PCI_IRQ_INTX = 1,
105 	ATH10K_PCI_IRQ_MSI = 2,
106 };
107 
108 struct ath10k_pci {
109 	struct pci_dev *pdev;
110 	struct device *dev;
111 	struct ath10k *ar;
112 	void __iomem *mem;
113 	size_t mem_len;
114 
115 	/* Operating interrupt mode */
116 	enum ath10k_pci_irq_mode oper_irq_mode;
117 
118 	struct ath10k_pci_pipe pipe_info[CE_COUNT_MAX];
119 
120 	/* Copy Engine used for Diagnostic Accesses */
121 	struct ath10k_ce_pipe *ce_diag;
122 	/* For protecting ce_diag */
123 	struct mutex ce_diag_mutex;
124 
125 	struct work_struct dump_work;
126 
127 	struct ath10k_ce ce;
128 	struct timer_list rx_post_retry;
129 
130 	/* Due to HW quirks it is recommended to disable ASPM during device
131 	 * bootup. To do that the original PCI-E Link Control is stored before
132 	 * device bootup is executed and re-programmed later.
133 	 */
134 	u16 link_ctl;
135 
136 	/* Protects ps_awake and ps_wake_refcount */
137 	spinlock_t ps_lock;
138 
139 	/* The device has a special powersave-oriented register. When device is
140 	 * considered asleep it drains less power and driver is forbidden from
141 	 * accessing most MMIO registers. If host were to access them without
142 	 * waking up the device might scribble over host memory or return
143 	 * 0xdeadbeef readouts.
144 	 */
145 	unsigned long ps_wake_refcount;
146 
147 	/* Waking up takes some time (up to 2ms in some cases) so it can be bad
148 	 * for latency. To mitigate this the device isn't immediately allowed
149 	 * to sleep after all references are undone - instead there's a grace
150 	 * period after which the powersave register is updated unless some
151 	 * activity to/from device happened in the meantime.
152 	 *
153 	 * Also see comments on ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC.
154 	 */
155 	struct timer_list ps_timer;
156 
157 	/* MMIO registers are used to communicate with the device. With
158 	 * intensive traffic accessing powersave register would be a bit
159 	 * wasteful overhead and would needlessly stall CPU. It is far more
160 	 * efficient to rely on a variable in RAM and update it only upon
161 	 * powersave register state changes.
162 	 */
163 	bool ps_awake;
164 
165 	/* pci power save, disable for QCA988X and QCA99X0.
166 	 * Writing 'false' to this variable avoids frequent locking
167 	 * on MMIO read/write.
168 	 */
169 	bool pci_ps;
170 
171 	/* Chip specific pci reset routine used to do a safe reset */
172 	int (*pci_soft_reset)(struct ath10k *ar);
173 
174 	/* Chip specific pci full reset function */
175 	int (*pci_hard_reset)(struct ath10k *ar);
176 
177 	/* chip specific methods for converting target CPU virtual address
178 	 * space to CE address space
179 	 */
180 	u32 (*targ_cpu_to_ce_addr)(struct ath10k *ar, u32 addr);
181 
182 	struct ce_attr *attr;
183 	struct ce_pipe_config *pipe_config;
184 	struct ce_service_to_pipe *serv_to_pipe;
185 
186 	/* Keep this entry in the last, memory for struct ath10k_ahb is
187 	 * allocated (ahb support enabled case) in the continuation of
188 	 * this struct.
189 	 */
190 	struct ath10k_ahb ahb[];
191 
192 };
193 
194 static inline struct ath10k_pci *ath10k_pci_priv(struct ath10k *ar)
195 {
196 	return (struct ath10k_pci *)ar->drv_priv;
197 }
198 
199 #define ATH10K_PCI_RX_POST_RETRY_MS 50
200 #define ATH_PCI_RESET_WAIT_MAX 10 /* ms */
201 #define PCIE_WAKE_TIMEOUT 30000	/* 30ms */
202 #define PCIE_WAKE_LATE_US 10000	/* 10ms */
203 
204 #define BAR_NUM 0
205 
206 #define CDC_WAR_MAGIC_STR   0xceef0000
207 #define CDC_WAR_DATA_CE     4
208 
209 /* Wait up to this many Ms for a Diagnostic Access CE operation to complete */
210 #define DIAG_ACCESS_CE_TIMEOUT_US 10000 /* 10 ms */
211 #define DIAG_ACCESS_CE_WAIT_US	50
212 
213 void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value);
214 void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val);
215 void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val);
216 
217 u32 ath10k_pci_read32(struct ath10k *ar, u32 offset);
218 u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr);
219 u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr);
220 
221 int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
222 			 struct ath10k_hif_sg_item *items, int n_items);
223 int ath10k_pci_hif_diag_read(struct ath10k *ar, u32 address, void *buf,
224 			     size_t buf_len);
225 int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address,
226 			      const void *data, int nbytes);
227 int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar, void *req, u32 req_len,
228 				    void *resp, u32 *resp_len);
229 int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar, u16 service_id,
230 				       u8 *ul_pipe, u8 *dl_pipe);
231 void ath10k_pci_hif_get_default_pipe(struct ath10k *ar, u8 *ul_pipe,
232 				     u8 *dl_pipe);
233 void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe,
234 					int force);
235 u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe);
236 void ath10k_pci_hif_power_down(struct ath10k *ar);
237 int ath10k_pci_alloc_pipes(struct ath10k *ar);
238 void ath10k_pci_free_pipes(struct ath10k *ar);
239 void ath10k_pci_rx_replenish_retry(struct timer_list *t);
240 void ath10k_pci_ce_deinit(struct ath10k *ar);
241 void ath10k_pci_init_napi(struct ath10k *ar);
242 int ath10k_pci_init_pipes(struct ath10k *ar);
243 int ath10k_pci_init_config(struct ath10k *ar);
244 void ath10k_pci_rx_post(struct ath10k *ar);
245 void ath10k_pci_flush(struct ath10k *ar);
246 void ath10k_pci_enable_intx_irq(struct ath10k *ar);
247 bool ath10k_pci_irq_pending(struct ath10k *ar);
248 void ath10k_pci_disable_and_clear_intx_irq(struct ath10k *ar);
249 void ath10k_pci_irq_msi_fw_mask(struct ath10k *ar);
250 int ath10k_pci_wait_for_target_init(struct ath10k *ar);
251 int ath10k_pci_setup_resource(struct ath10k *ar);
252 void ath10k_pci_release_resource(struct ath10k *ar);
253 
254 /* QCA6174 is known to have Tx/Rx issues when SOC_WAKE register is poked too
255  * frequently. To avoid this put SoC to sleep after a very conservative grace
256  * period. Adjust with great care.
257  */
258 #define ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC 60
259 
260 #endif /* _PCI_H_ */
261