1 /* 2 * Copyright (c) 2005-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #include <linux/pci.h> 19 #include <linux/module.h> 20 #include <linux/interrupt.h> 21 #include <linux/spinlock.h> 22 #include <linux/bitops.h> 23 24 #include "core.h" 25 #include "debug.h" 26 #include "coredump.h" 27 28 #include "targaddrs.h" 29 #include "bmi.h" 30 31 #include "hif.h" 32 #include "htc.h" 33 34 #include "ce.h" 35 #include "pci.h" 36 37 enum ath10k_pci_reset_mode { 38 ATH10K_PCI_RESET_AUTO = 0, 39 ATH10K_PCI_RESET_WARM_ONLY = 1, 40 }; 41 42 static unsigned int ath10k_pci_irq_mode = ATH10K_PCI_IRQ_AUTO; 43 static unsigned int ath10k_pci_reset_mode = ATH10K_PCI_RESET_AUTO; 44 45 module_param_named(irq_mode, ath10k_pci_irq_mode, uint, 0644); 46 MODULE_PARM_DESC(irq_mode, "0: auto, 1: legacy, 2: msi (default: 0)"); 47 48 module_param_named(reset_mode, ath10k_pci_reset_mode, uint, 0644); 49 MODULE_PARM_DESC(reset_mode, "0: auto, 1: warm only (default: 0)"); 50 51 /* how long wait to wait for target to initialise, in ms */ 52 #define ATH10K_PCI_TARGET_WAIT 3000 53 #define ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS 3 54 55 /* Maximum number of bytes that can be handled atomically by 56 * diag read and write. 57 */ 58 #define ATH10K_DIAG_TRANSFER_LIMIT 0x5000 59 60 #define QCA99X0_PCIE_BAR0_START_REG 0x81030 61 #define QCA99X0_CPU_MEM_ADDR_REG 0x4d00c 62 #define QCA99X0_CPU_MEM_DATA_REG 0x4d010 63 64 static const struct pci_device_id ath10k_pci_id_table[] = { 65 /* PCI-E QCA988X V2 (Ubiquiti branded) */ 66 { PCI_VDEVICE(UBIQUITI, QCA988X_2_0_DEVICE_ID_UBNT) }, 67 68 { PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */ 69 { PCI_VDEVICE(ATHEROS, QCA6164_2_1_DEVICE_ID) }, /* PCI-E QCA6164 V2.1 */ 70 { PCI_VDEVICE(ATHEROS, QCA6174_2_1_DEVICE_ID) }, /* PCI-E QCA6174 V2.1 */ 71 { PCI_VDEVICE(ATHEROS, QCA99X0_2_0_DEVICE_ID) }, /* PCI-E QCA99X0 V2 */ 72 { PCI_VDEVICE(ATHEROS, QCA9888_2_0_DEVICE_ID) }, /* PCI-E QCA9888 V2 */ 73 { PCI_VDEVICE(ATHEROS, QCA9984_1_0_DEVICE_ID) }, /* PCI-E QCA9984 V1 */ 74 { PCI_VDEVICE(ATHEROS, QCA9377_1_0_DEVICE_ID) }, /* PCI-E QCA9377 V1 */ 75 { PCI_VDEVICE(ATHEROS, QCA9887_1_0_DEVICE_ID) }, /* PCI-E QCA9887 */ 76 {0} 77 }; 78 79 static const struct ath10k_pci_supp_chip ath10k_pci_supp_chips[] = { 80 /* QCA988X pre 2.0 chips are not supported because they need some nasty 81 * hacks. ath10k doesn't have them and these devices crash horribly 82 * because of that. 83 */ 84 { QCA988X_2_0_DEVICE_ID_UBNT, QCA988X_HW_2_0_CHIP_ID_REV }, 85 { QCA988X_2_0_DEVICE_ID, QCA988X_HW_2_0_CHIP_ID_REV }, 86 87 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV }, 88 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV }, 89 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV }, 90 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV }, 91 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV }, 92 93 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV }, 94 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV }, 95 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV }, 96 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV }, 97 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV }, 98 99 { QCA99X0_2_0_DEVICE_ID, QCA99X0_HW_2_0_CHIP_ID_REV }, 100 101 { QCA9984_1_0_DEVICE_ID, QCA9984_HW_1_0_CHIP_ID_REV }, 102 103 { QCA9888_2_0_DEVICE_ID, QCA9888_HW_2_0_CHIP_ID_REV }, 104 105 { QCA9377_1_0_DEVICE_ID, QCA9377_HW_1_0_CHIP_ID_REV }, 106 { QCA9377_1_0_DEVICE_ID, QCA9377_HW_1_1_CHIP_ID_REV }, 107 108 { QCA9887_1_0_DEVICE_ID, QCA9887_HW_1_0_CHIP_ID_REV }, 109 }; 110 111 static void ath10k_pci_buffer_cleanup(struct ath10k *ar); 112 static int ath10k_pci_cold_reset(struct ath10k *ar); 113 static int ath10k_pci_safe_chip_reset(struct ath10k *ar); 114 static int ath10k_pci_init_irq(struct ath10k *ar); 115 static int ath10k_pci_deinit_irq(struct ath10k *ar); 116 static int ath10k_pci_request_irq(struct ath10k *ar); 117 static void ath10k_pci_free_irq(struct ath10k *ar); 118 static int ath10k_pci_bmi_wait(struct ath10k *ar, 119 struct ath10k_ce_pipe *tx_pipe, 120 struct ath10k_ce_pipe *rx_pipe, 121 struct bmi_xfer *xfer); 122 static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar); 123 static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe *ce_state); 124 static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state); 125 static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state); 126 static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe *ce_state); 127 static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state); 128 static void ath10k_pci_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state); 129 130 static struct ce_attr host_ce_config_wlan[] = { 131 /* CE0: host->target HTC control and raw streams */ 132 { 133 .flags = CE_ATTR_FLAGS, 134 .src_nentries = 16, 135 .src_sz_max = 256, 136 .dest_nentries = 0, 137 .send_cb = ath10k_pci_htc_tx_cb, 138 }, 139 140 /* CE1: target->host HTT + HTC control */ 141 { 142 .flags = CE_ATTR_FLAGS, 143 .src_nentries = 0, 144 .src_sz_max = 2048, 145 .dest_nentries = 512, 146 .recv_cb = ath10k_pci_htt_htc_rx_cb, 147 }, 148 149 /* CE2: target->host WMI */ 150 { 151 .flags = CE_ATTR_FLAGS, 152 .src_nentries = 0, 153 .src_sz_max = 2048, 154 .dest_nentries = 128, 155 .recv_cb = ath10k_pci_htc_rx_cb, 156 }, 157 158 /* CE3: host->target WMI */ 159 { 160 .flags = CE_ATTR_FLAGS, 161 .src_nentries = 32, 162 .src_sz_max = 2048, 163 .dest_nentries = 0, 164 .send_cb = ath10k_pci_htc_tx_cb, 165 }, 166 167 /* CE4: host->target HTT */ 168 { 169 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, 170 .src_nentries = CE_HTT_H2T_MSG_SRC_NENTRIES, 171 .src_sz_max = 256, 172 .dest_nentries = 0, 173 .send_cb = ath10k_pci_htt_tx_cb, 174 }, 175 176 /* CE5: target->host HTT (HIF->HTT) */ 177 { 178 .flags = CE_ATTR_FLAGS, 179 .src_nentries = 0, 180 .src_sz_max = 512, 181 .dest_nentries = 512, 182 .recv_cb = ath10k_pci_htt_rx_cb, 183 }, 184 185 /* CE6: target autonomous hif_memcpy */ 186 { 187 .flags = CE_ATTR_FLAGS, 188 .src_nentries = 0, 189 .src_sz_max = 0, 190 .dest_nentries = 0, 191 }, 192 193 /* CE7: ce_diag, the Diagnostic Window */ 194 { 195 .flags = CE_ATTR_FLAGS | CE_ATTR_POLL, 196 .src_nentries = 2, 197 .src_sz_max = DIAG_TRANSFER_LIMIT, 198 .dest_nentries = 2, 199 }, 200 201 /* CE8: target->host pktlog */ 202 { 203 .flags = CE_ATTR_FLAGS, 204 .src_nentries = 0, 205 .src_sz_max = 2048, 206 .dest_nentries = 128, 207 .recv_cb = ath10k_pci_pktlog_rx_cb, 208 }, 209 210 /* CE9 target autonomous qcache memcpy */ 211 { 212 .flags = CE_ATTR_FLAGS, 213 .src_nentries = 0, 214 .src_sz_max = 0, 215 .dest_nentries = 0, 216 }, 217 218 /* CE10: target autonomous hif memcpy */ 219 { 220 .flags = CE_ATTR_FLAGS, 221 .src_nentries = 0, 222 .src_sz_max = 0, 223 .dest_nentries = 0, 224 }, 225 226 /* CE11: target autonomous hif memcpy */ 227 { 228 .flags = CE_ATTR_FLAGS, 229 .src_nentries = 0, 230 .src_sz_max = 0, 231 .dest_nentries = 0, 232 }, 233 }; 234 235 /* Target firmware's Copy Engine configuration. */ 236 static struct ce_pipe_config target_ce_config_wlan[] = { 237 /* CE0: host->target HTC control and raw streams */ 238 { 239 .pipenum = __cpu_to_le32(0), 240 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 241 .nentries = __cpu_to_le32(32), 242 .nbytes_max = __cpu_to_le32(256), 243 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 244 .reserved = __cpu_to_le32(0), 245 }, 246 247 /* CE1: target->host HTT + HTC control */ 248 { 249 .pipenum = __cpu_to_le32(1), 250 .pipedir = __cpu_to_le32(PIPEDIR_IN), 251 .nentries = __cpu_to_le32(32), 252 .nbytes_max = __cpu_to_le32(2048), 253 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 254 .reserved = __cpu_to_le32(0), 255 }, 256 257 /* CE2: target->host WMI */ 258 { 259 .pipenum = __cpu_to_le32(2), 260 .pipedir = __cpu_to_le32(PIPEDIR_IN), 261 .nentries = __cpu_to_le32(64), 262 .nbytes_max = __cpu_to_le32(2048), 263 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 264 .reserved = __cpu_to_le32(0), 265 }, 266 267 /* CE3: host->target WMI */ 268 { 269 .pipenum = __cpu_to_le32(3), 270 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 271 .nentries = __cpu_to_le32(32), 272 .nbytes_max = __cpu_to_le32(2048), 273 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 274 .reserved = __cpu_to_le32(0), 275 }, 276 277 /* CE4: host->target HTT */ 278 { 279 .pipenum = __cpu_to_le32(4), 280 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 281 .nentries = __cpu_to_le32(256), 282 .nbytes_max = __cpu_to_le32(256), 283 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 284 .reserved = __cpu_to_le32(0), 285 }, 286 287 /* NB: 50% of src nentries, since tx has 2 frags */ 288 289 /* CE5: target->host HTT (HIF->HTT) */ 290 { 291 .pipenum = __cpu_to_le32(5), 292 .pipedir = __cpu_to_le32(PIPEDIR_IN), 293 .nentries = __cpu_to_le32(32), 294 .nbytes_max = __cpu_to_le32(512), 295 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 296 .reserved = __cpu_to_le32(0), 297 }, 298 299 /* CE6: Reserved for target autonomous hif_memcpy */ 300 { 301 .pipenum = __cpu_to_le32(6), 302 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 303 .nentries = __cpu_to_le32(32), 304 .nbytes_max = __cpu_to_le32(4096), 305 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 306 .reserved = __cpu_to_le32(0), 307 }, 308 309 /* CE7 used only by Host */ 310 { 311 .pipenum = __cpu_to_le32(7), 312 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 313 .nentries = __cpu_to_le32(0), 314 .nbytes_max = __cpu_to_le32(0), 315 .flags = __cpu_to_le32(0), 316 .reserved = __cpu_to_le32(0), 317 }, 318 319 /* CE8 target->host packtlog */ 320 { 321 .pipenum = __cpu_to_le32(8), 322 .pipedir = __cpu_to_le32(PIPEDIR_IN), 323 .nentries = __cpu_to_le32(64), 324 .nbytes_max = __cpu_to_le32(2048), 325 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 326 .reserved = __cpu_to_le32(0), 327 }, 328 329 /* CE9 target autonomous qcache memcpy */ 330 { 331 .pipenum = __cpu_to_le32(9), 332 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 333 .nentries = __cpu_to_le32(32), 334 .nbytes_max = __cpu_to_le32(2048), 335 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 336 .reserved = __cpu_to_le32(0), 337 }, 338 339 /* It not necessary to send target wlan configuration for CE10 & CE11 340 * as these CEs are not actively used in target. 341 */ 342 }; 343 344 /* 345 * Map from service/endpoint to Copy Engine. 346 * This table is derived from the CE_PCI TABLE, above. 347 * It is passed to the Target at startup for use by firmware. 348 */ 349 static struct service_to_pipe target_service_to_ce_map_wlan[] = { 350 { 351 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO), 352 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 353 __cpu_to_le32(3), 354 }, 355 { 356 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO), 357 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 358 __cpu_to_le32(2), 359 }, 360 { 361 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK), 362 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 363 __cpu_to_le32(3), 364 }, 365 { 366 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK), 367 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 368 __cpu_to_le32(2), 369 }, 370 { 371 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE), 372 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 373 __cpu_to_le32(3), 374 }, 375 { 376 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE), 377 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 378 __cpu_to_le32(2), 379 }, 380 { 381 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI), 382 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 383 __cpu_to_le32(3), 384 }, 385 { 386 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI), 387 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 388 __cpu_to_le32(2), 389 }, 390 { 391 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL), 392 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 393 __cpu_to_le32(3), 394 }, 395 { 396 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL), 397 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 398 __cpu_to_le32(2), 399 }, 400 { 401 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL), 402 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 403 __cpu_to_le32(0), 404 }, 405 { 406 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL), 407 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 408 __cpu_to_le32(1), 409 }, 410 { /* not used */ 411 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS), 412 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 413 __cpu_to_le32(0), 414 }, 415 { /* not used */ 416 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS), 417 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 418 __cpu_to_le32(1), 419 }, 420 { 421 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG), 422 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 423 __cpu_to_le32(4), 424 }, 425 { 426 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG), 427 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 428 __cpu_to_le32(5), 429 }, 430 431 /* (Additions here) */ 432 433 { /* must be last */ 434 __cpu_to_le32(0), 435 __cpu_to_le32(0), 436 __cpu_to_le32(0), 437 }, 438 }; 439 440 static bool ath10k_pci_is_awake(struct ath10k *ar) 441 { 442 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 443 u32 val = ioread32(ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + 444 RTC_STATE_ADDRESS); 445 446 return RTC_STATE_V_GET(val) == RTC_STATE_V_ON; 447 } 448 449 static void __ath10k_pci_wake(struct ath10k *ar) 450 { 451 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 452 453 lockdep_assert_held(&ar_pci->ps_lock); 454 455 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake reg refcount %lu awake %d\n", 456 ar_pci->ps_wake_refcount, ar_pci->ps_awake); 457 458 iowrite32(PCIE_SOC_WAKE_V_MASK, 459 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + 460 PCIE_SOC_WAKE_ADDRESS); 461 } 462 463 static void __ath10k_pci_sleep(struct ath10k *ar) 464 { 465 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 466 467 lockdep_assert_held(&ar_pci->ps_lock); 468 469 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep reg refcount %lu awake %d\n", 470 ar_pci->ps_wake_refcount, ar_pci->ps_awake); 471 472 iowrite32(PCIE_SOC_WAKE_RESET, 473 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + 474 PCIE_SOC_WAKE_ADDRESS); 475 ar_pci->ps_awake = false; 476 } 477 478 static int ath10k_pci_wake_wait(struct ath10k *ar) 479 { 480 int tot_delay = 0; 481 int curr_delay = 5; 482 483 while (tot_delay < PCIE_WAKE_TIMEOUT) { 484 if (ath10k_pci_is_awake(ar)) { 485 if (tot_delay > PCIE_WAKE_LATE_US) 486 ath10k_warn(ar, "device wakeup took %d ms which is unusually long, otherwise it works normally.\n", 487 tot_delay / 1000); 488 return 0; 489 } 490 491 udelay(curr_delay); 492 tot_delay += curr_delay; 493 494 if (curr_delay < 50) 495 curr_delay += 5; 496 } 497 498 return -ETIMEDOUT; 499 } 500 501 static int ath10k_pci_force_wake(struct ath10k *ar) 502 { 503 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 504 unsigned long flags; 505 int ret = 0; 506 507 if (ar_pci->pci_ps) 508 return ret; 509 510 spin_lock_irqsave(&ar_pci->ps_lock, flags); 511 512 if (!ar_pci->ps_awake) { 513 iowrite32(PCIE_SOC_WAKE_V_MASK, 514 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + 515 PCIE_SOC_WAKE_ADDRESS); 516 517 ret = ath10k_pci_wake_wait(ar); 518 if (ret == 0) 519 ar_pci->ps_awake = true; 520 } 521 522 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 523 524 return ret; 525 } 526 527 static void ath10k_pci_force_sleep(struct ath10k *ar) 528 { 529 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 530 unsigned long flags; 531 532 spin_lock_irqsave(&ar_pci->ps_lock, flags); 533 534 iowrite32(PCIE_SOC_WAKE_RESET, 535 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + 536 PCIE_SOC_WAKE_ADDRESS); 537 ar_pci->ps_awake = false; 538 539 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 540 } 541 542 static int ath10k_pci_wake(struct ath10k *ar) 543 { 544 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 545 unsigned long flags; 546 int ret = 0; 547 548 if (ar_pci->pci_ps == 0) 549 return ret; 550 551 spin_lock_irqsave(&ar_pci->ps_lock, flags); 552 553 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake refcount %lu awake %d\n", 554 ar_pci->ps_wake_refcount, ar_pci->ps_awake); 555 556 /* This function can be called very frequently. To avoid excessive 557 * CPU stalls for MMIO reads use a cache var to hold the device state. 558 */ 559 if (!ar_pci->ps_awake) { 560 __ath10k_pci_wake(ar); 561 562 ret = ath10k_pci_wake_wait(ar); 563 if (ret == 0) 564 ar_pci->ps_awake = true; 565 } 566 567 if (ret == 0) { 568 ar_pci->ps_wake_refcount++; 569 WARN_ON(ar_pci->ps_wake_refcount == 0); 570 } 571 572 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 573 574 return ret; 575 } 576 577 static void ath10k_pci_sleep(struct ath10k *ar) 578 { 579 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 580 unsigned long flags; 581 582 if (ar_pci->pci_ps == 0) 583 return; 584 585 spin_lock_irqsave(&ar_pci->ps_lock, flags); 586 587 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep refcount %lu awake %d\n", 588 ar_pci->ps_wake_refcount, ar_pci->ps_awake); 589 590 if (WARN_ON(ar_pci->ps_wake_refcount == 0)) 591 goto skip; 592 593 ar_pci->ps_wake_refcount--; 594 595 mod_timer(&ar_pci->ps_timer, jiffies + 596 msecs_to_jiffies(ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC)); 597 598 skip: 599 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 600 } 601 602 static void ath10k_pci_ps_timer(struct timer_list *t) 603 { 604 struct ath10k_pci *ar_pci = from_timer(ar_pci, t, ps_timer); 605 struct ath10k *ar = ar_pci->ar; 606 unsigned long flags; 607 608 spin_lock_irqsave(&ar_pci->ps_lock, flags); 609 610 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps timer refcount %lu awake %d\n", 611 ar_pci->ps_wake_refcount, ar_pci->ps_awake); 612 613 if (ar_pci->ps_wake_refcount > 0) 614 goto skip; 615 616 __ath10k_pci_sleep(ar); 617 618 skip: 619 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 620 } 621 622 static void ath10k_pci_sleep_sync(struct ath10k *ar) 623 { 624 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 625 unsigned long flags; 626 627 if (ar_pci->pci_ps == 0) { 628 ath10k_pci_force_sleep(ar); 629 return; 630 } 631 632 del_timer_sync(&ar_pci->ps_timer); 633 634 spin_lock_irqsave(&ar_pci->ps_lock, flags); 635 WARN_ON(ar_pci->ps_wake_refcount > 0); 636 __ath10k_pci_sleep(ar); 637 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 638 } 639 640 static void ath10k_bus_pci_write32(struct ath10k *ar, u32 offset, u32 value) 641 { 642 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 643 int ret; 644 645 if (unlikely(offset + sizeof(value) > ar_pci->mem_len)) { 646 ath10k_warn(ar, "refusing to write mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n", 647 offset, offset + sizeof(value), ar_pci->mem_len); 648 return; 649 } 650 651 ret = ath10k_pci_wake(ar); 652 if (ret) { 653 ath10k_warn(ar, "failed to wake target for write32 of 0x%08x at 0x%08x: %d\n", 654 value, offset, ret); 655 return; 656 } 657 658 iowrite32(value, ar_pci->mem + offset); 659 ath10k_pci_sleep(ar); 660 } 661 662 static u32 ath10k_bus_pci_read32(struct ath10k *ar, u32 offset) 663 { 664 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 665 u32 val; 666 int ret; 667 668 if (unlikely(offset + sizeof(val) > ar_pci->mem_len)) { 669 ath10k_warn(ar, "refusing to read mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n", 670 offset, offset + sizeof(val), ar_pci->mem_len); 671 return 0; 672 } 673 674 ret = ath10k_pci_wake(ar); 675 if (ret) { 676 ath10k_warn(ar, "failed to wake target for read32 at 0x%08x: %d\n", 677 offset, ret); 678 return 0xffffffff; 679 } 680 681 val = ioread32(ar_pci->mem + offset); 682 ath10k_pci_sleep(ar); 683 684 return val; 685 } 686 687 inline void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value) 688 { 689 struct ath10k_ce *ce = ath10k_ce_priv(ar); 690 691 ce->bus_ops->write32(ar, offset, value); 692 } 693 694 inline u32 ath10k_pci_read32(struct ath10k *ar, u32 offset) 695 { 696 struct ath10k_ce *ce = ath10k_ce_priv(ar); 697 698 return ce->bus_ops->read32(ar, offset); 699 } 700 701 u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr) 702 { 703 return ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + addr); 704 } 705 706 void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val) 707 { 708 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + addr, val); 709 } 710 711 u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr) 712 { 713 return ath10k_pci_read32(ar, PCIE_LOCAL_BASE_ADDRESS + addr); 714 } 715 716 void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val) 717 { 718 ath10k_pci_write32(ar, PCIE_LOCAL_BASE_ADDRESS + addr, val); 719 } 720 721 bool ath10k_pci_irq_pending(struct ath10k *ar) 722 { 723 u32 cause; 724 725 /* Check if the shared legacy irq is for us */ 726 cause = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 727 PCIE_INTR_CAUSE_ADDRESS); 728 if (cause & (PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL)) 729 return true; 730 731 return false; 732 } 733 734 void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k *ar) 735 { 736 /* IMPORTANT: INTR_CLR register has to be set after 737 * INTR_ENABLE is set to 0, otherwise interrupt can not be 738 * really cleared. 739 */ 740 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS, 741 0); 742 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_CLR_ADDRESS, 743 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); 744 745 /* IMPORTANT: this extra read transaction is required to 746 * flush the posted write buffer. 747 */ 748 (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 749 PCIE_INTR_ENABLE_ADDRESS); 750 } 751 752 void ath10k_pci_enable_legacy_irq(struct ath10k *ar) 753 { 754 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + 755 PCIE_INTR_ENABLE_ADDRESS, 756 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); 757 758 /* IMPORTANT: this extra read transaction is required to 759 * flush the posted write buffer. 760 */ 761 (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 762 PCIE_INTR_ENABLE_ADDRESS); 763 } 764 765 static inline const char *ath10k_pci_get_irq_method(struct ath10k *ar) 766 { 767 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 768 769 if (ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_MSI) 770 return "msi"; 771 772 return "legacy"; 773 } 774 775 static int __ath10k_pci_rx_post_buf(struct ath10k_pci_pipe *pipe) 776 { 777 struct ath10k *ar = pipe->hif_ce_state; 778 struct ath10k_ce *ce = ath10k_ce_priv(ar); 779 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl; 780 struct sk_buff *skb; 781 dma_addr_t paddr; 782 int ret; 783 784 skb = dev_alloc_skb(pipe->buf_sz); 785 if (!skb) 786 return -ENOMEM; 787 788 WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb"); 789 790 paddr = dma_map_single(ar->dev, skb->data, 791 skb->len + skb_tailroom(skb), 792 DMA_FROM_DEVICE); 793 if (unlikely(dma_mapping_error(ar->dev, paddr))) { 794 ath10k_warn(ar, "failed to dma map pci rx buf\n"); 795 dev_kfree_skb_any(skb); 796 return -EIO; 797 } 798 799 ATH10K_SKB_RXCB(skb)->paddr = paddr; 800 801 spin_lock_bh(&ce->ce_lock); 802 ret = ce_pipe->ops->ce_rx_post_buf(ce_pipe, skb, paddr); 803 spin_unlock_bh(&ce->ce_lock); 804 if (ret) { 805 dma_unmap_single(ar->dev, paddr, skb->len + skb_tailroom(skb), 806 DMA_FROM_DEVICE); 807 dev_kfree_skb_any(skb); 808 return ret; 809 } 810 811 return 0; 812 } 813 814 static void ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe *pipe) 815 { 816 struct ath10k *ar = pipe->hif_ce_state; 817 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 818 struct ath10k_ce *ce = ath10k_ce_priv(ar); 819 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl; 820 int ret, num; 821 822 if (pipe->buf_sz == 0) 823 return; 824 825 if (!ce_pipe->dest_ring) 826 return; 827 828 spin_lock_bh(&ce->ce_lock); 829 num = __ath10k_ce_rx_num_free_bufs(ce_pipe); 830 spin_unlock_bh(&ce->ce_lock); 831 832 while (num >= 0) { 833 ret = __ath10k_pci_rx_post_buf(pipe); 834 if (ret) { 835 if (ret == -ENOSPC) 836 break; 837 ath10k_warn(ar, "failed to post pci rx buf: %d\n", ret); 838 mod_timer(&ar_pci->rx_post_retry, jiffies + 839 ATH10K_PCI_RX_POST_RETRY_MS); 840 break; 841 } 842 num--; 843 } 844 } 845 846 void ath10k_pci_rx_post(struct ath10k *ar) 847 { 848 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 849 int i; 850 851 for (i = 0; i < CE_COUNT; i++) 852 ath10k_pci_rx_post_pipe(&ar_pci->pipe_info[i]); 853 } 854 855 void ath10k_pci_rx_replenish_retry(struct timer_list *t) 856 { 857 struct ath10k_pci *ar_pci = from_timer(ar_pci, t, rx_post_retry); 858 struct ath10k *ar = ar_pci->ar; 859 860 ath10k_pci_rx_post(ar); 861 } 862 863 static u32 ath10k_pci_qca988x_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr) 864 { 865 u32 val = 0, region = addr & 0xfffff; 866 867 val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS) 868 & 0x7ff) << 21; 869 val |= 0x100000 | region; 870 return val; 871 } 872 873 /* Refactor from ath10k_pci_qca988x_targ_cpu_to_ce_addr. 874 * Support to access target space below 1M for qca6174 and qca9377. 875 * If target space is below 1M, the bit[20] of converted CE addr is 0. 876 * Otherwise bit[20] of converted CE addr is 1. 877 */ 878 static u32 ath10k_pci_qca6174_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr) 879 { 880 u32 val = 0, region = addr & 0xfffff; 881 882 val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS) 883 & 0x7ff) << 21; 884 val |= ((addr >= 0x100000) ? 0x100000 : 0) | region; 885 return val; 886 } 887 888 static u32 ath10k_pci_qca99x0_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr) 889 { 890 u32 val = 0, region = addr & 0xfffff; 891 892 val = ath10k_pci_read32(ar, PCIE_BAR_REG_ADDRESS); 893 val |= 0x100000 | region; 894 return val; 895 } 896 897 static u32 ath10k_pci_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr) 898 { 899 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 900 901 if (WARN_ON_ONCE(!ar_pci->targ_cpu_to_ce_addr)) 902 return -ENOTSUPP; 903 904 return ar_pci->targ_cpu_to_ce_addr(ar, addr); 905 } 906 907 /* 908 * Diagnostic read/write access is provided for startup/config/debug usage. 909 * Caller must guarantee proper alignment, when applicable, and single user 910 * at any moment. 911 */ 912 static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data, 913 int nbytes) 914 { 915 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 916 struct ath10k_ce *ce = ath10k_ce_priv(ar); 917 int ret = 0; 918 u32 *buf; 919 unsigned int completed_nbytes, alloc_nbytes, remaining_bytes; 920 struct ath10k_ce_pipe *ce_diag; 921 /* Host buffer address in CE space */ 922 u32 ce_data; 923 dma_addr_t ce_data_base = 0; 924 void *data_buf = NULL; 925 int i; 926 927 spin_lock_bh(&ce->ce_lock); 928 929 ce_diag = ar_pci->ce_diag; 930 931 /* 932 * Allocate a temporary bounce buffer to hold caller's data 933 * to be DMA'ed from Target. This guarantees 934 * 1) 4-byte alignment 935 * 2) Buffer in DMA-able space 936 */ 937 alloc_nbytes = min_t(unsigned int, nbytes, DIAG_TRANSFER_LIMIT); 938 939 data_buf = (unsigned char *)dma_zalloc_coherent(ar->dev, 940 alloc_nbytes, 941 &ce_data_base, 942 GFP_ATOMIC); 943 944 if (!data_buf) { 945 ret = -ENOMEM; 946 goto done; 947 } 948 949 /* The address supplied by the caller is in the 950 * Target CPU virtual address space. 951 * 952 * In order to use this address with the diagnostic CE, 953 * convert it from Target CPU virtual address space 954 * to CE address space 955 */ 956 address = ath10k_pci_targ_cpu_to_ce_addr(ar, address); 957 958 remaining_bytes = nbytes; 959 ce_data = ce_data_base; 960 while (remaining_bytes) { 961 nbytes = min_t(unsigned int, remaining_bytes, 962 DIAG_TRANSFER_LIMIT); 963 964 ret = ce_diag->ops->ce_rx_post_buf(ce_diag, &ce_data, ce_data); 965 if (ret != 0) 966 goto done; 967 968 /* Request CE to send from Target(!) address to Host buffer */ 969 ret = ath10k_ce_send_nolock(ce_diag, NULL, (u32)address, nbytes, 0, 970 0); 971 if (ret) 972 goto done; 973 974 i = 0; 975 while (ath10k_ce_completed_send_next_nolock(ce_diag, 976 NULL) != 0) { 977 udelay(DIAG_ACCESS_CE_WAIT_US); 978 i += DIAG_ACCESS_CE_WAIT_US; 979 980 if (i > DIAG_ACCESS_CE_TIMEOUT_US) { 981 ret = -EBUSY; 982 goto done; 983 } 984 } 985 986 i = 0; 987 while (ath10k_ce_completed_recv_next_nolock(ce_diag, 988 (void **)&buf, 989 &completed_nbytes) 990 != 0) { 991 udelay(DIAG_ACCESS_CE_WAIT_US); 992 i += DIAG_ACCESS_CE_WAIT_US; 993 994 if (i > DIAG_ACCESS_CE_TIMEOUT_US) { 995 ret = -EBUSY; 996 goto done; 997 } 998 } 999 1000 if (nbytes != completed_nbytes) { 1001 ret = -EIO; 1002 goto done; 1003 } 1004 1005 if (*buf != ce_data) { 1006 ret = -EIO; 1007 goto done; 1008 } 1009 1010 remaining_bytes -= nbytes; 1011 memcpy(data, data_buf, nbytes); 1012 1013 address += nbytes; 1014 data += nbytes; 1015 } 1016 1017 done: 1018 1019 if (data_buf) 1020 dma_free_coherent(ar->dev, alloc_nbytes, data_buf, 1021 ce_data_base); 1022 1023 spin_unlock_bh(&ce->ce_lock); 1024 1025 return ret; 1026 } 1027 1028 static int ath10k_pci_diag_read32(struct ath10k *ar, u32 address, u32 *value) 1029 { 1030 __le32 val = 0; 1031 int ret; 1032 1033 ret = ath10k_pci_diag_read_mem(ar, address, &val, sizeof(val)); 1034 *value = __le32_to_cpu(val); 1035 1036 return ret; 1037 } 1038 1039 static int __ath10k_pci_diag_read_hi(struct ath10k *ar, void *dest, 1040 u32 src, u32 len) 1041 { 1042 u32 host_addr, addr; 1043 int ret; 1044 1045 host_addr = host_interest_item_address(src); 1046 1047 ret = ath10k_pci_diag_read32(ar, host_addr, &addr); 1048 if (ret != 0) { 1049 ath10k_warn(ar, "failed to get memcpy hi address for firmware address %d: %d\n", 1050 src, ret); 1051 return ret; 1052 } 1053 1054 ret = ath10k_pci_diag_read_mem(ar, addr, dest, len); 1055 if (ret != 0) { 1056 ath10k_warn(ar, "failed to memcpy firmware memory from %d (%d B): %d\n", 1057 addr, len, ret); 1058 return ret; 1059 } 1060 1061 return 0; 1062 } 1063 1064 #define ath10k_pci_diag_read_hi(ar, dest, src, len) \ 1065 __ath10k_pci_diag_read_hi(ar, dest, HI_ITEM(src), len) 1066 1067 int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address, 1068 const void *data, int nbytes) 1069 { 1070 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1071 struct ath10k_ce *ce = ath10k_ce_priv(ar); 1072 int ret = 0; 1073 u32 *buf; 1074 unsigned int completed_nbytes, orig_nbytes, remaining_bytes; 1075 struct ath10k_ce_pipe *ce_diag; 1076 void *data_buf = NULL; 1077 u32 ce_data; /* Host buffer address in CE space */ 1078 dma_addr_t ce_data_base = 0; 1079 int i; 1080 1081 spin_lock_bh(&ce->ce_lock); 1082 1083 ce_diag = ar_pci->ce_diag; 1084 1085 /* 1086 * Allocate a temporary bounce buffer to hold caller's data 1087 * to be DMA'ed to Target. This guarantees 1088 * 1) 4-byte alignment 1089 * 2) Buffer in DMA-able space 1090 */ 1091 orig_nbytes = nbytes; 1092 data_buf = (unsigned char *)dma_alloc_coherent(ar->dev, 1093 orig_nbytes, 1094 &ce_data_base, 1095 GFP_ATOMIC); 1096 if (!data_buf) { 1097 ret = -ENOMEM; 1098 goto done; 1099 } 1100 1101 /* Copy caller's data to allocated DMA buf */ 1102 memcpy(data_buf, data, orig_nbytes); 1103 1104 /* 1105 * The address supplied by the caller is in the 1106 * Target CPU virtual address space. 1107 * 1108 * In order to use this address with the diagnostic CE, 1109 * convert it from 1110 * Target CPU virtual address space 1111 * to 1112 * CE address space 1113 */ 1114 address = ath10k_pci_targ_cpu_to_ce_addr(ar, address); 1115 1116 remaining_bytes = orig_nbytes; 1117 ce_data = ce_data_base; 1118 while (remaining_bytes) { 1119 /* FIXME: check cast */ 1120 nbytes = min_t(int, remaining_bytes, DIAG_TRANSFER_LIMIT); 1121 1122 /* Set up to receive directly into Target(!) address */ 1123 ret = ce_diag->ops->ce_rx_post_buf(ce_diag, &address, address); 1124 if (ret != 0) 1125 goto done; 1126 1127 /* 1128 * Request CE to send caller-supplied data that 1129 * was copied to bounce buffer to Target(!) address. 1130 */ 1131 ret = ath10k_ce_send_nolock(ce_diag, NULL, (u32)ce_data, 1132 nbytes, 0, 0); 1133 if (ret != 0) 1134 goto done; 1135 1136 i = 0; 1137 while (ath10k_ce_completed_send_next_nolock(ce_diag, 1138 NULL) != 0) { 1139 udelay(DIAG_ACCESS_CE_WAIT_US); 1140 i += DIAG_ACCESS_CE_WAIT_US; 1141 1142 if (i > DIAG_ACCESS_CE_TIMEOUT_US) { 1143 ret = -EBUSY; 1144 goto done; 1145 } 1146 } 1147 1148 i = 0; 1149 while (ath10k_ce_completed_recv_next_nolock(ce_diag, 1150 (void **)&buf, 1151 &completed_nbytes) 1152 != 0) { 1153 udelay(DIAG_ACCESS_CE_WAIT_US); 1154 i += DIAG_ACCESS_CE_WAIT_US; 1155 1156 if (i > DIAG_ACCESS_CE_TIMEOUT_US) { 1157 ret = -EBUSY; 1158 goto done; 1159 } 1160 } 1161 1162 if (nbytes != completed_nbytes) { 1163 ret = -EIO; 1164 goto done; 1165 } 1166 1167 if (*buf != address) { 1168 ret = -EIO; 1169 goto done; 1170 } 1171 1172 remaining_bytes -= nbytes; 1173 address += nbytes; 1174 ce_data += nbytes; 1175 } 1176 1177 done: 1178 if (data_buf) { 1179 dma_free_coherent(ar->dev, orig_nbytes, data_buf, 1180 ce_data_base); 1181 } 1182 1183 if (ret != 0) 1184 ath10k_warn(ar, "failed to write diag value at 0x%x: %d\n", 1185 address, ret); 1186 1187 spin_unlock_bh(&ce->ce_lock); 1188 1189 return ret; 1190 } 1191 1192 static int ath10k_pci_diag_write32(struct ath10k *ar, u32 address, u32 value) 1193 { 1194 __le32 val = __cpu_to_le32(value); 1195 1196 return ath10k_pci_diag_write_mem(ar, address, &val, sizeof(val)); 1197 } 1198 1199 /* Called by lower (CE) layer when a send to Target completes. */ 1200 static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe *ce_state) 1201 { 1202 struct ath10k *ar = ce_state->ar; 1203 struct sk_buff_head list; 1204 struct sk_buff *skb; 1205 1206 __skb_queue_head_init(&list); 1207 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) { 1208 /* no need to call tx completion for NULL pointers */ 1209 if (skb == NULL) 1210 continue; 1211 1212 __skb_queue_tail(&list, skb); 1213 } 1214 1215 while ((skb = __skb_dequeue(&list))) 1216 ath10k_htc_tx_completion_handler(ar, skb); 1217 } 1218 1219 static void ath10k_pci_process_rx_cb(struct ath10k_ce_pipe *ce_state, 1220 void (*callback)(struct ath10k *ar, 1221 struct sk_buff *skb)) 1222 { 1223 struct ath10k *ar = ce_state->ar; 1224 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1225 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id]; 1226 struct sk_buff *skb; 1227 struct sk_buff_head list; 1228 void *transfer_context; 1229 unsigned int nbytes, max_nbytes; 1230 1231 __skb_queue_head_init(&list); 1232 while (ath10k_ce_completed_recv_next(ce_state, &transfer_context, 1233 &nbytes) == 0) { 1234 skb = transfer_context; 1235 max_nbytes = skb->len + skb_tailroom(skb); 1236 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, 1237 max_nbytes, DMA_FROM_DEVICE); 1238 1239 if (unlikely(max_nbytes < nbytes)) { 1240 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)", 1241 nbytes, max_nbytes); 1242 dev_kfree_skb_any(skb); 1243 continue; 1244 } 1245 1246 skb_put(skb, nbytes); 1247 __skb_queue_tail(&list, skb); 1248 } 1249 1250 while ((skb = __skb_dequeue(&list))) { 1251 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n", 1252 ce_state->id, skb->len); 1253 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci rx: ", 1254 skb->data, skb->len); 1255 1256 callback(ar, skb); 1257 } 1258 1259 ath10k_pci_rx_post_pipe(pipe_info); 1260 } 1261 1262 static void ath10k_pci_process_htt_rx_cb(struct ath10k_ce_pipe *ce_state, 1263 void (*callback)(struct ath10k *ar, 1264 struct sk_buff *skb)) 1265 { 1266 struct ath10k *ar = ce_state->ar; 1267 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1268 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id]; 1269 struct ath10k_ce_pipe *ce_pipe = pipe_info->ce_hdl; 1270 struct sk_buff *skb; 1271 struct sk_buff_head list; 1272 void *transfer_context; 1273 unsigned int nbytes, max_nbytes, nentries; 1274 int orig_len; 1275 1276 /* No need to aquire ce_lock for CE5, since this is the only place CE5 1277 * is processed other than init and deinit. Before releasing CE5 1278 * buffers, interrupts are disabled. Thus CE5 access is serialized. 1279 */ 1280 __skb_queue_head_init(&list); 1281 while (ath10k_ce_completed_recv_next_nolock(ce_state, &transfer_context, 1282 &nbytes) == 0) { 1283 skb = transfer_context; 1284 max_nbytes = skb->len + skb_tailroom(skb); 1285 1286 if (unlikely(max_nbytes < nbytes)) { 1287 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)", 1288 nbytes, max_nbytes); 1289 continue; 1290 } 1291 1292 dma_sync_single_for_cpu(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, 1293 max_nbytes, DMA_FROM_DEVICE); 1294 skb_put(skb, nbytes); 1295 __skb_queue_tail(&list, skb); 1296 } 1297 1298 nentries = skb_queue_len(&list); 1299 while ((skb = __skb_dequeue(&list))) { 1300 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n", 1301 ce_state->id, skb->len); 1302 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci rx: ", 1303 skb->data, skb->len); 1304 1305 orig_len = skb->len; 1306 callback(ar, skb); 1307 skb_push(skb, orig_len - skb->len); 1308 skb_reset_tail_pointer(skb); 1309 skb_trim(skb, 0); 1310 1311 /*let device gain the buffer again*/ 1312 dma_sync_single_for_device(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, 1313 skb->len + skb_tailroom(skb), 1314 DMA_FROM_DEVICE); 1315 } 1316 ath10k_ce_rx_update_write_idx(ce_pipe, nentries); 1317 } 1318 1319 /* Called by lower (CE) layer when data is received from the Target. */ 1320 static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state) 1321 { 1322 ath10k_pci_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler); 1323 } 1324 1325 static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state) 1326 { 1327 /* CE4 polling needs to be done whenever CE pipe which transports 1328 * HTT Rx (target->host) is processed. 1329 */ 1330 ath10k_ce_per_engine_service(ce_state->ar, 4); 1331 1332 ath10k_pci_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler); 1333 } 1334 1335 /* Called by lower (CE) layer when data is received from the Target. 1336 * Only 10.4 firmware uses separate CE to transfer pktlog data. 1337 */ 1338 static void ath10k_pci_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state) 1339 { 1340 ath10k_pci_process_rx_cb(ce_state, 1341 ath10k_htt_rx_pktlog_completion_handler); 1342 } 1343 1344 /* Called by lower (CE) layer when a send to HTT Target completes. */ 1345 static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state) 1346 { 1347 struct ath10k *ar = ce_state->ar; 1348 struct sk_buff *skb; 1349 1350 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) { 1351 /* no need to call tx completion for NULL pointers */ 1352 if (!skb) 1353 continue; 1354 1355 dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr, 1356 skb->len, DMA_TO_DEVICE); 1357 ath10k_htt_hif_tx_complete(ar, skb); 1358 } 1359 } 1360 1361 static void ath10k_pci_htt_rx_deliver(struct ath10k *ar, struct sk_buff *skb) 1362 { 1363 skb_pull(skb, sizeof(struct ath10k_htc_hdr)); 1364 ath10k_htt_t2h_msg_handler(ar, skb); 1365 } 1366 1367 /* Called by lower (CE) layer when HTT data is received from the Target. */ 1368 static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe *ce_state) 1369 { 1370 /* CE4 polling needs to be done whenever CE pipe which transports 1371 * HTT Rx (target->host) is processed. 1372 */ 1373 ath10k_ce_per_engine_service(ce_state->ar, 4); 1374 1375 ath10k_pci_process_htt_rx_cb(ce_state, ath10k_pci_htt_rx_deliver); 1376 } 1377 1378 int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id, 1379 struct ath10k_hif_sg_item *items, int n_items) 1380 { 1381 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1382 struct ath10k_ce *ce = ath10k_ce_priv(ar); 1383 struct ath10k_pci_pipe *pci_pipe = &ar_pci->pipe_info[pipe_id]; 1384 struct ath10k_ce_pipe *ce_pipe = pci_pipe->ce_hdl; 1385 struct ath10k_ce_ring *src_ring = ce_pipe->src_ring; 1386 unsigned int nentries_mask; 1387 unsigned int sw_index; 1388 unsigned int write_index; 1389 int err, i = 0; 1390 1391 spin_lock_bh(&ce->ce_lock); 1392 1393 nentries_mask = src_ring->nentries_mask; 1394 sw_index = src_ring->sw_index; 1395 write_index = src_ring->write_index; 1396 1397 if (unlikely(CE_RING_DELTA(nentries_mask, 1398 write_index, sw_index - 1) < n_items)) { 1399 err = -ENOBUFS; 1400 goto err; 1401 } 1402 1403 for (i = 0; i < n_items - 1; i++) { 1404 ath10k_dbg(ar, ATH10K_DBG_PCI, 1405 "pci tx item %d paddr %pad len %d n_items %d\n", 1406 i, &items[i].paddr, items[i].len, n_items); 1407 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ", 1408 items[i].vaddr, items[i].len); 1409 1410 err = ath10k_ce_send_nolock(ce_pipe, 1411 items[i].transfer_context, 1412 items[i].paddr, 1413 items[i].len, 1414 items[i].transfer_id, 1415 CE_SEND_FLAG_GATHER); 1416 if (err) 1417 goto err; 1418 } 1419 1420 /* `i` is equal to `n_items -1` after for() */ 1421 1422 ath10k_dbg(ar, ATH10K_DBG_PCI, 1423 "pci tx item %d paddr %pad len %d n_items %d\n", 1424 i, &items[i].paddr, items[i].len, n_items); 1425 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ", 1426 items[i].vaddr, items[i].len); 1427 1428 err = ath10k_ce_send_nolock(ce_pipe, 1429 items[i].transfer_context, 1430 items[i].paddr, 1431 items[i].len, 1432 items[i].transfer_id, 1433 0); 1434 if (err) 1435 goto err; 1436 1437 spin_unlock_bh(&ce->ce_lock); 1438 return 0; 1439 1440 err: 1441 for (; i > 0; i--) 1442 __ath10k_ce_send_revert(ce_pipe); 1443 1444 spin_unlock_bh(&ce->ce_lock); 1445 return err; 1446 } 1447 1448 int ath10k_pci_hif_diag_read(struct ath10k *ar, u32 address, void *buf, 1449 size_t buf_len) 1450 { 1451 return ath10k_pci_diag_read_mem(ar, address, buf, buf_len); 1452 } 1453 1454 u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe) 1455 { 1456 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1457 1458 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get free queue number\n"); 1459 1460 return ath10k_ce_num_free_src_entries(ar_pci->pipe_info[pipe].ce_hdl); 1461 } 1462 1463 static void ath10k_pci_dump_registers(struct ath10k *ar, 1464 struct ath10k_fw_crash_data *crash_data) 1465 { 1466 __le32 reg_dump_values[REG_DUMP_COUNT_QCA988X] = {}; 1467 int i, ret; 1468 1469 lockdep_assert_held(&ar->data_lock); 1470 1471 ret = ath10k_pci_diag_read_hi(ar, ®_dump_values[0], 1472 hi_failure_state, 1473 REG_DUMP_COUNT_QCA988X * sizeof(__le32)); 1474 if (ret) { 1475 ath10k_err(ar, "failed to read firmware dump area: %d\n", ret); 1476 return; 1477 } 1478 1479 BUILD_BUG_ON(REG_DUMP_COUNT_QCA988X % 4); 1480 1481 ath10k_err(ar, "firmware register dump:\n"); 1482 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i += 4) 1483 ath10k_err(ar, "[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X\n", 1484 i, 1485 __le32_to_cpu(reg_dump_values[i]), 1486 __le32_to_cpu(reg_dump_values[i + 1]), 1487 __le32_to_cpu(reg_dump_values[i + 2]), 1488 __le32_to_cpu(reg_dump_values[i + 3])); 1489 1490 if (!crash_data) 1491 return; 1492 1493 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i++) 1494 crash_data->registers[i] = reg_dump_values[i]; 1495 } 1496 1497 static int ath10k_pci_dump_memory_section(struct ath10k *ar, 1498 const struct ath10k_mem_region *mem_region, 1499 u8 *buf, size_t buf_len) 1500 { 1501 const struct ath10k_mem_section *cur_section, *next_section; 1502 unsigned int count, section_size, skip_size; 1503 int ret, i, j; 1504 1505 if (!mem_region || !buf) 1506 return 0; 1507 1508 cur_section = &mem_region->section_table.sections[0]; 1509 1510 if (mem_region->start > cur_section->start) { 1511 ath10k_warn(ar, "incorrect memdump region 0x%x with section start address 0x%x.\n", 1512 mem_region->start, cur_section->start); 1513 return 0; 1514 } 1515 1516 skip_size = cur_section->start - mem_region->start; 1517 1518 /* fill the gap between the first register section and register 1519 * start address 1520 */ 1521 for (i = 0; i < skip_size; i++) { 1522 *buf = ATH10K_MAGIC_NOT_COPIED; 1523 buf++; 1524 } 1525 1526 count = 0; 1527 1528 for (i = 0; cur_section != NULL; i++) { 1529 section_size = cur_section->end - cur_section->start; 1530 1531 if (section_size <= 0) { 1532 ath10k_warn(ar, "incorrect ramdump format with start address 0x%x and stop address 0x%x\n", 1533 cur_section->start, 1534 cur_section->end); 1535 break; 1536 } 1537 1538 if ((i + 1) == mem_region->section_table.size) { 1539 /* last section */ 1540 next_section = NULL; 1541 skip_size = 0; 1542 } else { 1543 next_section = cur_section + 1; 1544 1545 if (cur_section->end > next_section->start) { 1546 ath10k_warn(ar, "next ramdump section 0x%x is smaller than current end address 0x%x\n", 1547 next_section->start, 1548 cur_section->end); 1549 break; 1550 } 1551 1552 skip_size = next_section->start - cur_section->end; 1553 } 1554 1555 if (buf_len < (skip_size + section_size)) { 1556 ath10k_warn(ar, "ramdump buffer is too small: %zu\n", buf_len); 1557 break; 1558 } 1559 1560 buf_len -= skip_size + section_size; 1561 1562 /* read section to dest memory */ 1563 ret = ath10k_pci_diag_read_mem(ar, cur_section->start, 1564 buf, section_size); 1565 if (ret) { 1566 ath10k_warn(ar, "failed to read ramdump from section 0x%x: %d\n", 1567 cur_section->start, ret); 1568 break; 1569 } 1570 1571 buf += section_size; 1572 count += section_size; 1573 1574 /* fill in the gap between this section and the next */ 1575 for (j = 0; j < skip_size; j++) { 1576 *buf = ATH10K_MAGIC_NOT_COPIED; 1577 buf++; 1578 } 1579 1580 count += skip_size; 1581 1582 if (!next_section) 1583 /* this was the last section */ 1584 break; 1585 1586 cur_section = next_section; 1587 } 1588 1589 return count; 1590 } 1591 1592 static int ath10k_pci_set_ram_config(struct ath10k *ar, u32 config) 1593 { 1594 u32 val; 1595 1596 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + 1597 FW_RAM_CONFIG_ADDRESS, config); 1598 1599 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 1600 FW_RAM_CONFIG_ADDRESS); 1601 if (val != config) { 1602 ath10k_warn(ar, "failed to set RAM config from 0x%x to 0x%x\n", 1603 val, config); 1604 return -EIO; 1605 } 1606 1607 return 0; 1608 } 1609 1610 /* if an error happened returns < 0, otherwise the length */ 1611 static int ath10k_pci_dump_memory_sram(struct ath10k *ar, 1612 const struct ath10k_mem_region *region, 1613 u8 *buf) 1614 { 1615 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1616 u32 base_addr, i; 1617 1618 base_addr = ioread32(ar_pci->mem + QCA99X0_PCIE_BAR0_START_REG); 1619 base_addr += region->start; 1620 1621 for (i = 0; i < region->len; i += 4) { 1622 iowrite32(base_addr + i, ar_pci->mem + QCA99X0_CPU_MEM_ADDR_REG); 1623 *(u32 *)(buf + i) = ioread32(ar_pci->mem + QCA99X0_CPU_MEM_DATA_REG); 1624 } 1625 1626 return region->len; 1627 } 1628 1629 /* if an error happened returns < 0, otherwise the length */ 1630 static int ath10k_pci_dump_memory_reg(struct ath10k *ar, 1631 const struct ath10k_mem_region *region, 1632 u8 *buf) 1633 { 1634 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1635 u32 i; 1636 1637 for (i = 0; i < region->len; i += 4) 1638 *(u32 *)(buf + i) = ioread32(ar_pci->mem + region->start + i); 1639 1640 return region->len; 1641 } 1642 1643 /* if an error happened returns < 0, otherwise the length */ 1644 static int ath10k_pci_dump_memory_generic(struct ath10k *ar, 1645 const struct ath10k_mem_region *current_region, 1646 u8 *buf) 1647 { 1648 int ret; 1649 1650 if (current_region->section_table.size > 0) 1651 /* Copy each section individually. */ 1652 return ath10k_pci_dump_memory_section(ar, 1653 current_region, 1654 buf, 1655 current_region->len); 1656 1657 /* No individiual memory sections defined so we can 1658 * copy the entire memory region. 1659 */ 1660 ret = ath10k_pci_diag_read_mem(ar, 1661 current_region->start, 1662 buf, 1663 current_region->len); 1664 if (ret) { 1665 ath10k_warn(ar, "failed to copy ramdump region %s: %d\n", 1666 current_region->name, ret); 1667 return ret; 1668 } 1669 1670 return current_region->len; 1671 } 1672 1673 static void ath10k_pci_dump_memory(struct ath10k *ar, 1674 struct ath10k_fw_crash_data *crash_data) 1675 { 1676 const struct ath10k_hw_mem_layout *mem_layout; 1677 const struct ath10k_mem_region *current_region; 1678 struct ath10k_dump_ram_data_hdr *hdr; 1679 u32 count, shift; 1680 size_t buf_len; 1681 int ret, i; 1682 u8 *buf; 1683 1684 lockdep_assert_held(&ar->data_lock); 1685 1686 if (!crash_data) 1687 return; 1688 1689 mem_layout = ath10k_coredump_get_mem_layout(ar); 1690 if (!mem_layout) 1691 return; 1692 1693 current_region = &mem_layout->region_table.regions[0]; 1694 1695 buf = crash_data->ramdump_buf; 1696 buf_len = crash_data->ramdump_buf_len; 1697 1698 memset(buf, 0, buf_len); 1699 1700 for (i = 0; i < mem_layout->region_table.size; i++) { 1701 count = 0; 1702 1703 if (current_region->len > buf_len) { 1704 ath10k_warn(ar, "memory region %s size %d is larger that remaining ramdump buffer size %zu\n", 1705 current_region->name, 1706 current_region->len, 1707 buf_len); 1708 break; 1709 } 1710 1711 /* To get IRAM dump, the host driver needs to switch target 1712 * ram config from DRAM to IRAM. 1713 */ 1714 if (current_region->type == ATH10K_MEM_REGION_TYPE_IRAM1 || 1715 current_region->type == ATH10K_MEM_REGION_TYPE_IRAM2) { 1716 shift = current_region->start >> 20; 1717 1718 ret = ath10k_pci_set_ram_config(ar, shift); 1719 if (ret) { 1720 ath10k_warn(ar, "failed to switch ram config to IRAM for section %s: %d\n", 1721 current_region->name, ret); 1722 break; 1723 } 1724 } 1725 1726 /* Reserve space for the header. */ 1727 hdr = (void *)buf; 1728 buf += sizeof(*hdr); 1729 buf_len -= sizeof(*hdr); 1730 1731 switch (current_region->type) { 1732 case ATH10K_MEM_REGION_TYPE_IOSRAM: 1733 count = ath10k_pci_dump_memory_sram(ar, current_region, buf); 1734 break; 1735 case ATH10K_MEM_REGION_TYPE_IOREG: 1736 count = ath10k_pci_dump_memory_reg(ar, current_region, buf); 1737 break; 1738 default: 1739 ret = ath10k_pci_dump_memory_generic(ar, current_region, buf); 1740 if (ret < 0) 1741 break; 1742 1743 count = ret; 1744 break; 1745 } 1746 1747 hdr->region_type = cpu_to_le32(current_region->type); 1748 hdr->start = cpu_to_le32(current_region->start); 1749 hdr->length = cpu_to_le32(count); 1750 1751 if (count == 0) 1752 /* Note: the header remains, just with zero length. */ 1753 break; 1754 1755 buf += count; 1756 buf_len -= count; 1757 1758 current_region++; 1759 } 1760 } 1761 1762 static void ath10k_pci_fw_crashed_dump(struct ath10k *ar) 1763 { 1764 struct ath10k_fw_crash_data *crash_data; 1765 char guid[UUID_STRING_LEN + 1]; 1766 1767 spin_lock_bh(&ar->data_lock); 1768 1769 ar->stats.fw_crash_counter++; 1770 1771 crash_data = ath10k_coredump_new(ar); 1772 1773 if (crash_data) 1774 scnprintf(guid, sizeof(guid), "%pUl", &crash_data->guid); 1775 else 1776 scnprintf(guid, sizeof(guid), "n/a"); 1777 1778 ath10k_err(ar, "firmware crashed! (guid %s)\n", guid); 1779 ath10k_print_driver_info(ar); 1780 ath10k_pci_dump_registers(ar, crash_data); 1781 ath10k_ce_dump_registers(ar, crash_data); 1782 ath10k_pci_dump_memory(ar, crash_data); 1783 1784 spin_unlock_bh(&ar->data_lock); 1785 1786 queue_work(ar->workqueue, &ar->restart_work); 1787 } 1788 1789 void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe, 1790 int force) 1791 { 1792 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif send complete check\n"); 1793 1794 if (!force) { 1795 int resources; 1796 /* 1797 * Decide whether to actually poll for completions, or just 1798 * wait for a later chance. 1799 * If there seem to be plenty of resources left, then just wait 1800 * since checking involves reading a CE register, which is a 1801 * relatively expensive operation. 1802 */ 1803 resources = ath10k_pci_hif_get_free_queue_number(ar, pipe); 1804 1805 /* 1806 * If at least 50% of the total resources are still available, 1807 * don't bother checking again yet. 1808 */ 1809 if (resources > (host_ce_config_wlan[pipe].src_nentries >> 1)) 1810 return; 1811 } 1812 ath10k_ce_per_engine_service(ar, pipe); 1813 } 1814 1815 static void ath10k_pci_rx_retry_sync(struct ath10k *ar) 1816 { 1817 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1818 1819 del_timer_sync(&ar_pci->rx_post_retry); 1820 } 1821 1822 int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar, u16 service_id, 1823 u8 *ul_pipe, u8 *dl_pipe) 1824 { 1825 const struct service_to_pipe *entry; 1826 bool ul_set = false, dl_set = false; 1827 int i; 1828 1829 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif map service\n"); 1830 1831 for (i = 0; i < ARRAY_SIZE(target_service_to_ce_map_wlan); i++) { 1832 entry = &target_service_to_ce_map_wlan[i]; 1833 1834 if (__le32_to_cpu(entry->service_id) != service_id) 1835 continue; 1836 1837 switch (__le32_to_cpu(entry->pipedir)) { 1838 case PIPEDIR_NONE: 1839 break; 1840 case PIPEDIR_IN: 1841 WARN_ON(dl_set); 1842 *dl_pipe = __le32_to_cpu(entry->pipenum); 1843 dl_set = true; 1844 break; 1845 case PIPEDIR_OUT: 1846 WARN_ON(ul_set); 1847 *ul_pipe = __le32_to_cpu(entry->pipenum); 1848 ul_set = true; 1849 break; 1850 case PIPEDIR_INOUT: 1851 WARN_ON(dl_set); 1852 WARN_ON(ul_set); 1853 *dl_pipe = __le32_to_cpu(entry->pipenum); 1854 *ul_pipe = __le32_to_cpu(entry->pipenum); 1855 dl_set = true; 1856 ul_set = true; 1857 break; 1858 } 1859 } 1860 1861 if (!ul_set || !dl_set) 1862 return -ENOENT; 1863 1864 return 0; 1865 } 1866 1867 void ath10k_pci_hif_get_default_pipe(struct ath10k *ar, 1868 u8 *ul_pipe, u8 *dl_pipe) 1869 { 1870 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get default pipe\n"); 1871 1872 (void)ath10k_pci_hif_map_service_to_pipe(ar, 1873 ATH10K_HTC_SVC_ID_RSVD_CTRL, 1874 ul_pipe, dl_pipe); 1875 } 1876 1877 void ath10k_pci_irq_msi_fw_mask(struct ath10k *ar) 1878 { 1879 u32 val; 1880 1881 switch (ar->hw_rev) { 1882 case ATH10K_HW_QCA988X: 1883 case ATH10K_HW_QCA9887: 1884 case ATH10K_HW_QCA6174: 1885 case ATH10K_HW_QCA9377: 1886 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 1887 CORE_CTRL_ADDRESS); 1888 val &= ~CORE_CTRL_PCIE_REG_31_MASK; 1889 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + 1890 CORE_CTRL_ADDRESS, val); 1891 break; 1892 case ATH10K_HW_QCA99X0: 1893 case ATH10K_HW_QCA9984: 1894 case ATH10K_HW_QCA9888: 1895 case ATH10K_HW_QCA4019: 1896 /* TODO: Find appropriate register configuration for QCA99X0 1897 * to mask irq/MSI. 1898 */ 1899 break; 1900 case ATH10K_HW_WCN3990: 1901 break; 1902 } 1903 } 1904 1905 static void ath10k_pci_irq_msi_fw_unmask(struct ath10k *ar) 1906 { 1907 u32 val; 1908 1909 switch (ar->hw_rev) { 1910 case ATH10K_HW_QCA988X: 1911 case ATH10K_HW_QCA9887: 1912 case ATH10K_HW_QCA6174: 1913 case ATH10K_HW_QCA9377: 1914 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 1915 CORE_CTRL_ADDRESS); 1916 val |= CORE_CTRL_PCIE_REG_31_MASK; 1917 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + 1918 CORE_CTRL_ADDRESS, val); 1919 break; 1920 case ATH10K_HW_QCA99X0: 1921 case ATH10K_HW_QCA9984: 1922 case ATH10K_HW_QCA9888: 1923 case ATH10K_HW_QCA4019: 1924 /* TODO: Find appropriate register configuration for QCA99X0 1925 * to unmask irq/MSI. 1926 */ 1927 break; 1928 case ATH10K_HW_WCN3990: 1929 break; 1930 } 1931 } 1932 1933 static void ath10k_pci_irq_disable(struct ath10k *ar) 1934 { 1935 ath10k_ce_disable_interrupts(ar); 1936 ath10k_pci_disable_and_clear_legacy_irq(ar); 1937 ath10k_pci_irq_msi_fw_mask(ar); 1938 } 1939 1940 static void ath10k_pci_irq_sync(struct ath10k *ar) 1941 { 1942 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1943 1944 synchronize_irq(ar_pci->pdev->irq); 1945 } 1946 1947 static void ath10k_pci_irq_enable(struct ath10k *ar) 1948 { 1949 ath10k_ce_enable_interrupts(ar); 1950 ath10k_pci_enable_legacy_irq(ar); 1951 ath10k_pci_irq_msi_fw_unmask(ar); 1952 } 1953 1954 static int ath10k_pci_hif_start(struct ath10k *ar) 1955 { 1956 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1957 1958 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif start\n"); 1959 1960 napi_enable(&ar->napi); 1961 1962 ath10k_pci_irq_enable(ar); 1963 ath10k_pci_rx_post(ar); 1964 1965 pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL, 1966 ar_pci->link_ctl); 1967 1968 return 0; 1969 } 1970 1971 static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe) 1972 { 1973 struct ath10k *ar; 1974 struct ath10k_ce_pipe *ce_pipe; 1975 struct ath10k_ce_ring *ce_ring; 1976 struct sk_buff *skb; 1977 int i; 1978 1979 ar = pci_pipe->hif_ce_state; 1980 ce_pipe = pci_pipe->ce_hdl; 1981 ce_ring = ce_pipe->dest_ring; 1982 1983 if (!ce_ring) 1984 return; 1985 1986 if (!pci_pipe->buf_sz) 1987 return; 1988 1989 for (i = 0; i < ce_ring->nentries; i++) { 1990 skb = ce_ring->per_transfer_context[i]; 1991 if (!skb) 1992 continue; 1993 1994 ce_ring->per_transfer_context[i] = NULL; 1995 1996 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, 1997 skb->len + skb_tailroom(skb), 1998 DMA_FROM_DEVICE); 1999 dev_kfree_skb_any(skb); 2000 } 2001 } 2002 2003 static void ath10k_pci_tx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe) 2004 { 2005 struct ath10k *ar; 2006 struct ath10k_ce_pipe *ce_pipe; 2007 struct ath10k_ce_ring *ce_ring; 2008 struct sk_buff *skb; 2009 int i; 2010 2011 ar = pci_pipe->hif_ce_state; 2012 ce_pipe = pci_pipe->ce_hdl; 2013 ce_ring = ce_pipe->src_ring; 2014 2015 if (!ce_ring) 2016 return; 2017 2018 if (!pci_pipe->buf_sz) 2019 return; 2020 2021 for (i = 0; i < ce_ring->nentries; i++) { 2022 skb = ce_ring->per_transfer_context[i]; 2023 if (!skb) 2024 continue; 2025 2026 ce_ring->per_transfer_context[i] = NULL; 2027 2028 ath10k_htc_tx_completion_handler(ar, skb); 2029 } 2030 } 2031 2032 /* 2033 * Cleanup residual buffers for device shutdown: 2034 * buffers that were enqueued for receive 2035 * buffers that were to be sent 2036 * Note: Buffers that had completed but which were 2037 * not yet processed are on a completion queue. They 2038 * are handled when the completion thread shuts down. 2039 */ 2040 static void ath10k_pci_buffer_cleanup(struct ath10k *ar) 2041 { 2042 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2043 int pipe_num; 2044 2045 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) { 2046 struct ath10k_pci_pipe *pipe_info; 2047 2048 pipe_info = &ar_pci->pipe_info[pipe_num]; 2049 ath10k_pci_rx_pipe_cleanup(pipe_info); 2050 ath10k_pci_tx_pipe_cleanup(pipe_info); 2051 } 2052 } 2053 2054 void ath10k_pci_ce_deinit(struct ath10k *ar) 2055 { 2056 int i; 2057 2058 for (i = 0; i < CE_COUNT; i++) 2059 ath10k_ce_deinit_pipe(ar, i); 2060 } 2061 2062 void ath10k_pci_flush(struct ath10k *ar) 2063 { 2064 ath10k_pci_rx_retry_sync(ar); 2065 ath10k_pci_buffer_cleanup(ar); 2066 } 2067 2068 static void ath10k_pci_hif_stop(struct ath10k *ar) 2069 { 2070 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2071 unsigned long flags; 2072 2073 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif stop\n"); 2074 2075 /* Most likely the device has HTT Rx ring configured. The only way to 2076 * prevent the device from accessing (and possible corrupting) host 2077 * memory is to reset the chip now. 2078 * 2079 * There's also no known way of masking MSI interrupts on the device. 2080 * For ranged MSI the CE-related interrupts can be masked. However 2081 * regardless how many MSI interrupts are assigned the first one 2082 * is always used for firmware indications (crashes) and cannot be 2083 * masked. To prevent the device from asserting the interrupt reset it 2084 * before proceeding with cleanup. 2085 */ 2086 ath10k_pci_safe_chip_reset(ar); 2087 2088 ath10k_pci_irq_disable(ar); 2089 ath10k_pci_irq_sync(ar); 2090 napi_synchronize(&ar->napi); 2091 napi_disable(&ar->napi); 2092 ath10k_pci_flush(ar); 2093 2094 spin_lock_irqsave(&ar_pci->ps_lock, flags); 2095 WARN_ON(ar_pci->ps_wake_refcount > 0); 2096 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 2097 } 2098 2099 int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar, 2100 void *req, u32 req_len, 2101 void *resp, u32 *resp_len) 2102 { 2103 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2104 struct ath10k_pci_pipe *pci_tx = &ar_pci->pipe_info[BMI_CE_NUM_TO_TARG]; 2105 struct ath10k_pci_pipe *pci_rx = &ar_pci->pipe_info[BMI_CE_NUM_TO_HOST]; 2106 struct ath10k_ce_pipe *ce_tx = pci_tx->ce_hdl; 2107 struct ath10k_ce_pipe *ce_rx = pci_rx->ce_hdl; 2108 dma_addr_t req_paddr = 0; 2109 dma_addr_t resp_paddr = 0; 2110 struct bmi_xfer xfer = {}; 2111 void *treq, *tresp = NULL; 2112 int ret = 0; 2113 2114 might_sleep(); 2115 2116 if (resp && !resp_len) 2117 return -EINVAL; 2118 2119 if (resp && resp_len && *resp_len == 0) 2120 return -EINVAL; 2121 2122 treq = kmemdup(req, req_len, GFP_KERNEL); 2123 if (!treq) 2124 return -ENOMEM; 2125 2126 req_paddr = dma_map_single(ar->dev, treq, req_len, DMA_TO_DEVICE); 2127 ret = dma_mapping_error(ar->dev, req_paddr); 2128 if (ret) { 2129 ret = -EIO; 2130 goto err_dma; 2131 } 2132 2133 if (resp && resp_len) { 2134 tresp = kzalloc(*resp_len, GFP_KERNEL); 2135 if (!tresp) { 2136 ret = -ENOMEM; 2137 goto err_req; 2138 } 2139 2140 resp_paddr = dma_map_single(ar->dev, tresp, *resp_len, 2141 DMA_FROM_DEVICE); 2142 ret = dma_mapping_error(ar->dev, resp_paddr); 2143 if (ret) { 2144 ret = -EIO; 2145 goto err_req; 2146 } 2147 2148 xfer.wait_for_resp = true; 2149 xfer.resp_len = 0; 2150 2151 ath10k_ce_rx_post_buf(ce_rx, &xfer, resp_paddr); 2152 } 2153 2154 ret = ath10k_ce_send(ce_tx, &xfer, req_paddr, req_len, -1, 0); 2155 if (ret) 2156 goto err_resp; 2157 2158 ret = ath10k_pci_bmi_wait(ar, ce_tx, ce_rx, &xfer); 2159 if (ret) { 2160 dma_addr_t unused_buffer; 2161 unsigned int unused_nbytes; 2162 unsigned int unused_id; 2163 2164 ath10k_ce_cancel_send_next(ce_tx, NULL, &unused_buffer, 2165 &unused_nbytes, &unused_id); 2166 } else { 2167 /* non-zero means we did not time out */ 2168 ret = 0; 2169 } 2170 2171 err_resp: 2172 if (resp) { 2173 dma_addr_t unused_buffer; 2174 2175 ath10k_ce_revoke_recv_next(ce_rx, NULL, &unused_buffer); 2176 dma_unmap_single(ar->dev, resp_paddr, 2177 *resp_len, DMA_FROM_DEVICE); 2178 } 2179 err_req: 2180 dma_unmap_single(ar->dev, req_paddr, req_len, DMA_TO_DEVICE); 2181 2182 if (ret == 0 && resp_len) { 2183 *resp_len = min(*resp_len, xfer.resp_len); 2184 memcpy(resp, tresp, xfer.resp_len); 2185 } 2186 err_dma: 2187 kfree(treq); 2188 kfree(tresp); 2189 2190 return ret; 2191 } 2192 2193 static void ath10k_pci_bmi_send_done(struct ath10k_ce_pipe *ce_state) 2194 { 2195 struct bmi_xfer *xfer; 2196 2197 if (ath10k_ce_completed_send_next(ce_state, (void **)&xfer)) 2198 return; 2199 2200 xfer->tx_done = true; 2201 } 2202 2203 static void ath10k_pci_bmi_recv_data(struct ath10k_ce_pipe *ce_state) 2204 { 2205 struct ath10k *ar = ce_state->ar; 2206 struct bmi_xfer *xfer; 2207 unsigned int nbytes; 2208 2209 if (ath10k_ce_completed_recv_next(ce_state, (void **)&xfer, 2210 &nbytes)) 2211 return; 2212 2213 if (WARN_ON_ONCE(!xfer)) 2214 return; 2215 2216 if (!xfer->wait_for_resp) { 2217 ath10k_warn(ar, "unexpected: BMI data received; ignoring\n"); 2218 return; 2219 } 2220 2221 xfer->resp_len = nbytes; 2222 xfer->rx_done = true; 2223 } 2224 2225 static int ath10k_pci_bmi_wait(struct ath10k *ar, 2226 struct ath10k_ce_pipe *tx_pipe, 2227 struct ath10k_ce_pipe *rx_pipe, 2228 struct bmi_xfer *xfer) 2229 { 2230 unsigned long timeout = jiffies + BMI_COMMUNICATION_TIMEOUT_HZ; 2231 unsigned long started = jiffies; 2232 unsigned long dur; 2233 int ret; 2234 2235 while (time_before_eq(jiffies, timeout)) { 2236 ath10k_pci_bmi_send_done(tx_pipe); 2237 ath10k_pci_bmi_recv_data(rx_pipe); 2238 2239 if (xfer->tx_done && (xfer->rx_done == xfer->wait_for_resp)) { 2240 ret = 0; 2241 goto out; 2242 } 2243 2244 schedule(); 2245 } 2246 2247 ret = -ETIMEDOUT; 2248 2249 out: 2250 dur = jiffies - started; 2251 if (dur > HZ) 2252 ath10k_dbg(ar, ATH10K_DBG_BMI, 2253 "bmi cmd took %lu jiffies hz %d ret %d\n", 2254 dur, HZ, ret); 2255 return ret; 2256 } 2257 2258 /* 2259 * Send an interrupt to the device to wake up the Target CPU 2260 * so it has an opportunity to notice any changed state. 2261 */ 2262 static int ath10k_pci_wake_target_cpu(struct ath10k *ar) 2263 { 2264 u32 addr, val; 2265 2266 addr = SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS; 2267 val = ath10k_pci_read32(ar, addr); 2268 val |= CORE_CTRL_CPU_INTR_MASK; 2269 ath10k_pci_write32(ar, addr, val); 2270 2271 return 0; 2272 } 2273 2274 static int ath10k_pci_get_num_banks(struct ath10k *ar) 2275 { 2276 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2277 2278 switch (ar_pci->pdev->device) { 2279 case QCA988X_2_0_DEVICE_ID_UBNT: 2280 case QCA988X_2_0_DEVICE_ID: 2281 case QCA99X0_2_0_DEVICE_ID: 2282 case QCA9888_2_0_DEVICE_ID: 2283 case QCA9984_1_0_DEVICE_ID: 2284 case QCA9887_1_0_DEVICE_ID: 2285 return 1; 2286 case QCA6164_2_1_DEVICE_ID: 2287 case QCA6174_2_1_DEVICE_ID: 2288 switch (MS(ar->chip_id, SOC_CHIP_ID_REV)) { 2289 case QCA6174_HW_1_0_CHIP_ID_REV: 2290 case QCA6174_HW_1_1_CHIP_ID_REV: 2291 case QCA6174_HW_2_1_CHIP_ID_REV: 2292 case QCA6174_HW_2_2_CHIP_ID_REV: 2293 return 3; 2294 case QCA6174_HW_1_3_CHIP_ID_REV: 2295 return 2; 2296 case QCA6174_HW_3_0_CHIP_ID_REV: 2297 case QCA6174_HW_3_1_CHIP_ID_REV: 2298 case QCA6174_HW_3_2_CHIP_ID_REV: 2299 return 9; 2300 } 2301 break; 2302 case QCA9377_1_0_DEVICE_ID: 2303 return 9; 2304 } 2305 2306 ath10k_warn(ar, "unknown number of banks, assuming 1\n"); 2307 return 1; 2308 } 2309 2310 static int ath10k_bus_get_num_banks(struct ath10k *ar) 2311 { 2312 struct ath10k_ce *ce = ath10k_ce_priv(ar); 2313 2314 return ce->bus_ops->get_num_banks(ar); 2315 } 2316 2317 int ath10k_pci_init_config(struct ath10k *ar) 2318 { 2319 u32 interconnect_targ_addr; 2320 u32 pcie_state_targ_addr = 0; 2321 u32 pipe_cfg_targ_addr = 0; 2322 u32 svc_to_pipe_map = 0; 2323 u32 pcie_config_flags = 0; 2324 u32 ealloc_value; 2325 u32 ealloc_targ_addr; 2326 u32 flag2_value; 2327 u32 flag2_targ_addr; 2328 int ret = 0; 2329 2330 /* Download to Target the CE Config and the service-to-CE map */ 2331 interconnect_targ_addr = 2332 host_interest_item_address(HI_ITEM(hi_interconnect_state)); 2333 2334 /* Supply Target-side CE configuration */ 2335 ret = ath10k_pci_diag_read32(ar, interconnect_targ_addr, 2336 &pcie_state_targ_addr); 2337 if (ret != 0) { 2338 ath10k_err(ar, "Failed to get pcie state addr: %d\n", ret); 2339 return ret; 2340 } 2341 2342 if (pcie_state_targ_addr == 0) { 2343 ret = -EIO; 2344 ath10k_err(ar, "Invalid pcie state addr\n"); 2345 return ret; 2346 } 2347 2348 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr + 2349 offsetof(struct pcie_state, 2350 pipe_cfg_addr)), 2351 &pipe_cfg_targ_addr); 2352 if (ret != 0) { 2353 ath10k_err(ar, "Failed to get pipe cfg addr: %d\n", ret); 2354 return ret; 2355 } 2356 2357 if (pipe_cfg_targ_addr == 0) { 2358 ret = -EIO; 2359 ath10k_err(ar, "Invalid pipe cfg addr\n"); 2360 return ret; 2361 } 2362 2363 ret = ath10k_pci_diag_write_mem(ar, pipe_cfg_targ_addr, 2364 target_ce_config_wlan, 2365 sizeof(struct ce_pipe_config) * 2366 NUM_TARGET_CE_CONFIG_WLAN); 2367 2368 if (ret != 0) { 2369 ath10k_err(ar, "Failed to write pipe cfg: %d\n", ret); 2370 return ret; 2371 } 2372 2373 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr + 2374 offsetof(struct pcie_state, 2375 svc_to_pipe_map)), 2376 &svc_to_pipe_map); 2377 if (ret != 0) { 2378 ath10k_err(ar, "Failed to get svc/pipe map: %d\n", ret); 2379 return ret; 2380 } 2381 2382 if (svc_to_pipe_map == 0) { 2383 ret = -EIO; 2384 ath10k_err(ar, "Invalid svc_to_pipe map\n"); 2385 return ret; 2386 } 2387 2388 ret = ath10k_pci_diag_write_mem(ar, svc_to_pipe_map, 2389 target_service_to_ce_map_wlan, 2390 sizeof(target_service_to_ce_map_wlan)); 2391 if (ret != 0) { 2392 ath10k_err(ar, "Failed to write svc/pipe map: %d\n", ret); 2393 return ret; 2394 } 2395 2396 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr + 2397 offsetof(struct pcie_state, 2398 config_flags)), 2399 &pcie_config_flags); 2400 if (ret != 0) { 2401 ath10k_err(ar, "Failed to get pcie config_flags: %d\n", ret); 2402 return ret; 2403 } 2404 2405 pcie_config_flags &= ~PCIE_CONFIG_FLAG_ENABLE_L1; 2406 2407 ret = ath10k_pci_diag_write32(ar, (pcie_state_targ_addr + 2408 offsetof(struct pcie_state, 2409 config_flags)), 2410 pcie_config_flags); 2411 if (ret != 0) { 2412 ath10k_err(ar, "Failed to write pcie config_flags: %d\n", ret); 2413 return ret; 2414 } 2415 2416 /* configure early allocation */ 2417 ealloc_targ_addr = host_interest_item_address(HI_ITEM(hi_early_alloc)); 2418 2419 ret = ath10k_pci_diag_read32(ar, ealloc_targ_addr, &ealloc_value); 2420 if (ret != 0) { 2421 ath10k_err(ar, "Failed to get early alloc val: %d\n", ret); 2422 return ret; 2423 } 2424 2425 /* first bank is switched to IRAM */ 2426 ealloc_value |= ((HI_EARLY_ALLOC_MAGIC << HI_EARLY_ALLOC_MAGIC_SHIFT) & 2427 HI_EARLY_ALLOC_MAGIC_MASK); 2428 ealloc_value |= ((ath10k_bus_get_num_banks(ar) << 2429 HI_EARLY_ALLOC_IRAM_BANKS_SHIFT) & 2430 HI_EARLY_ALLOC_IRAM_BANKS_MASK); 2431 2432 ret = ath10k_pci_diag_write32(ar, ealloc_targ_addr, ealloc_value); 2433 if (ret != 0) { 2434 ath10k_err(ar, "Failed to set early alloc val: %d\n", ret); 2435 return ret; 2436 } 2437 2438 /* Tell Target to proceed with initialization */ 2439 flag2_targ_addr = host_interest_item_address(HI_ITEM(hi_option_flag2)); 2440 2441 ret = ath10k_pci_diag_read32(ar, flag2_targ_addr, &flag2_value); 2442 if (ret != 0) { 2443 ath10k_err(ar, "Failed to get option val: %d\n", ret); 2444 return ret; 2445 } 2446 2447 flag2_value |= HI_OPTION_EARLY_CFG_DONE; 2448 2449 ret = ath10k_pci_diag_write32(ar, flag2_targ_addr, flag2_value); 2450 if (ret != 0) { 2451 ath10k_err(ar, "Failed to set option val: %d\n", ret); 2452 return ret; 2453 } 2454 2455 return 0; 2456 } 2457 2458 static void ath10k_pci_override_ce_config(struct ath10k *ar) 2459 { 2460 struct ce_attr *attr; 2461 struct ce_pipe_config *config; 2462 2463 /* For QCA6174 we're overriding the Copy Engine 5 configuration, 2464 * since it is currently used for other feature. 2465 */ 2466 2467 /* Override Host's Copy Engine 5 configuration */ 2468 attr = &host_ce_config_wlan[5]; 2469 attr->src_sz_max = 0; 2470 attr->dest_nentries = 0; 2471 2472 /* Override Target firmware's Copy Engine configuration */ 2473 config = &target_ce_config_wlan[5]; 2474 config->pipedir = __cpu_to_le32(PIPEDIR_OUT); 2475 config->nbytes_max = __cpu_to_le32(2048); 2476 2477 /* Map from service/endpoint to Copy Engine */ 2478 target_service_to_ce_map_wlan[15].pipenum = __cpu_to_le32(1); 2479 } 2480 2481 int ath10k_pci_alloc_pipes(struct ath10k *ar) 2482 { 2483 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2484 struct ath10k_pci_pipe *pipe; 2485 struct ath10k_ce *ce = ath10k_ce_priv(ar); 2486 int i, ret; 2487 2488 for (i = 0; i < CE_COUNT; i++) { 2489 pipe = &ar_pci->pipe_info[i]; 2490 pipe->ce_hdl = &ce->ce_states[i]; 2491 pipe->pipe_num = i; 2492 pipe->hif_ce_state = ar; 2493 2494 ret = ath10k_ce_alloc_pipe(ar, i, &host_ce_config_wlan[i]); 2495 if (ret) { 2496 ath10k_err(ar, "failed to allocate copy engine pipe %d: %d\n", 2497 i, ret); 2498 return ret; 2499 } 2500 2501 /* Last CE is Diagnostic Window */ 2502 if (i == CE_DIAG_PIPE) { 2503 ar_pci->ce_diag = pipe->ce_hdl; 2504 continue; 2505 } 2506 2507 pipe->buf_sz = (size_t)(host_ce_config_wlan[i].src_sz_max); 2508 } 2509 2510 return 0; 2511 } 2512 2513 void ath10k_pci_free_pipes(struct ath10k *ar) 2514 { 2515 int i; 2516 2517 for (i = 0; i < CE_COUNT; i++) 2518 ath10k_ce_free_pipe(ar, i); 2519 } 2520 2521 int ath10k_pci_init_pipes(struct ath10k *ar) 2522 { 2523 int i, ret; 2524 2525 for (i = 0; i < CE_COUNT; i++) { 2526 ret = ath10k_ce_init_pipe(ar, i, &host_ce_config_wlan[i]); 2527 if (ret) { 2528 ath10k_err(ar, "failed to initialize copy engine pipe %d: %d\n", 2529 i, ret); 2530 return ret; 2531 } 2532 } 2533 2534 return 0; 2535 } 2536 2537 static bool ath10k_pci_has_fw_crashed(struct ath10k *ar) 2538 { 2539 return ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS) & 2540 FW_IND_EVENT_PENDING; 2541 } 2542 2543 static void ath10k_pci_fw_crashed_clear(struct ath10k *ar) 2544 { 2545 u32 val; 2546 2547 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS); 2548 val &= ~FW_IND_EVENT_PENDING; 2549 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, val); 2550 } 2551 2552 static bool ath10k_pci_has_device_gone(struct ath10k *ar) 2553 { 2554 u32 val; 2555 2556 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS); 2557 return (val == 0xffffffff); 2558 } 2559 2560 /* this function effectively clears target memory controller assert line */ 2561 static void ath10k_pci_warm_reset_si0(struct ath10k *ar) 2562 { 2563 u32 val; 2564 2565 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); 2566 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS, 2567 val | SOC_RESET_CONTROL_SI0_RST_MASK); 2568 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); 2569 2570 msleep(10); 2571 2572 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); 2573 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS, 2574 val & ~SOC_RESET_CONTROL_SI0_RST_MASK); 2575 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); 2576 2577 msleep(10); 2578 } 2579 2580 static void ath10k_pci_warm_reset_cpu(struct ath10k *ar) 2581 { 2582 u32 val; 2583 2584 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, 0); 2585 2586 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + 2587 SOC_RESET_CONTROL_ADDRESS); 2588 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS, 2589 val | SOC_RESET_CONTROL_CPU_WARM_RST_MASK); 2590 } 2591 2592 static void ath10k_pci_warm_reset_ce(struct ath10k *ar) 2593 { 2594 u32 val; 2595 2596 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + 2597 SOC_RESET_CONTROL_ADDRESS); 2598 2599 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS, 2600 val | SOC_RESET_CONTROL_CE_RST_MASK); 2601 msleep(10); 2602 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS, 2603 val & ~SOC_RESET_CONTROL_CE_RST_MASK); 2604 } 2605 2606 static void ath10k_pci_warm_reset_clear_lf(struct ath10k *ar) 2607 { 2608 u32 val; 2609 2610 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + 2611 SOC_LF_TIMER_CONTROL0_ADDRESS); 2612 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + 2613 SOC_LF_TIMER_CONTROL0_ADDRESS, 2614 val & ~SOC_LF_TIMER_CONTROL0_ENABLE_MASK); 2615 } 2616 2617 static int ath10k_pci_warm_reset(struct ath10k *ar) 2618 { 2619 int ret; 2620 2621 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset\n"); 2622 2623 spin_lock_bh(&ar->data_lock); 2624 ar->stats.fw_warm_reset_counter++; 2625 spin_unlock_bh(&ar->data_lock); 2626 2627 ath10k_pci_irq_disable(ar); 2628 2629 /* Make sure the target CPU is not doing anything dangerous, e.g. if it 2630 * were to access copy engine while host performs copy engine reset 2631 * then it is possible for the device to confuse pci-e controller to 2632 * the point of bringing host system to a complete stop (i.e. hang). 2633 */ 2634 ath10k_pci_warm_reset_si0(ar); 2635 ath10k_pci_warm_reset_cpu(ar); 2636 ath10k_pci_init_pipes(ar); 2637 ath10k_pci_wait_for_target_init(ar); 2638 2639 ath10k_pci_warm_reset_clear_lf(ar); 2640 ath10k_pci_warm_reset_ce(ar); 2641 ath10k_pci_warm_reset_cpu(ar); 2642 ath10k_pci_init_pipes(ar); 2643 2644 ret = ath10k_pci_wait_for_target_init(ar); 2645 if (ret) { 2646 ath10k_warn(ar, "failed to wait for target init: %d\n", ret); 2647 return ret; 2648 } 2649 2650 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset complete\n"); 2651 2652 return 0; 2653 } 2654 2655 static int ath10k_pci_qca99x0_soft_chip_reset(struct ath10k *ar) 2656 { 2657 ath10k_pci_irq_disable(ar); 2658 return ath10k_pci_qca99x0_chip_reset(ar); 2659 } 2660 2661 static int ath10k_pci_safe_chip_reset(struct ath10k *ar) 2662 { 2663 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2664 2665 if (!ar_pci->pci_soft_reset) 2666 return -ENOTSUPP; 2667 2668 return ar_pci->pci_soft_reset(ar); 2669 } 2670 2671 static int ath10k_pci_qca988x_chip_reset(struct ath10k *ar) 2672 { 2673 int i, ret; 2674 u32 val; 2675 2676 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot 988x chip reset\n"); 2677 2678 /* Some hardware revisions (e.g. CUS223v2) has issues with cold reset. 2679 * It is thus preferred to use warm reset which is safer but may not be 2680 * able to recover the device from all possible fail scenarios. 2681 * 2682 * Warm reset doesn't always work on first try so attempt it a few 2683 * times before giving up. 2684 */ 2685 for (i = 0; i < ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS; i++) { 2686 ret = ath10k_pci_warm_reset(ar); 2687 if (ret) { 2688 ath10k_warn(ar, "failed to warm reset attempt %d of %d: %d\n", 2689 i + 1, ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS, 2690 ret); 2691 continue; 2692 } 2693 2694 /* FIXME: Sometimes copy engine doesn't recover after warm 2695 * reset. In most cases this needs cold reset. In some of these 2696 * cases the device is in such a state that a cold reset may 2697 * lock up the host. 2698 * 2699 * Reading any host interest register via copy engine is 2700 * sufficient to verify if device is capable of booting 2701 * firmware blob. 2702 */ 2703 ret = ath10k_pci_init_pipes(ar); 2704 if (ret) { 2705 ath10k_warn(ar, "failed to init copy engine: %d\n", 2706 ret); 2707 continue; 2708 } 2709 2710 ret = ath10k_pci_diag_read32(ar, QCA988X_HOST_INTEREST_ADDRESS, 2711 &val); 2712 if (ret) { 2713 ath10k_warn(ar, "failed to poke copy engine: %d\n", 2714 ret); 2715 continue; 2716 } 2717 2718 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot chip reset complete (warm)\n"); 2719 return 0; 2720 } 2721 2722 if (ath10k_pci_reset_mode == ATH10K_PCI_RESET_WARM_ONLY) { 2723 ath10k_warn(ar, "refusing cold reset as requested\n"); 2724 return -EPERM; 2725 } 2726 2727 ret = ath10k_pci_cold_reset(ar); 2728 if (ret) { 2729 ath10k_warn(ar, "failed to cold reset: %d\n", ret); 2730 return ret; 2731 } 2732 2733 ret = ath10k_pci_wait_for_target_init(ar); 2734 if (ret) { 2735 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n", 2736 ret); 2737 return ret; 2738 } 2739 2740 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca988x chip reset complete (cold)\n"); 2741 2742 return 0; 2743 } 2744 2745 static int ath10k_pci_qca6174_chip_reset(struct ath10k *ar) 2746 { 2747 int ret; 2748 2749 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset\n"); 2750 2751 /* FIXME: QCA6174 requires cold + warm reset to work. */ 2752 2753 ret = ath10k_pci_cold_reset(ar); 2754 if (ret) { 2755 ath10k_warn(ar, "failed to cold reset: %d\n", ret); 2756 return ret; 2757 } 2758 2759 ret = ath10k_pci_wait_for_target_init(ar); 2760 if (ret) { 2761 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n", 2762 ret); 2763 return ret; 2764 } 2765 2766 ret = ath10k_pci_warm_reset(ar); 2767 if (ret) { 2768 ath10k_warn(ar, "failed to warm reset: %d\n", ret); 2769 return ret; 2770 } 2771 2772 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset complete (cold)\n"); 2773 2774 return 0; 2775 } 2776 2777 static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar) 2778 { 2779 int ret; 2780 2781 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca99x0 chip reset\n"); 2782 2783 ret = ath10k_pci_cold_reset(ar); 2784 if (ret) { 2785 ath10k_warn(ar, "failed to cold reset: %d\n", ret); 2786 return ret; 2787 } 2788 2789 ret = ath10k_pci_wait_for_target_init(ar); 2790 if (ret) { 2791 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n", 2792 ret); 2793 return ret; 2794 } 2795 2796 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca99x0 chip reset complete (cold)\n"); 2797 2798 return 0; 2799 } 2800 2801 static int ath10k_pci_chip_reset(struct ath10k *ar) 2802 { 2803 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2804 2805 if (WARN_ON(!ar_pci->pci_hard_reset)) 2806 return -ENOTSUPP; 2807 2808 return ar_pci->pci_hard_reset(ar); 2809 } 2810 2811 static int ath10k_pci_hif_power_up(struct ath10k *ar) 2812 { 2813 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2814 int ret; 2815 2816 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power up\n"); 2817 2818 pcie_capability_read_word(ar_pci->pdev, PCI_EXP_LNKCTL, 2819 &ar_pci->link_ctl); 2820 pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL, 2821 ar_pci->link_ctl & ~PCI_EXP_LNKCTL_ASPMC); 2822 2823 /* 2824 * Bring the target up cleanly. 2825 * 2826 * The target may be in an undefined state with an AUX-powered Target 2827 * and a Host in WoW mode. If the Host crashes, loses power, or is 2828 * restarted (without unloading the driver) then the Target is left 2829 * (aux) powered and running. On a subsequent driver load, the Target 2830 * is in an unexpected state. We try to catch that here in order to 2831 * reset the Target and retry the probe. 2832 */ 2833 ret = ath10k_pci_chip_reset(ar); 2834 if (ret) { 2835 if (ath10k_pci_has_fw_crashed(ar)) { 2836 ath10k_warn(ar, "firmware crashed during chip reset\n"); 2837 ath10k_pci_fw_crashed_clear(ar); 2838 ath10k_pci_fw_crashed_dump(ar); 2839 } 2840 2841 ath10k_err(ar, "failed to reset chip: %d\n", ret); 2842 goto err_sleep; 2843 } 2844 2845 ret = ath10k_pci_init_pipes(ar); 2846 if (ret) { 2847 ath10k_err(ar, "failed to initialize CE: %d\n", ret); 2848 goto err_sleep; 2849 } 2850 2851 ret = ath10k_pci_init_config(ar); 2852 if (ret) { 2853 ath10k_err(ar, "failed to setup init config: %d\n", ret); 2854 goto err_ce; 2855 } 2856 2857 ret = ath10k_pci_wake_target_cpu(ar); 2858 if (ret) { 2859 ath10k_err(ar, "could not wake up target CPU: %d\n", ret); 2860 goto err_ce; 2861 } 2862 2863 return 0; 2864 2865 err_ce: 2866 ath10k_pci_ce_deinit(ar); 2867 2868 err_sleep: 2869 return ret; 2870 } 2871 2872 void ath10k_pci_hif_power_down(struct ath10k *ar) 2873 { 2874 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power down\n"); 2875 2876 /* Currently hif_power_up performs effectively a reset and hif_stop 2877 * resets the chip as well so there's no point in resetting here. 2878 */ 2879 } 2880 2881 static int ath10k_pci_hif_suspend(struct ath10k *ar) 2882 { 2883 /* Nothing to do; the important stuff is in the driver suspend. */ 2884 return 0; 2885 } 2886 2887 static int ath10k_pci_suspend(struct ath10k *ar) 2888 { 2889 /* The grace timer can still be counting down and ar->ps_awake be true. 2890 * It is known that the device may be asleep after resuming regardless 2891 * of the SoC powersave state before suspending. Hence make sure the 2892 * device is asleep before proceeding. 2893 */ 2894 ath10k_pci_sleep_sync(ar); 2895 2896 return 0; 2897 } 2898 2899 static int ath10k_pci_hif_resume(struct ath10k *ar) 2900 { 2901 /* Nothing to do; the important stuff is in the driver resume. */ 2902 return 0; 2903 } 2904 2905 static int ath10k_pci_resume(struct ath10k *ar) 2906 { 2907 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2908 struct pci_dev *pdev = ar_pci->pdev; 2909 u32 val; 2910 int ret = 0; 2911 2912 ret = ath10k_pci_force_wake(ar); 2913 if (ret) { 2914 ath10k_err(ar, "failed to wake up target: %d\n", ret); 2915 return ret; 2916 } 2917 2918 /* Suspend/Resume resets the PCI configuration space, so we have to 2919 * re-disable the RETRY_TIMEOUT register (0x41) to keep PCI Tx retries 2920 * from interfering with C3 CPU state. pci_restore_state won't help 2921 * here since it only restores the first 64 bytes pci config header. 2922 */ 2923 pci_read_config_dword(pdev, 0x40, &val); 2924 if ((val & 0x0000ff00) != 0) 2925 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); 2926 2927 return ret; 2928 } 2929 2930 static bool ath10k_pci_validate_cal(void *data, size_t size) 2931 { 2932 __le16 *cal_words = data; 2933 u16 checksum = 0; 2934 size_t i; 2935 2936 if (size % 2 != 0) 2937 return false; 2938 2939 for (i = 0; i < size / 2; i++) 2940 checksum ^= le16_to_cpu(cal_words[i]); 2941 2942 return checksum == 0xffff; 2943 } 2944 2945 static void ath10k_pci_enable_eeprom(struct ath10k *ar) 2946 { 2947 /* Enable SI clock */ 2948 ath10k_pci_soc_write32(ar, CLOCK_CONTROL_OFFSET, 0x0); 2949 2950 /* Configure GPIOs for I2C operation */ 2951 ath10k_pci_write32(ar, 2952 GPIO_BASE_ADDRESS + GPIO_PIN0_OFFSET + 2953 4 * QCA9887_1_0_I2C_SDA_GPIO_PIN, 2954 SM(QCA9887_1_0_I2C_SDA_PIN_CONFIG, 2955 GPIO_PIN0_CONFIG) | 2956 SM(1, GPIO_PIN0_PAD_PULL)); 2957 2958 ath10k_pci_write32(ar, 2959 GPIO_BASE_ADDRESS + GPIO_PIN0_OFFSET + 2960 4 * QCA9887_1_0_SI_CLK_GPIO_PIN, 2961 SM(QCA9887_1_0_SI_CLK_PIN_CONFIG, GPIO_PIN0_CONFIG) | 2962 SM(1, GPIO_PIN0_PAD_PULL)); 2963 2964 ath10k_pci_write32(ar, 2965 GPIO_BASE_ADDRESS + 2966 QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS, 2967 1u << QCA9887_1_0_SI_CLK_GPIO_PIN); 2968 2969 /* In Swift ASIC - EEPROM clock will be (110MHz/512) = 214KHz */ 2970 ath10k_pci_write32(ar, 2971 SI_BASE_ADDRESS + SI_CONFIG_OFFSET, 2972 SM(1, SI_CONFIG_ERR_INT) | 2973 SM(1, SI_CONFIG_BIDIR_OD_DATA) | 2974 SM(1, SI_CONFIG_I2C) | 2975 SM(1, SI_CONFIG_POS_SAMPLE) | 2976 SM(1, SI_CONFIG_INACTIVE_DATA) | 2977 SM(1, SI_CONFIG_INACTIVE_CLK) | 2978 SM(8, SI_CONFIG_DIVIDER)); 2979 } 2980 2981 static int ath10k_pci_read_eeprom(struct ath10k *ar, u16 addr, u8 *out) 2982 { 2983 u32 reg; 2984 int wait_limit; 2985 2986 /* set device select byte and for the read operation */ 2987 reg = QCA9887_EEPROM_SELECT_READ | 2988 SM(addr, QCA9887_EEPROM_ADDR_LO) | 2989 SM(addr >> 8, QCA9887_EEPROM_ADDR_HI); 2990 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_TX_DATA0_OFFSET, reg); 2991 2992 /* write transmit data, transfer length, and START bit */ 2993 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET, 2994 SM(1, SI_CS_START) | SM(1, SI_CS_RX_CNT) | 2995 SM(4, SI_CS_TX_CNT)); 2996 2997 /* wait max 1 sec */ 2998 wait_limit = 100000; 2999 3000 /* wait for SI_CS_DONE_INT */ 3001 do { 3002 reg = ath10k_pci_read32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET); 3003 if (MS(reg, SI_CS_DONE_INT)) 3004 break; 3005 3006 wait_limit--; 3007 udelay(10); 3008 } while (wait_limit > 0); 3009 3010 if (!MS(reg, SI_CS_DONE_INT)) { 3011 ath10k_err(ar, "timeout while reading device EEPROM at %04x\n", 3012 addr); 3013 return -ETIMEDOUT; 3014 } 3015 3016 /* clear SI_CS_DONE_INT */ 3017 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET, reg); 3018 3019 if (MS(reg, SI_CS_DONE_ERR)) { 3020 ath10k_err(ar, "failed to read device EEPROM at %04x\n", addr); 3021 return -EIO; 3022 } 3023 3024 /* extract receive data */ 3025 reg = ath10k_pci_read32(ar, SI_BASE_ADDRESS + SI_RX_DATA0_OFFSET); 3026 *out = reg; 3027 3028 return 0; 3029 } 3030 3031 static int ath10k_pci_hif_fetch_cal_eeprom(struct ath10k *ar, void **data, 3032 size_t *data_len) 3033 { 3034 u8 *caldata = NULL; 3035 size_t calsize, i; 3036 int ret; 3037 3038 if (!QCA_REV_9887(ar)) 3039 return -EOPNOTSUPP; 3040 3041 calsize = ar->hw_params.cal_data_len; 3042 caldata = kmalloc(calsize, GFP_KERNEL); 3043 if (!caldata) 3044 return -ENOMEM; 3045 3046 ath10k_pci_enable_eeprom(ar); 3047 3048 for (i = 0; i < calsize; i++) { 3049 ret = ath10k_pci_read_eeprom(ar, i, &caldata[i]); 3050 if (ret) 3051 goto err_free; 3052 } 3053 3054 if (!ath10k_pci_validate_cal(caldata, calsize)) 3055 goto err_free; 3056 3057 *data = caldata; 3058 *data_len = calsize; 3059 3060 return 0; 3061 3062 err_free: 3063 kfree(caldata); 3064 3065 return -EINVAL; 3066 } 3067 3068 static const struct ath10k_hif_ops ath10k_pci_hif_ops = { 3069 .tx_sg = ath10k_pci_hif_tx_sg, 3070 .diag_read = ath10k_pci_hif_diag_read, 3071 .diag_write = ath10k_pci_diag_write_mem, 3072 .exchange_bmi_msg = ath10k_pci_hif_exchange_bmi_msg, 3073 .start = ath10k_pci_hif_start, 3074 .stop = ath10k_pci_hif_stop, 3075 .map_service_to_pipe = ath10k_pci_hif_map_service_to_pipe, 3076 .get_default_pipe = ath10k_pci_hif_get_default_pipe, 3077 .send_complete_check = ath10k_pci_hif_send_complete_check, 3078 .get_free_queue_number = ath10k_pci_hif_get_free_queue_number, 3079 .power_up = ath10k_pci_hif_power_up, 3080 .power_down = ath10k_pci_hif_power_down, 3081 .read32 = ath10k_pci_read32, 3082 .write32 = ath10k_pci_write32, 3083 .suspend = ath10k_pci_hif_suspend, 3084 .resume = ath10k_pci_hif_resume, 3085 .fetch_cal_eeprom = ath10k_pci_hif_fetch_cal_eeprom, 3086 }; 3087 3088 /* 3089 * Top-level interrupt handler for all PCI interrupts from a Target. 3090 * When a block of MSI interrupts is allocated, this top-level handler 3091 * is not used; instead, we directly call the correct sub-handler. 3092 */ 3093 static irqreturn_t ath10k_pci_interrupt_handler(int irq, void *arg) 3094 { 3095 struct ath10k *ar = arg; 3096 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3097 int ret; 3098 3099 if (ath10k_pci_has_device_gone(ar)) 3100 return IRQ_NONE; 3101 3102 ret = ath10k_pci_force_wake(ar); 3103 if (ret) { 3104 ath10k_warn(ar, "failed to wake device up on irq: %d\n", ret); 3105 return IRQ_NONE; 3106 } 3107 3108 if ((ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_LEGACY) && 3109 !ath10k_pci_irq_pending(ar)) 3110 return IRQ_NONE; 3111 3112 ath10k_pci_disable_and_clear_legacy_irq(ar); 3113 ath10k_pci_irq_msi_fw_mask(ar); 3114 napi_schedule(&ar->napi); 3115 3116 return IRQ_HANDLED; 3117 } 3118 3119 static int ath10k_pci_napi_poll(struct napi_struct *ctx, int budget) 3120 { 3121 struct ath10k *ar = container_of(ctx, struct ath10k, napi); 3122 int done = 0; 3123 3124 if (ath10k_pci_has_fw_crashed(ar)) { 3125 ath10k_pci_fw_crashed_clear(ar); 3126 ath10k_pci_fw_crashed_dump(ar); 3127 napi_complete(ctx); 3128 return done; 3129 } 3130 3131 ath10k_ce_per_engine_service_any(ar); 3132 3133 done = ath10k_htt_txrx_compl_task(ar, budget); 3134 3135 if (done < budget) { 3136 napi_complete_done(ctx, done); 3137 /* In case of MSI, it is possible that interrupts are received 3138 * while NAPI poll is inprogress. So pending interrupts that are 3139 * received after processing all copy engine pipes by NAPI poll 3140 * will not be handled again. This is causing failure to 3141 * complete boot sequence in x86 platform. So before enabling 3142 * interrupts safer to check for pending interrupts for 3143 * immediate servicing. 3144 */ 3145 if (ath10k_ce_interrupt_summary(ar)) { 3146 napi_reschedule(ctx); 3147 goto out; 3148 } 3149 ath10k_pci_enable_legacy_irq(ar); 3150 ath10k_pci_irq_msi_fw_unmask(ar); 3151 } 3152 3153 out: 3154 return done; 3155 } 3156 3157 static int ath10k_pci_request_irq_msi(struct ath10k *ar) 3158 { 3159 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3160 int ret; 3161 3162 ret = request_irq(ar_pci->pdev->irq, 3163 ath10k_pci_interrupt_handler, 3164 IRQF_SHARED, "ath10k_pci", ar); 3165 if (ret) { 3166 ath10k_warn(ar, "failed to request MSI irq %d: %d\n", 3167 ar_pci->pdev->irq, ret); 3168 return ret; 3169 } 3170 3171 return 0; 3172 } 3173 3174 static int ath10k_pci_request_irq_legacy(struct ath10k *ar) 3175 { 3176 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3177 int ret; 3178 3179 ret = request_irq(ar_pci->pdev->irq, 3180 ath10k_pci_interrupt_handler, 3181 IRQF_SHARED, "ath10k_pci", ar); 3182 if (ret) { 3183 ath10k_warn(ar, "failed to request legacy irq %d: %d\n", 3184 ar_pci->pdev->irq, ret); 3185 return ret; 3186 } 3187 3188 return 0; 3189 } 3190 3191 static int ath10k_pci_request_irq(struct ath10k *ar) 3192 { 3193 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3194 3195 switch (ar_pci->oper_irq_mode) { 3196 case ATH10K_PCI_IRQ_LEGACY: 3197 return ath10k_pci_request_irq_legacy(ar); 3198 case ATH10K_PCI_IRQ_MSI: 3199 return ath10k_pci_request_irq_msi(ar); 3200 default: 3201 return -EINVAL; 3202 } 3203 } 3204 3205 static void ath10k_pci_free_irq(struct ath10k *ar) 3206 { 3207 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3208 3209 free_irq(ar_pci->pdev->irq, ar); 3210 } 3211 3212 void ath10k_pci_init_napi(struct ath10k *ar) 3213 { 3214 netif_napi_add(&ar->napi_dev, &ar->napi, ath10k_pci_napi_poll, 3215 ATH10K_NAPI_BUDGET); 3216 } 3217 3218 static int ath10k_pci_init_irq(struct ath10k *ar) 3219 { 3220 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3221 int ret; 3222 3223 ath10k_pci_init_napi(ar); 3224 3225 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_AUTO) 3226 ath10k_info(ar, "limiting irq mode to: %d\n", 3227 ath10k_pci_irq_mode); 3228 3229 /* Try MSI */ 3230 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_LEGACY) { 3231 ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_MSI; 3232 ret = pci_enable_msi(ar_pci->pdev); 3233 if (ret == 0) 3234 return 0; 3235 3236 /* fall-through */ 3237 } 3238 3239 /* Try legacy irq 3240 * 3241 * A potential race occurs here: The CORE_BASE write 3242 * depends on target correctly decoding AXI address but 3243 * host won't know when target writes BAR to CORE_CTRL. 3244 * This write might get lost if target has NOT written BAR. 3245 * For now, fix the race by repeating the write in below 3246 * synchronization checking. 3247 */ 3248 ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_LEGACY; 3249 3250 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS, 3251 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); 3252 3253 return 0; 3254 } 3255 3256 static void ath10k_pci_deinit_irq_legacy(struct ath10k *ar) 3257 { 3258 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS, 3259 0); 3260 } 3261 3262 static int ath10k_pci_deinit_irq(struct ath10k *ar) 3263 { 3264 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3265 3266 switch (ar_pci->oper_irq_mode) { 3267 case ATH10K_PCI_IRQ_LEGACY: 3268 ath10k_pci_deinit_irq_legacy(ar); 3269 break; 3270 default: 3271 pci_disable_msi(ar_pci->pdev); 3272 break; 3273 } 3274 3275 return 0; 3276 } 3277 3278 int ath10k_pci_wait_for_target_init(struct ath10k *ar) 3279 { 3280 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3281 unsigned long timeout; 3282 u32 val; 3283 3284 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot waiting target to initialise\n"); 3285 3286 timeout = jiffies + msecs_to_jiffies(ATH10K_PCI_TARGET_WAIT); 3287 3288 do { 3289 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS); 3290 3291 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target indicator %x\n", 3292 val); 3293 3294 /* target should never return this */ 3295 if (val == 0xffffffff) 3296 continue; 3297 3298 /* the device has crashed so don't bother trying anymore */ 3299 if (val & FW_IND_EVENT_PENDING) 3300 break; 3301 3302 if (val & FW_IND_INITIALIZED) 3303 break; 3304 3305 if (ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_LEGACY) 3306 /* Fix potential race by repeating CORE_BASE writes */ 3307 ath10k_pci_enable_legacy_irq(ar); 3308 3309 mdelay(10); 3310 } while (time_before(jiffies, timeout)); 3311 3312 ath10k_pci_disable_and_clear_legacy_irq(ar); 3313 ath10k_pci_irq_msi_fw_mask(ar); 3314 3315 if (val == 0xffffffff) { 3316 ath10k_err(ar, "failed to read device register, device is gone\n"); 3317 return -EIO; 3318 } 3319 3320 if (val & FW_IND_EVENT_PENDING) { 3321 ath10k_warn(ar, "device has crashed during init\n"); 3322 return -ECOMM; 3323 } 3324 3325 if (!(val & FW_IND_INITIALIZED)) { 3326 ath10k_err(ar, "failed to receive initialized event from target: %08x\n", 3327 val); 3328 return -ETIMEDOUT; 3329 } 3330 3331 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target initialised\n"); 3332 return 0; 3333 } 3334 3335 static int ath10k_pci_cold_reset(struct ath10k *ar) 3336 { 3337 u32 val; 3338 3339 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset\n"); 3340 3341 spin_lock_bh(&ar->data_lock); 3342 3343 ar->stats.fw_cold_reset_counter++; 3344 3345 spin_unlock_bh(&ar->data_lock); 3346 3347 /* Put Target, including PCIe, into RESET. */ 3348 val = ath10k_pci_reg_read32(ar, SOC_GLOBAL_RESET_ADDRESS); 3349 val |= 1; 3350 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val); 3351 3352 /* After writing into SOC_GLOBAL_RESET to put device into 3353 * reset and pulling out of reset pcie may not be stable 3354 * for any immediate pcie register access and cause bus error, 3355 * add delay before any pcie access request to fix this issue. 3356 */ 3357 msleep(20); 3358 3359 /* Pull Target, including PCIe, out of RESET. */ 3360 val &= ~1; 3361 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val); 3362 3363 msleep(20); 3364 3365 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset complete\n"); 3366 3367 return 0; 3368 } 3369 3370 static int ath10k_pci_claim(struct ath10k *ar) 3371 { 3372 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3373 struct pci_dev *pdev = ar_pci->pdev; 3374 int ret; 3375 3376 pci_set_drvdata(pdev, ar); 3377 3378 ret = pci_enable_device(pdev); 3379 if (ret) { 3380 ath10k_err(ar, "failed to enable pci device: %d\n", ret); 3381 return ret; 3382 } 3383 3384 ret = pci_request_region(pdev, BAR_NUM, "ath"); 3385 if (ret) { 3386 ath10k_err(ar, "failed to request region BAR%d: %d\n", BAR_NUM, 3387 ret); 3388 goto err_device; 3389 } 3390 3391 /* Target expects 32 bit DMA. Enforce it. */ 3392 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 3393 if (ret) { 3394 ath10k_err(ar, "failed to set dma mask to 32-bit: %d\n", ret); 3395 goto err_region; 3396 } 3397 3398 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 3399 if (ret) { 3400 ath10k_err(ar, "failed to set consistent dma mask to 32-bit: %d\n", 3401 ret); 3402 goto err_region; 3403 } 3404 3405 pci_set_master(pdev); 3406 3407 /* Arrange for access to Target SoC registers. */ 3408 ar_pci->mem_len = pci_resource_len(pdev, BAR_NUM); 3409 ar_pci->mem = pci_iomap(pdev, BAR_NUM, 0); 3410 if (!ar_pci->mem) { 3411 ath10k_err(ar, "failed to iomap BAR%d\n", BAR_NUM); 3412 ret = -EIO; 3413 goto err_master; 3414 } 3415 3416 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot pci_mem 0x%pK\n", ar_pci->mem); 3417 return 0; 3418 3419 err_master: 3420 pci_clear_master(pdev); 3421 3422 err_region: 3423 pci_release_region(pdev, BAR_NUM); 3424 3425 err_device: 3426 pci_disable_device(pdev); 3427 3428 return ret; 3429 } 3430 3431 static void ath10k_pci_release(struct ath10k *ar) 3432 { 3433 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3434 struct pci_dev *pdev = ar_pci->pdev; 3435 3436 pci_iounmap(pdev, ar_pci->mem); 3437 pci_release_region(pdev, BAR_NUM); 3438 pci_clear_master(pdev); 3439 pci_disable_device(pdev); 3440 } 3441 3442 static bool ath10k_pci_chip_is_supported(u32 dev_id, u32 chip_id) 3443 { 3444 const struct ath10k_pci_supp_chip *supp_chip; 3445 int i; 3446 u32 rev_id = MS(chip_id, SOC_CHIP_ID_REV); 3447 3448 for (i = 0; i < ARRAY_SIZE(ath10k_pci_supp_chips); i++) { 3449 supp_chip = &ath10k_pci_supp_chips[i]; 3450 3451 if (supp_chip->dev_id == dev_id && 3452 supp_chip->rev_id == rev_id) 3453 return true; 3454 } 3455 3456 return false; 3457 } 3458 3459 int ath10k_pci_setup_resource(struct ath10k *ar) 3460 { 3461 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3462 struct ath10k_ce *ce = ath10k_ce_priv(ar); 3463 int ret; 3464 3465 spin_lock_init(&ce->ce_lock); 3466 spin_lock_init(&ar_pci->ps_lock); 3467 3468 timer_setup(&ar_pci->rx_post_retry, ath10k_pci_rx_replenish_retry, 0); 3469 3470 if (QCA_REV_6174(ar) || QCA_REV_9377(ar)) 3471 ath10k_pci_override_ce_config(ar); 3472 3473 ret = ath10k_pci_alloc_pipes(ar); 3474 if (ret) { 3475 ath10k_err(ar, "failed to allocate copy engine pipes: %d\n", 3476 ret); 3477 return ret; 3478 } 3479 3480 return 0; 3481 } 3482 3483 void ath10k_pci_release_resource(struct ath10k *ar) 3484 { 3485 ath10k_pci_rx_retry_sync(ar); 3486 netif_napi_del(&ar->napi); 3487 ath10k_pci_ce_deinit(ar); 3488 ath10k_pci_free_pipes(ar); 3489 } 3490 3491 static const struct ath10k_bus_ops ath10k_pci_bus_ops = { 3492 .read32 = ath10k_bus_pci_read32, 3493 .write32 = ath10k_bus_pci_write32, 3494 .get_num_banks = ath10k_pci_get_num_banks, 3495 }; 3496 3497 static int ath10k_pci_probe(struct pci_dev *pdev, 3498 const struct pci_device_id *pci_dev) 3499 { 3500 int ret = 0; 3501 struct ath10k *ar; 3502 struct ath10k_pci *ar_pci; 3503 enum ath10k_hw_rev hw_rev; 3504 struct ath10k_bus_params bus_params; 3505 bool pci_ps; 3506 int (*pci_soft_reset)(struct ath10k *ar); 3507 int (*pci_hard_reset)(struct ath10k *ar); 3508 u32 (*targ_cpu_to_ce_addr)(struct ath10k *ar, u32 addr); 3509 3510 switch (pci_dev->device) { 3511 case QCA988X_2_0_DEVICE_ID_UBNT: 3512 case QCA988X_2_0_DEVICE_ID: 3513 hw_rev = ATH10K_HW_QCA988X; 3514 pci_ps = false; 3515 pci_soft_reset = ath10k_pci_warm_reset; 3516 pci_hard_reset = ath10k_pci_qca988x_chip_reset; 3517 targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr; 3518 break; 3519 case QCA9887_1_0_DEVICE_ID: 3520 hw_rev = ATH10K_HW_QCA9887; 3521 pci_ps = false; 3522 pci_soft_reset = ath10k_pci_warm_reset; 3523 pci_hard_reset = ath10k_pci_qca988x_chip_reset; 3524 targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr; 3525 break; 3526 case QCA6164_2_1_DEVICE_ID: 3527 case QCA6174_2_1_DEVICE_ID: 3528 hw_rev = ATH10K_HW_QCA6174; 3529 pci_ps = true; 3530 pci_soft_reset = ath10k_pci_warm_reset; 3531 pci_hard_reset = ath10k_pci_qca6174_chip_reset; 3532 targ_cpu_to_ce_addr = ath10k_pci_qca6174_targ_cpu_to_ce_addr; 3533 break; 3534 case QCA99X0_2_0_DEVICE_ID: 3535 hw_rev = ATH10K_HW_QCA99X0; 3536 pci_ps = false; 3537 pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset; 3538 pci_hard_reset = ath10k_pci_qca99x0_chip_reset; 3539 targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr; 3540 break; 3541 case QCA9984_1_0_DEVICE_ID: 3542 hw_rev = ATH10K_HW_QCA9984; 3543 pci_ps = false; 3544 pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset; 3545 pci_hard_reset = ath10k_pci_qca99x0_chip_reset; 3546 targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr; 3547 break; 3548 case QCA9888_2_0_DEVICE_ID: 3549 hw_rev = ATH10K_HW_QCA9888; 3550 pci_ps = false; 3551 pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset; 3552 pci_hard_reset = ath10k_pci_qca99x0_chip_reset; 3553 targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr; 3554 break; 3555 case QCA9377_1_0_DEVICE_ID: 3556 hw_rev = ATH10K_HW_QCA9377; 3557 pci_ps = true; 3558 pci_soft_reset = NULL; 3559 pci_hard_reset = ath10k_pci_qca6174_chip_reset; 3560 targ_cpu_to_ce_addr = ath10k_pci_qca6174_targ_cpu_to_ce_addr; 3561 break; 3562 default: 3563 WARN_ON(1); 3564 return -ENOTSUPP; 3565 } 3566 3567 ar = ath10k_core_create(sizeof(*ar_pci), &pdev->dev, ATH10K_BUS_PCI, 3568 hw_rev, &ath10k_pci_hif_ops); 3569 if (!ar) { 3570 dev_err(&pdev->dev, "failed to allocate core\n"); 3571 return -ENOMEM; 3572 } 3573 3574 ath10k_dbg(ar, ATH10K_DBG_BOOT, "pci probe %04x:%04x %04x:%04x\n", 3575 pdev->vendor, pdev->device, 3576 pdev->subsystem_vendor, pdev->subsystem_device); 3577 3578 ar_pci = ath10k_pci_priv(ar); 3579 ar_pci->pdev = pdev; 3580 ar_pci->dev = &pdev->dev; 3581 ar_pci->ar = ar; 3582 ar->dev_id = pci_dev->device; 3583 ar_pci->pci_ps = pci_ps; 3584 ar_pci->ce.bus_ops = &ath10k_pci_bus_ops; 3585 ar_pci->pci_soft_reset = pci_soft_reset; 3586 ar_pci->pci_hard_reset = pci_hard_reset; 3587 ar_pci->targ_cpu_to_ce_addr = targ_cpu_to_ce_addr; 3588 ar->ce_priv = &ar_pci->ce; 3589 3590 ar->id.vendor = pdev->vendor; 3591 ar->id.device = pdev->device; 3592 ar->id.subsystem_vendor = pdev->subsystem_vendor; 3593 ar->id.subsystem_device = pdev->subsystem_device; 3594 3595 timer_setup(&ar_pci->ps_timer, ath10k_pci_ps_timer, 0); 3596 3597 ret = ath10k_pci_setup_resource(ar); 3598 if (ret) { 3599 ath10k_err(ar, "failed to setup resource: %d\n", ret); 3600 goto err_core_destroy; 3601 } 3602 3603 ret = ath10k_pci_claim(ar); 3604 if (ret) { 3605 ath10k_err(ar, "failed to claim device: %d\n", ret); 3606 goto err_free_pipes; 3607 } 3608 3609 ret = ath10k_pci_force_wake(ar); 3610 if (ret) { 3611 ath10k_warn(ar, "failed to wake up device : %d\n", ret); 3612 goto err_sleep; 3613 } 3614 3615 ath10k_pci_ce_deinit(ar); 3616 ath10k_pci_irq_disable(ar); 3617 3618 ret = ath10k_pci_init_irq(ar); 3619 if (ret) { 3620 ath10k_err(ar, "failed to init irqs: %d\n", ret); 3621 goto err_sleep; 3622 } 3623 3624 ath10k_info(ar, "pci irq %s oper_irq_mode %d irq_mode %d reset_mode %d\n", 3625 ath10k_pci_get_irq_method(ar), ar_pci->oper_irq_mode, 3626 ath10k_pci_irq_mode, ath10k_pci_reset_mode); 3627 3628 ret = ath10k_pci_request_irq(ar); 3629 if (ret) { 3630 ath10k_warn(ar, "failed to request irqs: %d\n", ret); 3631 goto err_deinit_irq; 3632 } 3633 3634 ret = ath10k_pci_chip_reset(ar); 3635 if (ret) { 3636 ath10k_err(ar, "failed to reset chip: %d\n", ret); 3637 goto err_free_irq; 3638 } 3639 3640 bus_params.dev_type = ATH10K_DEV_TYPE_LL; 3641 bus_params.chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS); 3642 if (bus_params.chip_id == 0xffffffff) { 3643 ath10k_err(ar, "failed to get chip id\n"); 3644 goto err_free_irq; 3645 } 3646 3647 if (!ath10k_pci_chip_is_supported(pdev->device, bus_params.chip_id)) { 3648 ath10k_err(ar, "device %04x with chip_id %08x isn't supported\n", 3649 pdev->device, bus_params.chip_id); 3650 goto err_free_irq; 3651 } 3652 3653 ret = ath10k_core_register(ar, &bus_params); 3654 if (ret) { 3655 ath10k_err(ar, "failed to register driver core: %d\n", ret); 3656 goto err_free_irq; 3657 } 3658 3659 return 0; 3660 3661 err_free_irq: 3662 ath10k_pci_free_irq(ar); 3663 ath10k_pci_rx_retry_sync(ar); 3664 3665 err_deinit_irq: 3666 ath10k_pci_deinit_irq(ar); 3667 3668 err_sleep: 3669 ath10k_pci_sleep_sync(ar); 3670 ath10k_pci_release(ar); 3671 3672 err_free_pipes: 3673 ath10k_pci_free_pipes(ar); 3674 3675 err_core_destroy: 3676 ath10k_core_destroy(ar); 3677 3678 return ret; 3679 } 3680 3681 static void ath10k_pci_remove(struct pci_dev *pdev) 3682 { 3683 struct ath10k *ar = pci_get_drvdata(pdev); 3684 struct ath10k_pci *ar_pci; 3685 3686 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci remove\n"); 3687 3688 if (!ar) 3689 return; 3690 3691 ar_pci = ath10k_pci_priv(ar); 3692 3693 if (!ar_pci) 3694 return; 3695 3696 ath10k_core_unregister(ar); 3697 ath10k_pci_free_irq(ar); 3698 ath10k_pci_deinit_irq(ar); 3699 ath10k_pci_release_resource(ar); 3700 ath10k_pci_sleep_sync(ar); 3701 ath10k_pci_release(ar); 3702 ath10k_core_destroy(ar); 3703 } 3704 3705 MODULE_DEVICE_TABLE(pci, ath10k_pci_id_table); 3706 3707 static __maybe_unused int ath10k_pci_pm_suspend(struct device *dev) 3708 { 3709 struct ath10k *ar = dev_get_drvdata(dev); 3710 int ret; 3711 3712 ret = ath10k_pci_suspend(ar); 3713 if (ret) 3714 ath10k_warn(ar, "failed to suspend hif: %d\n", ret); 3715 3716 return ret; 3717 } 3718 3719 static __maybe_unused int ath10k_pci_pm_resume(struct device *dev) 3720 { 3721 struct ath10k *ar = dev_get_drvdata(dev); 3722 int ret; 3723 3724 ret = ath10k_pci_resume(ar); 3725 if (ret) 3726 ath10k_warn(ar, "failed to resume hif: %d\n", ret); 3727 3728 return ret; 3729 } 3730 3731 static SIMPLE_DEV_PM_OPS(ath10k_pci_pm_ops, 3732 ath10k_pci_pm_suspend, 3733 ath10k_pci_pm_resume); 3734 3735 static struct pci_driver ath10k_pci_driver = { 3736 .name = "ath10k_pci", 3737 .id_table = ath10k_pci_id_table, 3738 .probe = ath10k_pci_probe, 3739 .remove = ath10k_pci_remove, 3740 #ifdef CONFIG_PM 3741 .driver.pm = &ath10k_pci_pm_ops, 3742 #endif 3743 }; 3744 3745 static int __init ath10k_pci_init(void) 3746 { 3747 int ret; 3748 3749 ret = pci_register_driver(&ath10k_pci_driver); 3750 if (ret) 3751 printk(KERN_ERR "failed to register ath10k pci driver: %d\n", 3752 ret); 3753 3754 ret = ath10k_ahb_init(); 3755 if (ret) 3756 printk(KERN_ERR "ahb init failed: %d\n", ret); 3757 3758 return ret; 3759 } 3760 module_init(ath10k_pci_init); 3761 3762 static void __exit ath10k_pci_exit(void) 3763 { 3764 pci_unregister_driver(&ath10k_pci_driver); 3765 ath10k_ahb_exit(); 3766 } 3767 3768 module_exit(ath10k_pci_exit); 3769 3770 MODULE_AUTHOR("Qualcomm Atheros"); 3771 MODULE_DESCRIPTION("Driver support for Qualcomm Atheros 802.11ac WLAN PCIe/AHB devices"); 3772 MODULE_LICENSE("Dual BSD/GPL"); 3773 3774 /* QCA988x 2.0 firmware files */ 3775 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API2_FILE); 3776 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API3_FILE); 3777 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API4_FILE); 3778 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API5_FILE); 3779 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_BOARD_DATA_FILE); 3780 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_BOARD_API2_FILE); 3781 3782 /* QCA9887 1.0 firmware files */ 3783 MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" ATH10K_FW_API5_FILE); 3784 MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" QCA9887_HW_1_0_BOARD_DATA_FILE); 3785 MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" ATH10K_BOARD_API2_FILE); 3786 3787 /* QCA6174 2.1 firmware files */ 3788 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_FW_API4_FILE); 3789 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_FW_API5_FILE); 3790 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" QCA6174_HW_2_1_BOARD_DATA_FILE); 3791 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_BOARD_API2_FILE); 3792 3793 /* QCA6174 3.1 firmware files */ 3794 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API4_FILE); 3795 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API5_FILE); 3796 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API6_FILE); 3797 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" QCA6174_HW_3_0_BOARD_DATA_FILE); 3798 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_BOARD_API2_FILE); 3799 3800 /* QCA9377 1.0 firmware files */ 3801 MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" ATH10K_FW_API6_FILE); 3802 MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" ATH10K_FW_API5_FILE); 3803 MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" QCA9377_HW_1_0_BOARD_DATA_FILE); 3804