1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (c) 2005-2011 Atheros Communications Inc. 4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. 5 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. 6 */ 7 8 #include <linux/pci.h> 9 #include <linux/module.h> 10 #include <linux/interrupt.h> 11 #include <linux/spinlock.h> 12 #include <linux/bitops.h> 13 14 #include "core.h" 15 #include "debug.h" 16 #include "coredump.h" 17 18 #include "targaddrs.h" 19 #include "bmi.h" 20 21 #include "hif.h" 22 #include "htc.h" 23 24 #include "ce.h" 25 #include "pci.h" 26 27 enum ath10k_pci_reset_mode { 28 ATH10K_PCI_RESET_AUTO = 0, 29 ATH10K_PCI_RESET_WARM_ONLY = 1, 30 }; 31 32 static unsigned int ath10k_pci_irq_mode = ATH10K_PCI_IRQ_AUTO; 33 static unsigned int ath10k_pci_reset_mode = ATH10K_PCI_RESET_AUTO; 34 35 module_param_named(irq_mode, ath10k_pci_irq_mode, uint, 0644); 36 MODULE_PARM_DESC(irq_mode, "0: auto, 1: legacy, 2: msi (default: 0)"); 37 38 module_param_named(reset_mode, ath10k_pci_reset_mode, uint, 0644); 39 MODULE_PARM_DESC(reset_mode, "0: auto, 1: warm only (default: 0)"); 40 41 /* how long wait to wait for target to initialise, in ms */ 42 #define ATH10K_PCI_TARGET_WAIT 3000 43 #define ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS 3 44 45 /* Maximum number of bytes that can be handled atomically by 46 * diag read and write. 47 */ 48 #define ATH10K_DIAG_TRANSFER_LIMIT 0x5000 49 50 #define QCA99X0_PCIE_BAR0_START_REG 0x81030 51 #define QCA99X0_CPU_MEM_ADDR_REG 0x4d00c 52 #define QCA99X0_CPU_MEM_DATA_REG 0x4d010 53 54 static const struct pci_device_id ath10k_pci_id_table[] = { 55 /* PCI-E QCA988X V2 (Ubiquiti branded) */ 56 { PCI_VDEVICE(UBIQUITI, QCA988X_2_0_DEVICE_ID_UBNT) }, 57 58 { PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */ 59 { PCI_VDEVICE(ATHEROS, QCA6164_2_1_DEVICE_ID) }, /* PCI-E QCA6164 V2.1 */ 60 { PCI_VDEVICE(ATHEROS, QCA6174_2_1_DEVICE_ID) }, /* PCI-E QCA6174 V2.1 */ 61 { PCI_VDEVICE(ATHEROS, QCA99X0_2_0_DEVICE_ID) }, /* PCI-E QCA99X0 V2 */ 62 { PCI_VDEVICE(ATHEROS, QCA9888_2_0_DEVICE_ID) }, /* PCI-E QCA9888 V2 */ 63 { PCI_VDEVICE(ATHEROS, QCA9984_1_0_DEVICE_ID) }, /* PCI-E QCA9984 V1 */ 64 { PCI_VDEVICE(ATHEROS, QCA9377_1_0_DEVICE_ID) }, /* PCI-E QCA9377 V1 */ 65 { PCI_VDEVICE(ATHEROS, QCA9887_1_0_DEVICE_ID) }, /* PCI-E QCA9887 */ 66 {0} 67 }; 68 69 static const struct ath10k_pci_supp_chip ath10k_pci_supp_chips[] = { 70 /* QCA988X pre 2.0 chips are not supported because they need some nasty 71 * hacks. ath10k doesn't have them and these devices crash horribly 72 * because of that. 73 */ 74 { QCA988X_2_0_DEVICE_ID_UBNT, QCA988X_HW_2_0_CHIP_ID_REV }, 75 { QCA988X_2_0_DEVICE_ID, QCA988X_HW_2_0_CHIP_ID_REV }, 76 77 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV }, 78 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV }, 79 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV }, 80 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV }, 81 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV }, 82 83 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV }, 84 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV }, 85 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV }, 86 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV }, 87 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV }, 88 89 { QCA99X0_2_0_DEVICE_ID, QCA99X0_HW_2_0_CHIP_ID_REV }, 90 91 { QCA9984_1_0_DEVICE_ID, QCA9984_HW_1_0_CHIP_ID_REV }, 92 93 { QCA9888_2_0_DEVICE_ID, QCA9888_HW_2_0_CHIP_ID_REV }, 94 95 { QCA9377_1_0_DEVICE_ID, QCA9377_HW_1_0_CHIP_ID_REV }, 96 { QCA9377_1_0_DEVICE_ID, QCA9377_HW_1_1_CHIP_ID_REV }, 97 98 { QCA9887_1_0_DEVICE_ID, QCA9887_HW_1_0_CHIP_ID_REV }, 99 }; 100 101 static void ath10k_pci_buffer_cleanup(struct ath10k *ar); 102 static int ath10k_pci_cold_reset(struct ath10k *ar); 103 static int ath10k_pci_safe_chip_reset(struct ath10k *ar); 104 static int ath10k_pci_init_irq(struct ath10k *ar); 105 static int ath10k_pci_deinit_irq(struct ath10k *ar); 106 static int ath10k_pci_request_irq(struct ath10k *ar); 107 static void ath10k_pci_free_irq(struct ath10k *ar); 108 static int ath10k_pci_bmi_wait(struct ath10k *ar, 109 struct ath10k_ce_pipe *tx_pipe, 110 struct ath10k_ce_pipe *rx_pipe, 111 struct bmi_xfer *xfer); 112 static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar); 113 static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe *ce_state); 114 static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state); 115 static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state); 116 static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe *ce_state); 117 static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state); 118 static void ath10k_pci_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state); 119 120 static const struct ce_attr pci_host_ce_config_wlan[] = { 121 /* CE0: host->target HTC control and raw streams */ 122 { 123 .flags = CE_ATTR_FLAGS, 124 .src_nentries = 16, 125 .src_sz_max = 256, 126 .dest_nentries = 0, 127 .send_cb = ath10k_pci_htc_tx_cb, 128 }, 129 130 /* CE1: target->host HTT + HTC control */ 131 { 132 .flags = CE_ATTR_FLAGS, 133 .src_nentries = 0, 134 .src_sz_max = 2048, 135 .dest_nentries = 512, 136 .recv_cb = ath10k_pci_htt_htc_rx_cb, 137 }, 138 139 /* CE2: target->host WMI */ 140 { 141 .flags = CE_ATTR_FLAGS, 142 .src_nentries = 0, 143 .src_sz_max = 2048, 144 .dest_nentries = 128, 145 .recv_cb = ath10k_pci_htc_rx_cb, 146 }, 147 148 /* CE3: host->target WMI */ 149 { 150 .flags = CE_ATTR_FLAGS, 151 .src_nentries = 32, 152 .src_sz_max = 2048, 153 .dest_nentries = 0, 154 .send_cb = ath10k_pci_htc_tx_cb, 155 }, 156 157 /* CE4: host->target HTT */ 158 { 159 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, 160 .src_nentries = CE_HTT_H2T_MSG_SRC_NENTRIES, 161 .src_sz_max = 256, 162 .dest_nentries = 0, 163 .send_cb = ath10k_pci_htt_tx_cb, 164 }, 165 166 /* CE5: target->host HTT (HIF->HTT) */ 167 { 168 .flags = CE_ATTR_FLAGS, 169 .src_nentries = 0, 170 .src_sz_max = 512, 171 .dest_nentries = 512, 172 .recv_cb = ath10k_pci_htt_rx_cb, 173 }, 174 175 /* CE6: target autonomous hif_memcpy */ 176 { 177 .flags = CE_ATTR_FLAGS, 178 .src_nentries = 0, 179 .src_sz_max = 0, 180 .dest_nentries = 0, 181 }, 182 183 /* CE7: ce_diag, the Diagnostic Window */ 184 { 185 .flags = CE_ATTR_FLAGS | CE_ATTR_POLL, 186 .src_nentries = 2, 187 .src_sz_max = DIAG_TRANSFER_LIMIT, 188 .dest_nentries = 2, 189 }, 190 191 /* CE8: target->host pktlog */ 192 { 193 .flags = CE_ATTR_FLAGS, 194 .src_nentries = 0, 195 .src_sz_max = 2048, 196 .dest_nentries = 128, 197 .recv_cb = ath10k_pci_pktlog_rx_cb, 198 }, 199 200 /* CE9 target autonomous qcache memcpy */ 201 { 202 .flags = CE_ATTR_FLAGS, 203 .src_nentries = 0, 204 .src_sz_max = 0, 205 .dest_nentries = 0, 206 }, 207 208 /* CE10: target autonomous hif memcpy */ 209 { 210 .flags = CE_ATTR_FLAGS, 211 .src_nentries = 0, 212 .src_sz_max = 0, 213 .dest_nentries = 0, 214 }, 215 216 /* CE11: target autonomous hif memcpy */ 217 { 218 .flags = CE_ATTR_FLAGS, 219 .src_nentries = 0, 220 .src_sz_max = 0, 221 .dest_nentries = 0, 222 }, 223 }; 224 225 /* Target firmware's Copy Engine configuration. */ 226 static const struct ce_pipe_config pci_target_ce_config_wlan[] = { 227 /* CE0: host->target HTC control and raw streams */ 228 { 229 .pipenum = __cpu_to_le32(0), 230 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 231 .nentries = __cpu_to_le32(32), 232 .nbytes_max = __cpu_to_le32(256), 233 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 234 .reserved = __cpu_to_le32(0), 235 }, 236 237 /* CE1: target->host HTT + HTC control */ 238 { 239 .pipenum = __cpu_to_le32(1), 240 .pipedir = __cpu_to_le32(PIPEDIR_IN), 241 .nentries = __cpu_to_le32(32), 242 .nbytes_max = __cpu_to_le32(2048), 243 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 244 .reserved = __cpu_to_le32(0), 245 }, 246 247 /* CE2: target->host WMI */ 248 { 249 .pipenum = __cpu_to_le32(2), 250 .pipedir = __cpu_to_le32(PIPEDIR_IN), 251 .nentries = __cpu_to_le32(64), 252 .nbytes_max = __cpu_to_le32(2048), 253 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 254 .reserved = __cpu_to_le32(0), 255 }, 256 257 /* CE3: host->target WMI */ 258 { 259 .pipenum = __cpu_to_le32(3), 260 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 261 .nentries = __cpu_to_le32(32), 262 .nbytes_max = __cpu_to_le32(2048), 263 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 264 .reserved = __cpu_to_le32(0), 265 }, 266 267 /* CE4: host->target HTT */ 268 { 269 .pipenum = __cpu_to_le32(4), 270 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 271 .nentries = __cpu_to_le32(256), 272 .nbytes_max = __cpu_to_le32(256), 273 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 274 .reserved = __cpu_to_le32(0), 275 }, 276 277 /* NB: 50% of src nentries, since tx has 2 frags */ 278 279 /* CE5: target->host HTT (HIF->HTT) */ 280 { 281 .pipenum = __cpu_to_le32(5), 282 .pipedir = __cpu_to_le32(PIPEDIR_IN), 283 .nentries = __cpu_to_le32(32), 284 .nbytes_max = __cpu_to_le32(512), 285 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 286 .reserved = __cpu_to_le32(0), 287 }, 288 289 /* CE6: Reserved for target autonomous hif_memcpy */ 290 { 291 .pipenum = __cpu_to_le32(6), 292 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 293 .nentries = __cpu_to_le32(32), 294 .nbytes_max = __cpu_to_le32(4096), 295 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 296 .reserved = __cpu_to_le32(0), 297 }, 298 299 /* CE7 used only by Host */ 300 { 301 .pipenum = __cpu_to_le32(7), 302 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 303 .nentries = __cpu_to_le32(0), 304 .nbytes_max = __cpu_to_le32(0), 305 .flags = __cpu_to_le32(0), 306 .reserved = __cpu_to_le32(0), 307 }, 308 309 /* CE8 target->host packtlog */ 310 { 311 .pipenum = __cpu_to_le32(8), 312 .pipedir = __cpu_to_le32(PIPEDIR_IN), 313 .nentries = __cpu_to_le32(64), 314 .nbytes_max = __cpu_to_le32(2048), 315 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 316 .reserved = __cpu_to_le32(0), 317 }, 318 319 /* CE9 target autonomous qcache memcpy */ 320 { 321 .pipenum = __cpu_to_le32(9), 322 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 323 .nentries = __cpu_to_le32(32), 324 .nbytes_max = __cpu_to_le32(2048), 325 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 326 .reserved = __cpu_to_le32(0), 327 }, 328 329 /* It not necessary to send target wlan configuration for CE10 & CE11 330 * as these CEs are not actively used in target. 331 */ 332 }; 333 334 /* 335 * Map from service/endpoint to Copy Engine. 336 * This table is derived from the CE_PCI TABLE, above. 337 * It is passed to the Target at startup for use by firmware. 338 */ 339 static const struct ce_service_to_pipe pci_target_service_to_ce_map_wlan[] = { 340 { 341 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO), 342 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 343 __cpu_to_le32(3), 344 }, 345 { 346 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO), 347 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 348 __cpu_to_le32(2), 349 }, 350 { 351 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK), 352 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 353 __cpu_to_le32(3), 354 }, 355 { 356 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK), 357 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 358 __cpu_to_le32(2), 359 }, 360 { 361 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE), 362 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 363 __cpu_to_le32(3), 364 }, 365 { 366 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE), 367 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 368 __cpu_to_le32(2), 369 }, 370 { 371 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI), 372 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 373 __cpu_to_le32(3), 374 }, 375 { 376 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI), 377 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 378 __cpu_to_le32(2), 379 }, 380 { 381 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL), 382 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 383 __cpu_to_le32(3), 384 }, 385 { 386 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL), 387 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 388 __cpu_to_le32(2), 389 }, 390 { 391 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL), 392 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 393 __cpu_to_le32(0), 394 }, 395 { 396 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL), 397 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 398 __cpu_to_le32(1), 399 }, 400 { /* not used */ 401 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS), 402 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 403 __cpu_to_le32(0), 404 }, 405 { /* not used */ 406 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS), 407 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 408 __cpu_to_le32(1), 409 }, 410 { 411 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG), 412 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 413 __cpu_to_le32(4), 414 }, 415 { 416 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG), 417 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 418 __cpu_to_le32(5), 419 }, 420 421 /* (Additions here) */ 422 423 { /* must be last */ 424 __cpu_to_le32(0), 425 __cpu_to_le32(0), 426 __cpu_to_le32(0), 427 }, 428 }; 429 430 static bool ath10k_pci_is_awake(struct ath10k *ar) 431 { 432 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 433 u32 val = ioread32(ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + 434 RTC_STATE_ADDRESS); 435 436 return RTC_STATE_V_GET(val) == RTC_STATE_V_ON; 437 } 438 439 static void __ath10k_pci_wake(struct ath10k *ar) 440 { 441 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 442 443 lockdep_assert_held(&ar_pci->ps_lock); 444 445 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake reg refcount %lu awake %d\n", 446 ar_pci->ps_wake_refcount, ar_pci->ps_awake); 447 448 iowrite32(PCIE_SOC_WAKE_V_MASK, 449 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + 450 PCIE_SOC_WAKE_ADDRESS); 451 } 452 453 static void __ath10k_pci_sleep(struct ath10k *ar) 454 { 455 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 456 457 lockdep_assert_held(&ar_pci->ps_lock); 458 459 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep reg refcount %lu awake %d\n", 460 ar_pci->ps_wake_refcount, ar_pci->ps_awake); 461 462 iowrite32(PCIE_SOC_WAKE_RESET, 463 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + 464 PCIE_SOC_WAKE_ADDRESS); 465 ar_pci->ps_awake = false; 466 } 467 468 static int ath10k_pci_wake_wait(struct ath10k *ar) 469 { 470 int tot_delay = 0; 471 int curr_delay = 5; 472 473 while (tot_delay < PCIE_WAKE_TIMEOUT) { 474 if (ath10k_pci_is_awake(ar)) { 475 if (tot_delay > PCIE_WAKE_LATE_US) 476 ath10k_warn(ar, "device wakeup took %d ms which is unusually long, otherwise it works normally.\n", 477 tot_delay / 1000); 478 return 0; 479 } 480 481 udelay(curr_delay); 482 tot_delay += curr_delay; 483 484 if (curr_delay < 50) 485 curr_delay += 5; 486 } 487 488 return -ETIMEDOUT; 489 } 490 491 static int ath10k_pci_force_wake(struct ath10k *ar) 492 { 493 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 494 unsigned long flags; 495 int ret = 0; 496 497 if (ar_pci->pci_ps) 498 return ret; 499 500 spin_lock_irqsave(&ar_pci->ps_lock, flags); 501 502 if (!ar_pci->ps_awake) { 503 iowrite32(PCIE_SOC_WAKE_V_MASK, 504 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + 505 PCIE_SOC_WAKE_ADDRESS); 506 507 ret = ath10k_pci_wake_wait(ar); 508 if (ret == 0) 509 ar_pci->ps_awake = true; 510 } 511 512 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 513 514 return ret; 515 } 516 517 static void ath10k_pci_force_sleep(struct ath10k *ar) 518 { 519 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 520 unsigned long flags; 521 522 spin_lock_irqsave(&ar_pci->ps_lock, flags); 523 524 iowrite32(PCIE_SOC_WAKE_RESET, 525 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + 526 PCIE_SOC_WAKE_ADDRESS); 527 ar_pci->ps_awake = false; 528 529 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 530 } 531 532 static int ath10k_pci_wake(struct ath10k *ar) 533 { 534 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 535 unsigned long flags; 536 int ret = 0; 537 538 if (ar_pci->pci_ps == 0) 539 return ret; 540 541 spin_lock_irqsave(&ar_pci->ps_lock, flags); 542 543 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake refcount %lu awake %d\n", 544 ar_pci->ps_wake_refcount, ar_pci->ps_awake); 545 546 /* This function can be called very frequently. To avoid excessive 547 * CPU stalls for MMIO reads use a cache var to hold the device state. 548 */ 549 if (!ar_pci->ps_awake) { 550 __ath10k_pci_wake(ar); 551 552 ret = ath10k_pci_wake_wait(ar); 553 if (ret == 0) 554 ar_pci->ps_awake = true; 555 } 556 557 if (ret == 0) { 558 ar_pci->ps_wake_refcount++; 559 WARN_ON(ar_pci->ps_wake_refcount == 0); 560 } 561 562 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 563 564 return ret; 565 } 566 567 static void ath10k_pci_sleep(struct ath10k *ar) 568 { 569 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 570 unsigned long flags; 571 572 if (ar_pci->pci_ps == 0) 573 return; 574 575 spin_lock_irqsave(&ar_pci->ps_lock, flags); 576 577 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep refcount %lu awake %d\n", 578 ar_pci->ps_wake_refcount, ar_pci->ps_awake); 579 580 if (WARN_ON(ar_pci->ps_wake_refcount == 0)) 581 goto skip; 582 583 ar_pci->ps_wake_refcount--; 584 585 mod_timer(&ar_pci->ps_timer, jiffies + 586 msecs_to_jiffies(ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC)); 587 588 skip: 589 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 590 } 591 592 static void ath10k_pci_ps_timer(struct timer_list *t) 593 { 594 struct ath10k_pci *ar_pci = timer_container_of(ar_pci, t, ps_timer); 595 struct ath10k *ar = ar_pci->ar; 596 unsigned long flags; 597 598 spin_lock_irqsave(&ar_pci->ps_lock, flags); 599 600 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps timer refcount %lu awake %d\n", 601 ar_pci->ps_wake_refcount, ar_pci->ps_awake); 602 603 if (ar_pci->ps_wake_refcount > 0) 604 goto skip; 605 606 __ath10k_pci_sleep(ar); 607 608 skip: 609 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 610 } 611 612 static void ath10k_pci_sleep_sync(struct ath10k *ar) 613 { 614 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 615 unsigned long flags; 616 617 if (ar_pci->pci_ps == 0) { 618 ath10k_pci_force_sleep(ar); 619 return; 620 } 621 622 timer_delete_sync(&ar_pci->ps_timer); 623 624 spin_lock_irqsave(&ar_pci->ps_lock, flags); 625 WARN_ON(ar_pci->ps_wake_refcount > 0); 626 __ath10k_pci_sleep(ar); 627 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 628 } 629 630 static void ath10k_bus_pci_write32(struct ath10k *ar, u32 offset, u32 value) 631 { 632 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 633 int ret; 634 635 if (unlikely(offset + sizeof(value) > ar_pci->mem_len)) { 636 ath10k_warn(ar, "refusing to write mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n", 637 offset, offset + sizeof(value), ar_pci->mem_len); 638 return; 639 } 640 641 ret = ath10k_pci_wake(ar); 642 if (ret) { 643 ath10k_warn(ar, "failed to wake target for write32 of 0x%08x at 0x%08x: %d\n", 644 value, offset, ret); 645 return; 646 } 647 648 iowrite32(value, ar_pci->mem + offset); 649 ath10k_pci_sleep(ar); 650 } 651 652 static u32 ath10k_bus_pci_read32(struct ath10k *ar, u32 offset) 653 { 654 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 655 u32 val; 656 int ret; 657 658 if (unlikely(offset + sizeof(val) > ar_pci->mem_len)) { 659 ath10k_warn(ar, "refusing to read mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n", 660 offset, offset + sizeof(val), ar_pci->mem_len); 661 return 0; 662 } 663 664 ret = ath10k_pci_wake(ar); 665 if (ret) { 666 ath10k_warn(ar, "failed to wake target for read32 at 0x%08x: %d\n", 667 offset, ret); 668 return 0xffffffff; 669 } 670 671 val = ioread32(ar_pci->mem + offset); 672 ath10k_pci_sleep(ar); 673 674 return val; 675 } 676 677 inline void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value) 678 { 679 struct ath10k_ce *ce = ath10k_ce_priv(ar); 680 681 ce->bus_ops->write32(ar, offset, value); 682 } 683 684 inline u32 ath10k_pci_read32(struct ath10k *ar, u32 offset) 685 { 686 struct ath10k_ce *ce = ath10k_ce_priv(ar); 687 688 return ce->bus_ops->read32(ar, offset); 689 } 690 691 u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr) 692 { 693 return ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + addr); 694 } 695 696 void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val) 697 { 698 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + addr, val); 699 } 700 701 u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr) 702 { 703 return ath10k_pci_read32(ar, PCIE_LOCAL_BASE_ADDRESS + addr); 704 } 705 706 void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val) 707 { 708 ath10k_pci_write32(ar, PCIE_LOCAL_BASE_ADDRESS + addr, val); 709 } 710 711 bool ath10k_pci_irq_pending(struct ath10k *ar) 712 { 713 u32 cause; 714 715 /* Check if the shared legacy irq is for us */ 716 cause = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 717 PCIE_INTR_CAUSE_ADDRESS); 718 if (cause & (PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL)) 719 return true; 720 721 return false; 722 } 723 724 void ath10k_pci_disable_and_clear_intx_irq(struct ath10k *ar) 725 { 726 /* IMPORTANT: INTR_CLR register has to be set after 727 * INTR_ENABLE is set to 0, otherwise interrupt can not be 728 * really cleared. 729 */ 730 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS, 731 0); 732 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_CLR_ADDRESS, 733 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); 734 735 /* IMPORTANT: this extra read transaction is required to 736 * flush the posted write buffer. 737 */ 738 (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 739 PCIE_INTR_ENABLE_ADDRESS); 740 } 741 742 void ath10k_pci_enable_intx_irq(struct ath10k *ar) 743 { 744 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + 745 PCIE_INTR_ENABLE_ADDRESS, 746 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); 747 748 /* IMPORTANT: this extra read transaction is required to 749 * flush the posted write buffer. 750 */ 751 (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 752 PCIE_INTR_ENABLE_ADDRESS); 753 } 754 755 static inline const char *ath10k_pci_get_irq_method(struct ath10k *ar) 756 { 757 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 758 759 if (ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_MSI) 760 return "msi"; 761 762 return "legacy"; 763 } 764 765 static int __ath10k_pci_rx_post_buf(struct ath10k_pci_pipe *pipe) 766 { 767 struct ath10k *ar = pipe->hif_ce_state; 768 struct ath10k_ce *ce = ath10k_ce_priv(ar); 769 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl; 770 struct sk_buff *skb; 771 dma_addr_t paddr; 772 int ret; 773 774 skb = dev_alloc_skb(pipe->buf_sz); 775 if (!skb) 776 return -ENOMEM; 777 778 WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb"); 779 780 paddr = dma_map_single(ar->dev, skb->data, 781 skb->len + skb_tailroom(skb), 782 DMA_FROM_DEVICE); 783 if (unlikely(dma_mapping_error(ar->dev, paddr))) { 784 ath10k_warn(ar, "failed to dma map pci rx buf\n"); 785 dev_kfree_skb_any(skb); 786 return -EIO; 787 } 788 789 ATH10K_SKB_RXCB(skb)->paddr = paddr; 790 791 spin_lock_bh(&ce->ce_lock); 792 ret = ce_pipe->ops->ce_rx_post_buf(ce_pipe, skb, paddr); 793 spin_unlock_bh(&ce->ce_lock); 794 if (ret) { 795 dma_unmap_single(ar->dev, paddr, skb->len + skb_tailroom(skb), 796 DMA_FROM_DEVICE); 797 dev_kfree_skb_any(skb); 798 return ret; 799 } 800 801 return 0; 802 } 803 804 static void ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe *pipe) 805 { 806 struct ath10k *ar = pipe->hif_ce_state; 807 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 808 struct ath10k_ce *ce = ath10k_ce_priv(ar); 809 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl; 810 int ret, num; 811 812 if (pipe->buf_sz == 0) 813 return; 814 815 if (!ce_pipe->dest_ring) 816 return; 817 818 spin_lock_bh(&ce->ce_lock); 819 num = __ath10k_ce_rx_num_free_bufs(ce_pipe); 820 spin_unlock_bh(&ce->ce_lock); 821 822 while (num >= 0) { 823 ret = __ath10k_pci_rx_post_buf(pipe); 824 if (ret) { 825 if (ret == -ENOSPC) 826 break; 827 ath10k_warn(ar, "failed to post pci rx buf: %d\n", ret); 828 mod_timer(&ar_pci->rx_post_retry, jiffies + 829 ATH10K_PCI_RX_POST_RETRY_MS); 830 break; 831 } 832 num--; 833 } 834 } 835 836 void ath10k_pci_rx_post(struct ath10k *ar) 837 { 838 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 839 int i; 840 841 for (i = 0; i < CE_COUNT; i++) 842 ath10k_pci_rx_post_pipe(&ar_pci->pipe_info[i]); 843 } 844 845 void ath10k_pci_rx_replenish_retry(struct timer_list *t) 846 { 847 struct ath10k_pci *ar_pci = timer_container_of(ar_pci, t, 848 rx_post_retry); 849 struct ath10k *ar = ar_pci->ar; 850 851 ath10k_pci_rx_post(ar); 852 } 853 854 static u32 ath10k_pci_qca988x_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr) 855 { 856 u32 val = 0, region = addr & 0xfffff; 857 858 val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS) 859 & 0x7ff) << 21; 860 val |= 0x100000 | region; 861 return val; 862 } 863 864 /* Refactor from ath10k_pci_qca988x_targ_cpu_to_ce_addr. 865 * Support to access target space below 1M for qca6174 and qca9377. 866 * If target space is below 1M, the bit[20] of converted CE addr is 0. 867 * Otherwise bit[20] of converted CE addr is 1. 868 */ 869 static u32 ath10k_pci_qca6174_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr) 870 { 871 u32 val = 0, region = addr & 0xfffff; 872 873 val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS) 874 & 0x7ff) << 21; 875 val |= ((addr >= 0x100000) ? 0x100000 : 0) | region; 876 return val; 877 } 878 879 static u32 ath10k_pci_qca99x0_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr) 880 { 881 u32 val = 0, region = addr & 0xfffff; 882 883 val = ath10k_pci_read32(ar, PCIE_BAR_REG_ADDRESS); 884 val |= 0x100000 | region; 885 return val; 886 } 887 888 static u32 ath10k_pci_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr) 889 { 890 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 891 892 if (WARN_ON_ONCE(!ar_pci->targ_cpu_to_ce_addr)) 893 return -EOPNOTSUPP; 894 895 return ar_pci->targ_cpu_to_ce_addr(ar, addr); 896 } 897 898 /* 899 * Diagnostic read/write access is provided for startup/config/debug usage. 900 * Caller must guarantee proper alignment, when applicable, and single user 901 * at any moment. 902 */ 903 static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data, 904 int nbytes) 905 { 906 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 907 int ret = 0; 908 u32 *buf; 909 unsigned int completed_nbytes, alloc_nbytes, remaining_bytes; 910 struct ath10k_ce_pipe *ce_diag; 911 /* Host buffer address in CE space */ 912 u32 ce_data; 913 dma_addr_t ce_data_base = 0; 914 void *data_buf; 915 int i; 916 917 mutex_lock(&ar_pci->ce_diag_mutex); 918 ce_diag = ar_pci->ce_diag; 919 920 /* 921 * Allocate a temporary bounce buffer to hold caller's data 922 * to be DMA'ed from Target. This guarantees 923 * 1) 4-byte alignment 924 * 2) Buffer in DMA-able space 925 */ 926 alloc_nbytes = min_t(unsigned int, nbytes, DIAG_TRANSFER_LIMIT); 927 928 data_buf = dma_alloc_coherent(ar->dev, alloc_nbytes, &ce_data_base, 929 GFP_ATOMIC); 930 if (!data_buf) { 931 ret = -ENOMEM; 932 goto done; 933 } 934 935 /* The address supplied by the caller is in the 936 * Target CPU virtual address space. 937 * 938 * In order to use this address with the diagnostic CE, 939 * convert it from Target CPU virtual address space 940 * to CE address space 941 */ 942 address = ath10k_pci_targ_cpu_to_ce_addr(ar, address); 943 944 remaining_bytes = nbytes; 945 ce_data = ce_data_base; 946 while (remaining_bytes) { 947 nbytes = min_t(unsigned int, remaining_bytes, 948 DIAG_TRANSFER_LIMIT); 949 950 ret = ath10k_ce_rx_post_buf(ce_diag, &ce_data, ce_data); 951 if (ret != 0) 952 goto done; 953 954 /* Request CE to send from Target(!) address to Host buffer */ 955 ret = ath10k_ce_send(ce_diag, NULL, (u32)address, nbytes, 0, 0); 956 if (ret) 957 goto done; 958 959 i = 0; 960 while (ath10k_ce_completed_send_next(ce_diag, NULL) != 0) { 961 udelay(DIAG_ACCESS_CE_WAIT_US); 962 i += DIAG_ACCESS_CE_WAIT_US; 963 964 if (i > DIAG_ACCESS_CE_TIMEOUT_US) { 965 ret = -EBUSY; 966 goto done; 967 } 968 } 969 970 i = 0; 971 while (ath10k_ce_completed_recv_next(ce_diag, (void **)&buf, 972 &completed_nbytes) != 0) { 973 udelay(DIAG_ACCESS_CE_WAIT_US); 974 i += DIAG_ACCESS_CE_WAIT_US; 975 976 if (i > DIAG_ACCESS_CE_TIMEOUT_US) { 977 ret = -EBUSY; 978 goto done; 979 } 980 } 981 982 if (nbytes != completed_nbytes) { 983 ret = -EIO; 984 goto done; 985 } 986 987 if (*buf != ce_data) { 988 ret = -EIO; 989 goto done; 990 } 991 992 remaining_bytes -= nbytes; 993 memcpy(data, data_buf, nbytes); 994 995 address += nbytes; 996 data += nbytes; 997 } 998 999 done: 1000 1001 if (data_buf) 1002 dma_free_coherent(ar->dev, alloc_nbytes, data_buf, 1003 ce_data_base); 1004 1005 mutex_unlock(&ar_pci->ce_diag_mutex); 1006 1007 return ret; 1008 } 1009 1010 static int ath10k_pci_diag_read32(struct ath10k *ar, u32 address, u32 *value) 1011 { 1012 __le32 val = 0; 1013 int ret; 1014 1015 ret = ath10k_pci_diag_read_mem(ar, address, &val, sizeof(val)); 1016 *value = __le32_to_cpu(val); 1017 1018 return ret; 1019 } 1020 1021 static int __ath10k_pci_diag_read_hi(struct ath10k *ar, void *dest, 1022 u32 src, u32 len) 1023 { 1024 u32 host_addr, addr; 1025 int ret; 1026 1027 host_addr = host_interest_item_address(src); 1028 1029 ret = ath10k_pci_diag_read32(ar, host_addr, &addr); 1030 if (ret != 0) { 1031 ath10k_warn(ar, "failed to get memcpy hi address for firmware address %d: %d\n", 1032 src, ret); 1033 return ret; 1034 } 1035 1036 ret = ath10k_pci_diag_read_mem(ar, addr, dest, len); 1037 if (ret != 0) { 1038 ath10k_warn(ar, "failed to memcpy firmware memory from %d (%d B): %d\n", 1039 addr, len, ret); 1040 return ret; 1041 } 1042 1043 return 0; 1044 } 1045 1046 #define ath10k_pci_diag_read_hi(ar, dest, src, len) \ 1047 __ath10k_pci_diag_read_hi(ar, dest, HI_ITEM(src), len) 1048 1049 int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address, 1050 const void *data, int nbytes) 1051 { 1052 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1053 int ret = 0; 1054 u32 *buf; 1055 unsigned int completed_nbytes, alloc_nbytes, remaining_bytes; 1056 struct ath10k_ce_pipe *ce_diag; 1057 void *data_buf; 1058 dma_addr_t ce_data_base = 0; 1059 int i; 1060 1061 mutex_lock(&ar_pci->ce_diag_mutex); 1062 ce_diag = ar_pci->ce_diag; 1063 1064 /* 1065 * Allocate a temporary bounce buffer to hold caller's data 1066 * to be DMA'ed to Target. This guarantees 1067 * 1) 4-byte alignment 1068 * 2) Buffer in DMA-able space 1069 */ 1070 alloc_nbytes = min_t(unsigned int, nbytes, DIAG_TRANSFER_LIMIT); 1071 1072 data_buf = dma_alloc_coherent(ar->dev, alloc_nbytes, &ce_data_base, 1073 GFP_ATOMIC); 1074 if (!data_buf) { 1075 ret = -ENOMEM; 1076 goto done; 1077 } 1078 1079 /* 1080 * The address supplied by the caller is in the 1081 * Target CPU virtual address space. 1082 * 1083 * In order to use this address with the diagnostic CE, 1084 * convert it from 1085 * Target CPU virtual address space 1086 * to 1087 * CE address space 1088 */ 1089 address = ath10k_pci_targ_cpu_to_ce_addr(ar, address); 1090 1091 remaining_bytes = nbytes; 1092 while (remaining_bytes) { 1093 /* FIXME: check cast */ 1094 nbytes = min_t(int, remaining_bytes, DIAG_TRANSFER_LIMIT); 1095 1096 /* Copy caller's data to allocated DMA buf */ 1097 memcpy(data_buf, data, nbytes); 1098 1099 /* Set up to receive directly into Target(!) address */ 1100 ret = ath10k_ce_rx_post_buf(ce_diag, &address, address); 1101 if (ret != 0) 1102 goto done; 1103 1104 /* 1105 * Request CE to send caller-supplied data that 1106 * was copied to bounce buffer to Target(!) address. 1107 */ 1108 ret = ath10k_ce_send(ce_diag, NULL, ce_data_base, nbytes, 0, 0); 1109 if (ret != 0) 1110 goto done; 1111 1112 i = 0; 1113 while (ath10k_ce_completed_send_next(ce_diag, NULL) != 0) { 1114 udelay(DIAG_ACCESS_CE_WAIT_US); 1115 i += DIAG_ACCESS_CE_WAIT_US; 1116 1117 if (i > DIAG_ACCESS_CE_TIMEOUT_US) { 1118 ret = -EBUSY; 1119 goto done; 1120 } 1121 } 1122 1123 i = 0; 1124 while (ath10k_ce_completed_recv_next(ce_diag, (void **)&buf, 1125 &completed_nbytes) != 0) { 1126 udelay(DIAG_ACCESS_CE_WAIT_US); 1127 i += DIAG_ACCESS_CE_WAIT_US; 1128 1129 if (i > DIAG_ACCESS_CE_TIMEOUT_US) { 1130 ret = -EBUSY; 1131 goto done; 1132 } 1133 } 1134 1135 if (nbytes != completed_nbytes) { 1136 ret = -EIO; 1137 goto done; 1138 } 1139 1140 if (*buf != address) { 1141 ret = -EIO; 1142 goto done; 1143 } 1144 1145 remaining_bytes -= nbytes; 1146 address += nbytes; 1147 data += nbytes; 1148 } 1149 1150 done: 1151 if (data_buf) { 1152 dma_free_coherent(ar->dev, alloc_nbytes, data_buf, 1153 ce_data_base); 1154 } 1155 1156 if (ret != 0) 1157 ath10k_warn(ar, "failed to write diag value at 0x%x: %d\n", 1158 address, ret); 1159 1160 mutex_unlock(&ar_pci->ce_diag_mutex); 1161 1162 return ret; 1163 } 1164 1165 static int ath10k_pci_diag_write32(struct ath10k *ar, u32 address, u32 value) 1166 { 1167 __le32 val = __cpu_to_le32(value); 1168 1169 return ath10k_pci_diag_write_mem(ar, address, &val, sizeof(val)); 1170 } 1171 1172 /* Called by lower (CE) layer when a send to Target completes. */ 1173 static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe *ce_state) 1174 { 1175 struct ath10k *ar = ce_state->ar; 1176 struct sk_buff_head list; 1177 struct sk_buff *skb; 1178 1179 __skb_queue_head_init(&list); 1180 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) { 1181 /* no need to call tx completion for NULL pointers */ 1182 if (skb == NULL) 1183 continue; 1184 1185 __skb_queue_tail(&list, skb); 1186 } 1187 1188 while ((skb = __skb_dequeue(&list))) 1189 ath10k_htc_tx_completion_handler(ar, skb); 1190 } 1191 1192 static void ath10k_pci_process_rx_cb(struct ath10k_ce_pipe *ce_state, 1193 void (*callback)(struct ath10k *ar, 1194 struct sk_buff *skb)) 1195 { 1196 struct ath10k *ar = ce_state->ar; 1197 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1198 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id]; 1199 struct sk_buff *skb; 1200 struct sk_buff_head list; 1201 void *transfer_context; 1202 unsigned int nbytes, max_nbytes; 1203 1204 __skb_queue_head_init(&list); 1205 while (ath10k_ce_completed_recv_next(ce_state, &transfer_context, 1206 &nbytes) == 0) { 1207 skb = transfer_context; 1208 max_nbytes = skb->len + skb_tailroom(skb); 1209 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, 1210 max_nbytes, DMA_FROM_DEVICE); 1211 1212 if (unlikely(max_nbytes < nbytes)) { 1213 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)", 1214 nbytes, max_nbytes); 1215 dev_kfree_skb_any(skb); 1216 continue; 1217 } 1218 1219 skb_put(skb, nbytes); 1220 __skb_queue_tail(&list, skb); 1221 } 1222 1223 while ((skb = __skb_dequeue(&list))) { 1224 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n", 1225 ce_state->id, skb->len); 1226 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci rx: ", 1227 skb->data, skb->len); 1228 1229 callback(ar, skb); 1230 } 1231 1232 ath10k_pci_rx_post_pipe(pipe_info); 1233 } 1234 1235 static void ath10k_pci_process_htt_rx_cb(struct ath10k_ce_pipe *ce_state, 1236 void (*callback)(struct ath10k *ar, 1237 struct sk_buff *skb)) 1238 { 1239 struct ath10k *ar = ce_state->ar; 1240 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1241 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id]; 1242 struct ath10k_ce_pipe *ce_pipe = pipe_info->ce_hdl; 1243 struct sk_buff *skb; 1244 struct sk_buff_head list; 1245 void *transfer_context; 1246 unsigned int nbytes, max_nbytes, nentries; 1247 int orig_len; 1248 1249 /* No need to acquire ce_lock for CE5, since this is the only place CE5 1250 * is processed other than init and deinit. Before releasing CE5 1251 * buffers, interrupts are disabled. Thus CE5 access is serialized. 1252 */ 1253 __skb_queue_head_init(&list); 1254 while (ath10k_ce_completed_recv_next_nolock(ce_state, &transfer_context, 1255 &nbytes) == 0) { 1256 skb = transfer_context; 1257 max_nbytes = skb->len + skb_tailroom(skb); 1258 1259 if (unlikely(max_nbytes < nbytes)) { 1260 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)", 1261 nbytes, max_nbytes); 1262 continue; 1263 } 1264 1265 dma_sync_single_for_cpu(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, 1266 max_nbytes, DMA_FROM_DEVICE); 1267 skb_put(skb, nbytes); 1268 __skb_queue_tail(&list, skb); 1269 } 1270 1271 nentries = skb_queue_len(&list); 1272 while ((skb = __skb_dequeue(&list))) { 1273 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n", 1274 ce_state->id, skb->len); 1275 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci rx: ", 1276 skb->data, skb->len); 1277 1278 orig_len = skb->len; 1279 callback(ar, skb); 1280 skb_push(skb, orig_len - skb->len); 1281 skb_reset_tail_pointer(skb); 1282 skb_trim(skb, 0); 1283 1284 /*let device gain the buffer again*/ 1285 dma_sync_single_for_device(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, 1286 skb->len + skb_tailroom(skb), 1287 DMA_FROM_DEVICE); 1288 } 1289 ath10k_ce_rx_update_write_idx(ce_pipe, nentries); 1290 } 1291 1292 /* Called by lower (CE) layer when data is received from the Target. */ 1293 static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state) 1294 { 1295 ath10k_pci_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler); 1296 } 1297 1298 static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state) 1299 { 1300 /* CE4 polling needs to be done whenever CE pipe which transports 1301 * HTT Rx (target->host) is processed. 1302 */ 1303 ath10k_ce_per_engine_service(ce_state->ar, 4); 1304 1305 ath10k_pci_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler); 1306 } 1307 1308 /* Called by lower (CE) layer when data is received from the Target. 1309 * Only 10.4 firmware uses separate CE to transfer pktlog data. 1310 */ 1311 static void ath10k_pci_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state) 1312 { 1313 ath10k_pci_process_rx_cb(ce_state, 1314 ath10k_htt_rx_pktlog_completion_handler); 1315 } 1316 1317 /* Called by lower (CE) layer when a send to HTT Target completes. */ 1318 static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state) 1319 { 1320 struct ath10k *ar = ce_state->ar; 1321 struct sk_buff *skb; 1322 1323 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) { 1324 /* no need to call tx completion for NULL pointers */ 1325 if (!skb) 1326 continue; 1327 1328 dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr, 1329 skb->len, DMA_TO_DEVICE); 1330 ath10k_htt_hif_tx_complete(ar, skb); 1331 } 1332 } 1333 1334 static void ath10k_pci_htt_rx_deliver(struct ath10k *ar, struct sk_buff *skb) 1335 { 1336 skb_pull(skb, sizeof(struct ath10k_htc_hdr)); 1337 ath10k_htt_t2h_msg_handler(ar, skb); 1338 } 1339 1340 /* Called by lower (CE) layer when HTT data is received from the Target. */ 1341 static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe *ce_state) 1342 { 1343 /* CE4 polling needs to be done whenever CE pipe which transports 1344 * HTT Rx (target->host) is processed. 1345 */ 1346 ath10k_ce_per_engine_service(ce_state->ar, 4); 1347 1348 ath10k_pci_process_htt_rx_cb(ce_state, ath10k_pci_htt_rx_deliver); 1349 } 1350 1351 int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id, 1352 struct ath10k_hif_sg_item *items, int n_items) 1353 { 1354 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1355 struct ath10k_ce *ce = ath10k_ce_priv(ar); 1356 struct ath10k_pci_pipe *pci_pipe = &ar_pci->pipe_info[pipe_id]; 1357 struct ath10k_ce_pipe *ce_pipe = pci_pipe->ce_hdl; 1358 struct ath10k_ce_ring *src_ring = ce_pipe->src_ring; 1359 unsigned int nentries_mask; 1360 unsigned int sw_index; 1361 unsigned int write_index; 1362 int err, i = 0; 1363 1364 spin_lock_bh(&ce->ce_lock); 1365 1366 nentries_mask = src_ring->nentries_mask; 1367 sw_index = src_ring->sw_index; 1368 write_index = src_ring->write_index; 1369 1370 if (unlikely(CE_RING_DELTA(nentries_mask, 1371 write_index, sw_index - 1) < n_items)) { 1372 err = -ENOBUFS; 1373 goto err; 1374 } 1375 1376 for (i = 0; i < n_items - 1; i++) { 1377 ath10k_dbg(ar, ATH10K_DBG_PCI, 1378 "pci tx item %d paddr %pad len %d n_items %d\n", 1379 i, &items[i].paddr, items[i].len, n_items); 1380 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ", 1381 items[i].vaddr, items[i].len); 1382 1383 err = ath10k_ce_send_nolock(ce_pipe, 1384 items[i].transfer_context, 1385 items[i].paddr, 1386 items[i].len, 1387 items[i].transfer_id, 1388 CE_SEND_FLAG_GATHER); 1389 if (err) 1390 goto err; 1391 } 1392 1393 /* `i` is equal to `n_items -1` after for() */ 1394 1395 ath10k_dbg(ar, ATH10K_DBG_PCI, 1396 "pci tx item %d paddr %pad len %d n_items %d\n", 1397 i, &items[i].paddr, items[i].len, n_items); 1398 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ", 1399 items[i].vaddr, items[i].len); 1400 1401 err = ath10k_ce_send_nolock(ce_pipe, 1402 items[i].transfer_context, 1403 items[i].paddr, 1404 items[i].len, 1405 items[i].transfer_id, 1406 0); 1407 if (err) 1408 goto err; 1409 1410 spin_unlock_bh(&ce->ce_lock); 1411 return 0; 1412 1413 err: 1414 for (; i > 0; i--) 1415 __ath10k_ce_send_revert(ce_pipe); 1416 1417 spin_unlock_bh(&ce->ce_lock); 1418 return err; 1419 } 1420 1421 int ath10k_pci_hif_diag_read(struct ath10k *ar, u32 address, void *buf, 1422 size_t buf_len) 1423 { 1424 return ath10k_pci_diag_read_mem(ar, address, buf, buf_len); 1425 } 1426 1427 u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe) 1428 { 1429 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1430 1431 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get free queue number\n"); 1432 1433 return ath10k_ce_num_free_src_entries(ar_pci->pipe_info[pipe].ce_hdl); 1434 } 1435 1436 static void ath10k_pci_dump_registers(struct ath10k *ar, 1437 struct ath10k_fw_crash_data *crash_data) 1438 { 1439 __le32 reg_dump_values[REG_DUMP_COUNT_QCA988X] = {}; 1440 int i, ret; 1441 1442 lockdep_assert_held(&ar->dump_mutex); 1443 1444 ret = ath10k_pci_diag_read_hi(ar, ®_dump_values[0], 1445 hi_failure_state, 1446 REG_DUMP_COUNT_QCA988X * sizeof(__le32)); 1447 if (ret) { 1448 ath10k_err(ar, "failed to read firmware dump area: %d\n", ret); 1449 return; 1450 } 1451 1452 BUILD_BUG_ON(REG_DUMP_COUNT_QCA988X % 4); 1453 1454 ath10k_err(ar, "firmware register dump:\n"); 1455 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i += 4) 1456 ath10k_err(ar, "[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X\n", 1457 i, 1458 __le32_to_cpu(reg_dump_values[i]), 1459 __le32_to_cpu(reg_dump_values[i + 1]), 1460 __le32_to_cpu(reg_dump_values[i + 2]), 1461 __le32_to_cpu(reg_dump_values[i + 3])); 1462 1463 if (!crash_data) 1464 return; 1465 1466 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i++) 1467 crash_data->registers[i] = reg_dump_values[i]; 1468 } 1469 1470 static int ath10k_pci_dump_memory_section(struct ath10k *ar, 1471 const struct ath10k_mem_region *mem_region, 1472 u8 *buf, size_t buf_len) 1473 { 1474 const struct ath10k_mem_section *cur_section, *next_section; 1475 unsigned int count, section_size, skip_size; 1476 int ret, i, j; 1477 1478 if (!mem_region || !buf) 1479 return 0; 1480 1481 cur_section = &mem_region->section_table.sections[0]; 1482 1483 if (mem_region->start > cur_section->start) { 1484 ath10k_warn(ar, "incorrect memdump region 0x%x with section start address 0x%x.\n", 1485 mem_region->start, cur_section->start); 1486 return 0; 1487 } 1488 1489 skip_size = cur_section->start - mem_region->start; 1490 1491 /* fill the gap between the first register section and register 1492 * start address 1493 */ 1494 for (i = 0; i < skip_size; i++) { 1495 *buf = ATH10K_MAGIC_NOT_COPIED; 1496 buf++; 1497 } 1498 1499 count = 0; 1500 1501 for (i = 0; cur_section != NULL; i++) { 1502 section_size = cur_section->end - cur_section->start; 1503 1504 if (section_size <= 0) { 1505 ath10k_warn(ar, "incorrect ramdump format with start address 0x%x and stop address 0x%x\n", 1506 cur_section->start, 1507 cur_section->end); 1508 break; 1509 } 1510 1511 if ((i + 1) == mem_region->section_table.size) { 1512 /* last section */ 1513 next_section = NULL; 1514 skip_size = 0; 1515 } else { 1516 next_section = cur_section + 1; 1517 1518 if (cur_section->end > next_section->start) { 1519 ath10k_warn(ar, "next ramdump section 0x%x is smaller than current end address 0x%x\n", 1520 next_section->start, 1521 cur_section->end); 1522 break; 1523 } 1524 1525 skip_size = next_section->start - cur_section->end; 1526 } 1527 1528 if (buf_len < (skip_size + section_size)) { 1529 ath10k_warn(ar, "ramdump buffer is too small: %zu\n", buf_len); 1530 break; 1531 } 1532 1533 buf_len -= skip_size + section_size; 1534 1535 /* read section to dest memory */ 1536 ret = ath10k_pci_diag_read_mem(ar, cur_section->start, 1537 buf, section_size); 1538 if (ret) { 1539 ath10k_warn(ar, "failed to read ramdump from section 0x%x: %d\n", 1540 cur_section->start, ret); 1541 break; 1542 } 1543 1544 buf += section_size; 1545 count += section_size; 1546 1547 /* fill in the gap between this section and the next */ 1548 for (j = 0; j < skip_size; j++) { 1549 *buf = ATH10K_MAGIC_NOT_COPIED; 1550 buf++; 1551 } 1552 1553 count += skip_size; 1554 1555 if (!next_section) 1556 /* this was the last section */ 1557 break; 1558 1559 cur_section = next_section; 1560 } 1561 1562 return count; 1563 } 1564 1565 static int ath10k_pci_set_ram_config(struct ath10k *ar, u32 config) 1566 { 1567 u32 val; 1568 1569 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + 1570 FW_RAM_CONFIG_ADDRESS, config); 1571 1572 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 1573 FW_RAM_CONFIG_ADDRESS); 1574 if (val != config) { 1575 ath10k_warn(ar, "failed to set RAM config from 0x%x to 0x%x\n", 1576 val, config); 1577 return -EIO; 1578 } 1579 1580 return 0; 1581 } 1582 1583 /* Always returns the length */ 1584 static int ath10k_pci_dump_memory_sram(struct ath10k *ar, 1585 const struct ath10k_mem_region *region, 1586 u8 *buf) 1587 { 1588 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1589 u32 base_addr, i; 1590 1591 base_addr = ioread32(ar_pci->mem + QCA99X0_PCIE_BAR0_START_REG); 1592 base_addr += region->start; 1593 1594 for (i = 0; i < region->len; i += 4) { 1595 iowrite32(base_addr + i, ar_pci->mem + QCA99X0_CPU_MEM_ADDR_REG); 1596 *(u32 *)(buf + i) = ioread32(ar_pci->mem + QCA99X0_CPU_MEM_DATA_REG); 1597 } 1598 1599 return region->len; 1600 } 1601 1602 /* if an error happened returns < 0, otherwise the length */ 1603 static int ath10k_pci_dump_memory_reg(struct ath10k *ar, 1604 const struct ath10k_mem_region *region, 1605 u8 *buf) 1606 { 1607 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1608 u32 i; 1609 int ret; 1610 1611 mutex_lock(&ar->conf_mutex); 1612 if (ar->state != ATH10K_STATE_ON) { 1613 ath10k_warn(ar, "Skipping pci_dump_memory_reg invalid state\n"); 1614 ret = -EIO; 1615 goto done; 1616 } 1617 1618 for (i = 0; i < region->len; i += 4) 1619 *(u32 *)(buf + i) = ioread32(ar_pci->mem + region->start + i); 1620 1621 ret = region->len; 1622 done: 1623 mutex_unlock(&ar->conf_mutex); 1624 return ret; 1625 } 1626 1627 /* if an error happened returns < 0, otherwise the length */ 1628 static int ath10k_pci_dump_memory_generic(struct ath10k *ar, 1629 const struct ath10k_mem_region *current_region, 1630 u8 *buf) 1631 { 1632 int ret; 1633 1634 if (current_region->section_table.size > 0) 1635 /* Copy each section individually. */ 1636 return ath10k_pci_dump_memory_section(ar, 1637 current_region, 1638 buf, 1639 current_region->len); 1640 1641 /* No individual memory sections defined so we can 1642 * copy the entire memory region. 1643 */ 1644 ret = ath10k_pci_diag_read_mem(ar, 1645 current_region->start, 1646 buf, 1647 current_region->len); 1648 if (ret) { 1649 ath10k_warn(ar, "failed to copy ramdump region %s: %d\n", 1650 current_region->name, ret); 1651 return ret; 1652 } 1653 1654 return current_region->len; 1655 } 1656 1657 static void ath10k_pci_dump_memory(struct ath10k *ar, 1658 struct ath10k_fw_crash_data *crash_data) 1659 { 1660 const struct ath10k_hw_mem_layout *mem_layout; 1661 const struct ath10k_mem_region *current_region; 1662 struct ath10k_dump_ram_data_hdr *hdr; 1663 u32 count, shift; 1664 size_t buf_len; 1665 int ret, i; 1666 u8 *buf; 1667 1668 lockdep_assert_held(&ar->dump_mutex); 1669 1670 if (!crash_data) 1671 return; 1672 1673 mem_layout = ath10k_coredump_get_mem_layout(ar); 1674 if (!mem_layout) 1675 return; 1676 1677 current_region = &mem_layout->region_table.regions[0]; 1678 1679 buf = crash_data->ramdump_buf; 1680 buf_len = crash_data->ramdump_buf_len; 1681 1682 memset(buf, 0, buf_len); 1683 1684 for (i = 0; i < mem_layout->region_table.size; i++) { 1685 count = 0; 1686 1687 if (current_region->len > buf_len) { 1688 ath10k_warn(ar, "memory region %s size %d is larger that remaining ramdump buffer size %zu\n", 1689 current_region->name, 1690 current_region->len, 1691 buf_len); 1692 break; 1693 } 1694 1695 /* To get IRAM dump, the host driver needs to switch target 1696 * ram config from DRAM to IRAM. 1697 */ 1698 if (current_region->type == ATH10K_MEM_REGION_TYPE_IRAM1 || 1699 current_region->type == ATH10K_MEM_REGION_TYPE_IRAM2) { 1700 shift = current_region->start >> 20; 1701 1702 ret = ath10k_pci_set_ram_config(ar, shift); 1703 if (ret) { 1704 ath10k_warn(ar, "failed to switch ram config to IRAM for section %s: %d\n", 1705 current_region->name, ret); 1706 break; 1707 } 1708 } 1709 1710 /* Reserve space for the header. */ 1711 hdr = (void *)buf; 1712 buf += sizeof(*hdr); 1713 buf_len -= sizeof(*hdr); 1714 1715 switch (current_region->type) { 1716 case ATH10K_MEM_REGION_TYPE_IOSRAM: 1717 count = ath10k_pci_dump_memory_sram(ar, current_region, buf); 1718 break; 1719 case ATH10K_MEM_REGION_TYPE_IOREG: 1720 ret = ath10k_pci_dump_memory_reg(ar, current_region, buf); 1721 if (ret < 0) 1722 break; 1723 1724 count = ret; 1725 break; 1726 default: 1727 ret = ath10k_pci_dump_memory_generic(ar, current_region, buf); 1728 if (ret < 0) 1729 break; 1730 1731 count = ret; 1732 break; 1733 } 1734 1735 hdr->region_type = cpu_to_le32(current_region->type); 1736 hdr->start = cpu_to_le32(current_region->start); 1737 hdr->length = cpu_to_le32(count); 1738 1739 if (count == 0) 1740 /* Note: the header remains, just with zero length. */ 1741 break; 1742 1743 buf += count; 1744 buf_len -= count; 1745 1746 current_region++; 1747 } 1748 } 1749 1750 static void ath10k_pci_fw_dump_work(struct work_struct *work) 1751 { 1752 struct ath10k_pci *ar_pci = container_of(work, struct ath10k_pci, 1753 dump_work); 1754 struct ath10k_fw_crash_data *crash_data; 1755 struct ath10k *ar = ar_pci->ar; 1756 char guid[UUID_STRING_LEN + 1]; 1757 1758 mutex_lock(&ar->dump_mutex); 1759 1760 spin_lock_bh(&ar->data_lock); 1761 ar->stats.fw_crash_counter++; 1762 spin_unlock_bh(&ar->data_lock); 1763 1764 crash_data = ath10k_coredump_new(ar); 1765 1766 if (crash_data) 1767 scnprintf(guid, sizeof(guid), "%pUl", &crash_data->guid); 1768 else 1769 scnprintf(guid, sizeof(guid), "n/a"); 1770 1771 ath10k_err(ar, "firmware crashed! (guid %s)\n", guid); 1772 ath10k_print_driver_info(ar); 1773 ath10k_pci_dump_registers(ar, crash_data); 1774 ath10k_ce_dump_registers(ar, crash_data); 1775 ath10k_pci_dump_memory(ar, crash_data); 1776 1777 mutex_unlock(&ar->dump_mutex); 1778 1779 ath10k_core_start_recovery(ar); 1780 } 1781 1782 static void ath10k_pci_fw_crashed_dump(struct ath10k *ar) 1783 { 1784 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1785 1786 queue_work(ar->workqueue, &ar_pci->dump_work); 1787 } 1788 1789 void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe, 1790 int force) 1791 { 1792 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1793 1794 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif send complete check\n"); 1795 1796 if (!force) { 1797 int resources; 1798 /* 1799 * Decide whether to actually poll for completions, or just 1800 * wait for a later chance. 1801 * If there seem to be plenty of resources left, then just wait 1802 * since checking involves reading a CE register, which is a 1803 * relatively expensive operation. 1804 */ 1805 resources = ath10k_pci_hif_get_free_queue_number(ar, pipe); 1806 1807 /* 1808 * If at least 50% of the total resources are still available, 1809 * don't bother checking again yet. 1810 */ 1811 if (resources > (ar_pci->attr[pipe].src_nentries >> 1)) 1812 return; 1813 } 1814 ath10k_ce_per_engine_service(ar, pipe); 1815 } 1816 1817 static void ath10k_pci_rx_retry_sync(struct ath10k *ar) 1818 { 1819 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1820 1821 timer_delete_sync(&ar_pci->rx_post_retry); 1822 } 1823 1824 int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar, u16 service_id, 1825 u8 *ul_pipe, u8 *dl_pipe) 1826 { 1827 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1828 const struct ce_service_to_pipe *entry; 1829 bool ul_set = false, dl_set = false; 1830 int i; 1831 1832 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif map service\n"); 1833 1834 for (i = 0; i < ARRAY_SIZE(pci_target_service_to_ce_map_wlan); i++) { 1835 entry = &ar_pci->serv_to_pipe[i]; 1836 1837 if (__le32_to_cpu(entry->service_id) != service_id) 1838 continue; 1839 1840 switch (__le32_to_cpu(entry->pipedir)) { 1841 case PIPEDIR_NONE: 1842 break; 1843 case PIPEDIR_IN: 1844 WARN_ON(dl_set); 1845 *dl_pipe = __le32_to_cpu(entry->pipenum); 1846 dl_set = true; 1847 break; 1848 case PIPEDIR_OUT: 1849 WARN_ON(ul_set); 1850 *ul_pipe = __le32_to_cpu(entry->pipenum); 1851 ul_set = true; 1852 break; 1853 case PIPEDIR_INOUT: 1854 WARN_ON(dl_set); 1855 WARN_ON(ul_set); 1856 *dl_pipe = __le32_to_cpu(entry->pipenum); 1857 *ul_pipe = __le32_to_cpu(entry->pipenum); 1858 dl_set = true; 1859 ul_set = true; 1860 break; 1861 } 1862 } 1863 1864 if (!ul_set || !dl_set) 1865 return -ENOENT; 1866 1867 return 0; 1868 } 1869 1870 void ath10k_pci_hif_get_default_pipe(struct ath10k *ar, 1871 u8 *ul_pipe, u8 *dl_pipe) 1872 { 1873 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get default pipe\n"); 1874 1875 (void)ath10k_pci_hif_map_service_to_pipe(ar, 1876 ATH10K_HTC_SVC_ID_RSVD_CTRL, 1877 ul_pipe, dl_pipe); 1878 } 1879 1880 void ath10k_pci_irq_msi_fw_mask(struct ath10k *ar) 1881 { 1882 u32 val; 1883 1884 switch (ar->hw_rev) { 1885 case ATH10K_HW_QCA988X: 1886 case ATH10K_HW_QCA9887: 1887 case ATH10K_HW_QCA6174: 1888 case ATH10K_HW_QCA9377: 1889 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 1890 CORE_CTRL_ADDRESS); 1891 val &= ~CORE_CTRL_PCIE_REG_31_MASK; 1892 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + 1893 CORE_CTRL_ADDRESS, val); 1894 break; 1895 case ATH10K_HW_QCA99X0: 1896 case ATH10K_HW_QCA9984: 1897 case ATH10K_HW_QCA9888: 1898 case ATH10K_HW_QCA4019: 1899 /* TODO: Find appropriate register configuration for QCA99X0 1900 * to mask irq/MSI. 1901 */ 1902 break; 1903 case ATH10K_HW_WCN3990: 1904 break; 1905 } 1906 } 1907 1908 static void ath10k_pci_irq_msi_fw_unmask(struct ath10k *ar) 1909 { 1910 u32 val; 1911 1912 switch (ar->hw_rev) { 1913 case ATH10K_HW_QCA988X: 1914 case ATH10K_HW_QCA9887: 1915 case ATH10K_HW_QCA6174: 1916 case ATH10K_HW_QCA9377: 1917 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 1918 CORE_CTRL_ADDRESS); 1919 val |= CORE_CTRL_PCIE_REG_31_MASK; 1920 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + 1921 CORE_CTRL_ADDRESS, val); 1922 break; 1923 case ATH10K_HW_QCA99X0: 1924 case ATH10K_HW_QCA9984: 1925 case ATH10K_HW_QCA9888: 1926 case ATH10K_HW_QCA4019: 1927 /* TODO: Find appropriate register configuration for QCA99X0 1928 * to unmask irq/MSI. 1929 */ 1930 break; 1931 case ATH10K_HW_WCN3990: 1932 break; 1933 } 1934 } 1935 1936 static void ath10k_pci_irq_disable(struct ath10k *ar) 1937 { 1938 ath10k_ce_disable_interrupts(ar); 1939 ath10k_pci_disable_and_clear_intx_irq(ar); 1940 ath10k_pci_irq_msi_fw_mask(ar); 1941 } 1942 1943 static void ath10k_pci_irq_sync(struct ath10k *ar) 1944 { 1945 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1946 1947 synchronize_irq(ar_pci->pdev->irq); 1948 } 1949 1950 static void ath10k_pci_irq_enable(struct ath10k *ar) 1951 { 1952 ath10k_ce_enable_interrupts(ar); 1953 ath10k_pci_enable_intx_irq(ar); 1954 ath10k_pci_irq_msi_fw_unmask(ar); 1955 } 1956 1957 static int ath10k_pci_hif_start(struct ath10k *ar) 1958 { 1959 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1960 1961 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif start\n"); 1962 1963 ath10k_core_napi_enable(ar); 1964 1965 ath10k_pci_irq_enable(ar); 1966 ath10k_pci_rx_post(ar); 1967 1968 pcie_capability_clear_and_set_word(ar_pci->pdev, PCI_EXP_LNKCTL, 1969 PCI_EXP_LNKCTL_ASPMC, 1970 ar_pci->link_ctl & PCI_EXP_LNKCTL_ASPMC); 1971 1972 return 0; 1973 } 1974 1975 static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe) 1976 { 1977 struct ath10k *ar; 1978 struct ath10k_ce_pipe *ce_pipe; 1979 struct ath10k_ce_ring *ce_ring; 1980 struct sk_buff *skb; 1981 int i; 1982 1983 ar = pci_pipe->hif_ce_state; 1984 ce_pipe = pci_pipe->ce_hdl; 1985 ce_ring = ce_pipe->dest_ring; 1986 1987 if (!ce_ring) 1988 return; 1989 1990 if (!pci_pipe->buf_sz) 1991 return; 1992 1993 for (i = 0; i < ce_ring->nentries; i++) { 1994 skb = ce_ring->per_transfer_context[i]; 1995 if (!skb) 1996 continue; 1997 1998 ce_ring->per_transfer_context[i] = NULL; 1999 2000 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, 2001 skb->len + skb_tailroom(skb), 2002 DMA_FROM_DEVICE); 2003 dev_kfree_skb_any(skb); 2004 } 2005 } 2006 2007 static void ath10k_pci_tx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe) 2008 { 2009 struct ath10k *ar; 2010 struct ath10k_ce_pipe *ce_pipe; 2011 struct ath10k_ce_ring *ce_ring; 2012 struct sk_buff *skb; 2013 int i; 2014 2015 ar = pci_pipe->hif_ce_state; 2016 ce_pipe = pci_pipe->ce_hdl; 2017 ce_ring = ce_pipe->src_ring; 2018 2019 if (!ce_ring) 2020 return; 2021 2022 if (!pci_pipe->buf_sz) 2023 return; 2024 2025 for (i = 0; i < ce_ring->nentries; i++) { 2026 skb = ce_ring->per_transfer_context[i]; 2027 if (!skb) 2028 continue; 2029 2030 ce_ring->per_transfer_context[i] = NULL; 2031 2032 ath10k_htc_tx_completion_handler(ar, skb); 2033 } 2034 } 2035 2036 /* 2037 * Cleanup residual buffers for device shutdown: 2038 * buffers that were enqueued for receive 2039 * buffers that were to be sent 2040 * Note: Buffers that had completed but which were 2041 * not yet processed are on a completion queue. They 2042 * are handled when the completion thread shuts down. 2043 */ 2044 static void ath10k_pci_buffer_cleanup(struct ath10k *ar) 2045 { 2046 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2047 int pipe_num; 2048 2049 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) { 2050 struct ath10k_pci_pipe *pipe_info; 2051 2052 pipe_info = &ar_pci->pipe_info[pipe_num]; 2053 ath10k_pci_rx_pipe_cleanup(pipe_info); 2054 ath10k_pci_tx_pipe_cleanup(pipe_info); 2055 } 2056 } 2057 2058 void ath10k_pci_ce_deinit(struct ath10k *ar) 2059 { 2060 int i; 2061 2062 for (i = 0; i < CE_COUNT; i++) 2063 ath10k_ce_deinit_pipe(ar, i); 2064 } 2065 2066 void ath10k_pci_flush(struct ath10k *ar) 2067 { 2068 ath10k_pci_rx_retry_sync(ar); 2069 ath10k_pci_buffer_cleanup(ar); 2070 } 2071 2072 static void ath10k_pci_hif_stop(struct ath10k *ar) 2073 { 2074 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2075 unsigned long flags; 2076 2077 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif stop\n"); 2078 2079 ath10k_pci_irq_disable(ar); 2080 ath10k_pci_irq_sync(ar); 2081 2082 ath10k_core_napi_sync_disable(ar); 2083 2084 cancel_work_sync(&ar_pci->dump_work); 2085 2086 /* Most likely the device has HTT Rx ring configured. The only way to 2087 * prevent the device from accessing (and possible corrupting) host 2088 * memory is to reset the chip now. 2089 * 2090 * There's also no known way of masking MSI interrupts on the device. 2091 * For ranged MSI the CE-related interrupts can be masked. However 2092 * regardless how many MSI interrupts are assigned the first one 2093 * is always used for firmware indications (crashes) and cannot be 2094 * masked. To prevent the device from asserting the interrupt reset it 2095 * before proceeding with cleanup. 2096 */ 2097 ath10k_pci_safe_chip_reset(ar); 2098 2099 ath10k_pci_flush(ar); 2100 2101 spin_lock_irqsave(&ar_pci->ps_lock, flags); 2102 WARN_ON(ar_pci->ps_wake_refcount > 0); 2103 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 2104 } 2105 2106 int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar, 2107 void *req, u32 req_len, 2108 void *resp, u32 *resp_len) 2109 { 2110 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2111 struct ath10k_pci_pipe *pci_tx = &ar_pci->pipe_info[BMI_CE_NUM_TO_TARG]; 2112 struct ath10k_pci_pipe *pci_rx = &ar_pci->pipe_info[BMI_CE_NUM_TO_HOST]; 2113 struct ath10k_ce_pipe *ce_tx = pci_tx->ce_hdl; 2114 struct ath10k_ce_pipe *ce_rx = pci_rx->ce_hdl; 2115 dma_addr_t req_paddr = 0; 2116 dma_addr_t resp_paddr = 0; 2117 struct bmi_xfer xfer = {}; 2118 void *treq, *tresp = NULL; 2119 int ret = 0; 2120 2121 might_sleep(); 2122 2123 if (resp && !resp_len) 2124 return -EINVAL; 2125 2126 if (resp && resp_len && *resp_len == 0) 2127 return -EINVAL; 2128 2129 treq = kmemdup(req, req_len, GFP_KERNEL); 2130 if (!treq) 2131 return -ENOMEM; 2132 2133 req_paddr = dma_map_single(ar->dev, treq, req_len, DMA_TO_DEVICE); 2134 ret = dma_mapping_error(ar->dev, req_paddr); 2135 if (ret) { 2136 ret = -EIO; 2137 goto err_dma; 2138 } 2139 2140 if (resp && resp_len) { 2141 tresp = kzalloc(*resp_len, GFP_KERNEL); 2142 if (!tresp) { 2143 ret = -ENOMEM; 2144 goto err_req; 2145 } 2146 2147 resp_paddr = dma_map_single(ar->dev, tresp, *resp_len, 2148 DMA_FROM_DEVICE); 2149 ret = dma_mapping_error(ar->dev, resp_paddr); 2150 if (ret) { 2151 ret = -EIO; 2152 goto err_req; 2153 } 2154 2155 xfer.wait_for_resp = true; 2156 xfer.resp_len = 0; 2157 2158 ath10k_ce_rx_post_buf(ce_rx, &xfer, resp_paddr); 2159 } 2160 2161 ret = ath10k_ce_send(ce_tx, &xfer, req_paddr, req_len, -1, 0); 2162 if (ret) 2163 goto err_resp; 2164 2165 ret = ath10k_pci_bmi_wait(ar, ce_tx, ce_rx, &xfer); 2166 if (ret) { 2167 dma_addr_t unused_buffer; 2168 unsigned int unused_nbytes; 2169 unsigned int unused_id; 2170 2171 ath10k_ce_cancel_send_next(ce_tx, NULL, &unused_buffer, 2172 &unused_nbytes, &unused_id); 2173 } else { 2174 /* non-zero means we did not time out */ 2175 ret = 0; 2176 } 2177 2178 err_resp: 2179 if (resp) { 2180 dma_addr_t unused_buffer; 2181 2182 ath10k_ce_revoke_recv_next(ce_rx, NULL, &unused_buffer); 2183 dma_unmap_single(ar->dev, resp_paddr, 2184 *resp_len, DMA_FROM_DEVICE); 2185 } 2186 err_req: 2187 dma_unmap_single(ar->dev, req_paddr, req_len, DMA_TO_DEVICE); 2188 2189 if (ret == 0 && resp_len) { 2190 *resp_len = min(*resp_len, xfer.resp_len); 2191 memcpy(resp, tresp, *resp_len); 2192 } 2193 err_dma: 2194 kfree(treq); 2195 kfree(tresp); 2196 2197 return ret; 2198 } 2199 2200 static void ath10k_pci_bmi_send_done(struct ath10k_ce_pipe *ce_state) 2201 { 2202 struct bmi_xfer *xfer; 2203 2204 if (ath10k_ce_completed_send_next(ce_state, (void **)&xfer)) 2205 return; 2206 2207 xfer->tx_done = true; 2208 } 2209 2210 static void ath10k_pci_bmi_recv_data(struct ath10k_ce_pipe *ce_state) 2211 { 2212 struct ath10k *ar = ce_state->ar; 2213 struct bmi_xfer *xfer; 2214 unsigned int nbytes; 2215 2216 if (ath10k_ce_completed_recv_next(ce_state, (void **)&xfer, 2217 &nbytes)) 2218 return; 2219 2220 if (WARN_ON_ONCE(!xfer)) 2221 return; 2222 2223 if (!xfer->wait_for_resp) { 2224 ath10k_warn(ar, "unexpected: BMI data received; ignoring\n"); 2225 return; 2226 } 2227 2228 xfer->resp_len = nbytes; 2229 xfer->rx_done = true; 2230 } 2231 2232 static int ath10k_pci_bmi_wait(struct ath10k *ar, 2233 struct ath10k_ce_pipe *tx_pipe, 2234 struct ath10k_ce_pipe *rx_pipe, 2235 struct bmi_xfer *xfer) 2236 { 2237 unsigned long timeout = jiffies + BMI_COMMUNICATION_TIMEOUT_HZ; 2238 unsigned long started = jiffies; 2239 unsigned long dur; 2240 int ret; 2241 2242 while (time_before_eq(jiffies, timeout)) { 2243 ath10k_pci_bmi_send_done(tx_pipe); 2244 ath10k_pci_bmi_recv_data(rx_pipe); 2245 2246 if (xfer->tx_done && (xfer->rx_done == xfer->wait_for_resp)) { 2247 ret = 0; 2248 goto out; 2249 } 2250 2251 schedule(); 2252 } 2253 2254 ret = -ETIMEDOUT; 2255 2256 out: 2257 dur = jiffies - started; 2258 if (dur > HZ) 2259 ath10k_dbg(ar, ATH10K_DBG_BMI, 2260 "bmi cmd took %lu jiffies hz %d ret %d\n", 2261 dur, HZ, ret); 2262 return ret; 2263 } 2264 2265 /* 2266 * Send an interrupt to the device to wake up the Target CPU 2267 * so it has an opportunity to notice any changed state. 2268 */ 2269 static int ath10k_pci_wake_target_cpu(struct ath10k *ar) 2270 { 2271 u32 addr, val; 2272 2273 addr = SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS; 2274 val = ath10k_pci_read32(ar, addr); 2275 val |= CORE_CTRL_CPU_INTR_MASK; 2276 ath10k_pci_write32(ar, addr, val); 2277 2278 return 0; 2279 } 2280 2281 static int ath10k_pci_get_num_banks(struct ath10k *ar) 2282 { 2283 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2284 2285 switch (ar_pci->pdev->device) { 2286 case QCA988X_2_0_DEVICE_ID_UBNT: 2287 case QCA988X_2_0_DEVICE_ID: 2288 case QCA99X0_2_0_DEVICE_ID: 2289 case QCA9888_2_0_DEVICE_ID: 2290 case QCA9984_1_0_DEVICE_ID: 2291 case QCA9887_1_0_DEVICE_ID: 2292 return 1; 2293 case QCA6164_2_1_DEVICE_ID: 2294 case QCA6174_2_1_DEVICE_ID: 2295 switch (MS(ar->bus_param.chip_id, SOC_CHIP_ID_REV)) { 2296 case QCA6174_HW_1_0_CHIP_ID_REV: 2297 case QCA6174_HW_1_1_CHIP_ID_REV: 2298 case QCA6174_HW_2_1_CHIP_ID_REV: 2299 case QCA6174_HW_2_2_CHIP_ID_REV: 2300 return 3; 2301 case QCA6174_HW_1_3_CHIP_ID_REV: 2302 return 2; 2303 case QCA6174_HW_3_0_CHIP_ID_REV: 2304 case QCA6174_HW_3_1_CHIP_ID_REV: 2305 case QCA6174_HW_3_2_CHIP_ID_REV: 2306 return 9; 2307 } 2308 break; 2309 case QCA9377_1_0_DEVICE_ID: 2310 return 9; 2311 } 2312 2313 ath10k_warn(ar, "unknown number of banks, assuming 1\n"); 2314 return 1; 2315 } 2316 2317 static int ath10k_bus_get_num_banks(struct ath10k *ar) 2318 { 2319 struct ath10k_ce *ce = ath10k_ce_priv(ar); 2320 2321 return ce->bus_ops->get_num_banks(ar); 2322 } 2323 2324 int ath10k_pci_init_config(struct ath10k *ar) 2325 { 2326 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2327 u32 interconnect_targ_addr; 2328 u32 pcie_state_targ_addr = 0; 2329 u32 pipe_cfg_targ_addr = 0; 2330 u32 svc_to_pipe_map = 0; 2331 u32 pcie_config_flags = 0; 2332 u32 ealloc_value; 2333 u32 ealloc_targ_addr; 2334 u32 flag2_value; 2335 u32 flag2_targ_addr; 2336 int ret = 0; 2337 2338 /* Download to Target the CE Config and the service-to-CE map */ 2339 interconnect_targ_addr = 2340 host_interest_item_address(HI_ITEM(hi_interconnect_state)); 2341 2342 /* Supply Target-side CE configuration */ 2343 ret = ath10k_pci_diag_read32(ar, interconnect_targ_addr, 2344 &pcie_state_targ_addr); 2345 if (ret != 0) { 2346 ath10k_err(ar, "Failed to get pcie state addr: %d\n", ret); 2347 return ret; 2348 } 2349 2350 if (pcie_state_targ_addr == 0) { 2351 ret = -EIO; 2352 ath10k_err(ar, "Invalid pcie state addr\n"); 2353 return ret; 2354 } 2355 2356 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr + 2357 offsetof(struct pcie_state, 2358 pipe_cfg_addr)), 2359 &pipe_cfg_targ_addr); 2360 if (ret != 0) { 2361 ath10k_err(ar, "Failed to get pipe cfg addr: %d\n", ret); 2362 return ret; 2363 } 2364 2365 if (pipe_cfg_targ_addr == 0) { 2366 ret = -EIO; 2367 ath10k_err(ar, "Invalid pipe cfg addr\n"); 2368 return ret; 2369 } 2370 2371 ret = ath10k_pci_diag_write_mem(ar, pipe_cfg_targ_addr, 2372 ar_pci->pipe_config, 2373 sizeof(struct ce_pipe_config) * 2374 NUM_TARGET_CE_CONFIG_WLAN); 2375 2376 if (ret != 0) { 2377 ath10k_err(ar, "Failed to write pipe cfg: %d\n", ret); 2378 return ret; 2379 } 2380 2381 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr + 2382 offsetof(struct pcie_state, 2383 svc_to_pipe_map)), 2384 &svc_to_pipe_map); 2385 if (ret != 0) { 2386 ath10k_err(ar, "Failed to get svc/pipe map: %d\n", ret); 2387 return ret; 2388 } 2389 2390 if (svc_to_pipe_map == 0) { 2391 ret = -EIO; 2392 ath10k_err(ar, "Invalid svc_to_pipe map\n"); 2393 return ret; 2394 } 2395 2396 ret = ath10k_pci_diag_write_mem(ar, svc_to_pipe_map, 2397 ar_pci->serv_to_pipe, 2398 sizeof(pci_target_service_to_ce_map_wlan)); 2399 if (ret != 0) { 2400 ath10k_err(ar, "Failed to write svc/pipe map: %d\n", ret); 2401 return ret; 2402 } 2403 2404 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr + 2405 offsetof(struct pcie_state, 2406 config_flags)), 2407 &pcie_config_flags); 2408 if (ret != 0) { 2409 ath10k_err(ar, "Failed to get pcie config_flags: %d\n", ret); 2410 return ret; 2411 } 2412 2413 pcie_config_flags &= ~PCIE_CONFIG_FLAG_ENABLE_L1; 2414 2415 ret = ath10k_pci_diag_write32(ar, (pcie_state_targ_addr + 2416 offsetof(struct pcie_state, 2417 config_flags)), 2418 pcie_config_flags); 2419 if (ret != 0) { 2420 ath10k_err(ar, "Failed to write pcie config_flags: %d\n", ret); 2421 return ret; 2422 } 2423 2424 /* configure early allocation */ 2425 ealloc_targ_addr = host_interest_item_address(HI_ITEM(hi_early_alloc)); 2426 2427 ret = ath10k_pci_diag_read32(ar, ealloc_targ_addr, &ealloc_value); 2428 if (ret != 0) { 2429 ath10k_err(ar, "Failed to get early alloc val: %d\n", ret); 2430 return ret; 2431 } 2432 2433 /* first bank is switched to IRAM */ 2434 ealloc_value |= ((HI_EARLY_ALLOC_MAGIC << HI_EARLY_ALLOC_MAGIC_SHIFT) & 2435 HI_EARLY_ALLOC_MAGIC_MASK); 2436 ealloc_value |= ((ath10k_bus_get_num_banks(ar) << 2437 HI_EARLY_ALLOC_IRAM_BANKS_SHIFT) & 2438 HI_EARLY_ALLOC_IRAM_BANKS_MASK); 2439 2440 ret = ath10k_pci_diag_write32(ar, ealloc_targ_addr, ealloc_value); 2441 if (ret != 0) { 2442 ath10k_err(ar, "Failed to set early alloc val: %d\n", ret); 2443 return ret; 2444 } 2445 2446 /* Tell Target to proceed with initialization */ 2447 flag2_targ_addr = host_interest_item_address(HI_ITEM(hi_option_flag2)); 2448 2449 ret = ath10k_pci_diag_read32(ar, flag2_targ_addr, &flag2_value); 2450 if (ret != 0) { 2451 ath10k_err(ar, "Failed to get option val: %d\n", ret); 2452 return ret; 2453 } 2454 2455 flag2_value |= HI_OPTION_EARLY_CFG_DONE; 2456 2457 ret = ath10k_pci_diag_write32(ar, flag2_targ_addr, flag2_value); 2458 if (ret != 0) { 2459 ath10k_err(ar, "Failed to set option val: %d\n", ret); 2460 return ret; 2461 } 2462 2463 return 0; 2464 } 2465 2466 static void ath10k_pci_override_ce_config(struct ath10k *ar) 2467 { 2468 struct ce_attr *attr; 2469 struct ce_pipe_config *config; 2470 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2471 2472 /* For QCA6174 we're overriding the Copy Engine 5 configuration, 2473 * since it is currently used for other feature. 2474 */ 2475 2476 /* Override Host's Copy Engine 5 configuration */ 2477 attr = &ar_pci->attr[5]; 2478 attr->src_sz_max = 0; 2479 attr->dest_nentries = 0; 2480 2481 /* Override Target firmware's Copy Engine configuration */ 2482 config = &ar_pci->pipe_config[5]; 2483 config->pipedir = __cpu_to_le32(PIPEDIR_OUT); 2484 config->nbytes_max = __cpu_to_le32(2048); 2485 2486 /* Map from service/endpoint to Copy Engine */ 2487 ar_pci->serv_to_pipe[15].pipenum = __cpu_to_le32(1); 2488 } 2489 2490 int ath10k_pci_alloc_pipes(struct ath10k *ar) 2491 { 2492 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2493 struct ath10k_pci_pipe *pipe; 2494 struct ath10k_ce *ce = ath10k_ce_priv(ar); 2495 int i, ret; 2496 2497 for (i = 0; i < CE_COUNT; i++) { 2498 pipe = &ar_pci->pipe_info[i]; 2499 pipe->ce_hdl = &ce->ce_states[i]; 2500 pipe->pipe_num = i; 2501 pipe->hif_ce_state = ar; 2502 2503 ret = ath10k_ce_alloc_pipe(ar, i, &ar_pci->attr[i]); 2504 if (ret) { 2505 ath10k_err(ar, "failed to allocate copy engine pipe %d: %d\n", 2506 i, ret); 2507 return ret; 2508 } 2509 2510 /* Last CE is Diagnostic Window */ 2511 if (i == CE_DIAG_PIPE) { 2512 ar_pci->ce_diag = pipe->ce_hdl; 2513 continue; 2514 } 2515 2516 pipe->buf_sz = (size_t)(ar_pci->attr[i].src_sz_max); 2517 } 2518 2519 return 0; 2520 } 2521 2522 void ath10k_pci_free_pipes(struct ath10k *ar) 2523 { 2524 int i; 2525 2526 for (i = 0; i < CE_COUNT; i++) 2527 ath10k_ce_free_pipe(ar, i); 2528 } 2529 2530 int ath10k_pci_init_pipes(struct ath10k *ar) 2531 { 2532 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2533 int i, ret; 2534 2535 for (i = 0; i < CE_COUNT; i++) { 2536 ret = ath10k_ce_init_pipe(ar, i, &ar_pci->attr[i]); 2537 if (ret) { 2538 ath10k_err(ar, "failed to initialize copy engine pipe %d: %d\n", 2539 i, ret); 2540 return ret; 2541 } 2542 } 2543 2544 return 0; 2545 } 2546 2547 static bool ath10k_pci_has_fw_crashed(struct ath10k *ar) 2548 { 2549 return ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS) & 2550 FW_IND_EVENT_PENDING; 2551 } 2552 2553 static void ath10k_pci_fw_crashed_clear(struct ath10k *ar) 2554 { 2555 u32 val; 2556 2557 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS); 2558 val &= ~FW_IND_EVENT_PENDING; 2559 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, val); 2560 } 2561 2562 static bool ath10k_pci_has_device_gone(struct ath10k *ar) 2563 { 2564 u32 val; 2565 2566 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS); 2567 return (val == 0xffffffff); 2568 } 2569 2570 /* this function effectively clears target memory controller assert line */ 2571 static void ath10k_pci_warm_reset_si0(struct ath10k *ar) 2572 { 2573 u32 val; 2574 2575 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); 2576 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS, 2577 val | SOC_RESET_CONTROL_SI0_RST_MASK); 2578 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); 2579 2580 msleep(10); 2581 2582 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); 2583 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS, 2584 val & ~SOC_RESET_CONTROL_SI0_RST_MASK); 2585 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); 2586 2587 msleep(10); 2588 } 2589 2590 static void ath10k_pci_warm_reset_cpu(struct ath10k *ar) 2591 { 2592 u32 val; 2593 2594 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, 0); 2595 2596 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); 2597 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS, 2598 val | SOC_RESET_CONTROL_CPU_WARM_RST_MASK); 2599 } 2600 2601 static void ath10k_pci_warm_reset_ce(struct ath10k *ar) 2602 { 2603 u32 val; 2604 2605 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); 2606 2607 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS, 2608 val | SOC_RESET_CONTROL_CE_RST_MASK); 2609 msleep(10); 2610 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS, 2611 val & ~SOC_RESET_CONTROL_CE_RST_MASK); 2612 } 2613 2614 static void ath10k_pci_warm_reset_clear_lf(struct ath10k *ar) 2615 { 2616 u32 val; 2617 2618 val = ath10k_pci_soc_read32(ar, SOC_LF_TIMER_CONTROL0_ADDRESS); 2619 ath10k_pci_soc_write32(ar, SOC_LF_TIMER_CONTROL0_ADDRESS, 2620 val & ~SOC_LF_TIMER_CONTROL0_ENABLE_MASK); 2621 } 2622 2623 static int ath10k_pci_warm_reset(struct ath10k *ar) 2624 { 2625 int ret; 2626 2627 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset\n"); 2628 2629 spin_lock_bh(&ar->data_lock); 2630 ar->stats.fw_warm_reset_counter++; 2631 spin_unlock_bh(&ar->data_lock); 2632 2633 ath10k_pci_irq_disable(ar); 2634 2635 /* Make sure the target CPU is not doing anything dangerous, e.g. if it 2636 * were to access copy engine while host performs copy engine reset 2637 * then it is possible for the device to confuse pci-e controller to 2638 * the point of bringing host system to a complete stop (i.e. hang). 2639 */ 2640 ath10k_pci_warm_reset_si0(ar); 2641 ath10k_pci_warm_reset_cpu(ar); 2642 ath10k_pci_init_pipes(ar); 2643 ath10k_pci_wait_for_target_init(ar); 2644 2645 ath10k_pci_warm_reset_clear_lf(ar); 2646 ath10k_pci_warm_reset_ce(ar); 2647 ath10k_pci_warm_reset_cpu(ar); 2648 ath10k_pci_init_pipes(ar); 2649 2650 ret = ath10k_pci_wait_for_target_init(ar); 2651 if (ret) { 2652 ath10k_warn(ar, "failed to wait for target init: %d\n", ret); 2653 return ret; 2654 } 2655 2656 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset complete\n"); 2657 2658 return 0; 2659 } 2660 2661 static int ath10k_pci_qca99x0_soft_chip_reset(struct ath10k *ar) 2662 { 2663 ath10k_pci_irq_disable(ar); 2664 return ath10k_pci_qca99x0_chip_reset(ar); 2665 } 2666 2667 static int ath10k_pci_safe_chip_reset(struct ath10k *ar) 2668 { 2669 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2670 2671 if (!ar_pci->pci_soft_reset) 2672 return -EOPNOTSUPP; 2673 2674 return ar_pci->pci_soft_reset(ar); 2675 } 2676 2677 static int ath10k_pci_qca988x_chip_reset(struct ath10k *ar) 2678 { 2679 int i, ret; 2680 u32 val; 2681 2682 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot 988x chip reset\n"); 2683 2684 /* Some hardware revisions (e.g. CUS223v2) has issues with cold reset. 2685 * It is thus preferred to use warm reset which is safer but may not be 2686 * able to recover the device from all possible fail scenarios. 2687 * 2688 * Warm reset doesn't always work on first try so attempt it a few 2689 * times before giving up. 2690 */ 2691 for (i = 0; i < ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS; i++) { 2692 ret = ath10k_pci_warm_reset(ar); 2693 if (ret) { 2694 ath10k_warn(ar, "failed to warm reset attempt %d of %d: %d\n", 2695 i + 1, ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS, 2696 ret); 2697 continue; 2698 } 2699 2700 /* FIXME: Sometimes copy engine doesn't recover after warm 2701 * reset. In most cases this needs cold reset. In some of these 2702 * cases the device is in such a state that a cold reset may 2703 * lock up the host. 2704 * 2705 * Reading any host interest register via copy engine is 2706 * sufficient to verify if device is capable of booting 2707 * firmware blob. 2708 */ 2709 ret = ath10k_pci_init_pipes(ar); 2710 if (ret) { 2711 ath10k_warn(ar, "failed to init copy engine: %d\n", 2712 ret); 2713 continue; 2714 } 2715 2716 ret = ath10k_pci_diag_read32(ar, QCA988X_HOST_INTEREST_ADDRESS, 2717 &val); 2718 if (ret) { 2719 ath10k_warn(ar, "failed to poke copy engine: %d\n", 2720 ret); 2721 continue; 2722 } 2723 2724 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot chip reset complete (warm)\n"); 2725 return 0; 2726 } 2727 2728 if (ath10k_pci_reset_mode == ATH10K_PCI_RESET_WARM_ONLY) { 2729 ath10k_warn(ar, "refusing cold reset as requested\n"); 2730 return -EPERM; 2731 } 2732 2733 ret = ath10k_pci_cold_reset(ar); 2734 if (ret) { 2735 ath10k_warn(ar, "failed to cold reset: %d\n", ret); 2736 return ret; 2737 } 2738 2739 ret = ath10k_pci_wait_for_target_init(ar); 2740 if (ret) { 2741 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n", 2742 ret); 2743 return ret; 2744 } 2745 2746 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca988x chip reset complete (cold)\n"); 2747 2748 return 0; 2749 } 2750 2751 static int ath10k_pci_qca6174_chip_reset(struct ath10k *ar) 2752 { 2753 int ret; 2754 2755 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset\n"); 2756 2757 /* FIXME: QCA6174 requires cold + warm reset to work. */ 2758 2759 ret = ath10k_pci_cold_reset(ar); 2760 if (ret) { 2761 ath10k_warn(ar, "failed to cold reset: %d\n", ret); 2762 return ret; 2763 } 2764 2765 ret = ath10k_pci_wait_for_target_init(ar); 2766 if (ret) { 2767 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n", 2768 ret); 2769 return ret; 2770 } 2771 2772 ret = ath10k_pci_warm_reset(ar); 2773 if (ret) { 2774 ath10k_warn(ar, "failed to warm reset: %d\n", ret); 2775 return ret; 2776 } 2777 2778 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset complete (cold)\n"); 2779 2780 return 0; 2781 } 2782 2783 static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar) 2784 { 2785 int ret; 2786 2787 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca99x0 chip reset\n"); 2788 2789 ret = ath10k_pci_cold_reset(ar); 2790 if (ret) { 2791 ath10k_warn(ar, "failed to cold reset: %d\n", ret); 2792 return ret; 2793 } 2794 2795 ret = ath10k_pci_wait_for_target_init(ar); 2796 if (ret) { 2797 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n", 2798 ret); 2799 return ret; 2800 } 2801 2802 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca99x0 chip reset complete (cold)\n"); 2803 2804 return 0; 2805 } 2806 2807 static int ath10k_pci_chip_reset(struct ath10k *ar) 2808 { 2809 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2810 2811 if (WARN_ON(!ar_pci->pci_hard_reset)) 2812 return -EOPNOTSUPP; 2813 2814 return ar_pci->pci_hard_reset(ar); 2815 } 2816 2817 static int ath10k_pci_hif_power_up(struct ath10k *ar, 2818 enum ath10k_firmware_mode fw_mode) 2819 { 2820 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2821 int ret; 2822 2823 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power up\n"); 2824 2825 pcie_capability_read_word(ar_pci->pdev, PCI_EXP_LNKCTL, 2826 &ar_pci->link_ctl); 2827 pcie_capability_clear_word(ar_pci->pdev, PCI_EXP_LNKCTL, 2828 PCI_EXP_LNKCTL_ASPMC); 2829 2830 /* 2831 * Bring the target up cleanly. 2832 * 2833 * The target may be in an undefined state with an AUX-powered Target 2834 * and a Host in WoW mode. If the Host crashes, loses power, or is 2835 * restarted (without unloading the driver) then the Target is left 2836 * (aux) powered and running. On a subsequent driver load, the Target 2837 * is in an unexpected state. We try to catch that here in order to 2838 * reset the Target and retry the probe. 2839 */ 2840 ret = ath10k_pci_chip_reset(ar); 2841 if (ret) { 2842 if (ath10k_pci_has_fw_crashed(ar)) { 2843 ath10k_warn(ar, "firmware crashed during chip reset\n"); 2844 ath10k_pci_fw_crashed_clear(ar); 2845 ath10k_pci_fw_crashed_dump(ar); 2846 } 2847 2848 ath10k_err(ar, "failed to reset chip: %d\n", ret); 2849 goto err_sleep; 2850 } 2851 2852 ret = ath10k_pci_init_pipes(ar); 2853 if (ret) { 2854 ath10k_err(ar, "failed to initialize CE: %d\n", ret); 2855 goto err_sleep; 2856 } 2857 2858 ret = ath10k_pci_init_config(ar); 2859 if (ret) { 2860 ath10k_err(ar, "failed to setup init config: %d\n", ret); 2861 goto err_ce; 2862 } 2863 2864 ret = ath10k_pci_wake_target_cpu(ar); 2865 if (ret) { 2866 ath10k_err(ar, "could not wake up target CPU: %d\n", ret); 2867 goto err_ce; 2868 } 2869 2870 return 0; 2871 2872 err_ce: 2873 ath10k_pci_ce_deinit(ar); 2874 2875 err_sleep: 2876 return ret; 2877 } 2878 2879 void ath10k_pci_hif_power_down(struct ath10k *ar) 2880 { 2881 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power down\n"); 2882 2883 /* Currently hif_power_up performs effectively a reset and hif_stop 2884 * resets the chip as well so there's no point in resetting here. 2885 */ 2886 } 2887 2888 static int ath10k_pci_hif_suspend(struct ath10k *ar) 2889 { 2890 /* Nothing to do; the important stuff is in the driver suspend. */ 2891 return 0; 2892 } 2893 2894 static int ath10k_pci_suspend(struct ath10k *ar) 2895 { 2896 /* The grace timer can still be counting down and ar->ps_awake be true. 2897 * It is known that the device may be asleep after resuming regardless 2898 * of the SoC powersave state before suspending. Hence make sure the 2899 * device is asleep before proceeding. 2900 */ 2901 ath10k_pci_sleep_sync(ar); 2902 2903 return 0; 2904 } 2905 2906 static int ath10k_pci_hif_resume(struct ath10k *ar) 2907 { 2908 /* Nothing to do; the important stuff is in the driver resume. */ 2909 return 0; 2910 } 2911 2912 static int ath10k_pci_resume(struct ath10k *ar) 2913 { 2914 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2915 struct pci_dev *pdev = ar_pci->pdev; 2916 u32 val; 2917 int ret = 0; 2918 2919 ret = ath10k_pci_force_wake(ar); 2920 if (ret) { 2921 ath10k_err(ar, "failed to wake up target: %d\n", ret); 2922 return ret; 2923 } 2924 2925 /* Suspend/Resume resets the PCI configuration space, so we have to 2926 * re-disable the RETRY_TIMEOUT register (0x41) to keep PCI Tx retries 2927 * from interfering with C3 CPU state. pci_restore_state won't help 2928 * here since it only restores the first 64 bytes pci config header. 2929 */ 2930 pci_read_config_dword(pdev, 0x40, &val); 2931 if ((val & 0x0000ff00) != 0) 2932 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); 2933 2934 return ret; 2935 } 2936 2937 static bool ath10k_pci_validate_cal(void *data, size_t size) 2938 { 2939 __le16 *cal_words = data; 2940 u16 checksum = 0; 2941 size_t i; 2942 2943 if (size % 2 != 0) 2944 return false; 2945 2946 for (i = 0; i < size / 2; i++) 2947 checksum ^= le16_to_cpu(cal_words[i]); 2948 2949 return checksum == 0xffff; 2950 } 2951 2952 static void ath10k_pci_enable_eeprom(struct ath10k *ar) 2953 { 2954 /* Enable SI clock */ 2955 ath10k_pci_soc_write32(ar, CLOCK_CONTROL_OFFSET, 0x0); 2956 2957 /* Configure GPIOs for I2C operation */ 2958 ath10k_pci_write32(ar, 2959 GPIO_BASE_ADDRESS + GPIO_PIN0_OFFSET + 2960 4 * QCA9887_1_0_I2C_SDA_GPIO_PIN, 2961 SM(QCA9887_1_0_I2C_SDA_PIN_CONFIG, 2962 GPIO_PIN0_CONFIG) | 2963 SM(1, GPIO_PIN0_PAD_PULL)); 2964 2965 ath10k_pci_write32(ar, 2966 GPIO_BASE_ADDRESS + GPIO_PIN0_OFFSET + 2967 4 * QCA9887_1_0_SI_CLK_GPIO_PIN, 2968 SM(QCA9887_1_0_SI_CLK_PIN_CONFIG, GPIO_PIN0_CONFIG) | 2969 SM(1, GPIO_PIN0_PAD_PULL)); 2970 2971 ath10k_pci_write32(ar, 2972 GPIO_BASE_ADDRESS + 2973 QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS, 2974 1u << QCA9887_1_0_SI_CLK_GPIO_PIN); 2975 2976 /* In Swift ASIC - EEPROM clock will be (110MHz/512) = 214KHz */ 2977 ath10k_pci_write32(ar, 2978 SI_BASE_ADDRESS + SI_CONFIG_OFFSET, 2979 SM(1, SI_CONFIG_ERR_INT) | 2980 SM(1, SI_CONFIG_BIDIR_OD_DATA) | 2981 SM(1, SI_CONFIG_I2C) | 2982 SM(1, SI_CONFIG_POS_SAMPLE) | 2983 SM(1, SI_CONFIG_INACTIVE_DATA) | 2984 SM(1, SI_CONFIG_INACTIVE_CLK) | 2985 SM(8, SI_CONFIG_DIVIDER)); 2986 } 2987 2988 static int ath10k_pci_read_eeprom(struct ath10k *ar, u16 addr, u8 *out) 2989 { 2990 u32 reg; 2991 int wait_limit; 2992 2993 /* set device select byte and for the read operation */ 2994 reg = QCA9887_EEPROM_SELECT_READ | 2995 SM(addr, QCA9887_EEPROM_ADDR_LO) | 2996 SM(addr >> 8, QCA9887_EEPROM_ADDR_HI); 2997 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_TX_DATA0_OFFSET, reg); 2998 2999 /* write transmit data, transfer length, and START bit */ 3000 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET, 3001 SM(1, SI_CS_START) | SM(1, SI_CS_RX_CNT) | 3002 SM(4, SI_CS_TX_CNT)); 3003 3004 /* wait max 1 sec */ 3005 wait_limit = 100000; 3006 3007 /* wait for SI_CS_DONE_INT */ 3008 do { 3009 reg = ath10k_pci_read32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET); 3010 if (MS(reg, SI_CS_DONE_INT)) 3011 break; 3012 3013 wait_limit--; 3014 udelay(10); 3015 } while (wait_limit > 0); 3016 3017 if (!MS(reg, SI_CS_DONE_INT)) { 3018 ath10k_err(ar, "timeout while reading device EEPROM at %04x\n", 3019 addr); 3020 return -ETIMEDOUT; 3021 } 3022 3023 /* clear SI_CS_DONE_INT */ 3024 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET, reg); 3025 3026 if (MS(reg, SI_CS_DONE_ERR)) { 3027 ath10k_err(ar, "failed to read device EEPROM at %04x\n", addr); 3028 return -EIO; 3029 } 3030 3031 /* extract receive data */ 3032 reg = ath10k_pci_read32(ar, SI_BASE_ADDRESS + SI_RX_DATA0_OFFSET); 3033 *out = reg; 3034 3035 return 0; 3036 } 3037 3038 static int ath10k_pci_hif_fetch_cal_eeprom(struct ath10k *ar, void **data, 3039 size_t *data_len) 3040 { 3041 u8 *caldata = NULL; 3042 size_t calsize, i; 3043 int ret; 3044 3045 if (!QCA_REV_9887(ar)) 3046 return -EOPNOTSUPP; 3047 3048 calsize = ar->hw_params.cal_data_len; 3049 caldata = kmalloc(calsize, GFP_KERNEL); 3050 if (!caldata) 3051 return -ENOMEM; 3052 3053 ath10k_pci_enable_eeprom(ar); 3054 3055 for (i = 0; i < calsize; i++) { 3056 ret = ath10k_pci_read_eeprom(ar, i, &caldata[i]); 3057 if (ret) 3058 goto err_free; 3059 } 3060 3061 if (!ath10k_pci_validate_cal(caldata, calsize)) 3062 goto err_free; 3063 3064 *data = caldata; 3065 *data_len = calsize; 3066 3067 return 0; 3068 3069 err_free: 3070 kfree(caldata); 3071 3072 return -EINVAL; 3073 } 3074 3075 static const struct ath10k_hif_ops ath10k_pci_hif_ops = { 3076 .tx_sg = ath10k_pci_hif_tx_sg, 3077 .diag_read = ath10k_pci_hif_diag_read, 3078 .diag_write = ath10k_pci_diag_write_mem, 3079 .exchange_bmi_msg = ath10k_pci_hif_exchange_bmi_msg, 3080 .start = ath10k_pci_hif_start, 3081 .stop = ath10k_pci_hif_stop, 3082 .map_service_to_pipe = ath10k_pci_hif_map_service_to_pipe, 3083 .get_default_pipe = ath10k_pci_hif_get_default_pipe, 3084 .send_complete_check = ath10k_pci_hif_send_complete_check, 3085 .get_free_queue_number = ath10k_pci_hif_get_free_queue_number, 3086 .power_up = ath10k_pci_hif_power_up, 3087 .power_down = ath10k_pci_hif_power_down, 3088 .read32 = ath10k_pci_read32, 3089 .write32 = ath10k_pci_write32, 3090 .suspend = ath10k_pci_hif_suspend, 3091 .resume = ath10k_pci_hif_resume, 3092 .fetch_cal_eeprom = ath10k_pci_hif_fetch_cal_eeprom, 3093 }; 3094 3095 /* 3096 * Top-level interrupt handler for all PCI interrupts from a Target. 3097 * When a block of MSI interrupts is allocated, this top-level handler 3098 * is not used; instead, we directly call the correct sub-handler. 3099 */ 3100 static irqreturn_t ath10k_pci_interrupt_handler(int irq, void *arg) 3101 { 3102 struct ath10k *ar = arg; 3103 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3104 int ret; 3105 3106 if (ath10k_pci_has_device_gone(ar)) 3107 return IRQ_NONE; 3108 3109 ret = ath10k_pci_force_wake(ar); 3110 if (ret) { 3111 ath10k_warn(ar, "failed to wake device up on irq: %d\n", ret); 3112 return IRQ_NONE; 3113 } 3114 3115 if ((ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_INTX) && 3116 !ath10k_pci_irq_pending(ar)) 3117 return IRQ_NONE; 3118 3119 ath10k_pci_disable_and_clear_intx_irq(ar); 3120 ath10k_pci_irq_msi_fw_mask(ar); 3121 napi_schedule(&ar->napi); 3122 3123 return IRQ_HANDLED; 3124 } 3125 3126 static int ath10k_pci_napi_poll(struct napi_struct *ctx, int budget) 3127 { 3128 struct ath10k *ar = container_of(ctx, struct ath10k, napi); 3129 int done = 0; 3130 3131 if (ath10k_pci_has_fw_crashed(ar)) { 3132 ath10k_pci_fw_crashed_clear(ar); 3133 ath10k_pci_fw_crashed_dump(ar); 3134 napi_complete(ctx); 3135 return done; 3136 } 3137 3138 ath10k_ce_per_engine_service_any(ar); 3139 3140 done = ath10k_htt_txrx_compl_task(ar, budget); 3141 3142 if (done < budget) { 3143 napi_complete_done(ctx, done); 3144 /* In case of MSI, it is possible that interrupts are received 3145 * while NAPI poll is inprogress. So pending interrupts that are 3146 * received after processing all copy engine pipes by NAPI poll 3147 * will not be handled again. This is causing failure to 3148 * complete boot sequence in x86 platform. So before enabling 3149 * interrupts safer to check for pending interrupts for 3150 * immediate servicing. 3151 */ 3152 if (ath10k_ce_interrupt_summary(ar)) { 3153 napi_schedule(ctx); 3154 goto out; 3155 } 3156 ath10k_pci_enable_intx_irq(ar); 3157 ath10k_pci_irq_msi_fw_unmask(ar); 3158 } 3159 3160 out: 3161 return done; 3162 } 3163 3164 static int ath10k_pci_request_irq_msi(struct ath10k *ar) 3165 { 3166 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3167 int ret; 3168 3169 ret = request_irq(ar_pci->pdev->irq, 3170 ath10k_pci_interrupt_handler, 3171 IRQF_SHARED, "ath10k_pci", ar); 3172 if (ret) { 3173 ath10k_warn(ar, "failed to request MSI irq %d: %d\n", 3174 ar_pci->pdev->irq, ret); 3175 return ret; 3176 } 3177 3178 return 0; 3179 } 3180 3181 static int ath10k_pci_request_irq_intx(struct ath10k *ar) 3182 { 3183 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3184 int ret; 3185 3186 ret = request_irq(ar_pci->pdev->irq, 3187 ath10k_pci_interrupt_handler, 3188 IRQF_SHARED, "ath10k_pci", ar); 3189 if (ret) { 3190 ath10k_warn(ar, "failed to request legacy irq %d: %d\n", 3191 ar_pci->pdev->irq, ret); 3192 return ret; 3193 } 3194 3195 return 0; 3196 } 3197 3198 static int ath10k_pci_request_irq(struct ath10k *ar) 3199 { 3200 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3201 3202 switch (ar_pci->oper_irq_mode) { 3203 case ATH10K_PCI_IRQ_INTX: 3204 return ath10k_pci_request_irq_intx(ar); 3205 case ATH10K_PCI_IRQ_MSI: 3206 return ath10k_pci_request_irq_msi(ar); 3207 default: 3208 return -EINVAL; 3209 } 3210 } 3211 3212 static void ath10k_pci_free_irq(struct ath10k *ar) 3213 { 3214 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3215 3216 free_irq(ar_pci->pdev->irq, ar); 3217 } 3218 3219 void ath10k_pci_init_napi(struct ath10k *ar) 3220 { 3221 netif_napi_add(ar->napi_dev, &ar->napi, ath10k_pci_napi_poll); 3222 } 3223 3224 static int ath10k_pci_init_irq(struct ath10k *ar) 3225 { 3226 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3227 int ret; 3228 3229 ath10k_pci_init_napi(ar); 3230 3231 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_AUTO) 3232 ath10k_info(ar, "limiting irq mode to: %d\n", 3233 ath10k_pci_irq_mode); 3234 3235 /* Try MSI */ 3236 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_INTX) { 3237 ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_MSI; 3238 ret = pci_enable_msi(ar_pci->pdev); 3239 if (ret == 0) 3240 return 0; 3241 3242 /* MHI failed, try legacy irq next */ 3243 } 3244 3245 /* Try legacy irq 3246 * 3247 * A potential race occurs here: The CORE_BASE write 3248 * depends on target correctly decoding AXI address but 3249 * host won't know when target writes BAR to CORE_CTRL. 3250 * This write might get lost if target has NOT written BAR. 3251 * For now, fix the race by repeating the write in below 3252 * synchronization checking. 3253 */ 3254 ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_INTX; 3255 3256 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS, 3257 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); 3258 3259 return 0; 3260 } 3261 3262 static void ath10k_pci_deinit_irq_intx(struct ath10k *ar) 3263 { 3264 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS, 3265 0); 3266 } 3267 3268 static int ath10k_pci_deinit_irq(struct ath10k *ar) 3269 { 3270 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3271 3272 switch (ar_pci->oper_irq_mode) { 3273 case ATH10K_PCI_IRQ_INTX: 3274 ath10k_pci_deinit_irq_intx(ar); 3275 break; 3276 default: 3277 pci_disable_msi(ar_pci->pdev); 3278 break; 3279 } 3280 3281 return 0; 3282 } 3283 3284 int ath10k_pci_wait_for_target_init(struct ath10k *ar) 3285 { 3286 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3287 unsigned long timeout; 3288 u32 val; 3289 3290 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot waiting target to initialise\n"); 3291 3292 timeout = jiffies + msecs_to_jiffies(ATH10K_PCI_TARGET_WAIT); 3293 3294 do { 3295 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS); 3296 3297 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target indicator %x\n", 3298 val); 3299 3300 /* target should never return this */ 3301 if (val == 0xffffffff) 3302 continue; 3303 3304 /* the device has crashed so don't bother trying anymore */ 3305 if (val & FW_IND_EVENT_PENDING) 3306 break; 3307 3308 if (val & FW_IND_INITIALIZED) 3309 break; 3310 3311 if (ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_INTX) 3312 /* Fix potential race by repeating CORE_BASE writes */ 3313 ath10k_pci_enable_intx_irq(ar); 3314 3315 mdelay(10); 3316 } while (time_before(jiffies, timeout)); 3317 3318 ath10k_pci_disable_and_clear_intx_irq(ar); 3319 ath10k_pci_irq_msi_fw_mask(ar); 3320 3321 if (val == 0xffffffff) { 3322 ath10k_err(ar, "failed to read device register, device is gone\n"); 3323 return -EIO; 3324 } 3325 3326 if (val & FW_IND_EVENT_PENDING) { 3327 ath10k_warn(ar, "device has crashed during init\n"); 3328 return -ECOMM; 3329 } 3330 3331 if (!(val & FW_IND_INITIALIZED)) { 3332 ath10k_err(ar, "failed to receive initialized event from target: %08x\n", 3333 val); 3334 return -ETIMEDOUT; 3335 } 3336 3337 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target initialised\n"); 3338 return 0; 3339 } 3340 3341 static int ath10k_pci_cold_reset(struct ath10k *ar) 3342 { 3343 u32 val; 3344 3345 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset\n"); 3346 3347 spin_lock_bh(&ar->data_lock); 3348 3349 ar->stats.fw_cold_reset_counter++; 3350 3351 spin_unlock_bh(&ar->data_lock); 3352 3353 /* Put Target, including PCIe, into RESET. */ 3354 val = ath10k_pci_reg_read32(ar, SOC_GLOBAL_RESET_ADDRESS); 3355 val |= 1; 3356 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val); 3357 3358 /* After writing into SOC_GLOBAL_RESET to put device into 3359 * reset and pulling out of reset pcie may not be stable 3360 * for any immediate pcie register access and cause bus error, 3361 * add delay before any pcie access request to fix this issue. 3362 */ 3363 msleep(20); 3364 3365 /* Pull Target, including PCIe, out of RESET. */ 3366 val &= ~1; 3367 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val); 3368 3369 msleep(20); 3370 3371 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset complete\n"); 3372 3373 return 0; 3374 } 3375 3376 static int ath10k_pci_claim(struct ath10k *ar) 3377 { 3378 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3379 struct pci_dev *pdev = ar_pci->pdev; 3380 int ret; 3381 3382 pci_set_drvdata(pdev, ar); 3383 3384 ret = pci_enable_device(pdev); 3385 if (ret) { 3386 ath10k_err(ar, "failed to enable pci device: %d\n", ret); 3387 return ret; 3388 } 3389 3390 ret = pci_request_region(pdev, BAR_NUM, "ath"); 3391 if (ret) { 3392 ath10k_err(ar, "failed to request region BAR%d: %d\n", BAR_NUM, 3393 ret); 3394 goto err_device; 3395 } 3396 3397 /* Target expects 32 bit DMA. Enforce it. */ 3398 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 3399 if (ret) { 3400 ath10k_err(ar, "failed to set dma mask to 32-bit: %d\n", ret); 3401 goto err_region; 3402 } 3403 3404 pci_set_master(pdev); 3405 3406 /* Arrange for access to Target SoC registers. */ 3407 ar_pci->mem_len = pci_resource_len(pdev, BAR_NUM); 3408 ar_pci->mem = pci_iomap(pdev, BAR_NUM, 0); 3409 if (!ar_pci->mem) { 3410 ath10k_err(ar, "failed to iomap BAR%d\n", BAR_NUM); 3411 ret = -EIO; 3412 goto err_region; 3413 } 3414 3415 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot pci_mem 0x%p\n", ar_pci->mem); 3416 return 0; 3417 3418 err_region: 3419 pci_release_region(pdev, BAR_NUM); 3420 3421 err_device: 3422 pci_disable_device(pdev); 3423 3424 return ret; 3425 } 3426 3427 static void ath10k_pci_release(struct ath10k *ar) 3428 { 3429 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3430 struct pci_dev *pdev = ar_pci->pdev; 3431 3432 pci_iounmap(pdev, ar_pci->mem); 3433 pci_release_region(pdev, BAR_NUM); 3434 pci_disable_device(pdev); 3435 } 3436 3437 static bool ath10k_pci_chip_is_supported(u32 dev_id, u32 chip_id) 3438 { 3439 const struct ath10k_pci_supp_chip *supp_chip; 3440 int i; 3441 u32 rev_id = MS(chip_id, SOC_CHIP_ID_REV); 3442 3443 for (i = 0; i < ARRAY_SIZE(ath10k_pci_supp_chips); i++) { 3444 supp_chip = &ath10k_pci_supp_chips[i]; 3445 3446 if (supp_chip->dev_id == dev_id && 3447 supp_chip->rev_id == rev_id) 3448 return true; 3449 } 3450 3451 return false; 3452 } 3453 3454 int ath10k_pci_setup_resource(struct ath10k *ar) 3455 { 3456 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3457 struct ath10k_ce *ce = ath10k_ce_priv(ar); 3458 int ret; 3459 3460 spin_lock_init(&ce->ce_lock); 3461 spin_lock_init(&ar_pci->ps_lock); 3462 mutex_init(&ar_pci->ce_diag_mutex); 3463 3464 INIT_WORK(&ar_pci->dump_work, ath10k_pci_fw_dump_work); 3465 3466 timer_setup(&ar_pci->rx_post_retry, ath10k_pci_rx_replenish_retry, 0); 3467 3468 ar_pci->attr = kmemdup(pci_host_ce_config_wlan, 3469 sizeof(pci_host_ce_config_wlan), 3470 GFP_KERNEL); 3471 if (!ar_pci->attr) 3472 return -ENOMEM; 3473 3474 ar_pci->pipe_config = kmemdup(pci_target_ce_config_wlan, 3475 sizeof(pci_target_ce_config_wlan), 3476 GFP_KERNEL); 3477 if (!ar_pci->pipe_config) { 3478 ret = -ENOMEM; 3479 goto err_free_attr; 3480 } 3481 3482 ar_pci->serv_to_pipe = kmemdup(pci_target_service_to_ce_map_wlan, 3483 sizeof(pci_target_service_to_ce_map_wlan), 3484 GFP_KERNEL); 3485 if (!ar_pci->serv_to_pipe) { 3486 ret = -ENOMEM; 3487 goto err_free_pipe_config; 3488 } 3489 3490 if (QCA_REV_6174(ar) || QCA_REV_9377(ar)) 3491 ath10k_pci_override_ce_config(ar); 3492 3493 ret = ath10k_pci_alloc_pipes(ar); 3494 if (ret) { 3495 ath10k_err(ar, "failed to allocate copy engine pipes: %d\n", 3496 ret); 3497 goto err_free_serv_to_pipe; 3498 } 3499 3500 return 0; 3501 3502 err_free_serv_to_pipe: 3503 kfree(ar_pci->serv_to_pipe); 3504 err_free_pipe_config: 3505 kfree(ar_pci->pipe_config); 3506 err_free_attr: 3507 kfree(ar_pci->attr); 3508 return ret; 3509 } 3510 3511 void ath10k_pci_release_resource(struct ath10k *ar) 3512 { 3513 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3514 3515 ath10k_pci_rx_retry_sync(ar); 3516 netif_napi_del(&ar->napi); 3517 ath10k_pci_ce_deinit(ar); 3518 ath10k_pci_free_pipes(ar); 3519 kfree(ar_pci->attr); 3520 kfree(ar_pci->pipe_config); 3521 kfree(ar_pci->serv_to_pipe); 3522 } 3523 3524 static const struct ath10k_bus_ops ath10k_pci_bus_ops = { 3525 .read32 = ath10k_bus_pci_read32, 3526 .write32 = ath10k_bus_pci_write32, 3527 .get_num_banks = ath10k_pci_get_num_banks, 3528 }; 3529 3530 static int ath10k_pci_probe(struct pci_dev *pdev, 3531 const struct pci_device_id *pci_dev) 3532 { 3533 int ret = 0; 3534 struct ath10k *ar; 3535 struct ath10k_pci *ar_pci; 3536 enum ath10k_hw_rev hw_rev; 3537 struct ath10k_bus_params bus_params = {}; 3538 bool pci_ps, is_qca988x = false; 3539 int (*pci_soft_reset)(struct ath10k *ar); 3540 int (*pci_hard_reset)(struct ath10k *ar); 3541 u32 (*targ_cpu_to_ce_addr)(struct ath10k *ar, u32 addr); 3542 3543 switch (pci_dev->device) { 3544 case QCA988X_2_0_DEVICE_ID_UBNT: 3545 case QCA988X_2_0_DEVICE_ID: 3546 hw_rev = ATH10K_HW_QCA988X; 3547 pci_ps = false; 3548 is_qca988x = true; 3549 pci_soft_reset = ath10k_pci_warm_reset; 3550 pci_hard_reset = ath10k_pci_qca988x_chip_reset; 3551 targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr; 3552 break; 3553 case QCA9887_1_0_DEVICE_ID: 3554 hw_rev = ATH10K_HW_QCA9887; 3555 pci_ps = false; 3556 pci_soft_reset = ath10k_pci_warm_reset; 3557 pci_hard_reset = ath10k_pci_qca988x_chip_reset; 3558 targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr; 3559 break; 3560 case QCA6164_2_1_DEVICE_ID: 3561 case QCA6174_2_1_DEVICE_ID: 3562 hw_rev = ATH10K_HW_QCA6174; 3563 pci_ps = true; 3564 pci_soft_reset = ath10k_pci_warm_reset; 3565 pci_hard_reset = ath10k_pci_qca6174_chip_reset; 3566 targ_cpu_to_ce_addr = ath10k_pci_qca6174_targ_cpu_to_ce_addr; 3567 break; 3568 case QCA99X0_2_0_DEVICE_ID: 3569 hw_rev = ATH10K_HW_QCA99X0; 3570 pci_ps = false; 3571 pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset; 3572 pci_hard_reset = ath10k_pci_qca99x0_chip_reset; 3573 targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr; 3574 break; 3575 case QCA9984_1_0_DEVICE_ID: 3576 hw_rev = ATH10K_HW_QCA9984; 3577 pci_ps = false; 3578 pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset; 3579 pci_hard_reset = ath10k_pci_qca99x0_chip_reset; 3580 targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr; 3581 break; 3582 case QCA9888_2_0_DEVICE_ID: 3583 hw_rev = ATH10K_HW_QCA9888; 3584 pci_ps = false; 3585 pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset; 3586 pci_hard_reset = ath10k_pci_qca99x0_chip_reset; 3587 targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr; 3588 break; 3589 case QCA9377_1_0_DEVICE_ID: 3590 hw_rev = ATH10K_HW_QCA9377; 3591 pci_ps = true; 3592 pci_soft_reset = ath10k_pci_warm_reset; 3593 pci_hard_reset = ath10k_pci_qca6174_chip_reset; 3594 targ_cpu_to_ce_addr = ath10k_pci_qca6174_targ_cpu_to_ce_addr; 3595 break; 3596 default: 3597 WARN_ON(1); 3598 return -EOPNOTSUPP; 3599 } 3600 3601 ar = ath10k_core_create(sizeof(*ar_pci), &pdev->dev, ATH10K_BUS_PCI, 3602 hw_rev, &ath10k_pci_hif_ops); 3603 if (!ar) { 3604 dev_err(&pdev->dev, "failed to allocate core\n"); 3605 return -ENOMEM; 3606 } 3607 3608 ath10k_dbg(ar, ATH10K_DBG_BOOT, "pci probe %04x:%04x %04x:%04x\n", 3609 pdev->vendor, pdev->device, 3610 pdev->subsystem_vendor, pdev->subsystem_device); 3611 3612 ar_pci = ath10k_pci_priv(ar); 3613 ar_pci->pdev = pdev; 3614 ar_pci->dev = &pdev->dev; 3615 ar_pci->ar = ar; 3616 ar->dev_id = pci_dev->device; 3617 ar_pci->pci_ps = pci_ps; 3618 ar_pci->ce.bus_ops = &ath10k_pci_bus_ops; 3619 ar_pci->pci_soft_reset = pci_soft_reset; 3620 ar_pci->pci_hard_reset = pci_hard_reset; 3621 ar_pci->targ_cpu_to_ce_addr = targ_cpu_to_ce_addr; 3622 ar->ce_priv = &ar_pci->ce; 3623 3624 ar->id.vendor = pdev->vendor; 3625 ar->id.device = pdev->device; 3626 ar->id.subsystem_vendor = pdev->subsystem_vendor; 3627 ar->id.subsystem_device = pdev->subsystem_device; 3628 3629 timer_setup(&ar_pci->ps_timer, ath10k_pci_ps_timer, 0); 3630 3631 ret = ath10k_pci_setup_resource(ar); 3632 if (ret) { 3633 ath10k_err(ar, "failed to setup resource: %d\n", ret); 3634 goto err_core_destroy; 3635 } 3636 3637 ret = ath10k_pci_claim(ar); 3638 if (ret) { 3639 ath10k_err(ar, "failed to claim device: %d\n", ret); 3640 goto err_free_pipes; 3641 } 3642 3643 ret = ath10k_pci_force_wake(ar); 3644 if (ret) { 3645 ath10k_warn(ar, "failed to wake up device : %d\n", ret); 3646 goto err_sleep; 3647 } 3648 3649 ath10k_pci_ce_deinit(ar); 3650 ath10k_pci_irq_disable(ar); 3651 3652 ret = ath10k_pci_init_irq(ar); 3653 if (ret) { 3654 ath10k_err(ar, "failed to init irqs: %d\n", ret); 3655 goto err_sleep; 3656 } 3657 3658 ath10k_info(ar, "pci irq %s oper_irq_mode %d irq_mode %d reset_mode %d\n", 3659 ath10k_pci_get_irq_method(ar), ar_pci->oper_irq_mode, 3660 ath10k_pci_irq_mode, ath10k_pci_reset_mode); 3661 3662 ret = ath10k_pci_request_irq(ar); 3663 if (ret) { 3664 ath10k_warn(ar, "failed to request irqs: %d\n", ret); 3665 goto err_deinit_irq; 3666 } 3667 3668 bus_params.dev_type = ATH10K_DEV_TYPE_LL; 3669 bus_params.link_can_suspend = true; 3670 /* Read CHIP_ID before reset to catch QCA9880-AR1A v1 devices that 3671 * fall off the bus during chip_reset. These chips have the same pci 3672 * device id as the QCA9880 BR4A or 2R4E. So that's why the check. 3673 */ 3674 if (is_qca988x) { 3675 bus_params.chip_id = 3676 ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS); 3677 if (bus_params.chip_id != 0xffffffff) { 3678 if (!ath10k_pci_chip_is_supported(pdev->device, 3679 bus_params.chip_id)) { 3680 ret = -ENODEV; 3681 goto err_unsupported; 3682 } 3683 } 3684 } 3685 3686 ret = ath10k_pci_chip_reset(ar); 3687 if (ret) { 3688 ath10k_err(ar, "failed to reset chip: %d\n", ret); 3689 goto err_free_irq; 3690 } 3691 3692 bus_params.chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS); 3693 if (bus_params.chip_id == 0xffffffff) { 3694 ret = -ENODEV; 3695 goto err_unsupported; 3696 } 3697 3698 if (!ath10k_pci_chip_is_supported(pdev->device, bus_params.chip_id)) { 3699 ret = -ENODEV; 3700 goto err_unsupported; 3701 } 3702 3703 ret = ath10k_core_register(ar, &bus_params); 3704 if (ret) { 3705 ath10k_err(ar, "failed to register driver core: %d\n", ret); 3706 goto err_free_irq; 3707 } 3708 3709 return 0; 3710 3711 err_unsupported: 3712 ath10k_err(ar, "device %04x with chip_id %08x isn't supported\n", 3713 pdev->device, bus_params.chip_id); 3714 3715 err_free_irq: 3716 ath10k_pci_free_irq(ar); 3717 3718 err_deinit_irq: 3719 ath10k_pci_release_resource(ar); 3720 3721 err_sleep: 3722 ath10k_pci_sleep_sync(ar); 3723 ath10k_pci_release(ar); 3724 3725 err_free_pipes: 3726 ath10k_pci_free_pipes(ar); 3727 3728 err_core_destroy: 3729 ath10k_core_destroy(ar); 3730 3731 return ret; 3732 } 3733 3734 static void ath10k_pci_remove(struct pci_dev *pdev) 3735 { 3736 struct ath10k *ar = pci_get_drvdata(pdev); 3737 3738 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci remove\n"); 3739 3740 if (!ar) 3741 return; 3742 3743 ath10k_core_unregister(ar); 3744 ath10k_pci_free_irq(ar); 3745 ath10k_pci_deinit_irq(ar); 3746 ath10k_pci_release_resource(ar); 3747 ath10k_pci_sleep_sync(ar); 3748 ath10k_pci_release(ar); 3749 ath10k_core_destroy(ar); 3750 } 3751 3752 MODULE_DEVICE_TABLE(pci, ath10k_pci_id_table); 3753 3754 static __maybe_unused int ath10k_pci_pm_suspend(struct device *dev) 3755 { 3756 struct ath10k *ar = dev_get_drvdata(dev); 3757 int ret; 3758 3759 ret = ath10k_pci_suspend(ar); 3760 if (ret) 3761 ath10k_warn(ar, "failed to suspend hif: %d\n", ret); 3762 3763 return ret; 3764 } 3765 3766 static __maybe_unused int ath10k_pci_pm_resume(struct device *dev) 3767 { 3768 struct ath10k *ar = dev_get_drvdata(dev); 3769 int ret; 3770 3771 ret = ath10k_pci_resume(ar); 3772 if (ret) 3773 ath10k_warn(ar, "failed to resume hif: %d\n", ret); 3774 3775 return ret; 3776 } 3777 3778 static SIMPLE_DEV_PM_OPS(ath10k_pci_pm_ops, 3779 ath10k_pci_pm_suspend, 3780 ath10k_pci_pm_resume); 3781 3782 static struct pci_driver ath10k_pci_driver = { 3783 .name = "ath10k_pci", 3784 .id_table = ath10k_pci_id_table, 3785 .probe = ath10k_pci_probe, 3786 .remove = ath10k_pci_remove, 3787 #ifdef CONFIG_PM 3788 .driver.pm = &ath10k_pci_pm_ops, 3789 #endif 3790 }; 3791 3792 static int __init ath10k_pci_init(void) 3793 { 3794 int ret1, ret2; 3795 3796 ret1 = pci_register_driver(&ath10k_pci_driver); 3797 if (ret1) 3798 printk(KERN_ERR "failed to register ath10k pci driver: %d\n", 3799 ret1); 3800 3801 ret2 = ath10k_ahb_init(); 3802 if (ret2) 3803 printk(KERN_ERR "ahb init failed: %d\n", ret2); 3804 3805 if (ret1 && ret2) 3806 return ret1; 3807 3808 /* registered to at least one bus */ 3809 return 0; 3810 } 3811 module_init(ath10k_pci_init); 3812 3813 static void __exit ath10k_pci_exit(void) 3814 { 3815 pci_unregister_driver(&ath10k_pci_driver); 3816 ath10k_ahb_exit(); 3817 } 3818 3819 module_exit(ath10k_pci_exit); 3820 3821 MODULE_AUTHOR("Qualcomm Atheros"); 3822 MODULE_DESCRIPTION("Driver support for Qualcomm Atheros PCIe/AHB 802.11ac WLAN devices"); 3823 MODULE_LICENSE("Dual BSD/GPL"); 3824 3825 /* QCA988x 2.0 firmware files */ 3826 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API2_FILE); 3827 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API3_FILE); 3828 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API4_FILE); 3829 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API5_FILE); 3830 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_BOARD_DATA_FILE); 3831 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_BOARD_API2_FILE); 3832 3833 /* QCA9887 1.0 firmware files */ 3834 MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" ATH10K_FW_API5_FILE); 3835 MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" ATH10K_BOARD_DATA_FILE); 3836 MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" ATH10K_BOARD_API2_FILE); 3837 3838 /* QCA6174 2.1 firmware files */ 3839 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_FW_API4_FILE); 3840 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_FW_API5_FILE); 3841 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_BOARD_DATA_FILE); 3842 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_BOARD_API2_FILE); 3843 3844 /* QCA6174 3.1 firmware files */ 3845 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API4_FILE); 3846 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API5_FILE); 3847 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API6_FILE); 3848 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_BOARD_DATA_FILE); 3849 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_BOARD_API2_FILE); 3850 3851 /* QCA9377 1.0 firmware files */ 3852 MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" ATH10K_FW_API6_FILE); 3853 MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" ATH10K_FW_API5_FILE); 3854 MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" ATH10K_BOARD_DATA_FILE); 3855