xref: /linux/drivers/net/wireless/ath/ath10k/hw.h (revision dd5b2498d845f925904cb2afabb6ba11bfc317c5)
1 /* SPDX-License-Identifier: ISC */
2 /*
3  * Copyright (c) 2005-2011 Atheros Communications Inc.
4  * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
5  * Copyright (c) 2018 The Linux Foundation. All rights reserved.
6  */
7 
8 #ifndef _HW_H_
9 #define _HW_H_
10 
11 #include "targaddrs.h"
12 
13 enum ath10k_bus {
14 	ATH10K_BUS_PCI,
15 	ATH10K_BUS_AHB,
16 	ATH10K_BUS_SDIO,
17 	ATH10K_BUS_USB,
18 	ATH10K_BUS_SNOC,
19 };
20 
21 #define ATH10K_FW_DIR			"ath10k"
22 
23 #define QCA988X_2_0_DEVICE_ID_UBNT   (0x11ac)
24 #define QCA988X_2_0_DEVICE_ID   (0x003c)
25 #define QCA6164_2_1_DEVICE_ID   (0x0041)
26 #define QCA6174_2_1_DEVICE_ID   (0x003e)
27 #define QCA99X0_2_0_DEVICE_ID   (0x0040)
28 #define QCA9888_2_0_DEVICE_ID	(0x0056)
29 #define QCA9984_1_0_DEVICE_ID	(0x0046)
30 #define QCA9377_1_0_DEVICE_ID   (0x0042)
31 #define QCA9887_1_0_DEVICE_ID   (0x0050)
32 
33 /* QCA988X 1.0 definitions (unsupported) */
34 #define QCA988X_HW_1_0_CHIP_ID_REV	0x0
35 
36 /* QCA988X 2.0 definitions */
37 #define QCA988X_HW_2_0_VERSION		0x4100016c
38 #define QCA988X_HW_2_0_CHIP_ID_REV	0x2
39 #define QCA988X_HW_2_0_FW_DIR		ATH10K_FW_DIR "/QCA988X/hw2.0"
40 #define QCA988X_HW_2_0_BOARD_DATA_FILE	"board.bin"
41 #define QCA988X_HW_2_0_PATCH_LOAD_ADDR	0x1234
42 
43 /* QCA9887 1.0 definitions */
44 #define QCA9887_HW_1_0_VERSION		0x4100016d
45 #define QCA9887_HW_1_0_CHIP_ID_REV	0
46 #define QCA9887_HW_1_0_FW_DIR		ATH10K_FW_DIR "/QCA9887/hw1.0"
47 #define QCA9887_HW_1_0_BOARD_DATA_FILE	"board.bin"
48 #define QCA9887_HW_1_0_PATCH_LOAD_ADDR	0x1234
49 
50 /* QCA6174 target BMI version signatures */
51 #define QCA6174_HW_1_0_VERSION		0x05000000
52 #define QCA6174_HW_1_1_VERSION		0x05000001
53 #define QCA6174_HW_1_3_VERSION		0x05000003
54 #define QCA6174_HW_2_1_VERSION		0x05010000
55 #define QCA6174_HW_3_0_VERSION		0x05020000
56 #define QCA6174_HW_3_2_VERSION		0x05030000
57 
58 /* QCA9377 target BMI version signatures */
59 #define QCA9377_HW_1_0_DEV_VERSION	0x05020000
60 #define QCA9377_HW_1_1_DEV_VERSION	0x05020001
61 
62 enum qca6174_pci_rev {
63 	QCA6174_PCI_REV_1_1 = 0x11,
64 	QCA6174_PCI_REV_1_3 = 0x13,
65 	QCA6174_PCI_REV_2_0 = 0x20,
66 	QCA6174_PCI_REV_3_0 = 0x30,
67 };
68 
69 enum qca6174_chip_id_rev {
70 	QCA6174_HW_1_0_CHIP_ID_REV = 0,
71 	QCA6174_HW_1_1_CHIP_ID_REV = 1,
72 	QCA6174_HW_1_3_CHIP_ID_REV = 2,
73 	QCA6174_HW_2_1_CHIP_ID_REV = 4,
74 	QCA6174_HW_2_2_CHIP_ID_REV = 5,
75 	QCA6174_HW_3_0_CHIP_ID_REV = 8,
76 	QCA6174_HW_3_1_CHIP_ID_REV = 9,
77 	QCA6174_HW_3_2_CHIP_ID_REV = 10,
78 };
79 
80 enum qca9377_chip_id_rev {
81 	QCA9377_HW_1_0_CHIP_ID_REV = 0x0,
82 	QCA9377_HW_1_1_CHIP_ID_REV = 0x1,
83 };
84 
85 #define QCA6174_HW_2_1_FW_DIR		ATH10K_FW_DIR "/QCA6174/hw2.1"
86 #define QCA6174_HW_2_1_BOARD_DATA_FILE	"board.bin"
87 #define QCA6174_HW_2_1_PATCH_LOAD_ADDR	0x1234
88 
89 #define QCA6174_HW_3_0_FW_DIR		ATH10K_FW_DIR "/QCA6174/hw3.0"
90 #define QCA6174_HW_3_0_BOARD_DATA_FILE	"board.bin"
91 #define QCA6174_HW_3_0_PATCH_LOAD_ADDR	0x1234
92 
93 /* QCA99X0 1.0 definitions (unsupported) */
94 #define QCA99X0_HW_1_0_CHIP_ID_REV     0x0
95 
96 /* QCA99X0 2.0 definitions */
97 #define QCA99X0_HW_2_0_DEV_VERSION     0x01000000
98 #define QCA99X0_HW_2_0_CHIP_ID_REV     0x1
99 #define QCA99X0_HW_2_0_FW_DIR          ATH10K_FW_DIR "/QCA99X0/hw2.0"
100 #define QCA99X0_HW_2_0_BOARD_DATA_FILE "board.bin"
101 #define QCA99X0_HW_2_0_PATCH_LOAD_ADDR	0x1234
102 
103 /* QCA9984 1.0 defines */
104 #define QCA9984_HW_1_0_DEV_VERSION	0x1000000
105 #define QCA9984_HW_DEV_TYPE		0xa
106 #define QCA9984_HW_1_0_CHIP_ID_REV	0x0
107 #define QCA9984_HW_1_0_FW_DIR		ATH10K_FW_DIR "/QCA9984/hw1.0"
108 #define QCA9984_HW_1_0_BOARD_DATA_FILE "board.bin"
109 #define QCA9984_HW_1_0_EBOARD_DATA_FILE "eboard.bin"
110 #define QCA9984_HW_1_0_PATCH_LOAD_ADDR	0x1234
111 
112 /* QCA9888 2.0 defines */
113 #define QCA9888_HW_2_0_DEV_VERSION	0x1000000
114 #define QCA9888_HW_DEV_TYPE		0xc
115 #define QCA9888_HW_2_0_CHIP_ID_REV	0x0
116 #define QCA9888_HW_2_0_FW_DIR		ATH10K_FW_DIR "/QCA9888/hw2.0"
117 #define QCA9888_HW_2_0_BOARD_DATA_FILE "board.bin"
118 #define QCA9888_HW_2_0_PATCH_LOAD_ADDR	0x1234
119 
120 /* QCA9377 1.0 definitions */
121 #define QCA9377_HW_1_0_FW_DIR          ATH10K_FW_DIR "/QCA9377/hw1.0"
122 #define QCA9377_HW_1_0_BOARD_DATA_FILE "board.bin"
123 #define QCA9377_HW_1_0_PATCH_LOAD_ADDR	0x1234
124 
125 /* QCA4019 1.0 definitions */
126 #define QCA4019_HW_1_0_DEV_VERSION     0x01000000
127 #define QCA4019_HW_1_0_FW_DIR          ATH10K_FW_DIR "/QCA4019/hw1.0"
128 #define QCA4019_HW_1_0_BOARD_DATA_FILE "board.bin"
129 #define QCA4019_HW_1_0_PATCH_LOAD_ADDR  0x1234
130 
131 /* WCN3990 1.0 definitions */
132 #define WCN3990_HW_1_0_DEV_VERSION	ATH10K_HW_WCN3990
133 #define WCN3990_HW_1_0_FW_DIR		ATH10K_FW_DIR "/WCN3990/hw1.0"
134 
135 #define ATH10K_FW_FILE_BASE		"firmware"
136 #define ATH10K_FW_API_MAX		6
137 #define ATH10K_FW_API_MIN		2
138 
139 #define ATH10K_FW_API2_FILE		"firmware-2.bin"
140 #define ATH10K_FW_API3_FILE		"firmware-3.bin"
141 
142 /* added support for ATH10K_FW_IE_WMI_OP_VERSION */
143 #define ATH10K_FW_API4_FILE		"firmware-4.bin"
144 
145 /* HTT id conflict fix for management frames over HTT */
146 #define ATH10K_FW_API5_FILE		"firmware-5.bin"
147 
148 /* the firmware-6.bin blob */
149 #define ATH10K_FW_API6_FILE		"firmware-6.bin"
150 
151 #define ATH10K_FW_UTF_FILE		"utf.bin"
152 #define ATH10K_FW_UTF_API2_FILE		"utf-2.bin"
153 
154 /* includes also the null byte */
155 #define ATH10K_FIRMWARE_MAGIC               "QCA-ATH10K"
156 #define ATH10K_BOARD_MAGIC                  "QCA-ATH10K-BOARD"
157 
158 #define ATH10K_BOARD_API2_FILE         "board-2.bin"
159 
160 #define REG_DUMP_COUNT_QCA988X 60
161 
162 struct ath10k_fw_ie {
163 	__le32 id;
164 	__le32 len;
165 	u8 data[0];
166 };
167 
168 enum ath10k_fw_ie_type {
169 	ATH10K_FW_IE_FW_VERSION = 0,
170 	ATH10K_FW_IE_TIMESTAMP = 1,
171 	ATH10K_FW_IE_FEATURES = 2,
172 	ATH10K_FW_IE_FW_IMAGE = 3,
173 	ATH10K_FW_IE_OTP_IMAGE = 4,
174 
175 	/* WMI "operations" interface version, 32 bit value. Supported from
176 	 * FW API 4 and above.
177 	 */
178 	ATH10K_FW_IE_WMI_OP_VERSION = 5,
179 
180 	/* HTT "operations" interface version, 32 bit value. Supported from
181 	 * FW API 5 and above.
182 	 */
183 	ATH10K_FW_IE_HTT_OP_VERSION = 6,
184 
185 	/* Code swap image for firmware binary */
186 	ATH10K_FW_IE_FW_CODE_SWAP_IMAGE = 7,
187 };
188 
189 enum ath10k_fw_wmi_op_version {
190 	ATH10K_FW_WMI_OP_VERSION_UNSET = 0,
191 
192 	ATH10K_FW_WMI_OP_VERSION_MAIN = 1,
193 	ATH10K_FW_WMI_OP_VERSION_10_1 = 2,
194 	ATH10K_FW_WMI_OP_VERSION_10_2 = 3,
195 	ATH10K_FW_WMI_OP_VERSION_TLV = 4,
196 	ATH10K_FW_WMI_OP_VERSION_10_2_4 = 5,
197 	ATH10K_FW_WMI_OP_VERSION_10_4 = 6,
198 
199 	/* keep last */
200 	ATH10K_FW_WMI_OP_VERSION_MAX,
201 };
202 
203 enum ath10k_fw_htt_op_version {
204 	ATH10K_FW_HTT_OP_VERSION_UNSET = 0,
205 
206 	ATH10K_FW_HTT_OP_VERSION_MAIN = 1,
207 
208 	/* also used in 10.2 and 10.2.4 branches */
209 	ATH10K_FW_HTT_OP_VERSION_10_1 = 2,
210 
211 	ATH10K_FW_HTT_OP_VERSION_TLV = 3,
212 
213 	ATH10K_FW_HTT_OP_VERSION_10_4 = 4,
214 
215 	/* keep last */
216 	ATH10K_FW_HTT_OP_VERSION_MAX,
217 };
218 
219 enum ath10k_bd_ie_type {
220 	/* contains sub IEs of enum ath10k_bd_ie_board_type */
221 	ATH10K_BD_IE_BOARD = 0,
222 	ATH10K_BD_IE_BOARD_EXT = 1,
223 };
224 
225 enum ath10k_bd_ie_board_type {
226 	ATH10K_BD_IE_BOARD_NAME = 0,
227 	ATH10K_BD_IE_BOARD_DATA = 1,
228 };
229 
230 enum ath10k_hw_rev {
231 	ATH10K_HW_QCA988X,
232 	ATH10K_HW_QCA6174,
233 	ATH10K_HW_QCA99X0,
234 	ATH10K_HW_QCA9888,
235 	ATH10K_HW_QCA9984,
236 	ATH10K_HW_QCA9377,
237 	ATH10K_HW_QCA4019,
238 	ATH10K_HW_QCA9887,
239 	ATH10K_HW_WCN3990,
240 };
241 
242 struct ath10k_hw_regs {
243 	u32 rtc_soc_base_address;
244 	u32 rtc_wmac_base_address;
245 	u32 soc_core_base_address;
246 	u32 wlan_mac_base_address;
247 	u32 ce_wrapper_base_address;
248 	u32 ce0_base_address;
249 	u32 ce1_base_address;
250 	u32 ce2_base_address;
251 	u32 ce3_base_address;
252 	u32 ce4_base_address;
253 	u32 ce5_base_address;
254 	u32 ce6_base_address;
255 	u32 ce7_base_address;
256 	u32 ce8_base_address;
257 	u32 ce9_base_address;
258 	u32 ce10_base_address;
259 	u32 ce11_base_address;
260 	u32 soc_reset_control_si0_rst_mask;
261 	u32 soc_reset_control_ce_rst_mask;
262 	u32 soc_chip_id_address;
263 	u32 scratch_3_address;
264 	u32 fw_indicator_address;
265 	u32 pcie_local_base_address;
266 	u32 ce_wrap_intr_sum_host_msi_lsb;
267 	u32 ce_wrap_intr_sum_host_msi_mask;
268 	u32 pcie_intr_fw_mask;
269 	u32 pcie_intr_ce_mask_all;
270 	u32 pcie_intr_clr_address;
271 	u32 cpu_pll_init_address;
272 	u32 cpu_speed_address;
273 	u32 core_clk_div_address;
274 };
275 
276 extern const struct ath10k_hw_regs qca988x_regs;
277 extern const struct ath10k_hw_regs qca6174_regs;
278 extern const struct ath10k_hw_regs qca99x0_regs;
279 extern const struct ath10k_hw_regs qca4019_regs;
280 extern const struct ath10k_hw_regs wcn3990_regs;
281 
282 struct ath10k_hw_ce_regs_addr_map {
283 	u32 msb;
284 	u32 lsb;
285 	u32 mask;
286 };
287 
288 struct ath10k_hw_ce_ctrl1 {
289 	u32 addr;
290 	u32 hw_mask;
291 	u32 sw_mask;
292 	u32 hw_wr_mask;
293 	u32 sw_wr_mask;
294 	u32 reset_mask;
295 	u32 reset;
296 	struct ath10k_hw_ce_regs_addr_map *src_ring;
297 	struct ath10k_hw_ce_regs_addr_map *dst_ring;
298 	struct ath10k_hw_ce_regs_addr_map *dmax; };
299 
300 struct ath10k_hw_ce_cmd_halt {
301 	u32 status_reset;
302 	u32 msb;
303 	u32 mask;
304 	struct ath10k_hw_ce_regs_addr_map *status; };
305 
306 struct ath10k_hw_ce_host_ie {
307 	u32 copy_complete_reset;
308 	struct ath10k_hw_ce_regs_addr_map *copy_complete; };
309 
310 struct ath10k_hw_ce_host_wm_regs {
311 	u32 dstr_lmask;
312 	u32 dstr_hmask;
313 	u32 srcr_lmask;
314 	u32 srcr_hmask;
315 	u32 cc_mask;
316 	u32 wm_mask;
317 	u32 addr;
318 };
319 
320 struct ath10k_hw_ce_misc_regs {
321 	u32 axi_err;
322 	u32 dstr_add_err;
323 	u32 srcr_len_err;
324 	u32 dstr_mlen_vio;
325 	u32 dstr_overflow;
326 	u32 srcr_overflow;
327 	u32 err_mask;
328 	u32 addr;
329 };
330 
331 struct ath10k_hw_ce_dst_src_wm_regs {
332 	u32 addr;
333 	u32 low_rst;
334 	u32 high_rst;
335 	struct ath10k_hw_ce_regs_addr_map *wm_low;
336 	struct ath10k_hw_ce_regs_addr_map *wm_high; };
337 
338 struct ath10k_hw_ce_ctrl1_upd {
339 	u32 shift;
340 	u32 mask;
341 	u32 enable;
342 };
343 
344 struct ath10k_hw_ce_regs {
345 	u32 sr_base_addr_lo;
346 	u32 sr_base_addr_hi;
347 	u32 sr_size_addr;
348 	u32 dr_base_addr_lo;
349 	u32 dr_base_addr_hi;
350 	u32 dr_size_addr;
351 	u32 ce_cmd_addr;
352 	u32 misc_ie_addr;
353 	u32 sr_wr_index_addr;
354 	u32 dst_wr_index_addr;
355 	u32 current_srri_addr;
356 	u32 current_drri_addr;
357 	u32 ddr_addr_for_rri_low;
358 	u32 ddr_addr_for_rri_high;
359 	u32 ce_rri_low;
360 	u32 ce_rri_high;
361 	u32 host_ie_addr;
362 	struct ath10k_hw_ce_host_wm_regs *wm_regs;
363 	struct ath10k_hw_ce_misc_regs *misc_regs;
364 	struct ath10k_hw_ce_ctrl1 *ctrl1_regs;
365 	struct ath10k_hw_ce_cmd_halt *cmd_halt;
366 	struct ath10k_hw_ce_host_ie *host_ie;
367 	struct ath10k_hw_ce_dst_src_wm_regs *wm_srcr;
368 	struct ath10k_hw_ce_dst_src_wm_regs *wm_dstr;
369 	struct ath10k_hw_ce_ctrl1_upd *upd;
370 };
371 
372 struct ath10k_hw_values {
373 	u32 rtc_state_val_on;
374 	u8 ce_count;
375 	u8 msi_assign_ce_max;
376 	u8 num_target_ce_config_wlan;
377 	u16 ce_desc_meta_data_mask;
378 	u8 ce_desc_meta_data_lsb;
379 };
380 
381 extern const struct ath10k_hw_values qca988x_values;
382 extern const struct ath10k_hw_values qca6174_values;
383 extern const struct ath10k_hw_values qca99x0_values;
384 extern const struct ath10k_hw_values qca9888_values;
385 extern const struct ath10k_hw_values qca4019_values;
386 extern const struct ath10k_hw_values wcn3990_values;
387 extern const struct ath10k_hw_ce_regs wcn3990_ce_regs;
388 extern const struct ath10k_hw_ce_regs qcax_ce_regs;
389 
390 void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey,
391 				u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev);
392 
393 int ath10k_hw_diag_fast_download(struct ath10k *ar,
394 				 u32 address,
395 				 const void *buffer,
396 				 u32 length);
397 
398 #define QCA_REV_988X(ar) ((ar)->hw_rev == ATH10K_HW_QCA988X)
399 #define QCA_REV_9887(ar) ((ar)->hw_rev == ATH10K_HW_QCA9887)
400 #define QCA_REV_6174(ar) ((ar)->hw_rev == ATH10K_HW_QCA6174)
401 #define QCA_REV_99X0(ar) ((ar)->hw_rev == ATH10K_HW_QCA99X0)
402 #define QCA_REV_9888(ar) ((ar)->hw_rev == ATH10K_HW_QCA9888)
403 #define QCA_REV_9984(ar) ((ar)->hw_rev == ATH10K_HW_QCA9984)
404 #define QCA_REV_9377(ar) ((ar)->hw_rev == ATH10K_HW_QCA9377)
405 #define QCA_REV_40XX(ar) ((ar)->hw_rev == ATH10K_HW_QCA4019)
406 #define QCA_REV_WCN3990(ar) ((ar)->hw_rev == ATH10K_HW_WCN3990)
407 
408 /* Known peculiarities:
409  *  - raw appears in nwifi decap, raw and nwifi appear in ethernet decap
410  *  - raw have FCS, nwifi doesn't
411  *  - ethernet frames have 802.11 header decapped and parts (base hdr, cipher
412  *    param, llc/snap) are aligned to 4byte boundaries each
413  */
414 enum ath10k_hw_txrx_mode {
415 	ATH10K_HW_TXRX_RAW = 0,
416 
417 	/* Native Wifi decap mode is used to align IP frames to 4-byte
418 	 * boundaries and avoid a very expensive re-alignment in mac80211.
419 	 */
420 	ATH10K_HW_TXRX_NATIVE_WIFI = 1,
421 	ATH10K_HW_TXRX_ETHERNET = 2,
422 
423 	/* Valid for HTT >= 3.0. Used for management frames in TX_FRM. */
424 	ATH10K_HW_TXRX_MGMT = 3,
425 };
426 
427 enum ath10k_mcast2ucast_mode {
428 	ATH10K_MCAST2UCAST_DISABLED = 0,
429 	ATH10K_MCAST2UCAST_ENABLED = 1,
430 };
431 
432 enum ath10k_hw_rate_ofdm {
433 	ATH10K_HW_RATE_OFDM_48M = 0,
434 	ATH10K_HW_RATE_OFDM_24M,
435 	ATH10K_HW_RATE_OFDM_12M,
436 	ATH10K_HW_RATE_OFDM_6M,
437 	ATH10K_HW_RATE_OFDM_54M,
438 	ATH10K_HW_RATE_OFDM_36M,
439 	ATH10K_HW_RATE_OFDM_18M,
440 	ATH10K_HW_RATE_OFDM_9M,
441 };
442 
443 enum ath10k_hw_rate_cck {
444 	ATH10K_HW_RATE_CCK_LP_11M = 0,
445 	ATH10K_HW_RATE_CCK_LP_5_5M,
446 	ATH10K_HW_RATE_CCK_LP_2M,
447 	ATH10K_HW_RATE_CCK_LP_1M,
448 	ATH10K_HW_RATE_CCK_SP_11M,
449 	ATH10K_HW_RATE_CCK_SP_5_5M,
450 	ATH10K_HW_RATE_CCK_SP_2M,
451 };
452 
453 enum ath10k_hw_rate_rev2_cck {
454 	ATH10K_HW_RATE_REV2_CCK_LP_1M = 1,
455 	ATH10K_HW_RATE_REV2_CCK_LP_2M,
456 	ATH10K_HW_RATE_REV2_CCK_LP_5_5M,
457 	ATH10K_HW_RATE_REV2_CCK_LP_11M,
458 	ATH10K_HW_RATE_REV2_CCK_SP_2M,
459 	ATH10K_HW_RATE_REV2_CCK_SP_5_5M,
460 	ATH10K_HW_RATE_REV2_CCK_SP_11M,
461 };
462 
463 enum ath10k_hw_cc_wraparound_type {
464 	ATH10K_HW_CC_WRAP_DISABLED = 0,
465 
466 	/* This type is when the HW chip has a quirky Cycle Counter
467 	 * wraparound which resets to 0x7fffffff instead of 0. All
468 	 * other CC related counters (e.g. Rx Clear Count) are divided
469 	 * by 2 so they never wraparound themselves.
470 	 */
471 	ATH10K_HW_CC_WRAP_SHIFTED_ALL = 1,
472 
473 	/* Each hw counter wrapsaround independently. When the
474 	 * counter overflows the repestive counter is right shifted
475 	 * by 1, i.e reset to 0x7fffffff, and other counters will be
476 	 * running unaffected. In this type of wraparound, it should
477 	 * be possible to report accurate Rx busy time unlike the
478 	 * first type.
479 	 */
480 	ATH10K_HW_CC_WRAP_SHIFTED_EACH = 2,
481 };
482 
483 enum ath10k_hw_refclk_speed {
484 	ATH10K_HW_REFCLK_UNKNOWN = -1,
485 	ATH10K_HW_REFCLK_48_MHZ = 0,
486 	ATH10K_HW_REFCLK_19_2_MHZ = 1,
487 	ATH10K_HW_REFCLK_24_MHZ = 2,
488 	ATH10K_HW_REFCLK_26_MHZ = 3,
489 	ATH10K_HW_REFCLK_37_4_MHZ = 4,
490 	ATH10K_HW_REFCLK_38_4_MHZ = 5,
491 	ATH10K_HW_REFCLK_40_MHZ = 6,
492 	ATH10K_HW_REFCLK_52_MHZ = 7,
493 
494 	/* must be the last one */
495 	ATH10K_HW_REFCLK_COUNT,
496 };
497 
498 struct ath10k_hw_clk_params {
499 	u32 refclk;
500 	u32 div;
501 	u32 rnfrac;
502 	u32 settle_time;
503 	u32 refdiv;
504 	u32 outdiv;
505 };
506 
507 struct ath10k_hw_params {
508 	u32 id;
509 	u16 dev_id;
510 	enum ath10k_bus bus;
511 	const char *name;
512 	u32 patch_load_addr;
513 	int uart_pin;
514 	u32 otp_exe_param;
515 
516 	/* Type of hw cycle counter wraparound logic, for more info
517 	 * refer enum ath10k_hw_cc_wraparound_type.
518 	 */
519 	enum ath10k_hw_cc_wraparound_type cc_wraparound_type;
520 
521 	/* Some of chip expects fragment descriptor to be continuous
522 	 * memory for any TX operation. Set continuous_frag_desc flag
523 	 * for the hardware which have such requirement.
524 	 */
525 	bool continuous_frag_desc;
526 
527 	/* CCK hardware rate table mapping for the newer chipsets
528 	 * like QCA99X0, QCA4019 got revised. The CCK h/w rate values
529 	 * are in a proper order with respect to the rate/preamble
530 	 */
531 	bool cck_rate_map_rev2;
532 
533 	u32 channel_counters_freq_hz;
534 
535 	/* Mgmt tx descriptors threshold for limiting probe response
536 	 * frames.
537 	 */
538 	u32 max_probe_resp_desc_thres;
539 
540 	u32 tx_chain_mask;
541 	u32 rx_chain_mask;
542 	u32 max_spatial_stream;
543 	u32 cal_data_len;
544 
545 	struct ath10k_hw_params_fw {
546 		const char *dir;
547 		const char *board;
548 		size_t board_size;
549 		const char *eboard;
550 		size_t ext_board_size;
551 		size_t board_ext_size;
552 	} fw;
553 
554 	/* qca99x0 family chips deliver broadcast/multicast management
555 	 * frames encrypted and expect software do decryption.
556 	 */
557 	bool sw_decrypt_mcast_mgmt;
558 
559 	const struct ath10k_hw_ops *hw_ops;
560 
561 	/* Number of bytes used for alignment in rx_hdr_status of rx desc. */
562 	int decap_align_bytes;
563 
564 	/* hw specific clock control parameters */
565 	const struct ath10k_hw_clk_params *hw_clk;
566 	int target_cpu_freq;
567 
568 	/* Number of bytes to be discarded for each FFT sample */
569 	int spectral_bin_discard;
570 
571 	/* The board may have a restricted NSS for 160 or 80+80 vs what it
572 	 * can do for 80Mhz.
573 	 */
574 	int vht160_mcs_rx_highest;
575 	int vht160_mcs_tx_highest;
576 
577 	/* Number of ciphers supported (i.e First N) in cipher_suites array */
578 	int n_cipher_suites;
579 
580 	u32 num_peers;
581 	u32 ast_skid_limit;
582 	u32 num_wds_entries;
583 
584 	/* Targets supporting physical addressing capability above 32-bits */
585 	bool target_64bit;
586 
587 	/* Target rx ring fill level */
588 	u32 rx_ring_fill_level;
589 
590 	/* target supporting per ce IRQ */
591 	bool per_ce_irq;
592 
593 	/* target supporting shadow register for ce write */
594 	bool shadow_reg_support;
595 
596 	/* target supporting retention restore on ddr */
597 	bool rri_on_ddr;
598 
599 	/* Number of bytes to be the offset for each FFT sample */
600 	int spectral_bin_offset;
601 
602 	/* targets which require hw filter reset during boot up,
603 	 * to avoid it sending spurious acks.
604 	 */
605 	bool hw_filter_reset_required;
606 
607 	/* target supporting fw download via diag ce */
608 	bool fw_diag_ce_download;
609 };
610 
611 struct htt_rx_desc;
612 struct htt_resp;
613 struct htt_data_tx_completion_ext;
614 
615 /* Defines needed for Rx descriptor abstraction */
616 struct ath10k_hw_ops {
617 	int (*rx_desc_get_l3_pad_bytes)(struct htt_rx_desc *rxd);
618 	void (*set_coverage_class)(struct ath10k *ar, s16 value);
619 	int (*enable_pll_clk)(struct ath10k *ar);
620 	bool (*rx_desc_get_msdu_limit_error)(struct htt_rx_desc *rxd);
621 	int (*tx_data_rssi_pad_bytes)(struct htt_resp *htt);
622 	int (*is_rssi_enable)(struct htt_resp *resp);
623 };
624 
625 extern const struct ath10k_hw_ops qca988x_ops;
626 extern const struct ath10k_hw_ops qca99x0_ops;
627 extern const struct ath10k_hw_ops qca6174_ops;
628 extern const struct ath10k_hw_ops wcn3990_ops;
629 
630 extern const struct ath10k_hw_clk_params qca6174_clk[];
631 
632 static inline int
633 ath10k_rx_desc_get_l3_pad_bytes(struct ath10k_hw_params *hw,
634 				struct htt_rx_desc *rxd)
635 {
636 	if (hw->hw_ops->rx_desc_get_l3_pad_bytes)
637 		return hw->hw_ops->rx_desc_get_l3_pad_bytes(rxd);
638 	return 0;
639 }
640 
641 static inline bool
642 ath10k_rx_desc_msdu_limit_error(struct ath10k_hw_params *hw,
643 				struct htt_rx_desc *rxd)
644 {
645 	if (hw->hw_ops->rx_desc_get_msdu_limit_error)
646 		return hw->hw_ops->rx_desc_get_msdu_limit_error(rxd);
647 	return false;
648 }
649 
650 static inline int
651 ath10k_tx_data_rssi_get_pad_bytes(struct ath10k_hw_params *hw,
652 				  struct htt_resp *htt)
653 {
654 	if (hw->hw_ops->tx_data_rssi_pad_bytes)
655 		return hw->hw_ops->tx_data_rssi_pad_bytes(htt);
656 	return 0;
657 }
658 
659 static inline int
660 ath10k_is_rssi_enable(struct ath10k_hw_params *hw,
661 		      struct htt_resp *resp)
662 {
663 	if (hw->hw_ops->is_rssi_enable)
664 		return hw->hw_ops->is_rssi_enable(resp);
665 	return 0;
666 }
667 
668 /* Target specific defines for MAIN firmware */
669 #define TARGET_NUM_VDEVS			8
670 #define TARGET_NUM_PEER_AST			2
671 #define TARGET_NUM_WDS_ENTRIES			32
672 #define TARGET_DMA_BURST_SIZE			0
673 #define TARGET_MAC_AGGR_DELIM			0
674 #define TARGET_AST_SKID_LIMIT			16
675 #define TARGET_NUM_STATIONS			16
676 #define TARGET_NUM_PEERS			((TARGET_NUM_STATIONS) + \
677 						 (TARGET_NUM_VDEVS))
678 #define TARGET_NUM_OFFLOAD_PEERS		0
679 #define TARGET_NUM_OFFLOAD_REORDER_BUFS         0
680 #define TARGET_NUM_PEER_KEYS			2
681 #define TARGET_NUM_TIDS				((TARGET_NUM_PEERS) * 2)
682 #define TARGET_TX_CHAIN_MASK			(BIT(0) | BIT(1) | BIT(2))
683 #define TARGET_RX_CHAIN_MASK			(BIT(0) | BIT(1) | BIT(2))
684 #define TARGET_RX_TIMEOUT_LO_PRI		100
685 #define TARGET_RX_TIMEOUT_HI_PRI		40
686 
687 #define TARGET_SCAN_MAX_PENDING_REQS		4
688 #define TARGET_BMISS_OFFLOAD_MAX_VDEV		3
689 #define TARGET_ROAM_OFFLOAD_MAX_VDEV		3
690 #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES	8
691 #define TARGET_GTK_OFFLOAD_MAX_VDEV		3
692 #define TARGET_NUM_MCAST_GROUPS			0
693 #define TARGET_NUM_MCAST_TABLE_ELEMS		0
694 #define TARGET_MCAST2UCAST_MODE			ATH10K_MCAST2UCAST_DISABLED
695 #define TARGET_TX_DBG_LOG_SIZE			1024
696 #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0
697 #define TARGET_VOW_CONFIG			0
698 #define TARGET_NUM_MSDU_DESC			(1024 + 400)
699 #define TARGET_MAX_FRAG_ENTRIES			0
700 
701 /* Target specific defines for 10.X firmware */
702 #define TARGET_10X_NUM_VDEVS			16
703 #define TARGET_10X_NUM_PEER_AST			2
704 #define TARGET_10X_NUM_WDS_ENTRIES		32
705 #define TARGET_10X_DMA_BURST_SIZE		0
706 #define TARGET_10X_MAC_AGGR_DELIM		0
707 #define TARGET_10X_AST_SKID_LIMIT		128
708 #define TARGET_10X_NUM_STATIONS			128
709 #define TARGET_10X_TX_STATS_NUM_STATIONS	118
710 #define TARGET_10X_NUM_PEERS			((TARGET_10X_NUM_STATIONS) + \
711 						 (TARGET_10X_NUM_VDEVS))
712 #define TARGET_10X_TX_STATS_NUM_PEERS		((TARGET_10X_TX_STATS_NUM_STATIONS) + \
713 						 (TARGET_10X_NUM_VDEVS))
714 #define TARGET_10X_NUM_OFFLOAD_PEERS		0
715 #define TARGET_10X_NUM_OFFLOAD_REORDER_BUFS	0
716 #define TARGET_10X_NUM_PEER_KEYS		2
717 #define TARGET_10X_NUM_TIDS_MAX			256
718 #define TARGET_10X_NUM_TIDS			min((TARGET_10X_NUM_TIDS_MAX), \
719 						    (TARGET_10X_NUM_PEERS) * 2)
720 #define TARGET_10X_TX_STATS_NUM_TIDS		min((TARGET_10X_NUM_TIDS_MAX), \
721 						    (TARGET_10X_TX_STATS_NUM_PEERS) * 2)
722 #define TARGET_10X_TX_CHAIN_MASK		(BIT(0) | BIT(1) | BIT(2))
723 #define TARGET_10X_RX_CHAIN_MASK		(BIT(0) | BIT(1) | BIT(2))
724 #define TARGET_10X_RX_TIMEOUT_LO_PRI		100
725 #define TARGET_10X_RX_TIMEOUT_HI_PRI		40
726 #define TARGET_10X_SCAN_MAX_PENDING_REQS	4
727 #define TARGET_10X_BMISS_OFFLOAD_MAX_VDEV	2
728 #define TARGET_10X_ROAM_OFFLOAD_MAX_VDEV	2
729 #define TARGET_10X_ROAM_OFFLOAD_MAX_AP_PROFILES	8
730 #define TARGET_10X_GTK_OFFLOAD_MAX_VDEV		3
731 #define TARGET_10X_NUM_MCAST_GROUPS		0
732 #define TARGET_10X_NUM_MCAST_TABLE_ELEMS	0
733 #define TARGET_10X_MCAST2UCAST_MODE		ATH10K_MCAST2UCAST_DISABLED
734 #define TARGET_10X_TX_DBG_LOG_SIZE		1024
735 #define TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1
736 #define TARGET_10X_VOW_CONFIG			0
737 #define TARGET_10X_NUM_MSDU_DESC		(1024 + 400)
738 #define TARGET_10X_MAX_FRAG_ENTRIES		0
739 
740 /* 10.2 parameters */
741 #define TARGET_10_2_DMA_BURST_SIZE		0
742 
743 /* Target specific defines for WMI-TLV firmware */
744 #define TARGET_TLV_NUM_VDEVS			4
745 #define TARGET_TLV_NUM_STATIONS			32
746 #define TARGET_TLV_NUM_PEERS			33
747 #define TARGET_TLV_NUM_TDLS_VDEVS		1
748 #define TARGET_TLV_NUM_TIDS			((TARGET_TLV_NUM_PEERS) * 2)
749 #define TARGET_TLV_NUM_MSDU_DESC		(1024 + 32)
750 #define TARGET_TLV_NUM_MSDU_DESC_HL		64
751 #define TARGET_TLV_NUM_WOW_PATTERNS		22
752 #define TARGET_TLV_MGMT_NUM_MSDU_DESC		(50)
753 
754 /* Target specific defines for WMI-HL-1.0 firmware */
755 #define TARGET_HL_TLV_NUM_PEERS			33
756 #define TARGET_HL_TLV_AST_SKID_LIMIT		16
757 #define TARGET_HL_TLV_NUM_WDS_ENTRIES		2
758 
759 /* Diagnostic Window */
760 #define CE_DIAG_PIPE	7
761 
762 #define NUM_TARGET_CE_CONFIG_WLAN ar->hw_values->num_target_ce_config_wlan
763 
764 /* Target specific defines for 10.4 firmware */
765 #define TARGET_10_4_NUM_VDEVS			16
766 #define TARGET_10_4_NUM_STATIONS		32
767 #define TARGET_10_4_NUM_PEERS			((TARGET_10_4_NUM_STATIONS) + \
768 						 (TARGET_10_4_NUM_VDEVS))
769 #define TARGET_10_4_ACTIVE_PEERS		0
770 
771 #define TARGET_10_4_NUM_QCACHE_PEERS_MAX	512
772 #define TARGET_10_4_QCACHE_ACTIVE_PEERS		50
773 #define TARGET_10_4_QCACHE_ACTIVE_PEERS_PFC	35
774 #define TARGET_10_4_NUM_OFFLOAD_PEERS		0
775 #define TARGET_10_4_NUM_OFFLOAD_REORDER_BUFFS	0
776 #define TARGET_10_4_NUM_PEER_KEYS		2
777 #define TARGET_10_4_TGT_NUM_TIDS		((TARGET_10_4_NUM_PEERS) * 2)
778 #define TARGET_10_4_NUM_MSDU_DESC		(1024 + 400)
779 #define TARGET_10_4_NUM_MSDU_DESC_PFC		2500
780 #define TARGET_10_4_AST_SKID_LIMIT		32
781 
782 /* 100 ms for video, best-effort, and background */
783 #define TARGET_10_4_RX_TIMEOUT_LO_PRI		100
784 
785 /* 40 ms for voice */
786 #define TARGET_10_4_RX_TIMEOUT_HI_PRI		40
787 
788 #define TARGET_10_4_RX_DECAP_MODE		ATH10K_HW_TXRX_NATIVE_WIFI
789 #define TARGET_10_4_SCAN_MAX_REQS		4
790 #define TARGET_10_4_BMISS_OFFLOAD_MAX_VDEV	3
791 #define TARGET_10_4_ROAM_OFFLOAD_MAX_VDEV	3
792 #define TARGET_10_4_ROAM_OFFLOAD_MAX_PROFILES   8
793 
794 /* Note: mcast to ucast is disabled by default */
795 #define TARGET_10_4_NUM_MCAST_GROUPS		0
796 #define TARGET_10_4_NUM_MCAST_TABLE_ELEMS	0
797 #define TARGET_10_4_MCAST2UCAST_MODE		0
798 
799 #define TARGET_10_4_TX_DBG_LOG_SIZE		1024
800 #define TARGET_10_4_NUM_WDS_ENTRIES		32
801 #define TARGET_10_4_DMA_BURST_SIZE		0
802 #define TARGET_10_4_MAC_AGGR_DELIM		0
803 #define TARGET_10_4_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1
804 #define TARGET_10_4_VOW_CONFIG			0
805 #define TARGET_10_4_GTK_OFFLOAD_MAX_VDEV	3
806 #define TARGET_10_4_11AC_TX_MAX_FRAGS		2
807 #define TARGET_10_4_MAX_PEER_EXT_STATS		16
808 #define TARGET_10_4_SMART_ANT_CAP		0
809 #define TARGET_10_4_BK_MIN_FREE			0
810 #define TARGET_10_4_BE_MIN_FREE			0
811 #define TARGET_10_4_VI_MIN_FREE			0
812 #define TARGET_10_4_VO_MIN_FREE			0
813 #define TARGET_10_4_RX_BATCH_MODE		1
814 #define TARGET_10_4_THERMAL_THROTTLING_CONFIG	0
815 #define TARGET_10_4_ATF_CONFIG			0
816 #define TARGET_10_4_IPHDR_PAD_CONFIG		1
817 #define TARGET_10_4_QWRAP_CONFIG		0
818 
819 /* TDLS config */
820 #define TARGET_10_4_NUM_TDLS_VDEVS		1
821 #define TARGET_10_4_NUM_TDLS_BUFFER_STA		1
822 #define TARGET_10_4_NUM_TDLS_SLEEP_STA		1
823 
824 /* Maximum number of Copy Engine's supported */
825 #define CE_COUNT_MAX 12
826 
827 /* Number of Copy Engines supported */
828 #define CE_COUNT ar->hw_values->ce_count
829 
830 /*
831  * Granted MSIs are assigned as follows:
832  * Firmware uses the first
833  * Remaining MSIs, if any, are used by Copy Engines
834  * This mapping is known to both Target firmware and Host software.
835  * It may be changed as long as Host and Target are kept in sync.
836  */
837 /* MSI for firmware (errors, etc.) */
838 #define MSI_ASSIGN_FW		0
839 
840 /* MSIs for Copy Engines */
841 #define MSI_ASSIGN_CE_INITIAL	1
842 #define MSI_ASSIGN_CE_MAX	ar->hw_values->msi_assign_ce_max
843 
844 /* as of IP3.7.1 */
845 #define RTC_STATE_V_ON				ar->hw_values->rtc_state_val_on
846 
847 #define RTC_STATE_V_LSB				0
848 #define RTC_STATE_V_MASK			0x00000007
849 #define RTC_STATE_ADDRESS			0x0000
850 #define PCIE_SOC_WAKE_V_MASK			0x00000001
851 #define PCIE_SOC_WAKE_ADDRESS			0x0004
852 #define PCIE_SOC_WAKE_RESET			0x00000000
853 #define SOC_GLOBAL_RESET_ADDRESS		0x0008
854 
855 #define RTC_SOC_BASE_ADDRESS			ar->regs->rtc_soc_base_address
856 #define RTC_WMAC_BASE_ADDRESS			ar->regs->rtc_wmac_base_address
857 #define MAC_COEX_BASE_ADDRESS			0x00006000
858 #define BT_COEX_BASE_ADDRESS			0x00007000
859 #define SOC_PCIE_BASE_ADDRESS			0x00008000
860 #define SOC_CORE_BASE_ADDRESS			ar->regs->soc_core_base_address
861 #define WLAN_UART_BASE_ADDRESS			0x0000c000
862 #define WLAN_SI_BASE_ADDRESS			0x00010000
863 #define WLAN_GPIO_BASE_ADDRESS			0x00014000
864 #define WLAN_ANALOG_INTF_BASE_ADDRESS		0x0001c000
865 #define WLAN_MAC_BASE_ADDRESS			ar->regs->wlan_mac_base_address
866 #define EFUSE_BASE_ADDRESS			0x00030000
867 #define FPGA_REG_BASE_ADDRESS			0x00039000
868 #define WLAN_UART2_BASE_ADDRESS			0x00054c00
869 #define CE_WRAPPER_BASE_ADDRESS			ar->regs->ce_wrapper_base_address
870 #define CE0_BASE_ADDRESS			ar->regs->ce0_base_address
871 #define CE1_BASE_ADDRESS			ar->regs->ce1_base_address
872 #define CE2_BASE_ADDRESS			ar->regs->ce2_base_address
873 #define CE3_BASE_ADDRESS			ar->regs->ce3_base_address
874 #define CE4_BASE_ADDRESS			ar->regs->ce4_base_address
875 #define CE5_BASE_ADDRESS			ar->regs->ce5_base_address
876 #define CE6_BASE_ADDRESS			ar->regs->ce6_base_address
877 #define CE7_BASE_ADDRESS			ar->regs->ce7_base_address
878 #define DBI_BASE_ADDRESS			0x00060000
879 #define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS	0x0006c000
880 #define PCIE_LOCAL_BASE_ADDRESS		ar->regs->pcie_local_base_address
881 
882 #define SOC_RESET_CONTROL_ADDRESS		0x00000000
883 #define SOC_RESET_CONTROL_OFFSET		0x00000000
884 #define SOC_RESET_CONTROL_SI0_RST_MASK		ar->regs->soc_reset_control_si0_rst_mask
885 #define SOC_RESET_CONTROL_CE_RST_MASK		ar->regs->soc_reset_control_ce_rst_mask
886 #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK	0x00000040
887 #define SOC_CPU_CLOCK_OFFSET			0x00000020
888 #define SOC_CPU_CLOCK_STANDARD_LSB		0
889 #define SOC_CPU_CLOCK_STANDARD_MASK		0x00000003
890 #define SOC_CLOCK_CONTROL_OFFSET		0x00000028
891 #define SOC_CLOCK_CONTROL_SI0_CLK_MASK		0x00000001
892 #define SOC_SYSTEM_SLEEP_OFFSET			0x000000c4
893 #define SOC_LPO_CAL_OFFSET			0x000000e0
894 #define SOC_LPO_CAL_ENABLE_LSB			20
895 #define SOC_LPO_CAL_ENABLE_MASK			0x00100000
896 #define SOC_LF_TIMER_CONTROL0_ADDRESS		0x00000050
897 #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK	0x00000004
898 
899 #define SOC_CHIP_ID_ADDRESS			ar->regs->soc_chip_id_address
900 #define SOC_CHIP_ID_REV_LSB			8
901 #define SOC_CHIP_ID_REV_MASK			0x00000f00
902 
903 #define WLAN_RESET_CONTROL_COLD_RST_MASK	0x00000008
904 #define WLAN_RESET_CONTROL_WARM_RST_MASK	0x00000004
905 #define WLAN_SYSTEM_SLEEP_DISABLE_LSB		0
906 #define WLAN_SYSTEM_SLEEP_DISABLE_MASK		0x00000001
907 
908 #define WLAN_GPIO_PIN0_ADDRESS			0x00000028
909 #define WLAN_GPIO_PIN0_CONFIG_LSB		11
910 #define WLAN_GPIO_PIN0_CONFIG_MASK		0x00007800
911 #define WLAN_GPIO_PIN0_PAD_PULL_LSB		5
912 #define WLAN_GPIO_PIN0_PAD_PULL_MASK		0x00000060
913 #define WLAN_GPIO_PIN1_ADDRESS			0x0000002c
914 #define WLAN_GPIO_PIN1_CONFIG_MASK		0x00007800
915 #define WLAN_GPIO_PIN10_ADDRESS			0x00000050
916 #define WLAN_GPIO_PIN11_ADDRESS			0x00000054
917 #define WLAN_GPIO_PIN12_ADDRESS			0x00000058
918 #define WLAN_GPIO_PIN13_ADDRESS			0x0000005c
919 
920 #define CLOCK_GPIO_OFFSET			0xffffffff
921 #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB		0
922 #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK		0
923 
924 #define SI_CONFIG_OFFSET			0x00000000
925 #define SI_CONFIG_ERR_INT_LSB			19
926 #define SI_CONFIG_ERR_INT_MASK			0x00080000
927 #define SI_CONFIG_BIDIR_OD_DATA_LSB		18
928 #define SI_CONFIG_BIDIR_OD_DATA_MASK		0x00040000
929 #define SI_CONFIG_I2C_LSB			16
930 #define SI_CONFIG_I2C_MASK			0x00010000
931 #define SI_CONFIG_POS_SAMPLE_LSB		7
932 #define SI_CONFIG_POS_SAMPLE_MASK		0x00000080
933 #define SI_CONFIG_INACTIVE_DATA_LSB		5
934 #define SI_CONFIG_INACTIVE_DATA_MASK		0x00000020
935 #define SI_CONFIG_INACTIVE_CLK_LSB		4
936 #define SI_CONFIG_INACTIVE_CLK_MASK		0x00000010
937 #define SI_CONFIG_DIVIDER_LSB			0
938 #define SI_CONFIG_DIVIDER_MASK			0x0000000f
939 #define SI_CS_OFFSET				0x00000004
940 #define SI_CS_DONE_ERR_LSB			10
941 #define SI_CS_DONE_ERR_MASK			0x00000400
942 #define SI_CS_DONE_INT_LSB			9
943 #define SI_CS_DONE_INT_MASK			0x00000200
944 #define SI_CS_START_LSB				8
945 #define SI_CS_START_MASK			0x00000100
946 #define SI_CS_RX_CNT_LSB			4
947 #define SI_CS_RX_CNT_MASK			0x000000f0
948 #define SI_CS_TX_CNT_LSB			0
949 #define SI_CS_TX_CNT_MASK			0x0000000f
950 
951 #define SI_TX_DATA0_OFFSET			0x00000008
952 #define SI_TX_DATA1_OFFSET			0x0000000c
953 #define SI_RX_DATA0_OFFSET			0x00000010
954 #define SI_RX_DATA1_OFFSET			0x00000014
955 
956 #define CORE_CTRL_CPU_INTR_MASK			0x00002000
957 #define CORE_CTRL_PCIE_REG_31_MASK		0x00000800
958 #define CORE_CTRL_ADDRESS			0x0000
959 #define PCIE_INTR_ENABLE_ADDRESS		0x0008
960 #define PCIE_INTR_CAUSE_ADDRESS			0x000c
961 #define PCIE_INTR_CLR_ADDRESS			ar->regs->pcie_intr_clr_address
962 #define SCRATCH_3_ADDRESS			ar->regs->scratch_3_address
963 #define CPU_INTR_ADDRESS			0x0010
964 #define FW_RAM_CONFIG_ADDRESS			0x0018
965 
966 #define CCNT_TO_MSEC(ar, x) ((x) / ar->hw_params.channel_counters_freq_hz)
967 
968 /* Firmware indications to the Host via SCRATCH_3 register. */
969 #define FW_INDICATOR_ADDRESS			ar->regs->fw_indicator_address
970 #define FW_IND_EVENT_PENDING			1
971 #define FW_IND_INITIALIZED			2
972 #define FW_IND_HOST_READY			0x80000000
973 
974 /* HOST_REG interrupt from firmware */
975 #define PCIE_INTR_FIRMWARE_MASK			ar->regs->pcie_intr_fw_mask
976 #define PCIE_INTR_CE_MASK_ALL			ar->regs->pcie_intr_ce_mask_all
977 
978 #define DRAM_BASE_ADDRESS			0x00400000
979 
980 #define PCIE_BAR_REG_ADDRESS			0x40030
981 
982 #define MISSING 0
983 
984 #define SYSTEM_SLEEP_OFFSET			SOC_SYSTEM_SLEEP_OFFSET
985 #define WLAN_SYSTEM_SLEEP_OFFSET		SOC_SYSTEM_SLEEP_OFFSET
986 #define WLAN_RESET_CONTROL_OFFSET		SOC_RESET_CONTROL_OFFSET
987 #define CLOCK_CONTROL_OFFSET			SOC_CLOCK_CONTROL_OFFSET
988 #define CLOCK_CONTROL_SI0_CLK_MASK		SOC_CLOCK_CONTROL_SI0_CLK_MASK
989 #define RESET_CONTROL_MBOX_RST_MASK		MISSING
990 #define RESET_CONTROL_SI0_RST_MASK		SOC_RESET_CONTROL_SI0_RST_MASK
991 #define GPIO_BASE_ADDRESS			WLAN_GPIO_BASE_ADDRESS
992 #define GPIO_PIN0_OFFSET			WLAN_GPIO_PIN0_ADDRESS
993 #define GPIO_PIN1_OFFSET			WLAN_GPIO_PIN1_ADDRESS
994 #define GPIO_PIN0_CONFIG_LSB			WLAN_GPIO_PIN0_CONFIG_LSB
995 #define GPIO_PIN0_CONFIG_MASK			WLAN_GPIO_PIN0_CONFIG_MASK
996 #define GPIO_PIN0_PAD_PULL_LSB			WLAN_GPIO_PIN0_PAD_PULL_LSB
997 #define GPIO_PIN0_PAD_PULL_MASK			WLAN_GPIO_PIN0_PAD_PULL_MASK
998 #define GPIO_PIN1_CONFIG_MASK			WLAN_GPIO_PIN1_CONFIG_MASK
999 #define SI_BASE_ADDRESS				WLAN_SI_BASE_ADDRESS
1000 #define SCRATCH_BASE_ADDRESS			SOC_CORE_BASE_ADDRESS
1001 #define LOCAL_SCRATCH_OFFSET			0x18
1002 #define CPU_CLOCK_OFFSET			SOC_CPU_CLOCK_OFFSET
1003 #define LPO_CAL_OFFSET				SOC_LPO_CAL_OFFSET
1004 #define GPIO_PIN10_OFFSET			WLAN_GPIO_PIN10_ADDRESS
1005 #define GPIO_PIN11_OFFSET			WLAN_GPIO_PIN11_ADDRESS
1006 #define GPIO_PIN12_OFFSET			WLAN_GPIO_PIN12_ADDRESS
1007 #define GPIO_PIN13_OFFSET			WLAN_GPIO_PIN13_ADDRESS
1008 #define CPU_CLOCK_STANDARD_LSB			SOC_CPU_CLOCK_STANDARD_LSB
1009 #define CPU_CLOCK_STANDARD_MASK			SOC_CPU_CLOCK_STANDARD_MASK
1010 #define LPO_CAL_ENABLE_LSB			SOC_LPO_CAL_ENABLE_LSB
1011 #define LPO_CAL_ENABLE_MASK			SOC_LPO_CAL_ENABLE_MASK
1012 #define ANALOG_INTF_BASE_ADDRESS		WLAN_ANALOG_INTF_BASE_ADDRESS
1013 #define MBOX_BASE_ADDRESS			MISSING
1014 #define INT_STATUS_ENABLE_ERROR_LSB		MISSING
1015 #define INT_STATUS_ENABLE_ERROR_MASK		MISSING
1016 #define INT_STATUS_ENABLE_CPU_LSB		MISSING
1017 #define INT_STATUS_ENABLE_CPU_MASK		MISSING
1018 #define INT_STATUS_ENABLE_COUNTER_LSB		MISSING
1019 #define INT_STATUS_ENABLE_COUNTER_MASK		MISSING
1020 #define INT_STATUS_ENABLE_MBOX_DATA_LSB		MISSING
1021 #define INT_STATUS_ENABLE_MBOX_DATA_MASK	MISSING
1022 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB	MISSING
1023 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK	MISSING
1024 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB	MISSING
1025 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK	MISSING
1026 #define COUNTER_INT_STATUS_ENABLE_BIT_LSB	MISSING
1027 #define COUNTER_INT_STATUS_ENABLE_BIT_MASK	MISSING
1028 #define INT_STATUS_ENABLE_ADDRESS		MISSING
1029 #define CPU_INT_STATUS_ENABLE_BIT_LSB		MISSING
1030 #define CPU_INT_STATUS_ENABLE_BIT_MASK		MISSING
1031 #define HOST_INT_STATUS_ADDRESS			MISSING
1032 #define CPU_INT_STATUS_ADDRESS			MISSING
1033 #define ERROR_INT_STATUS_ADDRESS		MISSING
1034 #define ERROR_INT_STATUS_WAKEUP_MASK		MISSING
1035 #define ERROR_INT_STATUS_WAKEUP_LSB		MISSING
1036 #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK	MISSING
1037 #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB	MISSING
1038 #define ERROR_INT_STATUS_TX_OVERFLOW_MASK	MISSING
1039 #define ERROR_INT_STATUS_TX_OVERFLOW_LSB	MISSING
1040 #define COUNT_DEC_ADDRESS			MISSING
1041 #define HOST_INT_STATUS_CPU_MASK		MISSING
1042 #define HOST_INT_STATUS_CPU_LSB			MISSING
1043 #define HOST_INT_STATUS_ERROR_MASK		MISSING
1044 #define HOST_INT_STATUS_ERROR_LSB		MISSING
1045 #define HOST_INT_STATUS_COUNTER_MASK		MISSING
1046 #define HOST_INT_STATUS_COUNTER_LSB		MISSING
1047 #define RX_LOOKAHEAD_VALID_ADDRESS		MISSING
1048 #define WINDOW_DATA_ADDRESS			MISSING
1049 #define WINDOW_READ_ADDR_ADDRESS		MISSING
1050 #define WINDOW_WRITE_ADDR_ADDRESS		MISSING
1051 
1052 #define QCA9887_1_0_I2C_SDA_GPIO_PIN		5
1053 #define QCA9887_1_0_I2C_SDA_PIN_CONFIG		3
1054 #define QCA9887_1_0_SI_CLK_GPIO_PIN		17
1055 #define QCA9887_1_0_SI_CLK_PIN_CONFIG		3
1056 #define QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS 0x00000010
1057 
1058 #define QCA9887_EEPROM_SELECT_READ		0xa10000a0
1059 #define QCA9887_EEPROM_ADDR_HI_MASK		0x0000ff00
1060 #define QCA9887_EEPROM_ADDR_HI_LSB		8
1061 #define QCA9887_EEPROM_ADDR_LO_MASK		0x00ff0000
1062 #define QCA9887_EEPROM_ADDR_LO_LSB		16
1063 
1064 #define MBOX_RESET_CONTROL_ADDRESS		0x00000000
1065 #define MBOX_HOST_INT_STATUS_ADDRESS		0x00000800
1066 #define MBOX_HOST_INT_STATUS_ERROR_LSB		7
1067 #define MBOX_HOST_INT_STATUS_ERROR_MASK		0x00000080
1068 #define MBOX_HOST_INT_STATUS_CPU_LSB		6
1069 #define MBOX_HOST_INT_STATUS_CPU_MASK		0x00000040
1070 #define MBOX_HOST_INT_STATUS_COUNTER_LSB	4
1071 #define MBOX_HOST_INT_STATUS_COUNTER_MASK	0x00000010
1072 #define MBOX_CPU_INT_STATUS_ADDRESS		0x00000801
1073 #define MBOX_ERROR_INT_STATUS_ADDRESS		0x00000802
1074 #define MBOX_ERROR_INT_STATUS_WAKEUP_LSB	2
1075 #define MBOX_ERROR_INT_STATUS_WAKEUP_MASK	0x00000004
1076 #define MBOX_ERROR_INT_STATUS_RX_UNDERFLOW_LSB	1
1077 #define MBOX_ERROR_INT_STATUS_RX_UNDERFLOW_MASK	0x00000002
1078 #define MBOX_ERROR_INT_STATUS_TX_OVERFLOW_LSB	0
1079 #define MBOX_ERROR_INT_STATUS_TX_OVERFLOW_MASK	0x00000001
1080 #define MBOX_COUNTER_INT_STATUS_ADDRESS		0x00000803
1081 #define MBOX_COUNTER_INT_STATUS_COUNTER_LSB	0
1082 #define MBOX_COUNTER_INT_STATUS_COUNTER_MASK	0x000000ff
1083 #define MBOX_RX_LOOKAHEAD_VALID_ADDRESS		0x00000805
1084 #define MBOX_INT_STATUS_ENABLE_ADDRESS		0x00000828
1085 #define MBOX_INT_STATUS_ENABLE_ERROR_LSB	7
1086 #define MBOX_INT_STATUS_ENABLE_ERROR_MASK	0x00000080
1087 #define MBOX_INT_STATUS_ENABLE_CPU_LSB		6
1088 #define MBOX_INT_STATUS_ENABLE_CPU_MASK		0x00000040
1089 #define MBOX_INT_STATUS_ENABLE_INT_LSB		5
1090 #define MBOX_INT_STATUS_ENABLE_INT_MASK		0x00000020
1091 #define MBOX_INT_STATUS_ENABLE_COUNTER_LSB	4
1092 #define MBOX_INT_STATUS_ENABLE_COUNTER_MASK	0x00000010
1093 #define MBOX_INT_STATUS_ENABLE_MBOX_DATA_LSB	0
1094 #define MBOX_INT_STATUS_ENABLE_MBOX_DATA_MASK	0x0000000f
1095 #define MBOX_CPU_INT_STATUS_ENABLE_ADDRESS	0x00000819
1096 #define MBOX_CPU_INT_STATUS_ENABLE_BIT_LSB	0
1097 #define MBOX_CPU_INT_STATUS_ENABLE_BIT_MASK	0x000000ff
1098 #define MBOX_ERROR_STATUS_ENABLE_ADDRESS	0x0000081a
1099 #define MBOX_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB  1
1100 #define MBOX_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00000002
1101 #define MBOX_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB   0
1102 #define MBOX_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK  0x00000001
1103 #define MBOX_COUNTER_INT_STATUS_ENABLE_ADDRESS	0x0000081b
1104 #define MBOX_COUNTER_INT_STATUS_ENABLE_BIT_LSB	0
1105 #define MBOX_COUNTER_INT_STATUS_ENABLE_BIT_MASK	0x000000ff
1106 #define MBOX_COUNT_ADDRESS			0x00000820
1107 #define MBOX_COUNT_DEC_ADDRESS			0x00000840
1108 #define MBOX_WINDOW_DATA_ADDRESS		0x00000874
1109 #define MBOX_WINDOW_WRITE_ADDR_ADDRESS		0x00000878
1110 #define MBOX_WINDOW_READ_ADDR_ADDRESS		0x0000087c
1111 #define MBOX_CPU_DBG_SEL_ADDRESS		0x00000883
1112 #define MBOX_CPU_DBG_ADDRESS			0x00000884
1113 #define MBOX_RTC_BASE_ADDRESS			0x00000000
1114 #define MBOX_GPIO_BASE_ADDRESS			0x00005000
1115 #define MBOX_MBOX_BASE_ADDRESS			0x00008000
1116 
1117 #define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB)
1118 
1119 /* Register definitions for first generation ath10k cards. These cards include
1120  * a mac thich has a register allocation similar to ath9k and at least some
1121  * registers including the ones relevant for modifying the coverage class are
1122  * identical to the ath9k definitions.
1123  * These registers are usually managed by the ath10k firmware. However by
1124  * overriding them it is possible to support coverage class modifications.
1125  */
1126 #define WAVE1_PCU_ACK_CTS_TIMEOUT		0x8014
1127 #define WAVE1_PCU_ACK_CTS_TIMEOUT_MAX		0x00003FFF
1128 #define WAVE1_PCU_ACK_CTS_TIMEOUT_ACK_MASK	0x00003FFF
1129 #define WAVE1_PCU_ACK_CTS_TIMEOUT_ACK_LSB	0
1130 #define WAVE1_PCU_ACK_CTS_TIMEOUT_CTS_MASK	0x3FFF0000
1131 #define WAVE1_PCU_ACK_CTS_TIMEOUT_CTS_LSB	16
1132 
1133 #define WAVE1_PCU_GBL_IFS_SLOT			0x1070
1134 #define WAVE1_PCU_GBL_IFS_SLOT_MASK		0x0000FFFF
1135 #define WAVE1_PCU_GBL_IFS_SLOT_MAX		0x0000FFFF
1136 #define WAVE1_PCU_GBL_IFS_SLOT_LSB		0
1137 #define WAVE1_PCU_GBL_IFS_SLOT_RESV0		0xFFFF0000
1138 
1139 #define WAVE1_PHYCLK				0x801C
1140 #define WAVE1_PHYCLK_USEC_MASK			0x0000007F
1141 #define WAVE1_PHYCLK_USEC_LSB			0
1142 
1143 /* qca6174 PLL offset/mask */
1144 #define SOC_CORE_CLK_CTRL_OFFSET		0x00000114
1145 #define SOC_CORE_CLK_CTRL_DIV_LSB		0
1146 #define SOC_CORE_CLK_CTRL_DIV_MASK		0x00000007
1147 
1148 #define EFUSE_OFFSET				0x0000032c
1149 #define EFUSE_XTAL_SEL_LSB			8
1150 #define EFUSE_XTAL_SEL_MASK			0x00000700
1151 
1152 #define BB_PLL_CONFIG_OFFSET			0x000002f4
1153 #define BB_PLL_CONFIG_FRAC_LSB			0
1154 #define BB_PLL_CONFIG_FRAC_MASK			0x0003ffff
1155 #define BB_PLL_CONFIG_OUTDIV_LSB		18
1156 #define BB_PLL_CONFIG_OUTDIV_MASK		0x001c0000
1157 
1158 #define WLAN_PLL_SETTLE_OFFSET			0x0018
1159 #define WLAN_PLL_SETTLE_TIME_LSB		0
1160 #define WLAN_PLL_SETTLE_TIME_MASK		0x000007ff
1161 
1162 #define WLAN_PLL_CONTROL_OFFSET			0x0014
1163 #define WLAN_PLL_CONTROL_DIV_LSB		0
1164 #define WLAN_PLL_CONTROL_DIV_MASK		0x000003ff
1165 #define WLAN_PLL_CONTROL_REFDIV_LSB		10
1166 #define WLAN_PLL_CONTROL_REFDIV_MASK		0x00003c00
1167 #define WLAN_PLL_CONTROL_BYPASS_LSB		16
1168 #define WLAN_PLL_CONTROL_BYPASS_MASK		0x00010000
1169 #define WLAN_PLL_CONTROL_NOPWD_LSB		18
1170 #define WLAN_PLL_CONTROL_NOPWD_MASK		0x00040000
1171 
1172 #define RTC_SYNC_STATUS_OFFSET			0x0244
1173 #define RTC_SYNC_STATUS_PLL_CHANGING_LSB	5
1174 #define RTC_SYNC_STATUS_PLL_CHANGING_MASK	0x00000020
1175 /* qca6174 PLL offset/mask end */
1176 
1177 /* CPU_ADDR_MSB is a register, bit[3:0] is to specify which memory
1178  * region is accessed. The memory region size is 1M.
1179  * If host wants to access 0xX12345 at target, then CPU_ADDR_MSB[3:0]
1180  * is 0xX.
1181  * The following MACROs are defined to get the 0xX and the size limit.
1182  */
1183 #define CPU_ADDR_MSB_REGION_MASK	GENMASK(23, 20)
1184 #define CPU_ADDR_MSB_REGION_VAL(X)	FIELD_GET(CPU_ADDR_MSB_REGION_MASK, X)
1185 #define REGION_ACCESS_SIZE_LIMIT	0x100000
1186 #define REGION_ACCESS_SIZE_MASK		(REGION_ACCESS_SIZE_LIMIT - 1)
1187 
1188 #endif /* _HW_H_ */
1189