1 /* SPDX-License-Identifier: ISC */ 2 /* 3 * Copyright (c) 2005-2011 Atheros Communications Inc. 4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. 5 * Copyright (c) 2018 The Linux Foundation. All rights reserved. 6 */ 7 8 #ifndef _HW_H_ 9 #define _HW_H_ 10 11 #include "targaddrs.h" 12 13 enum ath10k_bus { 14 ATH10K_BUS_PCI, 15 ATH10K_BUS_AHB, 16 ATH10K_BUS_SDIO, 17 ATH10K_BUS_USB, 18 ATH10K_BUS_SNOC, 19 }; 20 21 #define ATH10K_FW_DIR "ath10k" 22 23 #define QCA988X_2_0_DEVICE_ID_UBNT (0x11ac) 24 #define QCA988X_2_0_DEVICE_ID (0x003c) 25 #define QCA6164_2_1_DEVICE_ID (0x0041) 26 #define QCA6174_2_1_DEVICE_ID (0x003e) 27 #define QCA6174_3_2_DEVICE_ID (0x0042) 28 #define QCA99X0_2_0_DEVICE_ID (0x0040) 29 #define QCA9888_2_0_DEVICE_ID (0x0056) 30 #define QCA9984_1_0_DEVICE_ID (0x0046) 31 #define QCA9377_1_0_DEVICE_ID (0x0042) 32 #define QCA9887_1_0_DEVICE_ID (0x0050) 33 34 /* QCA988X 1.0 definitions (unsupported) */ 35 #define QCA988X_HW_1_0_CHIP_ID_REV 0x0 36 37 /* QCA988X 2.0 definitions */ 38 #define QCA988X_HW_2_0_VERSION 0x4100016c 39 #define QCA988X_HW_2_0_CHIP_ID_REV 0x2 40 #define QCA988X_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA988X/hw2.0" 41 #define QCA988X_HW_2_0_BOARD_DATA_FILE "board.bin" 42 #define QCA988X_HW_2_0_PATCH_LOAD_ADDR 0x1234 43 44 /* QCA9887 1.0 definitions */ 45 #define QCA9887_HW_1_0_VERSION 0x4100016d 46 #define QCA9887_HW_1_0_CHIP_ID_REV 0 47 #define QCA9887_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9887/hw1.0" 48 #define QCA9887_HW_1_0_BOARD_DATA_FILE "board.bin" 49 #define QCA9887_HW_1_0_PATCH_LOAD_ADDR 0x1234 50 51 /* QCA6174 target BMI version signatures */ 52 #define QCA6174_HW_1_0_VERSION 0x05000000 53 #define QCA6174_HW_1_1_VERSION 0x05000001 54 #define QCA6174_HW_1_3_VERSION 0x05000003 55 #define QCA6174_HW_2_1_VERSION 0x05010000 56 #define QCA6174_HW_3_0_VERSION 0x05020000 57 #define QCA6174_HW_3_2_VERSION 0x05030000 58 59 /* QCA9377 target BMI version signatures */ 60 #define QCA9377_HW_1_0_DEV_VERSION 0x05020000 61 #define QCA9377_HW_1_1_DEV_VERSION 0x05020001 62 63 enum qca6174_pci_rev { 64 QCA6174_PCI_REV_1_1 = 0x11, 65 QCA6174_PCI_REV_1_3 = 0x13, 66 QCA6174_PCI_REV_2_0 = 0x20, 67 QCA6174_PCI_REV_3_0 = 0x30, 68 }; 69 70 enum qca6174_chip_id_rev { 71 QCA6174_HW_1_0_CHIP_ID_REV = 0, 72 QCA6174_HW_1_1_CHIP_ID_REV = 1, 73 QCA6174_HW_1_3_CHIP_ID_REV = 2, 74 QCA6174_HW_2_1_CHIP_ID_REV = 4, 75 QCA6174_HW_2_2_CHIP_ID_REV = 5, 76 QCA6174_HW_3_0_CHIP_ID_REV = 8, 77 QCA6174_HW_3_1_CHIP_ID_REV = 9, 78 QCA6174_HW_3_2_CHIP_ID_REV = 10, 79 }; 80 81 enum qca9377_chip_id_rev { 82 QCA9377_HW_1_0_CHIP_ID_REV = 0x0, 83 QCA9377_HW_1_1_CHIP_ID_REV = 0x1, 84 }; 85 86 #define QCA6174_HW_2_1_FW_DIR ATH10K_FW_DIR "/QCA6174/hw2.1" 87 #define QCA6174_HW_2_1_BOARD_DATA_FILE "board.bin" 88 #define QCA6174_HW_2_1_PATCH_LOAD_ADDR 0x1234 89 90 #define QCA6174_HW_3_0_FW_DIR ATH10K_FW_DIR "/QCA6174/hw3.0" 91 #define QCA6174_HW_3_0_BOARD_DATA_FILE "board.bin" 92 #define QCA6174_HW_3_0_PATCH_LOAD_ADDR 0x1234 93 94 /* QCA99X0 1.0 definitions (unsupported) */ 95 #define QCA99X0_HW_1_0_CHIP_ID_REV 0x0 96 97 /* QCA99X0 2.0 definitions */ 98 #define QCA99X0_HW_2_0_DEV_VERSION 0x01000000 99 #define QCA99X0_HW_2_0_CHIP_ID_REV 0x1 100 #define QCA99X0_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA99X0/hw2.0" 101 #define QCA99X0_HW_2_0_BOARD_DATA_FILE "board.bin" 102 #define QCA99X0_HW_2_0_PATCH_LOAD_ADDR 0x1234 103 104 /* QCA9984 1.0 defines */ 105 #define QCA9984_HW_1_0_DEV_VERSION 0x1000000 106 #define QCA9984_HW_DEV_TYPE 0xa 107 #define QCA9984_HW_1_0_CHIP_ID_REV 0x0 108 #define QCA9984_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9984/hw1.0" 109 #define QCA9984_HW_1_0_BOARD_DATA_FILE "board.bin" 110 #define QCA9984_HW_1_0_EBOARD_DATA_FILE "eboard.bin" 111 #define QCA9984_HW_1_0_PATCH_LOAD_ADDR 0x1234 112 113 /* QCA9888 2.0 defines */ 114 #define QCA9888_HW_2_0_DEV_VERSION 0x1000000 115 #define QCA9888_HW_DEV_TYPE 0xc 116 #define QCA9888_HW_2_0_CHIP_ID_REV 0x0 117 #define QCA9888_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA9888/hw2.0" 118 #define QCA9888_HW_2_0_BOARD_DATA_FILE "board.bin" 119 #define QCA9888_HW_2_0_PATCH_LOAD_ADDR 0x1234 120 121 /* QCA9377 1.0 definitions */ 122 #define QCA9377_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9377/hw1.0" 123 #define QCA9377_HW_1_0_BOARD_DATA_FILE "board.bin" 124 #define QCA9377_HW_1_0_PATCH_LOAD_ADDR 0x1234 125 126 /* QCA4019 1.0 definitions */ 127 #define QCA4019_HW_1_0_DEV_VERSION 0x01000000 128 #define QCA4019_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA4019/hw1.0" 129 #define QCA4019_HW_1_0_BOARD_DATA_FILE "board.bin" 130 #define QCA4019_HW_1_0_PATCH_LOAD_ADDR 0x1234 131 132 /* WCN3990 1.0 definitions */ 133 #define WCN3990_HW_1_0_DEV_VERSION ATH10K_HW_WCN3990 134 #define WCN3990_HW_1_0_FW_DIR ATH10K_FW_DIR "/WCN3990/hw1.0" 135 136 #define ATH10K_FW_FILE_BASE "firmware" 137 #define ATH10K_FW_API_MAX 6 138 #define ATH10K_FW_API_MIN 2 139 140 #define ATH10K_FW_API2_FILE "firmware-2.bin" 141 #define ATH10K_FW_API3_FILE "firmware-3.bin" 142 143 /* added support for ATH10K_FW_IE_WMI_OP_VERSION */ 144 #define ATH10K_FW_API4_FILE "firmware-4.bin" 145 146 /* HTT id conflict fix for management frames over HTT */ 147 #define ATH10K_FW_API5_FILE "firmware-5.bin" 148 149 /* the firmware-6.bin blob */ 150 #define ATH10K_FW_API6_FILE "firmware-6.bin" 151 152 #define ATH10K_FW_UTF_FILE "utf.bin" 153 #define ATH10K_FW_UTF_API2_FILE "utf-2.bin" 154 155 /* includes also the null byte */ 156 #define ATH10K_FIRMWARE_MAGIC "QCA-ATH10K" 157 #define ATH10K_BOARD_MAGIC "QCA-ATH10K-BOARD" 158 159 #define ATH10K_BOARD_API2_FILE "board-2.bin" 160 161 #define REG_DUMP_COUNT_QCA988X 60 162 163 struct ath10k_fw_ie { 164 __le32 id; 165 __le32 len; 166 u8 data[0]; 167 }; 168 169 enum ath10k_fw_ie_type { 170 ATH10K_FW_IE_FW_VERSION = 0, 171 ATH10K_FW_IE_TIMESTAMP = 1, 172 ATH10K_FW_IE_FEATURES = 2, 173 ATH10K_FW_IE_FW_IMAGE = 3, 174 ATH10K_FW_IE_OTP_IMAGE = 4, 175 176 /* WMI "operations" interface version, 32 bit value. Supported from 177 * FW API 4 and above. 178 */ 179 ATH10K_FW_IE_WMI_OP_VERSION = 5, 180 181 /* HTT "operations" interface version, 32 bit value. Supported from 182 * FW API 5 and above. 183 */ 184 ATH10K_FW_IE_HTT_OP_VERSION = 6, 185 186 /* Code swap image for firmware binary */ 187 ATH10K_FW_IE_FW_CODE_SWAP_IMAGE = 7, 188 }; 189 190 enum ath10k_fw_wmi_op_version { 191 ATH10K_FW_WMI_OP_VERSION_UNSET = 0, 192 193 ATH10K_FW_WMI_OP_VERSION_MAIN = 1, 194 ATH10K_FW_WMI_OP_VERSION_10_1 = 2, 195 ATH10K_FW_WMI_OP_VERSION_10_2 = 3, 196 ATH10K_FW_WMI_OP_VERSION_TLV = 4, 197 ATH10K_FW_WMI_OP_VERSION_10_2_4 = 5, 198 ATH10K_FW_WMI_OP_VERSION_10_4 = 6, 199 200 /* keep last */ 201 ATH10K_FW_WMI_OP_VERSION_MAX, 202 }; 203 204 enum ath10k_fw_htt_op_version { 205 ATH10K_FW_HTT_OP_VERSION_UNSET = 0, 206 207 ATH10K_FW_HTT_OP_VERSION_MAIN = 1, 208 209 /* also used in 10.2 and 10.2.4 branches */ 210 ATH10K_FW_HTT_OP_VERSION_10_1 = 2, 211 212 ATH10K_FW_HTT_OP_VERSION_TLV = 3, 213 214 ATH10K_FW_HTT_OP_VERSION_10_4 = 4, 215 216 /* keep last */ 217 ATH10K_FW_HTT_OP_VERSION_MAX, 218 }; 219 220 enum ath10k_bd_ie_type { 221 /* contains sub IEs of enum ath10k_bd_ie_board_type */ 222 ATH10K_BD_IE_BOARD = 0, 223 ATH10K_BD_IE_BOARD_EXT = 1, 224 }; 225 226 enum ath10k_bd_ie_board_type { 227 ATH10K_BD_IE_BOARD_NAME = 0, 228 ATH10K_BD_IE_BOARD_DATA = 1, 229 }; 230 231 enum ath10k_hw_rev { 232 ATH10K_HW_QCA988X, 233 ATH10K_HW_QCA6174, 234 ATH10K_HW_QCA99X0, 235 ATH10K_HW_QCA9888, 236 ATH10K_HW_QCA9984, 237 ATH10K_HW_QCA9377, 238 ATH10K_HW_QCA4019, 239 ATH10K_HW_QCA9887, 240 ATH10K_HW_WCN3990, 241 }; 242 243 struct ath10k_hw_regs { 244 u32 rtc_soc_base_address; 245 u32 rtc_wmac_base_address; 246 u32 soc_core_base_address; 247 u32 wlan_mac_base_address; 248 u32 ce_wrapper_base_address; 249 u32 ce0_base_address; 250 u32 ce1_base_address; 251 u32 ce2_base_address; 252 u32 ce3_base_address; 253 u32 ce4_base_address; 254 u32 ce5_base_address; 255 u32 ce6_base_address; 256 u32 ce7_base_address; 257 u32 ce8_base_address; 258 u32 ce9_base_address; 259 u32 ce10_base_address; 260 u32 ce11_base_address; 261 u32 soc_reset_control_si0_rst_mask; 262 u32 soc_reset_control_ce_rst_mask; 263 u32 soc_chip_id_address; 264 u32 scratch_3_address; 265 u32 fw_indicator_address; 266 u32 pcie_local_base_address; 267 u32 ce_wrap_intr_sum_host_msi_lsb; 268 u32 ce_wrap_intr_sum_host_msi_mask; 269 u32 pcie_intr_fw_mask; 270 u32 pcie_intr_ce_mask_all; 271 u32 pcie_intr_clr_address; 272 u32 cpu_pll_init_address; 273 u32 cpu_speed_address; 274 u32 core_clk_div_address; 275 }; 276 277 extern const struct ath10k_hw_regs qca988x_regs; 278 extern const struct ath10k_hw_regs qca6174_regs; 279 extern const struct ath10k_hw_regs qca99x0_regs; 280 extern const struct ath10k_hw_regs qca4019_regs; 281 extern const struct ath10k_hw_regs wcn3990_regs; 282 283 struct ath10k_hw_ce_regs_addr_map { 284 u32 msb; 285 u32 lsb; 286 u32 mask; 287 }; 288 289 struct ath10k_hw_ce_ctrl1 { 290 u32 addr; 291 u32 hw_mask; 292 u32 sw_mask; 293 u32 hw_wr_mask; 294 u32 sw_wr_mask; 295 u32 reset_mask; 296 u32 reset; 297 struct ath10k_hw_ce_regs_addr_map *src_ring; 298 struct ath10k_hw_ce_regs_addr_map *dst_ring; 299 struct ath10k_hw_ce_regs_addr_map *dmax; }; 300 301 struct ath10k_hw_ce_cmd_halt { 302 u32 status_reset; 303 u32 msb; 304 u32 mask; 305 struct ath10k_hw_ce_regs_addr_map *status; }; 306 307 struct ath10k_hw_ce_host_ie { 308 u32 copy_complete_reset; 309 struct ath10k_hw_ce_regs_addr_map *copy_complete; }; 310 311 struct ath10k_hw_ce_host_wm_regs { 312 u32 dstr_lmask; 313 u32 dstr_hmask; 314 u32 srcr_lmask; 315 u32 srcr_hmask; 316 u32 cc_mask; 317 u32 wm_mask; 318 u32 addr; 319 }; 320 321 struct ath10k_hw_ce_misc_regs { 322 u32 axi_err; 323 u32 dstr_add_err; 324 u32 srcr_len_err; 325 u32 dstr_mlen_vio; 326 u32 dstr_overflow; 327 u32 srcr_overflow; 328 u32 err_mask; 329 u32 addr; 330 }; 331 332 struct ath10k_hw_ce_dst_src_wm_regs { 333 u32 addr; 334 u32 low_rst; 335 u32 high_rst; 336 struct ath10k_hw_ce_regs_addr_map *wm_low; 337 struct ath10k_hw_ce_regs_addr_map *wm_high; }; 338 339 struct ath10k_hw_ce_ctrl1_upd { 340 u32 shift; 341 u32 mask; 342 u32 enable; 343 }; 344 345 struct ath10k_hw_ce_regs { 346 u32 sr_base_addr_lo; 347 u32 sr_base_addr_hi; 348 u32 sr_size_addr; 349 u32 dr_base_addr_lo; 350 u32 dr_base_addr_hi; 351 u32 dr_size_addr; 352 u32 ce_cmd_addr; 353 u32 misc_ie_addr; 354 u32 sr_wr_index_addr; 355 u32 dst_wr_index_addr; 356 u32 current_srri_addr; 357 u32 current_drri_addr; 358 u32 ddr_addr_for_rri_low; 359 u32 ddr_addr_for_rri_high; 360 u32 ce_rri_low; 361 u32 ce_rri_high; 362 u32 host_ie_addr; 363 struct ath10k_hw_ce_host_wm_regs *wm_regs; 364 struct ath10k_hw_ce_misc_regs *misc_regs; 365 struct ath10k_hw_ce_ctrl1 *ctrl1_regs; 366 struct ath10k_hw_ce_cmd_halt *cmd_halt; 367 struct ath10k_hw_ce_host_ie *host_ie; 368 struct ath10k_hw_ce_dst_src_wm_regs *wm_srcr; 369 struct ath10k_hw_ce_dst_src_wm_regs *wm_dstr; 370 struct ath10k_hw_ce_ctrl1_upd *upd; 371 }; 372 373 struct ath10k_hw_values { 374 u32 rtc_state_val_on; 375 u8 ce_count; 376 u8 msi_assign_ce_max; 377 u8 num_target_ce_config_wlan; 378 u16 ce_desc_meta_data_mask; 379 u8 ce_desc_meta_data_lsb; 380 }; 381 382 extern const struct ath10k_hw_values qca988x_values; 383 extern const struct ath10k_hw_values qca6174_values; 384 extern const struct ath10k_hw_values qca99x0_values; 385 extern const struct ath10k_hw_values qca9888_values; 386 extern const struct ath10k_hw_values qca4019_values; 387 extern const struct ath10k_hw_values wcn3990_values; 388 extern const struct ath10k_hw_ce_regs wcn3990_ce_regs; 389 extern const struct ath10k_hw_ce_regs qcax_ce_regs; 390 391 void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey, 392 u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev); 393 394 int ath10k_hw_diag_fast_download(struct ath10k *ar, 395 u32 address, 396 const void *buffer, 397 u32 length); 398 399 #define QCA_REV_988X(ar) ((ar)->hw_rev == ATH10K_HW_QCA988X) 400 #define QCA_REV_9887(ar) ((ar)->hw_rev == ATH10K_HW_QCA9887) 401 #define QCA_REV_6174(ar) ((ar)->hw_rev == ATH10K_HW_QCA6174) 402 #define QCA_REV_99X0(ar) ((ar)->hw_rev == ATH10K_HW_QCA99X0) 403 #define QCA_REV_9888(ar) ((ar)->hw_rev == ATH10K_HW_QCA9888) 404 #define QCA_REV_9984(ar) ((ar)->hw_rev == ATH10K_HW_QCA9984) 405 #define QCA_REV_9377(ar) ((ar)->hw_rev == ATH10K_HW_QCA9377) 406 #define QCA_REV_40XX(ar) ((ar)->hw_rev == ATH10K_HW_QCA4019) 407 #define QCA_REV_WCN3990(ar) ((ar)->hw_rev == ATH10K_HW_WCN3990) 408 409 /* Known peculiarities: 410 * - raw appears in nwifi decap, raw and nwifi appear in ethernet decap 411 * - raw have FCS, nwifi doesn't 412 * - ethernet frames have 802.11 header decapped and parts (base hdr, cipher 413 * param, llc/snap) are aligned to 4byte boundaries each 414 */ 415 enum ath10k_hw_txrx_mode { 416 ATH10K_HW_TXRX_RAW = 0, 417 418 /* Native Wifi decap mode is used to align IP frames to 4-byte 419 * boundaries and avoid a very expensive re-alignment in mac80211. 420 */ 421 ATH10K_HW_TXRX_NATIVE_WIFI = 1, 422 ATH10K_HW_TXRX_ETHERNET = 2, 423 424 /* Valid for HTT >= 3.0. Used for management frames in TX_FRM. */ 425 ATH10K_HW_TXRX_MGMT = 3, 426 }; 427 428 enum ath10k_mcast2ucast_mode { 429 ATH10K_MCAST2UCAST_DISABLED = 0, 430 ATH10K_MCAST2UCAST_ENABLED = 1, 431 }; 432 433 enum ath10k_hw_rate_ofdm { 434 ATH10K_HW_RATE_OFDM_48M = 0, 435 ATH10K_HW_RATE_OFDM_24M, 436 ATH10K_HW_RATE_OFDM_12M, 437 ATH10K_HW_RATE_OFDM_6M, 438 ATH10K_HW_RATE_OFDM_54M, 439 ATH10K_HW_RATE_OFDM_36M, 440 ATH10K_HW_RATE_OFDM_18M, 441 ATH10K_HW_RATE_OFDM_9M, 442 }; 443 444 enum ath10k_hw_rate_cck { 445 ATH10K_HW_RATE_CCK_LP_11M = 0, 446 ATH10K_HW_RATE_CCK_LP_5_5M, 447 ATH10K_HW_RATE_CCK_LP_2M, 448 ATH10K_HW_RATE_CCK_LP_1M, 449 ATH10K_HW_RATE_CCK_SP_11M, 450 ATH10K_HW_RATE_CCK_SP_5_5M, 451 ATH10K_HW_RATE_CCK_SP_2M, 452 }; 453 454 enum ath10k_hw_rate_rev2_cck { 455 ATH10K_HW_RATE_REV2_CCK_LP_1M = 1, 456 ATH10K_HW_RATE_REV2_CCK_LP_2M, 457 ATH10K_HW_RATE_REV2_CCK_LP_5_5M, 458 ATH10K_HW_RATE_REV2_CCK_LP_11M, 459 ATH10K_HW_RATE_REV2_CCK_SP_2M, 460 ATH10K_HW_RATE_REV2_CCK_SP_5_5M, 461 ATH10K_HW_RATE_REV2_CCK_SP_11M, 462 }; 463 464 enum ath10k_hw_cc_wraparound_type { 465 ATH10K_HW_CC_WRAP_DISABLED = 0, 466 467 /* This type is when the HW chip has a quirky Cycle Counter 468 * wraparound which resets to 0x7fffffff instead of 0. All 469 * other CC related counters (e.g. Rx Clear Count) are divided 470 * by 2 so they never wraparound themselves. 471 */ 472 ATH10K_HW_CC_WRAP_SHIFTED_ALL = 1, 473 474 /* Each hw counter wrapsaround independently. When the 475 * counter overflows the repestive counter is right shifted 476 * by 1, i.e reset to 0x7fffffff, and other counters will be 477 * running unaffected. In this type of wraparound, it should 478 * be possible to report accurate Rx busy time unlike the 479 * first type. 480 */ 481 ATH10K_HW_CC_WRAP_SHIFTED_EACH = 2, 482 }; 483 484 enum ath10k_hw_refclk_speed { 485 ATH10K_HW_REFCLK_UNKNOWN = -1, 486 ATH10K_HW_REFCLK_48_MHZ = 0, 487 ATH10K_HW_REFCLK_19_2_MHZ = 1, 488 ATH10K_HW_REFCLK_24_MHZ = 2, 489 ATH10K_HW_REFCLK_26_MHZ = 3, 490 ATH10K_HW_REFCLK_37_4_MHZ = 4, 491 ATH10K_HW_REFCLK_38_4_MHZ = 5, 492 ATH10K_HW_REFCLK_40_MHZ = 6, 493 ATH10K_HW_REFCLK_52_MHZ = 7, 494 495 /* must be the last one */ 496 ATH10K_HW_REFCLK_COUNT, 497 }; 498 499 struct ath10k_hw_clk_params { 500 u32 refclk; 501 u32 div; 502 u32 rnfrac; 503 u32 settle_time; 504 u32 refdiv; 505 u32 outdiv; 506 }; 507 508 struct ath10k_hw_params { 509 u32 id; 510 u16 dev_id; 511 enum ath10k_bus bus; 512 const char *name; 513 u32 patch_load_addr; 514 int uart_pin; 515 u32 otp_exe_param; 516 517 /* Type of hw cycle counter wraparound logic, for more info 518 * refer enum ath10k_hw_cc_wraparound_type. 519 */ 520 enum ath10k_hw_cc_wraparound_type cc_wraparound_type; 521 522 /* Some of chip expects fragment descriptor to be continuous 523 * memory for any TX operation. Set continuous_frag_desc flag 524 * for the hardware which have such requirement. 525 */ 526 bool continuous_frag_desc; 527 528 /* CCK hardware rate table mapping for the newer chipsets 529 * like QCA99X0, QCA4019 got revised. The CCK h/w rate values 530 * are in a proper order with respect to the rate/preamble 531 */ 532 bool cck_rate_map_rev2; 533 534 u32 channel_counters_freq_hz; 535 536 /* Mgmt tx descriptors threshold for limiting probe response 537 * frames. 538 */ 539 u32 max_probe_resp_desc_thres; 540 541 u32 tx_chain_mask; 542 u32 rx_chain_mask; 543 u32 max_spatial_stream; 544 u32 cal_data_len; 545 546 struct ath10k_hw_params_fw { 547 const char *dir; 548 const char *board; 549 size_t board_size; 550 const char *eboard; 551 size_t ext_board_size; 552 size_t board_ext_size; 553 } fw; 554 555 /* qca99x0 family chips deliver broadcast/multicast management 556 * frames encrypted and expect software do decryption. 557 */ 558 bool sw_decrypt_mcast_mgmt; 559 560 const struct ath10k_hw_ops *hw_ops; 561 562 /* Number of bytes used for alignment in rx_hdr_status of rx desc. */ 563 int decap_align_bytes; 564 565 /* hw specific clock control parameters */ 566 const struct ath10k_hw_clk_params *hw_clk; 567 int target_cpu_freq; 568 569 /* Number of bytes to be discarded for each FFT sample */ 570 int spectral_bin_discard; 571 572 /* The board may have a restricted NSS for 160 or 80+80 vs what it 573 * can do for 80Mhz. 574 */ 575 int vht160_mcs_rx_highest; 576 int vht160_mcs_tx_highest; 577 578 /* Number of ciphers supported (i.e First N) in cipher_suites array */ 579 int n_cipher_suites; 580 581 u32 num_peers; 582 u32 ast_skid_limit; 583 u32 num_wds_entries; 584 585 /* Targets supporting physical addressing capability above 32-bits */ 586 bool target_64bit; 587 588 /* Target rx ring fill level */ 589 u32 rx_ring_fill_level; 590 591 /* target supporting per ce IRQ */ 592 bool per_ce_irq; 593 594 /* target supporting shadow register for ce write */ 595 bool shadow_reg_support; 596 597 /* target supporting retention restore on ddr */ 598 bool rri_on_ddr; 599 600 /* Number of bytes to be the offset for each FFT sample */ 601 int spectral_bin_offset; 602 603 /* targets which require hw filter reset during boot up, 604 * to avoid it sending spurious acks. 605 */ 606 bool hw_filter_reset_required; 607 608 /* target supporting fw download via diag ce */ 609 bool fw_diag_ce_download; 610 611 /* need to set uart pin if disable uart print, workaround for a 612 * firmware bug 613 */ 614 bool uart_pin_workaround; 615 }; 616 617 struct htt_rx_desc; 618 struct htt_resp; 619 struct htt_data_tx_completion_ext; 620 621 /* Defines needed for Rx descriptor abstraction */ 622 struct ath10k_hw_ops { 623 int (*rx_desc_get_l3_pad_bytes)(struct htt_rx_desc *rxd); 624 void (*set_coverage_class)(struct ath10k *ar, s16 value); 625 int (*enable_pll_clk)(struct ath10k *ar); 626 bool (*rx_desc_get_msdu_limit_error)(struct htt_rx_desc *rxd); 627 int (*tx_data_rssi_pad_bytes)(struct htt_resp *htt); 628 int (*is_rssi_enable)(struct htt_resp *resp); 629 }; 630 631 extern const struct ath10k_hw_ops qca988x_ops; 632 extern const struct ath10k_hw_ops qca99x0_ops; 633 extern const struct ath10k_hw_ops qca6174_ops; 634 extern const struct ath10k_hw_ops wcn3990_ops; 635 636 extern const struct ath10k_hw_clk_params qca6174_clk[]; 637 638 static inline int 639 ath10k_rx_desc_get_l3_pad_bytes(struct ath10k_hw_params *hw, 640 struct htt_rx_desc *rxd) 641 { 642 if (hw->hw_ops->rx_desc_get_l3_pad_bytes) 643 return hw->hw_ops->rx_desc_get_l3_pad_bytes(rxd); 644 return 0; 645 } 646 647 static inline bool 648 ath10k_rx_desc_msdu_limit_error(struct ath10k_hw_params *hw, 649 struct htt_rx_desc *rxd) 650 { 651 if (hw->hw_ops->rx_desc_get_msdu_limit_error) 652 return hw->hw_ops->rx_desc_get_msdu_limit_error(rxd); 653 return false; 654 } 655 656 static inline int 657 ath10k_tx_data_rssi_get_pad_bytes(struct ath10k_hw_params *hw, 658 struct htt_resp *htt) 659 { 660 if (hw->hw_ops->tx_data_rssi_pad_bytes) 661 return hw->hw_ops->tx_data_rssi_pad_bytes(htt); 662 return 0; 663 } 664 665 static inline int 666 ath10k_is_rssi_enable(struct ath10k_hw_params *hw, 667 struct htt_resp *resp) 668 { 669 if (hw->hw_ops->is_rssi_enable) 670 return hw->hw_ops->is_rssi_enable(resp); 671 return 0; 672 } 673 674 /* Target specific defines for MAIN firmware */ 675 #define TARGET_NUM_VDEVS 8 676 #define TARGET_NUM_PEER_AST 2 677 #define TARGET_NUM_WDS_ENTRIES 32 678 #define TARGET_DMA_BURST_SIZE 0 679 #define TARGET_MAC_AGGR_DELIM 0 680 #define TARGET_AST_SKID_LIMIT 16 681 #define TARGET_NUM_STATIONS 16 682 #define TARGET_NUM_PEERS ((TARGET_NUM_STATIONS) + \ 683 (TARGET_NUM_VDEVS)) 684 #define TARGET_NUM_OFFLOAD_PEERS 0 685 #define TARGET_NUM_OFFLOAD_REORDER_BUFS 0 686 #define TARGET_NUM_PEER_KEYS 2 687 #define TARGET_NUM_TIDS ((TARGET_NUM_PEERS) * 2) 688 #define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 689 #define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 690 #define TARGET_RX_TIMEOUT_LO_PRI 100 691 #define TARGET_RX_TIMEOUT_HI_PRI 40 692 693 #define TARGET_SCAN_MAX_PENDING_REQS 4 694 #define TARGET_BMISS_OFFLOAD_MAX_VDEV 3 695 #define TARGET_ROAM_OFFLOAD_MAX_VDEV 3 696 #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8 697 #define TARGET_GTK_OFFLOAD_MAX_VDEV 3 698 #define TARGET_NUM_MCAST_GROUPS 0 699 #define TARGET_NUM_MCAST_TABLE_ELEMS 0 700 #define TARGET_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED 701 #define TARGET_TX_DBG_LOG_SIZE 1024 702 #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0 703 #define TARGET_VOW_CONFIG 0 704 #define TARGET_NUM_MSDU_DESC (1024 + 400) 705 #define TARGET_MAX_FRAG_ENTRIES 0 706 707 /* Target specific defines for 10.X firmware */ 708 #define TARGET_10X_NUM_VDEVS 16 709 #define TARGET_10X_NUM_PEER_AST 2 710 #define TARGET_10X_NUM_WDS_ENTRIES 32 711 #define TARGET_10X_DMA_BURST_SIZE 0 712 #define TARGET_10X_MAC_AGGR_DELIM 0 713 #define TARGET_10X_AST_SKID_LIMIT 128 714 #define TARGET_10X_NUM_STATIONS 128 715 #define TARGET_10X_TX_STATS_NUM_STATIONS 118 716 #define TARGET_10X_NUM_PEERS ((TARGET_10X_NUM_STATIONS) + \ 717 (TARGET_10X_NUM_VDEVS)) 718 #define TARGET_10X_TX_STATS_NUM_PEERS ((TARGET_10X_TX_STATS_NUM_STATIONS) + \ 719 (TARGET_10X_NUM_VDEVS)) 720 #define TARGET_10X_NUM_OFFLOAD_PEERS 0 721 #define TARGET_10X_NUM_OFFLOAD_REORDER_BUFS 0 722 #define TARGET_10X_NUM_PEER_KEYS 2 723 #define TARGET_10X_NUM_TIDS_MAX 256 724 #define TARGET_10X_NUM_TIDS min((TARGET_10X_NUM_TIDS_MAX), \ 725 (TARGET_10X_NUM_PEERS) * 2) 726 #define TARGET_10X_TX_STATS_NUM_TIDS min((TARGET_10X_NUM_TIDS_MAX), \ 727 (TARGET_10X_TX_STATS_NUM_PEERS) * 2) 728 #define TARGET_10X_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 729 #define TARGET_10X_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 730 #define TARGET_10X_RX_TIMEOUT_LO_PRI 100 731 #define TARGET_10X_RX_TIMEOUT_HI_PRI 40 732 #define TARGET_10X_SCAN_MAX_PENDING_REQS 4 733 #define TARGET_10X_BMISS_OFFLOAD_MAX_VDEV 2 734 #define TARGET_10X_ROAM_OFFLOAD_MAX_VDEV 2 735 #define TARGET_10X_ROAM_OFFLOAD_MAX_AP_PROFILES 8 736 #define TARGET_10X_GTK_OFFLOAD_MAX_VDEV 3 737 #define TARGET_10X_NUM_MCAST_GROUPS 0 738 #define TARGET_10X_NUM_MCAST_TABLE_ELEMS 0 739 #define TARGET_10X_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED 740 #define TARGET_10X_TX_DBG_LOG_SIZE 1024 741 #define TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1 742 #define TARGET_10X_VOW_CONFIG 0 743 #define TARGET_10X_NUM_MSDU_DESC (1024 + 400) 744 #define TARGET_10X_MAX_FRAG_ENTRIES 0 745 746 /* 10.2 parameters */ 747 #define TARGET_10_2_DMA_BURST_SIZE 0 748 749 /* Target specific defines for WMI-TLV firmware */ 750 #define TARGET_TLV_NUM_VDEVS 4 751 #define TARGET_TLV_NUM_STATIONS 32 752 #define TARGET_TLV_NUM_PEERS 33 753 #define TARGET_TLV_NUM_TDLS_VDEVS 1 754 #define TARGET_TLV_NUM_TIDS ((TARGET_TLV_NUM_PEERS) * 2) 755 #define TARGET_TLV_NUM_MSDU_DESC (1024 + 32) 756 #define TARGET_TLV_NUM_MSDU_DESC_HL 64 757 #define TARGET_TLV_NUM_WOW_PATTERNS 22 758 #define TARGET_TLV_MGMT_NUM_MSDU_DESC (50) 759 760 /* Target specific defines for WMI-HL-1.0 firmware */ 761 #define TARGET_HL_TLV_NUM_PEERS 33 762 #define TARGET_HL_TLV_AST_SKID_LIMIT 16 763 #define TARGET_HL_TLV_NUM_WDS_ENTRIES 2 764 765 /* Diagnostic Window */ 766 #define CE_DIAG_PIPE 7 767 768 #define NUM_TARGET_CE_CONFIG_WLAN ar->hw_values->num_target_ce_config_wlan 769 770 /* Target specific defines for 10.4 firmware */ 771 #define TARGET_10_4_NUM_VDEVS 16 772 #define TARGET_10_4_NUM_STATIONS 32 773 #define TARGET_10_4_NUM_PEERS ((TARGET_10_4_NUM_STATIONS) + \ 774 (TARGET_10_4_NUM_VDEVS)) 775 #define TARGET_10_4_ACTIVE_PEERS 0 776 777 #define TARGET_10_4_NUM_QCACHE_PEERS_MAX 512 778 #define TARGET_10_4_QCACHE_ACTIVE_PEERS 50 779 #define TARGET_10_4_QCACHE_ACTIVE_PEERS_PFC 35 780 #define TARGET_10_4_NUM_OFFLOAD_PEERS 0 781 #define TARGET_10_4_NUM_OFFLOAD_REORDER_BUFFS 0 782 #define TARGET_10_4_NUM_PEER_KEYS 2 783 #define TARGET_10_4_TGT_NUM_TIDS ((TARGET_10_4_NUM_PEERS) * 2) 784 #define TARGET_10_4_NUM_MSDU_DESC (1024 + 400) 785 #define TARGET_10_4_NUM_MSDU_DESC_PFC 2500 786 #define TARGET_10_4_AST_SKID_LIMIT 32 787 788 /* 100 ms for video, best-effort, and background */ 789 #define TARGET_10_4_RX_TIMEOUT_LO_PRI 100 790 791 /* 40 ms for voice */ 792 #define TARGET_10_4_RX_TIMEOUT_HI_PRI 40 793 794 #define TARGET_10_4_RX_DECAP_MODE ATH10K_HW_TXRX_NATIVE_WIFI 795 #define TARGET_10_4_SCAN_MAX_REQS 4 796 #define TARGET_10_4_BMISS_OFFLOAD_MAX_VDEV 3 797 #define TARGET_10_4_ROAM_OFFLOAD_MAX_VDEV 3 798 #define TARGET_10_4_ROAM_OFFLOAD_MAX_PROFILES 8 799 800 /* Note: mcast to ucast is disabled by default */ 801 #define TARGET_10_4_NUM_MCAST_GROUPS 0 802 #define TARGET_10_4_NUM_MCAST_TABLE_ELEMS 0 803 #define TARGET_10_4_MCAST2UCAST_MODE 0 804 805 #define TARGET_10_4_TX_DBG_LOG_SIZE 1024 806 #define TARGET_10_4_NUM_WDS_ENTRIES 32 807 #define TARGET_10_4_DMA_BURST_SIZE 0 808 #define TARGET_10_4_MAC_AGGR_DELIM 0 809 #define TARGET_10_4_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1 810 #define TARGET_10_4_VOW_CONFIG 0 811 #define TARGET_10_4_GTK_OFFLOAD_MAX_VDEV 3 812 #define TARGET_10_4_11AC_TX_MAX_FRAGS 2 813 #define TARGET_10_4_MAX_PEER_EXT_STATS 16 814 #define TARGET_10_4_SMART_ANT_CAP 0 815 #define TARGET_10_4_BK_MIN_FREE 0 816 #define TARGET_10_4_BE_MIN_FREE 0 817 #define TARGET_10_4_VI_MIN_FREE 0 818 #define TARGET_10_4_VO_MIN_FREE 0 819 #define TARGET_10_4_RX_BATCH_MODE 1 820 #define TARGET_10_4_THERMAL_THROTTLING_CONFIG 0 821 #define TARGET_10_4_ATF_CONFIG 0 822 #define TARGET_10_4_IPHDR_PAD_CONFIG 1 823 #define TARGET_10_4_QWRAP_CONFIG 0 824 825 /* TDLS config */ 826 #define TARGET_10_4_NUM_TDLS_VDEVS 1 827 #define TARGET_10_4_NUM_TDLS_BUFFER_STA 1 828 #define TARGET_10_4_NUM_TDLS_SLEEP_STA 1 829 830 /* Maximum number of Copy Engine's supported */ 831 #define CE_COUNT_MAX 12 832 833 /* Number of Copy Engines supported */ 834 #define CE_COUNT ar->hw_values->ce_count 835 836 /* 837 * Granted MSIs are assigned as follows: 838 * Firmware uses the first 839 * Remaining MSIs, if any, are used by Copy Engines 840 * This mapping is known to both Target firmware and Host software. 841 * It may be changed as long as Host and Target are kept in sync. 842 */ 843 /* MSI for firmware (errors, etc.) */ 844 #define MSI_ASSIGN_FW 0 845 846 /* MSIs for Copy Engines */ 847 #define MSI_ASSIGN_CE_INITIAL 1 848 #define MSI_ASSIGN_CE_MAX ar->hw_values->msi_assign_ce_max 849 850 /* as of IP3.7.1 */ 851 #define RTC_STATE_V_ON ar->hw_values->rtc_state_val_on 852 853 #define RTC_STATE_V_LSB 0 854 #define RTC_STATE_V_MASK 0x00000007 855 #define RTC_STATE_ADDRESS 0x0000 856 #define PCIE_SOC_WAKE_V_MASK 0x00000001 857 #define PCIE_SOC_WAKE_ADDRESS 0x0004 858 #define PCIE_SOC_WAKE_RESET 0x00000000 859 #define SOC_GLOBAL_RESET_ADDRESS 0x0008 860 861 #define RTC_SOC_BASE_ADDRESS ar->regs->rtc_soc_base_address 862 #define RTC_WMAC_BASE_ADDRESS ar->regs->rtc_wmac_base_address 863 #define MAC_COEX_BASE_ADDRESS 0x00006000 864 #define BT_COEX_BASE_ADDRESS 0x00007000 865 #define SOC_PCIE_BASE_ADDRESS 0x00008000 866 #define SOC_CORE_BASE_ADDRESS ar->regs->soc_core_base_address 867 #define WLAN_UART_BASE_ADDRESS 0x0000c000 868 #define WLAN_SI_BASE_ADDRESS 0x00010000 869 #define WLAN_GPIO_BASE_ADDRESS 0x00014000 870 #define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000 871 #define WLAN_MAC_BASE_ADDRESS ar->regs->wlan_mac_base_address 872 #define EFUSE_BASE_ADDRESS 0x00030000 873 #define FPGA_REG_BASE_ADDRESS 0x00039000 874 #define WLAN_UART2_BASE_ADDRESS 0x00054c00 875 #define CE_WRAPPER_BASE_ADDRESS ar->regs->ce_wrapper_base_address 876 #define CE0_BASE_ADDRESS ar->regs->ce0_base_address 877 #define CE1_BASE_ADDRESS ar->regs->ce1_base_address 878 #define CE2_BASE_ADDRESS ar->regs->ce2_base_address 879 #define CE3_BASE_ADDRESS ar->regs->ce3_base_address 880 #define CE4_BASE_ADDRESS ar->regs->ce4_base_address 881 #define CE5_BASE_ADDRESS ar->regs->ce5_base_address 882 #define CE6_BASE_ADDRESS ar->regs->ce6_base_address 883 #define CE7_BASE_ADDRESS ar->regs->ce7_base_address 884 #define DBI_BASE_ADDRESS 0x00060000 885 #define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x0006c000 886 #define PCIE_LOCAL_BASE_ADDRESS ar->regs->pcie_local_base_address 887 888 #define SOC_RESET_CONTROL_ADDRESS 0x00000000 889 #define SOC_RESET_CONTROL_OFFSET 0x00000000 890 #define SOC_RESET_CONTROL_SI0_RST_MASK ar->regs->soc_reset_control_si0_rst_mask 891 #define SOC_RESET_CONTROL_CE_RST_MASK ar->regs->soc_reset_control_ce_rst_mask 892 #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040 893 #define SOC_CPU_CLOCK_OFFSET 0x00000020 894 #define SOC_CPU_CLOCK_STANDARD_LSB 0 895 #define SOC_CPU_CLOCK_STANDARD_MASK 0x00000003 896 #define SOC_CLOCK_CONTROL_OFFSET 0x00000028 897 #define SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001 898 #define SOC_SYSTEM_SLEEP_OFFSET 0x000000c4 899 #define SOC_LPO_CAL_OFFSET 0x000000e0 900 #define SOC_LPO_CAL_ENABLE_LSB 20 901 #define SOC_LPO_CAL_ENABLE_MASK 0x00100000 902 #define SOC_LF_TIMER_CONTROL0_ADDRESS 0x00000050 903 #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004 904 905 #define SOC_CHIP_ID_ADDRESS ar->regs->soc_chip_id_address 906 #define SOC_CHIP_ID_REV_LSB 8 907 #define SOC_CHIP_ID_REV_MASK 0x00000f00 908 909 #define WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000008 910 #define WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000004 911 #define WLAN_SYSTEM_SLEEP_DISABLE_LSB 0 912 #define WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001 913 914 #define WLAN_GPIO_PIN0_ADDRESS 0x00000028 915 #define WLAN_GPIO_PIN0_CONFIG_LSB 11 916 #define WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800 917 #define WLAN_GPIO_PIN0_PAD_PULL_LSB 5 918 #define WLAN_GPIO_PIN0_PAD_PULL_MASK 0x00000060 919 #define WLAN_GPIO_PIN1_ADDRESS 0x0000002c 920 #define WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800 921 #define WLAN_GPIO_PIN10_ADDRESS 0x00000050 922 #define WLAN_GPIO_PIN11_ADDRESS 0x00000054 923 #define WLAN_GPIO_PIN12_ADDRESS 0x00000058 924 #define WLAN_GPIO_PIN13_ADDRESS 0x0000005c 925 926 #define CLOCK_GPIO_OFFSET 0xffffffff 927 #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0 928 #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0 929 930 #define SI_CONFIG_OFFSET 0x00000000 931 #define SI_CONFIG_ERR_INT_LSB 19 932 #define SI_CONFIG_ERR_INT_MASK 0x00080000 933 #define SI_CONFIG_BIDIR_OD_DATA_LSB 18 934 #define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000 935 #define SI_CONFIG_I2C_LSB 16 936 #define SI_CONFIG_I2C_MASK 0x00010000 937 #define SI_CONFIG_POS_SAMPLE_LSB 7 938 #define SI_CONFIG_POS_SAMPLE_MASK 0x00000080 939 #define SI_CONFIG_INACTIVE_DATA_LSB 5 940 #define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020 941 #define SI_CONFIG_INACTIVE_CLK_LSB 4 942 #define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010 943 #define SI_CONFIG_DIVIDER_LSB 0 944 #define SI_CONFIG_DIVIDER_MASK 0x0000000f 945 #define SI_CS_OFFSET 0x00000004 946 #define SI_CS_DONE_ERR_LSB 10 947 #define SI_CS_DONE_ERR_MASK 0x00000400 948 #define SI_CS_DONE_INT_LSB 9 949 #define SI_CS_DONE_INT_MASK 0x00000200 950 #define SI_CS_START_LSB 8 951 #define SI_CS_START_MASK 0x00000100 952 #define SI_CS_RX_CNT_LSB 4 953 #define SI_CS_RX_CNT_MASK 0x000000f0 954 #define SI_CS_TX_CNT_LSB 0 955 #define SI_CS_TX_CNT_MASK 0x0000000f 956 957 #define SI_TX_DATA0_OFFSET 0x00000008 958 #define SI_TX_DATA1_OFFSET 0x0000000c 959 #define SI_RX_DATA0_OFFSET 0x00000010 960 #define SI_RX_DATA1_OFFSET 0x00000014 961 962 #define CORE_CTRL_CPU_INTR_MASK 0x00002000 963 #define CORE_CTRL_PCIE_REG_31_MASK 0x00000800 964 #define CORE_CTRL_ADDRESS 0x0000 965 #define PCIE_INTR_ENABLE_ADDRESS 0x0008 966 #define PCIE_INTR_CAUSE_ADDRESS 0x000c 967 #define PCIE_INTR_CLR_ADDRESS ar->regs->pcie_intr_clr_address 968 #define SCRATCH_3_ADDRESS ar->regs->scratch_3_address 969 #define CPU_INTR_ADDRESS 0x0010 970 #define FW_RAM_CONFIG_ADDRESS 0x0018 971 972 #define CCNT_TO_MSEC(ar, x) ((x) / ar->hw_params.channel_counters_freq_hz) 973 974 /* Firmware indications to the Host via SCRATCH_3 register. */ 975 #define FW_INDICATOR_ADDRESS ar->regs->fw_indicator_address 976 #define FW_IND_EVENT_PENDING 1 977 #define FW_IND_INITIALIZED 2 978 #define FW_IND_HOST_READY 0x80000000 979 980 /* HOST_REG interrupt from firmware */ 981 #define PCIE_INTR_FIRMWARE_MASK ar->regs->pcie_intr_fw_mask 982 #define PCIE_INTR_CE_MASK_ALL ar->regs->pcie_intr_ce_mask_all 983 984 #define DRAM_BASE_ADDRESS 0x00400000 985 986 #define PCIE_BAR_REG_ADDRESS 0x40030 987 988 #define MISSING 0 989 990 #define SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET 991 #define WLAN_SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET 992 #define WLAN_RESET_CONTROL_OFFSET SOC_RESET_CONTROL_OFFSET 993 #define CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_OFFSET 994 #define CLOCK_CONTROL_SI0_CLK_MASK SOC_CLOCK_CONTROL_SI0_CLK_MASK 995 #define RESET_CONTROL_MBOX_RST_MASK MISSING 996 #define RESET_CONTROL_SI0_RST_MASK SOC_RESET_CONTROL_SI0_RST_MASK 997 #define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS 998 #define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_ADDRESS 999 #define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_ADDRESS 1000 #define GPIO_PIN0_CONFIG_LSB WLAN_GPIO_PIN0_CONFIG_LSB 1001 #define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK 1002 #define GPIO_PIN0_PAD_PULL_LSB WLAN_GPIO_PIN0_PAD_PULL_LSB 1003 #define GPIO_PIN0_PAD_PULL_MASK WLAN_GPIO_PIN0_PAD_PULL_MASK 1004 #define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK 1005 #define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS 1006 #define SCRATCH_BASE_ADDRESS SOC_CORE_BASE_ADDRESS 1007 #define LOCAL_SCRATCH_OFFSET 0x18 1008 #define CPU_CLOCK_OFFSET SOC_CPU_CLOCK_OFFSET 1009 #define LPO_CAL_OFFSET SOC_LPO_CAL_OFFSET 1010 #define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_ADDRESS 1011 #define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_ADDRESS 1012 #define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_ADDRESS 1013 #define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_ADDRESS 1014 #define CPU_CLOCK_STANDARD_LSB SOC_CPU_CLOCK_STANDARD_LSB 1015 #define CPU_CLOCK_STANDARD_MASK SOC_CPU_CLOCK_STANDARD_MASK 1016 #define LPO_CAL_ENABLE_LSB SOC_LPO_CAL_ENABLE_LSB 1017 #define LPO_CAL_ENABLE_MASK SOC_LPO_CAL_ENABLE_MASK 1018 #define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS 1019 #define MBOX_BASE_ADDRESS MISSING 1020 #define INT_STATUS_ENABLE_ERROR_LSB MISSING 1021 #define INT_STATUS_ENABLE_ERROR_MASK MISSING 1022 #define INT_STATUS_ENABLE_CPU_LSB MISSING 1023 #define INT_STATUS_ENABLE_CPU_MASK MISSING 1024 #define INT_STATUS_ENABLE_COUNTER_LSB MISSING 1025 #define INT_STATUS_ENABLE_COUNTER_MASK MISSING 1026 #define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING 1027 #define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING 1028 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING 1029 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING 1030 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING 1031 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING 1032 #define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING 1033 #define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING 1034 #define INT_STATUS_ENABLE_ADDRESS MISSING 1035 #define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING 1036 #define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING 1037 #define HOST_INT_STATUS_ADDRESS MISSING 1038 #define CPU_INT_STATUS_ADDRESS MISSING 1039 #define ERROR_INT_STATUS_ADDRESS MISSING 1040 #define ERROR_INT_STATUS_WAKEUP_MASK MISSING 1041 #define ERROR_INT_STATUS_WAKEUP_LSB MISSING 1042 #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING 1043 #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING 1044 #define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING 1045 #define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING 1046 #define COUNT_DEC_ADDRESS MISSING 1047 #define HOST_INT_STATUS_CPU_MASK MISSING 1048 #define HOST_INT_STATUS_CPU_LSB MISSING 1049 #define HOST_INT_STATUS_ERROR_MASK MISSING 1050 #define HOST_INT_STATUS_ERROR_LSB MISSING 1051 #define HOST_INT_STATUS_COUNTER_MASK MISSING 1052 #define HOST_INT_STATUS_COUNTER_LSB MISSING 1053 #define RX_LOOKAHEAD_VALID_ADDRESS MISSING 1054 #define WINDOW_DATA_ADDRESS MISSING 1055 #define WINDOW_READ_ADDR_ADDRESS MISSING 1056 #define WINDOW_WRITE_ADDR_ADDRESS MISSING 1057 1058 #define QCA9887_1_0_I2C_SDA_GPIO_PIN 5 1059 #define QCA9887_1_0_I2C_SDA_PIN_CONFIG 3 1060 #define QCA9887_1_0_SI_CLK_GPIO_PIN 17 1061 #define QCA9887_1_0_SI_CLK_PIN_CONFIG 3 1062 #define QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS 0x00000010 1063 1064 #define QCA9887_EEPROM_SELECT_READ 0xa10000a0 1065 #define QCA9887_EEPROM_ADDR_HI_MASK 0x0000ff00 1066 #define QCA9887_EEPROM_ADDR_HI_LSB 8 1067 #define QCA9887_EEPROM_ADDR_LO_MASK 0x00ff0000 1068 #define QCA9887_EEPROM_ADDR_LO_LSB 16 1069 1070 #define MBOX_RESET_CONTROL_ADDRESS 0x00000000 1071 #define MBOX_HOST_INT_STATUS_ADDRESS 0x00000800 1072 #define MBOX_HOST_INT_STATUS_ERROR_LSB 7 1073 #define MBOX_HOST_INT_STATUS_ERROR_MASK 0x00000080 1074 #define MBOX_HOST_INT_STATUS_CPU_LSB 6 1075 #define MBOX_HOST_INT_STATUS_CPU_MASK 0x00000040 1076 #define MBOX_HOST_INT_STATUS_COUNTER_LSB 4 1077 #define MBOX_HOST_INT_STATUS_COUNTER_MASK 0x00000010 1078 #define MBOX_CPU_INT_STATUS_ADDRESS 0x00000801 1079 #define MBOX_ERROR_INT_STATUS_ADDRESS 0x00000802 1080 #define MBOX_ERROR_INT_STATUS_WAKEUP_LSB 2 1081 #define MBOX_ERROR_INT_STATUS_WAKEUP_MASK 0x00000004 1082 #define MBOX_ERROR_INT_STATUS_RX_UNDERFLOW_LSB 1 1083 #define MBOX_ERROR_INT_STATUS_RX_UNDERFLOW_MASK 0x00000002 1084 #define MBOX_ERROR_INT_STATUS_TX_OVERFLOW_LSB 0 1085 #define MBOX_ERROR_INT_STATUS_TX_OVERFLOW_MASK 0x00000001 1086 #define MBOX_COUNTER_INT_STATUS_ADDRESS 0x00000803 1087 #define MBOX_COUNTER_INT_STATUS_COUNTER_LSB 0 1088 #define MBOX_COUNTER_INT_STATUS_COUNTER_MASK 0x000000ff 1089 #define MBOX_RX_LOOKAHEAD_VALID_ADDRESS 0x00000805 1090 #define MBOX_INT_STATUS_ENABLE_ADDRESS 0x00000828 1091 #define MBOX_INT_STATUS_ENABLE_ERROR_LSB 7 1092 #define MBOX_INT_STATUS_ENABLE_ERROR_MASK 0x00000080 1093 #define MBOX_INT_STATUS_ENABLE_CPU_LSB 6 1094 #define MBOX_INT_STATUS_ENABLE_CPU_MASK 0x00000040 1095 #define MBOX_INT_STATUS_ENABLE_INT_LSB 5 1096 #define MBOX_INT_STATUS_ENABLE_INT_MASK 0x00000020 1097 #define MBOX_INT_STATUS_ENABLE_COUNTER_LSB 4 1098 #define MBOX_INT_STATUS_ENABLE_COUNTER_MASK 0x00000010 1099 #define MBOX_INT_STATUS_ENABLE_MBOX_DATA_LSB 0 1100 #define MBOX_INT_STATUS_ENABLE_MBOX_DATA_MASK 0x0000000f 1101 #define MBOX_CPU_INT_STATUS_ENABLE_ADDRESS 0x00000819 1102 #define MBOX_CPU_INT_STATUS_ENABLE_BIT_LSB 0 1103 #define MBOX_CPU_INT_STATUS_ENABLE_BIT_MASK 0x000000ff 1104 #define MBOX_ERROR_STATUS_ENABLE_ADDRESS 0x0000081a 1105 #define MBOX_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB 1 1106 #define MBOX_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00000002 1107 #define MBOX_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB 0 1108 #define MBOX_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK 0x00000001 1109 #define MBOX_COUNTER_INT_STATUS_ENABLE_ADDRESS 0x0000081b 1110 #define MBOX_COUNTER_INT_STATUS_ENABLE_BIT_LSB 0 1111 #define MBOX_COUNTER_INT_STATUS_ENABLE_BIT_MASK 0x000000ff 1112 #define MBOX_COUNT_ADDRESS 0x00000820 1113 #define MBOX_COUNT_DEC_ADDRESS 0x00000840 1114 #define MBOX_WINDOW_DATA_ADDRESS 0x00000874 1115 #define MBOX_WINDOW_WRITE_ADDR_ADDRESS 0x00000878 1116 #define MBOX_WINDOW_READ_ADDR_ADDRESS 0x0000087c 1117 #define MBOX_CPU_DBG_SEL_ADDRESS 0x00000883 1118 #define MBOX_CPU_DBG_ADDRESS 0x00000884 1119 #define MBOX_RTC_BASE_ADDRESS 0x00000000 1120 #define MBOX_GPIO_BASE_ADDRESS 0x00005000 1121 #define MBOX_MBOX_BASE_ADDRESS 0x00008000 1122 1123 #define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB) 1124 1125 /* Register definitions for first generation ath10k cards. These cards include 1126 * a mac thich has a register allocation similar to ath9k and at least some 1127 * registers including the ones relevant for modifying the coverage class are 1128 * identical to the ath9k definitions. 1129 * These registers are usually managed by the ath10k firmware. However by 1130 * overriding them it is possible to support coverage class modifications. 1131 */ 1132 #define WAVE1_PCU_ACK_CTS_TIMEOUT 0x8014 1133 #define WAVE1_PCU_ACK_CTS_TIMEOUT_MAX 0x00003FFF 1134 #define WAVE1_PCU_ACK_CTS_TIMEOUT_ACK_MASK 0x00003FFF 1135 #define WAVE1_PCU_ACK_CTS_TIMEOUT_ACK_LSB 0 1136 #define WAVE1_PCU_ACK_CTS_TIMEOUT_CTS_MASK 0x3FFF0000 1137 #define WAVE1_PCU_ACK_CTS_TIMEOUT_CTS_LSB 16 1138 1139 #define WAVE1_PCU_GBL_IFS_SLOT 0x1070 1140 #define WAVE1_PCU_GBL_IFS_SLOT_MASK 0x0000FFFF 1141 #define WAVE1_PCU_GBL_IFS_SLOT_MAX 0x0000FFFF 1142 #define WAVE1_PCU_GBL_IFS_SLOT_LSB 0 1143 #define WAVE1_PCU_GBL_IFS_SLOT_RESV0 0xFFFF0000 1144 1145 #define WAVE1_PHYCLK 0x801C 1146 #define WAVE1_PHYCLK_USEC_MASK 0x0000007F 1147 #define WAVE1_PHYCLK_USEC_LSB 0 1148 1149 /* qca6174 PLL offset/mask */ 1150 #define SOC_CORE_CLK_CTRL_OFFSET 0x00000114 1151 #define SOC_CORE_CLK_CTRL_DIV_LSB 0 1152 #define SOC_CORE_CLK_CTRL_DIV_MASK 0x00000007 1153 1154 #define EFUSE_OFFSET 0x0000032c 1155 #define EFUSE_XTAL_SEL_LSB 8 1156 #define EFUSE_XTAL_SEL_MASK 0x00000700 1157 1158 #define BB_PLL_CONFIG_OFFSET 0x000002f4 1159 #define BB_PLL_CONFIG_FRAC_LSB 0 1160 #define BB_PLL_CONFIG_FRAC_MASK 0x0003ffff 1161 #define BB_PLL_CONFIG_OUTDIV_LSB 18 1162 #define BB_PLL_CONFIG_OUTDIV_MASK 0x001c0000 1163 1164 #define WLAN_PLL_SETTLE_OFFSET 0x0018 1165 #define WLAN_PLL_SETTLE_TIME_LSB 0 1166 #define WLAN_PLL_SETTLE_TIME_MASK 0x000007ff 1167 1168 #define WLAN_PLL_CONTROL_OFFSET 0x0014 1169 #define WLAN_PLL_CONTROL_DIV_LSB 0 1170 #define WLAN_PLL_CONTROL_DIV_MASK 0x000003ff 1171 #define WLAN_PLL_CONTROL_REFDIV_LSB 10 1172 #define WLAN_PLL_CONTROL_REFDIV_MASK 0x00003c00 1173 #define WLAN_PLL_CONTROL_BYPASS_LSB 16 1174 #define WLAN_PLL_CONTROL_BYPASS_MASK 0x00010000 1175 #define WLAN_PLL_CONTROL_NOPWD_LSB 18 1176 #define WLAN_PLL_CONTROL_NOPWD_MASK 0x00040000 1177 1178 #define RTC_SYNC_STATUS_OFFSET 0x0244 1179 #define RTC_SYNC_STATUS_PLL_CHANGING_LSB 5 1180 #define RTC_SYNC_STATUS_PLL_CHANGING_MASK 0x00000020 1181 /* qca6174 PLL offset/mask end */ 1182 1183 /* CPU_ADDR_MSB is a register, bit[3:0] is to specify which memory 1184 * region is accessed. The memory region size is 1M. 1185 * If host wants to access 0xX12345 at target, then CPU_ADDR_MSB[3:0] 1186 * is 0xX. 1187 * The following MACROs are defined to get the 0xX and the size limit. 1188 */ 1189 #define CPU_ADDR_MSB_REGION_MASK GENMASK(23, 20) 1190 #define CPU_ADDR_MSB_REGION_VAL(X) FIELD_GET(CPU_ADDR_MSB_REGION_MASK, X) 1191 #define REGION_ACCESS_SIZE_LIMIT 0x100000 1192 #define REGION_ACCESS_SIZE_MASK (REGION_ACCESS_SIZE_LIMIT - 1) 1193 1194 #endif /* _HW_H_ */ 1195