1 /* 2 * Copyright (c) 2005-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef _HW_H_ 19 #define _HW_H_ 20 21 #include "targaddrs.h" 22 23 #define ATH10K_FW_DIR "ath10k" 24 25 /* QCA988X 1.0 definitions (unsupported) */ 26 #define QCA988X_HW_1_0_CHIP_ID_REV 0x0 27 28 /* QCA988X 2.0 definitions */ 29 #define QCA988X_HW_2_0_VERSION 0x4100016c 30 #define QCA988X_HW_2_0_CHIP_ID_REV 0x2 31 #define QCA988X_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA988X/hw2.0" 32 #define QCA988X_HW_2_0_FW_FILE "firmware.bin" 33 #define QCA988X_HW_2_0_OTP_FILE "otp.bin" 34 #define QCA988X_HW_2_0_BOARD_DATA_FILE "board.bin" 35 #define QCA988X_HW_2_0_PATCH_LOAD_ADDR 0x1234 36 37 /* QCA6174 target BMI version signatures */ 38 #define QCA6174_HW_1_0_VERSION 0x05000000 39 #define QCA6174_HW_1_1_VERSION 0x05000001 40 #define QCA6174_HW_1_3_VERSION 0x05000003 41 #define QCA6174_HW_2_1_VERSION 0x05010000 42 #define QCA6174_HW_3_0_VERSION 0x05020000 43 #define QCA6174_HW_3_2_VERSION 0x05030000 44 45 enum qca6174_pci_rev { 46 QCA6174_PCI_REV_1_1 = 0x11, 47 QCA6174_PCI_REV_1_3 = 0x13, 48 QCA6174_PCI_REV_2_0 = 0x20, 49 QCA6174_PCI_REV_3_0 = 0x30, 50 }; 51 52 enum qca6174_chip_id_rev { 53 QCA6174_HW_1_0_CHIP_ID_REV = 0, 54 QCA6174_HW_1_1_CHIP_ID_REV = 1, 55 QCA6174_HW_1_3_CHIP_ID_REV = 2, 56 QCA6174_HW_2_1_CHIP_ID_REV = 4, 57 QCA6174_HW_2_2_CHIP_ID_REV = 5, 58 QCA6174_HW_3_0_CHIP_ID_REV = 8, 59 QCA6174_HW_3_1_CHIP_ID_REV = 9, 60 QCA6174_HW_3_2_CHIP_ID_REV = 10, 61 }; 62 63 #define QCA6174_HW_2_1_FW_DIR "ath10k/QCA6174/hw2.1" 64 #define QCA6174_HW_2_1_FW_FILE "firmware.bin" 65 #define QCA6174_HW_2_1_OTP_FILE "otp.bin" 66 #define QCA6174_HW_2_1_BOARD_DATA_FILE "board.bin" 67 #define QCA6174_HW_2_1_PATCH_LOAD_ADDR 0x1234 68 69 #define QCA6174_HW_3_0_FW_DIR "ath10k/QCA6174/hw3.0" 70 #define QCA6174_HW_3_0_FW_FILE "firmware.bin" 71 #define QCA6174_HW_3_0_OTP_FILE "otp.bin" 72 #define QCA6174_HW_3_0_BOARD_DATA_FILE "board.bin" 73 #define QCA6174_HW_3_0_PATCH_LOAD_ADDR 0x1234 74 75 /* QCA99X0 1.0 definitions (unsupported) */ 76 #define QCA99X0_HW_1_0_CHIP_ID_REV 0x0 77 78 /* QCA99X0 2.0 definitions */ 79 #define QCA99X0_HW_2_0_DEV_VERSION 0x01000000 80 #define QCA99X0_HW_2_0_CHIP_ID_REV 0x1 81 #define QCA99X0_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA99X0/hw2.0" 82 #define QCA99X0_HW_2_0_FW_FILE "firmware.bin" 83 #define QCA99X0_HW_2_0_OTP_FILE "otp.bin" 84 #define QCA99X0_HW_2_0_BOARD_DATA_FILE "board.bin" 85 #define QCA99X0_HW_2_0_PATCH_LOAD_ADDR 0x1234 86 87 /* QCA9377 1.0 definitions */ 88 #define QCA9377_HW_1_0_DEV_VERSION 0x05020001 89 #define QCA9377_HW_1_0_CHIP_ID_REV 0x1 90 #define QCA9377_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9377/hw1.0" 91 #define QCA9377_HW_1_0_FW_FILE "firmware.bin" 92 #define QCA9377_HW_1_0_OTP_FILE "otp.bin" 93 #define QCA9377_HW_1_0_BOARD_DATA_FILE "board.bin" 94 #define QCA9377_HW_1_0_PATCH_LOAD_ADDR 0x1234 95 96 #define ATH10K_FW_API2_FILE "firmware-2.bin" 97 #define ATH10K_FW_API3_FILE "firmware-3.bin" 98 99 /* added support for ATH10K_FW_IE_WMI_OP_VERSION */ 100 #define ATH10K_FW_API4_FILE "firmware-4.bin" 101 102 /* HTT id conflict fix for management frames over HTT */ 103 #define ATH10K_FW_API5_FILE "firmware-5.bin" 104 105 #define ATH10K_FW_UTF_FILE "utf.bin" 106 #define ATH10K_FW_UTF_API2_FILE "utf-2.bin" 107 108 /* includes also the null byte */ 109 #define ATH10K_FIRMWARE_MAGIC "QCA-ATH10K" 110 #define ATH10K_BOARD_MAGIC "QCA-ATH10K-BOARD" 111 112 #define ATH10K_BOARD_API2_FILE "board-2.bin" 113 114 #define REG_DUMP_COUNT_QCA988X 60 115 116 #define QCA988X_CAL_DATA_LEN 2116 117 118 struct ath10k_fw_ie { 119 __le32 id; 120 __le32 len; 121 u8 data[0]; 122 }; 123 124 enum ath10k_fw_ie_type { 125 ATH10K_FW_IE_FW_VERSION = 0, 126 ATH10K_FW_IE_TIMESTAMP = 1, 127 ATH10K_FW_IE_FEATURES = 2, 128 ATH10K_FW_IE_FW_IMAGE = 3, 129 ATH10K_FW_IE_OTP_IMAGE = 4, 130 131 /* WMI "operations" interface version, 32 bit value. Supported from 132 * FW API 4 and above. 133 */ 134 ATH10K_FW_IE_WMI_OP_VERSION = 5, 135 136 /* HTT "operations" interface version, 32 bit value. Supported from 137 * FW API 5 and above. 138 */ 139 ATH10K_FW_IE_HTT_OP_VERSION = 6, 140 141 /* Code swap image for firmware binary */ 142 ATH10K_FW_IE_FW_CODE_SWAP_IMAGE = 7, 143 }; 144 145 enum ath10k_fw_wmi_op_version { 146 ATH10K_FW_WMI_OP_VERSION_UNSET = 0, 147 148 ATH10K_FW_WMI_OP_VERSION_MAIN = 1, 149 ATH10K_FW_WMI_OP_VERSION_10_1 = 2, 150 ATH10K_FW_WMI_OP_VERSION_10_2 = 3, 151 ATH10K_FW_WMI_OP_VERSION_TLV = 4, 152 ATH10K_FW_WMI_OP_VERSION_10_2_4 = 5, 153 ATH10K_FW_WMI_OP_VERSION_10_4 = 6, 154 155 /* keep last */ 156 ATH10K_FW_WMI_OP_VERSION_MAX, 157 }; 158 159 enum ath10k_fw_htt_op_version { 160 ATH10K_FW_HTT_OP_VERSION_UNSET = 0, 161 162 ATH10K_FW_HTT_OP_VERSION_MAIN = 1, 163 164 /* also used in 10.2 and 10.2.4 branches */ 165 ATH10K_FW_HTT_OP_VERSION_10_1 = 2, 166 167 ATH10K_FW_HTT_OP_VERSION_TLV = 3, 168 169 ATH10K_FW_HTT_OP_VERSION_10_4 = 4, 170 171 /* keep last */ 172 ATH10K_FW_HTT_OP_VERSION_MAX, 173 }; 174 175 enum ath10k_bd_ie_type { 176 /* contains sub IEs of enum ath10k_bd_ie_board_type */ 177 ATH10K_BD_IE_BOARD = 0, 178 }; 179 180 enum ath10k_bd_ie_board_type { 181 ATH10K_BD_IE_BOARD_NAME = 0, 182 ATH10K_BD_IE_BOARD_DATA = 1, 183 }; 184 185 enum ath10k_hw_rev { 186 ATH10K_HW_QCA988X, 187 ATH10K_HW_QCA6174, 188 ATH10K_HW_QCA99X0, 189 ATH10K_HW_QCA9377, 190 }; 191 192 struct ath10k_hw_regs { 193 u32 rtc_state_cold_reset_mask; 194 u32 rtc_soc_base_address; 195 u32 rtc_wmac_base_address; 196 u32 soc_core_base_address; 197 u32 ce_wrapper_base_address; 198 u32 ce0_base_address; 199 u32 ce1_base_address; 200 u32 ce2_base_address; 201 u32 ce3_base_address; 202 u32 ce4_base_address; 203 u32 ce5_base_address; 204 u32 ce6_base_address; 205 u32 ce7_base_address; 206 u32 soc_reset_control_si0_rst_mask; 207 u32 soc_reset_control_ce_rst_mask; 208 u32 soc_chip_id_address; 209 u32 scratch_3_address; 210 u32 fw_indicator_address; 211 u32 pcie_local_base_address; 212 u32 ce_wrap_intr_sum_host_msi_lsb; 213 u32 ce_wrap_intr_sum_host_msi_mask; 214 u32 pcie_intr_fw_mask; 215 u32 pcie_intr_ce_mask_all; 216 u32 pcie_intr_clr_address; 217 }; 218 219 extern const struct ath10k_hw_regs qca988x_regs; 220 extern const struct ath10k_hw_regs qca6174_regs; 221 extern const struct ath10k_hw_regs qca99x0_regs; 222 223 struct ath10k_hw_values { 224 u32 rtc_state_val_on; 225 u8 ce_count; 226 u8 msi_assign_ce_max; 227 u8 num_target_ce_config_wlan; 228 u16 ce_desc_meta_data_mask; 229 u8 ce_desc_meta_data_lsb; 230 }; 231 232 extern const struct ath10k_hw_values qca988x_values; 233 extern const struct ath10k_hw_values qca6174_values; 234 extern const struct ath10k_hw_values qca99x0_values; 235 236 void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey, 237 u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev); 238 239 #define QCA_REV_988X(ar) ((ar)->hw_rev == ATH10K_HW_QCA988X) 240 #define QCA_REV_6174(ar) ((ar)->hw_rev == ATH10K_HW_QCA6174) 241 #define QCA_REV_99X0(ar) ((ar)->hw_rev == ATH10K_HW_QCA99X0) 242 #define QCA_REV_9377(ar) ((ar)->hw_rev == ATH10K_HW_QCA9377) 243 244 /* Known pecularities: 245 * - raw appears in nwifi decap, raw and nwifi appear in ethernet decap 246 * - raw have FCS, nwifi doesn't 247 * - ethernet frames have 802.11 header decapped and parts (base hdr, cipher 248 * param, llc/snap) are aligned to 4byte boundaries each */ 249 enum ath10k_hw_txrx_mode { 250 ATH10K_HW_TXRX_RAW = 0, 251 252 /* Native Wifi decap mode is used to align IP frames to 4-byte 253 * boundaries and avoid a very expensive re-alignment in mac80211. 254 */ 255 ATH10K_HW_TXRX_NATIVE_WIFI = 1, 256 ATH10K_HW_TXRX_ETHERNET = 2, 257 258 /* Valid for HTT >= 3.0. Used for management frames in TX_FRM. */ 259 ATH10K_HW_TXRX_MGMT = 3, 260 }; 261 262 enum ath10k_mcast2ucast_mode { 263 ATH10K_MCAST2UCAST_DISABLED = 0, 264 ATH10K_MCAST2UCAST_ENABLED = 1, 265 }; 266 267 struct ath10k_pktlog_hdr { 268 __le16 flags; 269 __le16 missed_cnt; 270 __le16 log_type; 271 __le16 size; 272 __le32 timestamp; 273 u8 payload[0]; 274 } __packed; 275 276 enum ath10k_hw_rate_ofdm { 277 ATH10K_HW_RATE_OFDM_48M = 0, 278 ATH10K_HW_RATE_OFDM_24M, 279 ATH10K_HW_RATE_OFDM_12M, 280 ATH10K_HW_RATE_OFDM_6M, 281 ATH10K_HW_RATE_OFDM_54M, 282 ATH10K_HW_RATE_OFDM_36M, 283 ATH10K_HW_RATE_OFDM_18M, 284 ATH10K_HW_RATE_OFDM_9M, 285 }; 286 287 enum ath10k_hw_rate_cck { 288 ATH10K_HW_RATE_CCK_LP_11M = 0, 289 ATH10K_HW_RATE_CCK_LP_5_5M, 290 ATH10K_HW_RATE_CCK_LP_2M, 291 ATH10K_HW_RATE_CCK_LP_1M, 292 ATH10K_HW_RATE_CCK_SP_11M, 293 ATH10K_HW_RATE_CCK_SP_5_5M, 294 ATH10K_HW_RATE_CCK_SP_2M, 295 }; 296 297 /* Target specific defines for MAIN firmware */ 298 #define TARGET_NUM_VDEVS 8 299 #define TARGET_NUM_PEER_AST 2 300 #define TARGET_NUM_WDS_ENTRIES 32 301 #define TARGET_DMA_BURST_SIZE 0 302 #define TARGET_MAC_AGGR_DELIM 0 303 #define TARGET_AST_SKID_LIMIT 16 304 #define TARGET_NUM_STATIONS 16 305 #define TARGET_NUM_PEERS ((TARGET_NUM_STATIONS) + \ 306 (TARGET_NUM_VDEVS)) 307 #define TARGET_NUM_OFFLOAD_PEERS 0 308 #define TARGET_NUM_OFFLOAD_REORDER_BUFS 0 309 #define TARGET_NUM_PEER_KEYS 2 310 #define TARGET_NUM_TIDS ((TARGET_NUM_PEERS) * 2) 311 #define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 312 #define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 313 #define TARGET_RX_TIMEOUT_LO_PRI 100 314 #define TARGET_RX_TIMEOUT_HI_PRI 40 315 316 #define TARGET_SCAN_MAX_PENDING_REQS 4 317 #define TARGET_BMISS_OFFLOAD_MAX_VDEV 3 318 #define TARGET_ROAM_OFFLOAD_MAX_VDEV 3 319 #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8 320 #define TARGET_GTK_OFFLOAD_MAX_VDEV 3 321 #define TARGET_NUM_MCAST_GROUPS 0 322 #define TARGET_NUM_MCAST_TABLE_ELEMS 0 323 #define TARGET_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED 324 #define TARGET_TX_DBG_LOG_SIZE 1024 325 #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0 326 #define TARGET_VOW_CONFIG 0 327 #define TARGET_NUM_MSDU_DESC (1024 + 400) 328 #define TARGET_MAX_FRAG_ENTRIES 0 329 330 /* Target specific defines for 10.X firmware */ 331 #define TARGET_10X_NUM_VDEVS 16 332 #define TARGET_10X_NUM_PEER_AST 2 333 #define TARGET_10X_NUM_WDS_ENTRIES 32 334 #define TARGET_10X_DMA_BURST_SIZE 0 335 #define TARGET_10X_MAC_AGGR_DELIM 0 336 #define TARGET_10X_AST_SKID_LIMIT 128 337 #define TARGET_10X_NUM_STATIONS 128 338 #define TARGET_10X_NUM_PEERS ((TARGET_10X_NUM_STATIONS) + \ 339 (TARGET_10X_NUM_VDEVS)) 340 #define TARGET_10X_NUM_OFFLOAD_PEERS 0 341 #define TARGET_10X_NUM_OFFLOAD_REORDER_BUFS 0 342 #define TARGET_10X_NUM_PEER_KEYS 2 343 #define TARGET_10X_NUM_TIDS_MAX 256 344 #define TARGET_10X_NUM_TIDS min((TARGET_10X_NUM_TIDS_MAX), \ 345 (TARGET_10X_NUM_PEERS) * 2) 346 #define TARGET_10X_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 347 #define TARGET_10X_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 348 #define TARGET_10X_RX_TIMEOUT_LO_PRI 100 349 #define TARGET_10X_RX_TIMEOUT_HI_PRI 40 350 #define TARGET_10X_SCAN_MAX_PENDING_REQS 4 351 #define TARGET_10X_BMISS_OFFLOAD_MAX_VDEV 2 352 #define TARGET_10X_ROAM_OFFLOAD_MAX_VDEV 2 353 #define TARGET_10X_ROAM_OFFLOAD_MAX_AP_PROFILES 8 354 #define TARGET_10X_GTK_OFFLOAD_MAX_VDEV 3 355 #define TARGET_10X_NUM_MCAST_GROUPS 0 356 #define TARGET_10X_NUM_MCAST_TABLE_ELEMS 0 357 #define TARGET_10X_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED 358 #define TARGET_10X_TX_DBG_LOG_SIZE 1024 359 #define TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1 360 #define TARGET_10X_VOW_CONFIG 0 361 #define TARGET_10X_NUM_MSDU_DESC (1024 + 400) 362 #define TARGET_10X_MAX_FRAG_ENTRIES 0 363 364 /* 10.2 parameters */ 365 #define TARGET_10_2_DMA_BURST_SIZE 0 366 367 /* Target specific defines for WMI-TLV firmware */ 368 #define TARGET_TLV_NUM_VDEVS 4 369 #define TARGET_TLV_NUM_STATIONS 32 370 #define TARGET_TLV_NUM_PEERS 35 371 #define TARGET_TLV_NUM_TDLS_VDEVS 1 372 #define TARGET_TLV_NUM_TIDS ((TARGET_TLV_NUM_PEERS) * 2) 373 #define TARGET_TLV_NUM_MSDU_DESC (1024 + 32) 374 #define TARGET_TLV_NUM_WOW_PATTERNS 22 375 376 /* Diagnostic Window */ 377 #define CE_DIAG_PIPE 7 378 379 #define NUM_TARGET_CE_CONFIG_WLAN ar->hw_values->num_target_ce_config_wlan 380 381 /* Target specific defines for 10.4 firmware */ 382 #define TARGET_10_4_NUM_VDEVS 16 383 #define TARGET_10_4_NUM_STATIONS 32 384 #define TARGET_10_4_NUM_PEERS ((TARGET_10_4_NUM_STATIONS) + \ 385 (TARGET_10_4_NUM_VDEVS)) 386 #define TARGET_10_4_ACTIVE_PEERS 0 387 388 #define TARGET_10_4_NUM_QCACHE_PEERS_MAX 512 389 #define TARGET_10_4_QCACHE_ACTIVE_PEERS 50 390 #define TARGET_10_4_NUM_OFFLOAD_PEERS 0 391 #define TARGET_10_4_NUM_OFFLOAD_REORDER_BUFFS 0 392 #define TARGET_10_4_NUM_PEER_KEYS 2 393 #define TARGET_10_4_TGT_NUM_TIDS ((TARGET_10_4_NUM_PEERS) * 2) 394 #define TARGET_10_4_AST_SKID_LIMIT 32 395 #define TARGET_10_4_TX_CHAIN_MASK (BIT(0) | BIT(1) | \ 396 BIT(2) | BIT(3)) 397 #define TARGET_10_4_RX_CHAIN_MASK (BIT(0) | BIT(1) | \ 398 BIT(2) | BIT(3)) 399 400 /* 100 ms for video, best-effort, and background */ 401 #define TARGET_10_4_RX_TIMEOUT_LO_PRI 100 402 403 /* 40 ms for voice */ 404 #define TARGET_10_4_RX_TIMEOUT_HI_PRI 40 405 406 #define TARGET_10_4_RX_DECAP_MODE ATH10K_HW_TXRX_NATIVE_WIFI 407 #define TARGET_10_4_SCAN_MAX_REQS 4 408 #define TARGET_10_4_BMISS_OFFLOAD_MAX_VDEV 3 409 #define TARGET_10_4_ROAM_OFFLOAD_MAX_VDEV 3 410 #define TARGET_10_4_ROAM_OFFLOAD_MAX_PROFILES 8 411 412 /* Note: mcast to ucast is disabled by default */ 413 #define TARGET_10_4_NUM_MCAST_GROUPS 0 414 #define TARGET_10_4_NUM_MCAST_TABLE_ELEMS 0 415 #define TARGET_10_4_MCAST2UCAST_MODE 0 416 417 #define TARGET_10_4_TX_DBG_LOG_SIZE 1024 418 #define TARGET_10_4_NUM_WDS_ENTRIES 32 419 #define TARGET_10_4_DMA_BURST_SIZE 0 420 #define TARGET_10_4_MAC_AGGR_DELIM 0 421 #define TARGET_10_4_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1 422 #define TARGET_10_4_VOW_CONFIG 0 423 #define TARGET_10_4_GTK_OFFLOAD_MAX_VDEV 3 424 #define TARGET_10_4_NUM_MSDU_DESC (1024 + 400) 425 #define TARGET_10_4_11AC_TX_MAX_FRAGS 2 426 #define TARGET_10_4_MAX_PEER_EXT_STATS 16 427 #define TARGET_10_4_SMART_ANT_CAP 0 428 #define TARGET_10_4_BK_MIN_FREE 0 429 #define TARGET_10_4_BE_MIN_FREE 0 430 #define TARGET_10_4_VI_MIN_FREE 0 431 #define TARGET_10_4_VO_MIN_FREE 0 432 #define TARGET_10_4_RX_BATCH_MODE 1 433 #define TARGET_10_4_THERMAL_THROTTLING_CONFIG 0 434 #define TARGET_10_4_ATF_CONFIG 0 435 #define TARGET_10_4_IPHDR_PAD_CONFIG 1 436 #define TARGET_10_4_QWRAP_CONFIG 0 437 438 /* Number of Copy Engines supported */ 439 #define CE_COUNT ar->hw_values->ce_count 440 441 /* 442 * Granted MSIs are assigned as follows: 443 * Firmware uses the first 444 * Remaining MSIs, if any, are used by Copy Engines 445 * This mapping is known to both Target firmware and Host software. 446 * It may be changed as long as Host and Target are kept in sync. 447 */ 448 /* MSI for firmware (errors, etc.) */ 449 #define MSI_ASSIGN_FW 0 450 451 /* MSIs for Copy Engines */ 452 #define MSI_ASSIGN_CE_INITIAL 1 453 #define MSI_ASSIGN_CE_MAX ar->hw_values->msi_assign_ce_max 454 455 /* as of IP3.7.1 */ 456 #define RTC_STATE_V_ON ar->hw_values->rtc_state_val_on 457 458 #define RTC_STATE_COLD_RESET_MASK ar->regs->rtc_state_cold_reset_mask 459 #define RTC_STATE_V_LSB 0 460 #define RTC_STATE_V_MASK 0x00000007 461 #define RTC_STATE_ADDRESS 0x0000 462 #define PCIE_SOC_WAKE_V_MASK 0x00000001 463 #define PCIE_SOC_WAKE_ADDRESS 0x0004 464 #define PCIE_SOC_WAKE_RESET 0x00000000 465 #define SOC_GLOBAL_RESET_ADDRESS 0x0008 466 467 #define RTC_SOC_BASE_ADDRESS ar->regs->rtc_soc_base_address 468 #define RTC_WMAC_BASE_ADDRESS ar->regs->rtc_wmac_base_address 469 #define MAC_COEX_BASE_ADDRESS 0x00006000 470 #define BT_COEX_BASE_ADDRESS 0x00007000 471 #define SOC_PCIE_BASE_ADDRESS 0x00008000 472 #define SOC_CORE_BASE_ADDRESS ar->regs->soc_core_base_address 473 #define WLAN_UART_BASE_ADDRESS 0x0000c000 474 #define WLAN_SI_BASE_ADDRESS 0x00010000 475 #define WLAN_GPIO_BASE_ADDRESS 0x00014000 476 #define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000 477 #define WLAN_MAC_BASE_ADDRESS 0x00020000 478 #define EFUSE_BASE_ADDRESS 0x00030000 479 #define FPGA_REG_BASE_ADDRESS 0x00039000 480 #define WLAN_UART2_BASE_ADDRESS 0x00054c00 481 #define CE_WRAPPER_BASE_ADDRESS ar->regs->ce_wrapper_base_address 482 #define CE0_BASE_ADDRESS ar->regs->ce0_base_address 483 #define CE1_BASE_ADDRESS ar->regs->ce1_base_address 484 #define CE2_BASE_ADDRESS ar->regs->ce2_base_address 485 #define CE3_BASE_ADDRESS ar->regs->ce3_base_address 486 #define CE4_BASE_ADDRESS ar->regs->ce4_base_address 487 #define CE5_BASE_ADDRESS ar->regs->ce5_base_address 488 #define CE6_BASE_ADDRESS ar->regs->ce6_base_address 489 #define CE7_BASE_ADDRESS ar->regs->ce7_base_address 490 #define DBI_BASE_ADDRESS 0x00060000 491 #define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x0006c000 492 #define PCIE_LOCAL_BASE_ADDRESS ar->regs->pcie_local_base_address 493 494 #define SOC_RESET_CONTROL_ADDRESS 0x00000000 495 #define SOC_RESET_CONTROL_OFFSET 0x00000000 496 #define SOC_RESET_CONTROL_SI0_RST_MASK ar->regs->soc_reset_control_si0_rst_mask 497 #define SOC_RESET_CONTROL_CE_RST_MASK ar->regs->soc_reset_control_ce_rst_mask 498 #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040 499 #define SOC_CPU_CLOCK_OFFSET 0x00000020 500 #define SOC_CPU_CLOCK_STANDARD_LSB 0 501 #define SOC_CPU_CLOCK_STANDARD_MASK 0x00000003 502 #define SOC_CLOCK_CONTROL_OFFSET 0x00000028 503 #define SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001 504 #define SOC_SYSTEM_SLEEP_OFFSET 0x000000c4 505 #define SOC_LPO_CAL_OFFSET 0x000000e0 506 #define SOC_LPO_CAL_ENABLE_LSB 20 507 #define SOC_LPO_CAL_ENABLE_MASK 0x00100000 508 #define SOC_LF_TIMER_CONTROL0_ADDRESS 0x00000050 509 #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004 510 511 #define SOC_CHIP_ID_ADDRESS ar->regs->soc_chip_id_address 512 #define SOC_CHIP_ID_REV_LSB 8 513 #define SOC_CHIP_ID_REV_MASK 0x00000f00 514 515 #define WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000008 516 #define WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000004 517 #define WLAN_SYSTEM_SLEEP_DISABLE_LSB 0 518 #define WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001 519 520 #define WLAN_GPIO_PIN0_ADDRESS 0x00000028 521 #define WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800 522 #define WLAN_GPIO_PIN1_ADDRESS 0x0000002c 523 #define WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800 524 #define WLAN_GPIO_PIN10_ADDRESS 0x00000050 525 #define WLAN_GPIO_PIN11_ADDRESS 0x00000054 526 #define WLAN_GPIO_PIN12_ADDRESS 0x00000058 527 #define WLAN_GPIO_PIN13_ADDRESS 0x0000005c 528 529 #define CLOCK_GPIO_OFFSET 0xffffffff 530 #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0 531 #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0 532 533 #define SI_CONFIG_OFFSET 0x00000000 534 #define SI_CONFIG_BIDIR_OD_DATA_LSB 18 535 #define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000 536 #define SI_CONFIG_I2C_LSB 16 537 #define SI_CONFIG_I2C_MASK 0x00010000 538 #define SI_CONFIG_POS_SAMPLE_LSB 7 539 #define SI_CONFIG_POS_SAMPLE_MASK 0x00000080 540 #define SI_CONFIG_INACTIVE_DATA_LSB 5 541 #define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020 542 #define SI_CONFIG_INACTIVE_CLK_LSB 4 543 #define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010 544 #define SI_CONFIG_DIVIDER_LSB 0 545 #define SI_CONFIG_DIVIDER_MASK 0x0000000f 546 #define SI_CS_OFFSET 0x00000004 547 #define SI_CS_DONE_ERR_MASK 0x00000400 548 #define SI_CS_DONE_INT_MASK 0x00000200 549 #define SI_CS_START_LSB 8 550 #define SI_CS_START_MASK 0x00000100 551 #define SI_CS_RX_CNT_LSB 4 552 #define SI_CS_RX_CNT_MASK 0x000000f0 553 #define SI_CS_TX_CNT_LSB 0 554 #define SI_CS_TX_CNT_MASK 0x0000000f 555 556 #define SI_TX_DATA0_OFFSET 0x00000008 557 #define SI_TX_DATA1_OFFSET 0x0000000c 558 #define SI_RX_DATA0_OFFSET 0x00000010 559 #define SI_RX_DATA1_OFFSET 0x00000014 560 561 #define CORE_CTRL_CPU_INTR_MASK 0x00002000 562 #define CORE_CTRL_PCIE_REG_31_MASK 0x00000800 563 #define CORE_CTRL_ADDRESS 0x0000 564 #define PCIE_INTR_ENABLE_ADDRESS 0x0008 565 #define PCIE_INTR_CAUSE_ADDRESS 0x000c 566 #define PCIE_INTR_CLR_ADDRESS ar->regs->pcie_intr_clr_address 567 #define SCRATCH_3_ADDRESS ar->regs->scratch_3_address 568 #define CPU_INTR_ADDRESS 0x0010 569 570 #define CCNT_TO_MSEC(ar, x) ((x) / ar->hw_params.channel_counters_freq_hz) 571 572 /* Firmware indications to the Host via SCRATCH_3 register. */ 573 #define FW_INDICATOR_ADDRESS ar->regs->fw_indicator_address 574 #define FW_IND_EVENT_PENDING 1 575 #define FW_IND_INITIALIZED 2 576 577 /* HOST_REG interrupt from firmware */ 578 #define PCIE_INTR_FIRMWARE_MASK ar->regs->pcie_intr_fw_mask 579 #define PCIE_INTR_CE_MASK_ALL ar->regs->pcie_intr_ce_mask_all 580 581 #define DRAM_BASE_ADDRESS 0x00400000 582 583 #define PCIE_BAR_REG_ADDRESS 0x40030 584 585 #define MISSING 0 586 587 #define SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET 588 #define WLAN_SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET 589 #define WLAN_RESET_CONTROL_OFFSET SOC_RESET_CONTROL_OFFSET 590 #define CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_OFFSET 591 #define CLOCK_CONTROL_SI0_CLK_MASK SOC_CLOCK_CONTROL_SI0_CLK_MASK 592 #define RESET_CONTROL_MBOX_RST_MASK MISSING 593 #define RESET_CONTROL_SI0_RST_MASK SOC_RESET_CONTROL_SI0_RST_MASK 594 #define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS 595 #define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_ADDRESS 596 #define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_ADDRESS 597 #define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK 598 #define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK 599 #define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS 600 #define SCRATCH_BASE_ADDRESS SOC_CORE_BASE_ADDRESS 601 #define LOCAL_SCRATCH_OFFSET 0x18 602 #define CPU_CLOCK_OFFSET SOC_CPU_CLOCK_OFFSET 603 #define LPO_CAL_OFFSET SOC_LPO_CAL_OFFSET 604 #define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_ADDRESS 605 #define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_ADDRESS 606 #define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_ADDRESS 607 #define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_ADDRESS 608 #define CPU_CLOCK_STANDARD_LSB SOC_CPU_CLOCK_STANDARD_LSB 609 #define CPU_CLOCK_STANDARD_MASK SOC_CPU_CLOCK_STANDARD_MASK 610 #define LPO_CAL_ENABLE_LSB SOC_LPO_CAL_ENABLE_LSB 611 #define LPO_CAL_ENABLE_MASK SOC_LPO_CAL_ENABLE_MASK 612 #define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS 613 #define MBOX_BASE_ADDRESS MISSING 614 #define INT_STATUS_ENABLE_ERROR_LSB MISSING 615 #define INT_STATUS_ENABLE_ERROR_MASK MISSING 616 #define INT_STATUS_ENABLE_CPU_LSB MISSING 617 #define INT_STATUS_ENABLE_CPU_MASK MISSING 618 #define INT_STATUS_ENABLE_COUNTER_LSB MISSING 619 #define INT_STATUS_ENABLE_COUNTER_MASK MISSING 620 #define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING 621 #define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING 622 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING 623 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING 624 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING 625 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING 626 #define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING 627 #define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING 628 #define INT_STATUS_ENABLE_ADDRESS MISSING 629 #define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING 630 #define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING 631 #define HOST_INT_STATUS_ADDRESS MISSING 632 #define CPU_INT_STATUS_ADDRESS MISSING 633 #define ERROR_INT_STATUS_ADDRESS MISSING 634 #define ERROR_INT_STATUS_WAKEUP_MASK MISSING 635 #define ERROR_INT_STATUS_WAKEUP_LSB MISSING 636 #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING 637 #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING 638 #define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING 639 #define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING 640 #define COUNT_DEC_ADDRESS MISSING 641 #define HOST_INT_STATUS_CPU_MASK MISSING 642 #define HOST_INT_STATUS_CPU_LSB MISSING 643 #define HOST_INT_STATUS_ERROR_MASK MISSING 644 #define HOST_INT_STATUS_ERROR_LSB MISSING 645 #define HOST_INT_STATUS_COUNTER_MASK MISSING 646 #define HOST_INT_STATUS_COUNTER_LSB MISSING 647 #define RX_LOOKAHEAD_VALID_ADDRESS MISSING 648 #define WINDOW_DATA_ADDRESS MISSING 649 #define WINDOW_READ_ADDR_ADDRESS MISSING 650 #define WINDOW_WRITE_ADDR_ADDRESS MISSING 651 652 #define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB) 653 654 #endif /* _HW_H_ */ 655