1 /* 2 * Copyright (c) 2005-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef _HW_H_ 19 #define _HW_H_ 20 21 #include "targaddrs.h" 22 23 #define ATH10K_FW_DIR "ath10k" 24 25 #define QCA988X_2_0_DEVICE_ID (0x003c) 26 #define QCA6164_2_1_DEVICE_ID (0x0041) 27 #define QCA6174_2_1_DEVICE_ID (0x003e) 28 #define QCA99X0_2_0_DEVICE_ID (0x0040) 29 #define QCA9888_2_0_DEVICE_ID (0x0056) 30 #define QCA9984_1_0_DEVICE_ID (0x0046) 31 #define QCA9377_1_0_DEVICE_ID (0x0042) 32 #define QCA9887_1_0_DEVICE_ID (0x0050) 33 34 /* QCA988X 1.0 definitions (unsupported) */ 35 #define QCA988X_HW_1_0_CHIP_ID_REV 0x0 36 37 /* QCA988X 2.0 definitions */ 38 #define QCA988X_HW_2_0_VERSION 0x4100016c 39 #define QCA988X_HW_2_0_CHIP_ID_REV 0x2 40 #define QCA988X_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA988X/hw2.0" 41 #define QCA988X_HW_2_0_BOARD_DATA_FILE "board.bin" 42 #define QCA988X_HW_2_0_PATCH_LOAD_ADDR 0x1234 43 44 /* QCA9887 1.0 definitions */ 45 #define QCA9887_HW_1_0_VERSION 0x4100016d 46 #define QCA9887_HW_1_0_CHIP_ID_REV 0 47 #define QCA9887_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9887/hw1.0" 48 #define QCA9887_HW_1_0_BOARD_DATA_FILE "board.bin" 49 #define QCA9887_HW_1_0_PATCH_LOAD_ADDR 0x1234 50 51 /* QCA6174 target BMI version signatures */ 52 #define QCA6174_HW_1_0_VERSION 0x05000000 53 #define QCA6174_HW_1_1_VERSION 0x05000001 54 #define QCA6174_HW_1_3_VERSION 0x05000003 55 #define QCA6174_HW_2_1_VERSION 0x05010000 56 #define QCA6174_HW_3_0_VERSION 0x05020000 57 #define QCA6174_HW_3_2_VERSION 0x05030000 58 59 /* QCA9377 target BMI version signatures */ 60 #define QCA9377_HW_1_0_DEV_VERSION 0x05020000 61 #define QCA9377_HW_1_1_DEV_VERSION 0x05020001 62 63 enum qca6174_pci_rev { 64 QCA6174_PCI_REV_1_1 = 0x11, 65 QCA6174_PCI_REV_1_3 = 0x13, 66 QCA6174_PCI_REV_2_0 = 0x20, 67 QCA6174_PCI_REV_3_0 = 0x30, 68 }; 69 70 enum qca6174_chip_id_rev { 71 QCA6174_HW_1_0_CHIP_ID_REV = 0, 72 QCA6174_HW_1_1_CHIP_ID_REV = 1, 73 QCA6174_HW_1_3_CHIP_ID_REV = 2, 74 QCA6174_HW_2_1_CHIP_ID_REV = 4, 75 QCA6174_HW_2_2_CHIP_ID_REV = 5, 76 QCA6174_HW_3_0_CHIP_ID_REV = 8, 77 QCA6174_HW_3_1_CHIP_ID_REV = 9, 78 QCA6174_HW_3_2_CHIP_ID_REV = 10, 79 }; 80 81 enum qca9377_chip_id_rev { 82 QCA9377_HW_1_0_CHIP_ID_REV = 0x0, 83 QCA9377_HW_1_1_CHIP_ID_REV = 0x1, 84 }; 85 86 #define QCA6174_HW_2_1_FW_DIR "ath10k/QCA6174/hw2.1" 87 #define QCA6174_HW_2_1_BOARD_DATA_FILE "board.bin" 88 #define QCA6174_HW_2_1_PATCH_LOAD_ADDR 0x1234 89 90 #define QCA6174_HW_3_0_FW_DIR "ath10k/QCA6174/hw3.0" 91 #define QCA6174_HW_3_0_BOARD_DATA_FILE "board.bin" 92 #define QCA6174_HW_3_0_PATCH_LOAD_ADDR 0x1234 93 94 /* QCA99X0 1.0 definitions (unsupported) */ 95 #define QCA99X0_HW_1_0_CHIP_ID_REV 0x0 96 97 /* QCA99X0 2.0 definitions */ 98 #define QCA99X0_HW_2_0_DEV_VERSION 0x01000000 99 #define QCA99X0_HW_2_0_CHIP_ID_REV 0x1 100 #define QCA99X0_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA99X0/hw2.0" 101 #define QCA99X0_HW_2_0_BOARD_DATA_FILE "board.bin" 102 #define QCA99X0_HW_2_0_PATCH_LOAD_ADDR 0x1234 103 104 /* QCA9984 1.0 defines */ 105 #define QCA9984_HW_1_0_DEV_VERSION 0x1000000 106 #define QCA9984_HW_DEV_TYPE 0xa 107 #define QCA9984_HW_1_0_CHIP_ID_REV 0x0 108 #define QCA9984_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9984/hw1.0" 109 #define QCA9984_HW_1_0_BOARD_DATA_FILE "board.bin" 110 #define QCA9984_HW_1_0_PATCH_LOAD_ADDR 0x1234 111 112 /* QCA9888 2.0 defines */ 113 #define QCA9888_HW_2_0_DEV_VERSION 0x1000000 114 #define QCA9888_HW_DEV_TYPE 0xc 115 #define QCA9888_HW_2_0_CHIP_ID_REV 0x0 116 #define QCA9888_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA9888/hw2.0" 117 #define QCA9888_HW_2_0_BOARD_DATA_FILE "board.bin" 118 #define QCA9888_HW_2_0_PATCH_LOAD_ADDR 0x1234 119 120 /* QCA9377 1.0 definitions */ 121 #define QCA9377_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9377/hw1.0" 122 #define QCA9377_HW_1_0_BOARD_DATA_FILE "board.bin" 123 #define QCA9377_HW_1_0_PATCH_LOAD_ADDR 0x1234 124 125 /* QCA4019 1.0 definitions */ 126 #define QCA4019_HW_1_0_DEV_VERSION 0x01000000 127 #define QCA4019_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA4019/hw1.0" 128 #define QCA4019_HW_1_0_BOARD_DATA_FILE "board.bin" 129 #define QCA4019_HW_1_0_PATCH_LOAD_ADDR 0x1234 130 131 /* WCN3990 1.0 definitions */ 132 #define WCN3990_HW_1_0_DEV_VERSION ATH10K_HW_WCN3990 133 #define WCN3990_HW_1_0_FW_DIR ATH10K_FW_DIR "/WCN3990/hw3.0" 134 135 #define ATH10K_FW_FILE_BASE "firmware" 136 #define ATH10K_FW_API_MAX 6 137 #define ATH10K_FW_API_MIN 2 138 139 #define ATH10K_FW_API2_FILE "firmware-2.bin" 140 #define ATH10K_FW_API3_FILE "firmware-3.bin" 141 142 /* added support for ATH10K_FW_IE_WMI_OP_VERSION */ 143 #define ATH10K_FW_API4_FILE "firmware-4.bin" 144 145 /* HTT id conflict fix for management frames over HTT */ 146 #define ATH10K_FW_API5_FILE "firmware-5.bin" 147 148 /* the firmware-6.bin blob */ 149 #define ATH10K_FW_API6_FILE "firmware-6.bin" 150 151 #define ATH10K_FW_UTF_FILE "utf.bin" 152 #define ATH10K_FW_UTF_API2_FILE "utf-2.bin" 153 154 /* includes also the null byte */ 155 #define ATH10K_FIRMWARE_MAGIC "QCA-ATH10K" 156 #define ATH10K_BOARD_MAGIC "QCA-ATH10K-BOARD" 157 158 #define ATH10K_BOARD_API2_FILE "board-2.bin" 159 160 #define REG_DUMP_COUNT_QCA988X 60 161 162 struct ath10k_fw_ie { 163 __le32 id; 164 __le32 len; 165 u8 data[0]; 166 }; 167 168 enum ath10k_fw_ie_type { 169 ATH10K_FW_IE_FW_VERSION = 0, 170 ATH10K_FW_IE_TIMESTAMP = 1, 171 ATH10K_FW_IE_FEATURES = 2, 172 ATH10K_FW_IE_FW_IMAGE = 3, 173 ATH10K_FW_IE_OTP_IMAGE = 4, 174 175 /* WMI "operations" interface version, 32 bit value. Supported from 176 * FW API 4 and above. 177 */ 178 ATH10K_FW_IE_WMI_OP_VERSION = 5, 179 180 /* HTT "operations" interface version, 32 bit value. Supported from 181 * FW API 5 and above. 182 */ 183 ATH10K_FW_IE_HTT_OP_VERSION = 6, 184 185 /* Code swap image for firmware binary */ 186 ATH10K_FW_IE_FW_CODE_SWAP_IMAGE = 7, 187 }; 188 189 enum ath10k_fw_wmi_op_version { 190 ATH10K_FW_WMI_OP_VERSION_UNSET = 0, 191 192 ATH10K_FW_WMI_OP_VERSION_MAIN = 1, 193 ATH10K_FW_WMI_OP_VERSION_10_1 = 2, 194 ATH10K_FW_WMI_OP_VERSION_10_2 = 3, 195 ATH10K_FW_WMI_OP_VERSION_TLV = 4, 196 ATH10K_FW_WMI_OP_VERSION_10_2_4 = 5, 197 ATH10K_FW_WMI_OP_VERSION_10_4 = 6, 198 199 /* keep last */ 200 ATH10K_FW_WMI_OP_VERSION_MAX, 201 }; 202 203 enum ath10k_fw_htt_op_version { 204 ATH10K_FW_HTT_OP_VERSION_UNSET = 0, 205 206 ATH10K_FW_HTT_OP_VERSION_MAIN = 1, 207 208 /* also used in 10.2 and 10.2.4 branches */ 209 ATH10K_FW_HTT_OP_VERSION_10_1 = 2, 210 211 ATH10K_FW_HTT_OP_VERSION_TLV = 3, 212 213 ATH10K_FW_HTT_OP_VERSION_10_4 = 4, 214 215 /* keep last */ 216 ATH10K_FW_HTT_OP_VERSION_MAX, 217 }; 218 219 enum ath10k_bd_ie_type { 220 /* contains sub IEs of enum ath10k_bd_ie_board_type */ 221 ATH10K_BD_IE_BOARD = 0, 222 }; 223 224 enum ath10k_bd_ie_board_type { 225 ATH10K_BD_IE_BOARD_NAME = 0, 226 ATH10K_BD_IE_BOARD_DATA = 1, 227 }; 228 229 enum ath10k_hw_rev { 230 ATH10K_HW_QCA988X, 231 ATH10K_HW_QCA6174, 232 ATH10K_HW_QCA99X0, 233 ATH10K_HW_QCA9888, 234 ATH10K_HW_QCA9984, 235 ATH10K_HW_QCA9377, 236 ATH10K_HW_QCA4019, 237 ATH10K_HW_QCA9887, 238 ATH10K_HW_WCN3990, 239 }; 240 241 struct ath10k_hw_regs { 242 u32 rtc_soc_base_address; 243 u32 rtc_wmac_base_address; 244 u32 soc_core_base_address; 245 u32 wlan_mac_base_address; 246 u32 ce_wrapper_base_address; 247 u32 ce0_base_address; 248 u32 ce1_base_address; 249 u32 ce2_base_address; 250 u32 ce3_base_address; 251 u32 ce4_base_address; 252 u32 ce5_base_address; 253 u32 ce6_base_address; 254 u32 ce7_base_address; 255 u32 ce8_base_address; 256 u32 ce9_base_address; 257 u32 ce10_base_address; 258 u32 ce11_base_address; 259 u32 soc_reset_control_si0_rst_mask; 260 u32 soc_reset_control_ce_rst_mask; 261 u32 soc_chip_id_address; 262 u32 scratch_3_address; 263 u32 fw_indicator_address; 264 u32 pcie_local_base_address; 265 u32 ce_wrap_intr_sum_host_msi_lsb; 266 u32 ce_wrap_intr_sum_host_msi_mask; 267 u32 pcie_intr_fw_mask; 268 u32 pcie_intr_ce_mask_all; 269 u32 pcie_intr_clr_address; 270 u32 cpu_pll_init_address; 271 u32 cpu_speed_address; 272 u32 core_clk_div_address; 273 }; 274 275 extern const struct ath10k_hw_regs qca988x_regs; 276 extern const struct ath10k_hw_regs qca6174_regs; 277 extern const struct ath10k_hw_regs qca99x0_regs; 278 extern const struct ath10k_hw_regs qca4019_regs; 279 extern const struct ath10k_hw_regs wcn3990_regs; 280 281 struct ath10k_hw_ce_regs_addr_map { 282 u32 msb; 283 u32 lsb; 284 u32 mask; 285 }; 286 287 struct ath10k_hw_ce_ctrl1 { 288 u32 addr; 289 u32 hw_mask; 290 u32 sw_mask; 291 u32 hw_wr_mask; 292 u32 sw_wr_mask; 293 u32 reset_mask; 294 u32 reset; 295 struct ath10k_hw_ce_regs_addr_map *src_ring; 296 struct ath10k_hw_ce_regs_addr_map *dst_ring; 297 struct ath10k_hw_ce_regs_addr_map *dmax; }; 298 299 struct ath10k_hw_ce_cmd_halt { 300 u32 status_reset; 301 u32 msb; 302 u32 mask; 303 struct ath10k_hw_ce_regs_addr_map *status; }; 304 305 struct ath10k_hw_ce_host_ie { 306 u32 copy_complete_reset; 307 struct ath10k_hw_ce_regs_addr_map *copy_complete; }; 308 309 struct ath10k_hw_ce_host_wm_regs { 310 u32 dstr_lmask; 311 u32 dstr_hmask; 312 u32 srcr_lmask; 313 u32 srcr_hmask; 314 u32 cc_mask; 315 u32 wm_mask; 316 u32 addr; 317 }; 318 319 struct ath10k_hw_ce_misc_regs { 320 u32 axi_err; 321 u32 dstr_add_err; 322 u32 srcr_len_err; 323 u32 dstr_mlen_vio; 324 u32 dstr_overflow; 325 u32 srcr_overflow; 326 u32 err_mask; 327 u32 addr; 328 }; 329 330 struct ath10k_hw_ce_dst_src_wm_regs { 331 u32 addr; 332 u32 low_rst; 333 u32 high_rst; 334 struct ath10k_hw_ce_regs_addr_map *wm_low; 335 struct ath10k_hw_ce_regs_addr_map *wm_high; }; 336 337 struct ath10k_hw_ce_regs { 338 u32 sr_base_addr; 339 u32 sr_size_addr; 340 u32 dr_base_addr; 341 u32 dr_size_addr; 342 u32 ce_cmd_addr; 343 u32 misc_ie_addr; 344 u32 sr_wr_index_addr; 345 u32 dst_wr_index_addr; 346 u32 current_srri_addr; 347 u32 current_drri_addr; 348 u32 ddr_addr_for_rri_low; 349 u32 ddr_addr_for_rri_high; 350 u32 ce_rri_low; 351 u32 ce_rri_high; 352 u32 host_ie_addr; 353 struct ath10k_hw_ce_host_wm_regs *wm_regs; 354 struct ath10k_hw_ce_misc_regs *misc_regs; 355 struct ath10k_hw_ce_ctrl1 *ctrl1_regs; 356 struct ath10k_hw_ce_cmd_halt *cmd_halt; 357 struct ath10k_hw_ce_host_ie *host_ie; 358 struct ath10k_hw_ce_dst_src_wm_regs *wm_srcr; 359 struct ath10k_hw_ce_dst_src_wm_regs *wm_dstr; }; 360 361 struct ath10k_hw_values { 362 u32 rtc_state_val_on; 363 u8 ce_count; 364 u8 msi_assign_ce_max; 365 u8 num_target_ce_config_wlan; 366 u16 ce_desc_meta_data_mask; 367 u8 ce_desc_meta_data_lsb; 368 }; 369 370 extern const struct ath10k_hw_values qca988x_values; 371 extern const struct ath10k_hw_values qca6174_values; 372 extern const struct ath10k_hw_values qca99x0_values; 373 extern const struct ath10k_hw_values qca9888_values; 374 extern const struct ath10k_hw_values qca4019_values; 375 extern const struct ath10k_hw_values wcn3990_values; 376 extern const struct ath10k_hw_ce_regs wcn3990_ce_regs; 377 extern const struct ath10k_hw_ce_regs qcax_ce_regs; 378 379 void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey, 380 u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev); 381 382 #define QCA_REV_988X(ar) ((ar)->hw_rev == ATH10K_HW_QCA988X) 383 #define QCA_REV_9887(ar) ((ar)->hw_rev == ATH10K_HW_QCA9887) 384 #define QCA_REV_6174(ar) ((ar)->hw_rev == ATH10K_HW_QCA6174) 385 #define QCA_REV_99X0(ar) ((ar)->hw_rev == ATH10K_HW_QCA99X0) 386 #define QCA_REV_9888(ar) ((ar)->hw_rev == ATH10K_HW_QCA9888) 387 #define QCA_REV_9984(ar) ((ar)->hw_rev == ATH10K_HW_QCA9984) 388 #define QCA_REV_9377(ar) ((ar)->hw_rev == ATH10K_HW_QCA9377) 389 #define QCA_REV_40XX(ar) ((ar)->hw_rev == ATH10K_HW_QCA4019) 390 #define QCA_REV_WCN3990(ar) ((ar)->hw_rev == ATH10K_HW_WCN3990) 391 392 /* Known peculiarities: 393 * - raw appears in nwifi decap, raw and nwifi appear in ethernet decap 394 * - raw have FCS, nwifi doesn't 395 * - ethernet frames have 802.11 header decapped and parts (base hdr, cipher 396 * param, llc/snap) are aligned to 4byte boundaries each 397 */ 398 enum ath10k_hw_txrx_mode { 399 ATH10K_HW_TXRX_RAW = 0, 400 401 /* Native Wifi decap mode is used to align IP frames to 4-byte 402 * boundaries and avoid a very expensive re-alignment in mac80211. 403 */ 404 ATH10K_HW_TXRX_NATIVE_WIFI = 1, 405 ATH10K_HW_TXRX_ETHERNET = 2, 406 407 /* Valid for HTT >= 3.0. Used for management frames in TX_FRM. */ 408 ATH10K_HW_TXRX_MGMT = 3, 409 }; 410 411 enum ath10k_mcast2ucast_mode { 412 ATH10K_MCAST2UCAST_DISABLED = 0, 413 ATH10K_MCAST2UCAST_ENABLED = 1, 414 }; 415 416 enum ath10k_hw_rate_ofdm { 417 ATH10K_HW_RATE_OFDM_48M = 0, 418 ATH10K_HW_RATE_OFDM_24M, 419 ATH10K_HW_RATE_OFDM_12M, 420 ATH10K_HW_RATE_OFDM_6M, 421 ATH10K_HW_RATE_OFDM_54M, 422 ATH10K_HW_RATE_OFDM_36M, 423 ATH10K_HW_RATE_OFDM_18M, 424 ATH10K_HW_RATE_OFDM_9M, 425 }; 426 427 enum ath10k_hw_rate_cck { 428 ATH10K_HW_RATE_CCK_LP_11M = 0, 429 ATH10K_HW_RATE_CCK_LP_5_5M, 430 ATH10K_HW_RATE_CCK_LP_2M, 431 ATH10K_HW_RATE_CCK_LP_1M, 432 ATH10K_HW_RATE_CCK_SP_11M, 433 ATH10K_HW_RATE_CCK_SP_5_5M, 434 ATH10K_HW_RATE_CCK_SP_2M, 435 }; 436 437 enum ath10k_hw_rate_rev2_cck { 438 ATH10K_HW_RATE_REV2_CCK_LP_1M = 1, 439 ATH10K_HW_RATE_REV2_CCK_LP_2M, 440 ATH10K_HW_RATE_REV2_CCK_LP_5_5M, 441 ATH10K_HW_RATE_REV2_CCK_LP_11M, 442 ATH10K_HW_RATE_REV2_CCK_SP_2M, 443 ATH10K_HW_RATE_REV2_CCK_SP_5_5M, 444 ATH10K_HW_RATE_REV2_CCK_SP_11M, 445 }; 446 447 enum ath10k_hw_cc_wraparound_type { 448 ATH10K_HW_CC_WRAP_DISABLED = 0, 449 450 /* This type is when the HW chip has a quirky Cycle Counter 451 * wraparound which resets to 0x7fffffff instead of 0. All 452 * other CC related counters (e.g. Rx Clear Count) are divided 453 * by 2 so they never wraparound themselves. 454 */ 455 ATH10K_HW_CC_WRAP_SHIFTED_ALL = 1, 456 457 /* Each hw counter wrapsaround independently. When the 458 * counter overflows the repestive counter is right shifted 459 * by 1, i.e reset to 0x7fffffff, and other counters will be 460 * running unaffected. In this type of wraparound, it should 461 * be possible to report accurate Rx busy time unlike the 462 * first type. 463 */ 464 ATH10K_HW_CC_WRAP_SHIFTED_EACH = 2, 465 }; 466 467 enum ath10k_hw_refclk_speed { 468 ATH10K_HW_REFCLK_UNKNOWN = -1, 469 ATH10K_HW_REFCLK_48_MHZ = 0, 470 ATH10K_HW_REFCLK_19_2_MHZ = 1, 471 ATH10K_HW_REFCLK_24_MHZ = 2, 472 ATH10K_HW_REFCLK_26_MHZ = 3, 473 ATH10K_HW_REFCLK_37_4_MHZ = 4, 474 ATH10K_HW_REFCLK_38_4_MHZ = 5, 475 ATH10K_HW_REFCLK_40_MHZ = 6, 476 ATH10K_HW_REFCLK_52_MHZ = 7, 477 478 /* must be the last one */ 479 ATH10K_HW_REFCLK_COUNT, 480 }; 481 482 struct ath10k_hw_clk_params { 483 u32 refclk; 484 u32 div; 485 u32 rnfrac; 486 u32 settle_time; 487 u32 refdiv; 488 u32 outdiv; 489 }; 490 491 struct ath10k_hw_params { 492 u32 id; 493 u16 dev_id; 494 const char *name; 495 u32 patch_load_addr; 496 int uart_pin; 497 u32 otp_exe_param; 498 499 /* Type of hw cycle counter wraparound logic, for more info 500 * refer enum ath10k_hw_cc_wraparound_type. 501 */ 502 enum ath10k_hw_cc_wraparound_type cc_wraparound_type; 503 504 /* Some of chip expects fragment descriptor to be continuous 505 * memory for any TX operation. Set continuous_frag_desc flag 506 * for the hardware which have such requirement. 507 */ 508 bool continuous_frag_desc; 509 510 /* CCK hardware rate table mapping for the newer chipsets 511 * like QCA99X0, QCA4019 got revised. The CCK h/w rate values 512 * are in a proper order with respect to the rate/preamble 513 */ 514 bool cck_rate_map_rev2; 515 516 u32 channel_counters_freq_hz; 517 518 /* Mgmt tx descriptors threshold for limiting probe response 519 * frames. 520 */ 521 u32 max_probe_resp_desc_thres; 522 523 u32 tx_chain_mask; 524 u32 rx_chain_mask; 525 u32 max_spatial_stream; 526 u32 cal_data_len; 527 528 struct ath10k_hw_params_fw { 529 const char *dir; 530 const char *board; 531 size_t board_size; 532 size_t board_ext_size; 533 } fw; 534 535 /* qca99x0 family chips deliver broadcast/multicast management 536 * frames encrypted and expect software do decryption. 537 */ 538 bool sw_decrypt_mcast_mgmt; 539 540 const struct ath10k_hw_ops *hw_ops; 541 542 /* Number of bytes used for alignment in rx_hdr_status of rx desc. */ 543 int decap_align_bytes; 544 545 /* hw specific clock control parameters */ 546 const struct ath10k_hw_clk_params *hw_clk; 547 int target_cpu_freq; 548 549 /* Number of bytes to be discarded for each FFT sample */ 550 int spectral_bin_discard; 551 552 /* The board may have a restricted NSS for 160 or 80+80 vs what it 553 * can do for 80Mhz. 554 */ 555 int vht160_mcs_rx_highest; 556 int vht160_mcs_tx_highest; 557 558 /* Number of ciphers supported (i.e First N) in cipher_suites array */ 559 int n_cipher_suites; 560 561 u32 num_peers; 562 u32 ast_skid_limit; 563 u32 num_wds_entries; 564 }; 565 566 struct htt_rx_desc; 567 568 /* Defines needed for Rx descriptor abstraction */ 569 struct ath10k_hw_ops { 570 int (*rx_desc_get_l3_pad_bytes)(struct htt_rx_desc *rxd); 571 void (*set_coverage_class)(struct ath10k *ar, s16 value); 572 int (*enable_pll_clk)(struct ath10k *ar); 573 }; 574 575 extern const struct ath10k_hw_ops qca988x_ops; 576 extern const struct ath10k_hw_ops qca99x0_ops; 577 extern const struct ath10k_hw_ops qca6174_ops; 578 extern const struct ath10k_hw_ops wcn3990_ops; 579 580 extern const struct ath10k_hw_clk_params qca6174_clk[]; 581 582 static inline int 583 ath10k_rx_desc_get_l3_pad_bytes(struct ath10k_hw_params *hw, 584 struct htt_rx_desc *rxd) 585 { 586 if (hw->hw_ops->rx_desc_get_l3_pad_bytes) 587 return hw->hw_ops->rx_desc_get_l3_pad_bytes(rxd); 588 return 0; 589 } 590 591 /* Target specific defines for MAIN firmware */ 592 #define TARGET_NUM_VDEVS 8 593 #define TARGET_NUM_PEER_AST 2 594 #define TARGET_NUM_WDS_ENTRIES 32 595 #define TARGET_DMA_BURST_SIZE 0 596 #define TARGET_MAC_AGGR_DELIM 0 597 #define TARGET_AST_SKID_LIMIT 16 598 #define TARGET_NUM_STATIONS 16 599 #define TARGET_NUM_PEERS ((TARGET_NUM_STATIONS) + \ 600 (TARGET_NUM_VDEVS)) 601 #define TARGET_NUM_OFFLOAD_PEERS 0 602 #define TARGET_NUM_OFFLOAD_REORDER_BUFS 0 603 #define TARGET_NUM_PEER_KEYS 2 604 #define TARGET_NUM_TIDS ((TARGET_NUM_PEERS) * 2) 605 #define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 606 #define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 607 #define TARGET_RX_TIMEOUT_LO_PRI 100 608 #define TARGET_RX_TIMEOUT_HI_PRI 40 609 610 #define TARGET_SCAN_MAX_PENDING_REQS 4 611 #define TARGET_BMISS_OFFLOAD_MAX_VDEV 3 612 #define TARGET_ROAM_OFFLOAD_MAX_VDEV 3 613 #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8 614 #define TARGET_GTK_OFFLOAD_MAX_VDEV 3 615 #define TARGET_NUM_MCAST_GROUPS 0 616 #define TARGET_NUM_MCAST_TABLE_ELEMS 0 617 #define TARGET_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED 618 #define TARGET_TX_DBG_LOG_SIZE 1024 619 #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0 620 #define TARGET_VOW_CONFIG 0 621 #define TARGET_NUM_MSDU_DESC (1024 + 400) 622 #define TARGET_MAX_FRAG_ENTRIES 0 623 624 /* Target specific defines for 10.X firmware */ 625 #define TARGET_10X_NUM_VDEVS 16 626 #define TARGET_10X_NUM_PEER_AST 2 627 #define TARGET_10X_NUM_WDS_ENTRIES 32 628 #define TARGET_10X_DMA_BURST_SIZE 0 629 #define TARGET_10X_MAC_AGGR_DELIM 0 630 #define TARGET_10X_AST_SKID_LIMIT 128 631 #define TARGET_10X_NUM_STATIONS 128 632 #define TARGET_10X_TX_STATS_NUM_STATIONS 118 633 #define TARGET_10X_NUM_PEERS ((TARGET_10X_NUM_STATIONS) + \ 634 (TARGET_10X_NUM_VDEVS)) 635 #define TARGET_10X_TX_STATS_NUM_PEERS ((TARGET_10X_TX_STATS_NUM_STATIONS) + \ 636 (TARGET_10X_NUM_VDEVS)) 637 #define TARGET_10X_NUM_OFFLOAD_PEERS 0 638 #define TARGET_10X_NUM_OFFLOAD_REORDER_BUFS 0 639 #define TARGET_10X_NUM_PEER_KEYS 2 640 #define TARGET_10X_NUM_TIDS_MAX 256 641 #define TARGET_10X_NUM_TIDS min((TARGET_10X_NUM_TIDS_MAX), \ 642 (TARGET_10X_NUM_PEERS) * 2) 643 #define TARGET_10X_TX_STATS_NUM_TIDS min((TARGET_10X_NUM_TIDS_MAX), \ 644 (TARGET_10X_TX_STATS_NUM_PEERS) * 2) 645 #define TARGET_10X_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 646 #define TARGET_10X_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 647 #define TARGET_10X_RX_TIMEOUT_LO_PRI 100 648 #define TARGET_10X_RX_TIMEOUT_HI_PRI 40 649 #define TARGET_10X_SCAN_MAX_PENDING_REQS 4 650 #define TARGET_10X_BMISS_OFFLOAD_MAX_VDEV 2 651 #define TARGET_10X_ROAM_OFFLOAD_MAX_VDEV 2 652 #define TARGET_10X_ROAM_OFFLOAD_MAX_AP_PROFILES 8 653 #define TARGET_10X_GTK_OFFLOAD_MAX_VDEV 3 654 #define TARGET_10X_NUM_MCAST_GROUPS 0 655 #define TARGET_10X_NUM_MCAST_TABLE_ELEMS 0 656 #define TARGET_10X_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED 657 #define TARGET_10X_TX_DBG_LOG_SIZE 1024 658 #define TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1 659 #define TARGET_10X_VOW_CONFIG 0 660 #define TARGET_10X_NUM_MSDU_DESC (1024 + 400) 661 #define TARGET_10X_MAX_FRAG_ENTRIES 0 662 663 /* 10.2 parameters */ 664 #define TARGET_10_2_DMA_BURST_SIZE 0 665 666 /* Target specific defines for WMI-TLV firmware */ 667 #define TARGET_TLV_NUM_VDEVS 4 668 #define TARGET_TLV_NUM_STATIONS 32 669 #define TARGET_TLV_NUM_PEERS 33 670 #define TARGET_TLV_NUM_TDLS_VDEVS 1 671 #define TARGET_TLV_NUM_TIDS ((TARGET_TLV_NUM_PEERS) * 2) 672 #define TARGET_TLV_NUM_MSDU_DESC (1024 + 32) 673 #define TARGET_TLV_NUM_WOW_PATTERNS 22 674 675 /* Target specific defines for WMI-HL-1.0 firmware */ 676 #define TARGET_HL_10_TLV_NUM_PEERS 14 677 #define TARGET_HL_10_TLV_AST_SKID_LIMIT 6 678 #define TARGET_HL_10_TLV_NUM_WDS_ENTRIES 2 679 680 /* Diagnostic Window */ 681 #define CE_DIAG_PIPE 7 682 683 #define NUM_TARGET_CE_CONFIG_WLAN ar->hw_values->num_target_ce_config_wlan 684 685 /* Target specific defines for 10.4 firmware */ 686 #define TARGET_10_4_NUM_VDEVS 16 687 #define TARGET_10_4_NUM_STATIONS 32 688 #define TARGET_10_4_NUM_PEERS ((TARGET_10_4_NUM_STATIONS) + \ 689 (TARGET_10_4_NUM_VDEVS)) 690 #define TARGET_10_4_ACTIVE_PEERS 0 691 692 #define TARGET_10_4_NUM_QCACHE_PEERS_MAX 512 693 #define TARGET_10_4_QCACHE_ACTIVE_PEERS 50 694 #define TARGET_10_4_QCACHE_ACTIVE_PEERS_PFC 35 695 #define TARGET_10_4_NUM_OFFLOAD_PEERS 0 696 #define TARGET_10_4_NUM_OFFLOAD_REORDER_BUFFS 0 697 #define TARGET_10_4_NUM_PEER_KEYS 2 698 #define TARGET_10_4_TGT_NUM_TIDS ((TARGET_10_4_NUM_PEERS) * 2) 699 #define TARGET_10_4_NUM_MSDU_DESC (1024 + 400) 700 #define TARGET_10_4_NUM_MSDU_DESC_PFC 2500 701 #define TARGET_10_4_AST_SKID_LIMIT 32 702 703 /* 100 ms for video, best-effort, and background */ 704 #define TARGET_10_4_RX_TIMEOUT_LO_PRI 100 705 706 /* 40 ms for voice */ 707 #define TARGET_10_4_RX_TIMEOUT_HI_PRI 40 708 709 #define TARGET_10_4_RX_DECAP_MODE ATH10K_HW_TXRX_NATIVE_WIFI 710 #define TARGET_10_4_SCAN_MAX_REQS 4 711 #define TARGET_10_4_BMISS_OFFLOAD_MAX_VDEV 3 712 #define TARGET_10_4_ROAM_OFFLOAD_MAX_VDEV 3 713 #define TARGET_10_4_ROAM_OFFLOAD_MAX_PROFILES 8 714 715 /* Note: mcast to ucast is disabled by default */ 716 #define TARGET_10_4_NUM_MCAST_GROUPS 0 717 #define TARGET_10_4_NUM_MCAST_TABLE_ELEMS 0 718 #define TARGET_10_4_MCAST2UCAST_MODE 0 719 720 #define TARGET_10_4_TX_DBG_LOG_SIZE 1024 721 #define TARGET_10_4_NUM_WDS_ENTRIES 32 722 #define TARGET_10_4_DMA_BURST_SIZE 0 723 #define TARGET_10_4_MAC_AGGR_DELIM 0 724 #define TARGET_10_4_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1 725 #define TARGET_10_4_VOW_CONFIG 0 726 #define TARGET_10_4_GTK_OFFLOAD_MAX_VDEV 3 727 #define TARGET_10_4_11AC_TX_MAX_FRAGS 2 728 #define TARGET_10_4_MAX_PEER_EXT_STATS 16 729 #define TARGET_10_4_SMART_ANT_CAP 0 730 #define TARGET_10_4_BK_MIN_FREE 0 731 #define TARGET_10_4_BE_MIN_FREE 0 732 #define TARGET_10_4_VI_MIN_FREE 0 733 #define TARGET_10_4_VO_MIN_FREE 0 734 #define TARGET_10_4_RX_BATCH_MODE 1 735 #define TARGET_10_4_THERMAL_THROTTLING_CONFIG 0 736 #define TARGET_10_4_ATF_CONFIG 0 737 #define TARGET_10_4_IPHDR_PAD_CONFIG 1 738 #define TARGET_10_4_QWRAP_CONFIG 0 739 740 /* TDLS config */ 741 #define TARGET_10_4_NUM_TDLS_VDEVS 1 742 #define TARGET_10_4_NUM_TDLS_BUFFER_STA 1 743 #define TARGET_10_4_NUM_TDLS_SLEEP_STA 1 744 745 /* Maximum number of Copy Engine's supported */ 746 #define CE_COUNT_MAX 12 747 748 /* Number of Copy Engines supported */ 749 #define CE_COUNT ar->hw_values->ce_count 750 751 /* 752 * Granted MSIs are assigned as follows: 753 * Firmware uses the first 754 * Remaining MSIs, if any, are used by Copy Engines 755 * This mapping is known to both Target firmware and Host software. 756 * It may be changed as long as Host and Target are kept in sync. 757 */ 758 /* MSI for firmware (errors, etc.) */ 759 #define MSI_ASSIGN_FW 0 760 761 /* MSIs for Copy Engines */ 762 #define MSI_ASSIGN_CE_INITIAL 1 763 #define MSI_ASSIGN_CE_MAX ar->hw_values->msi_assign_ce_max 764 765 /* as of IP3.7.1 */ 766 #define RTC_STATE_V_ON ar->hw_values->rtc_state_val_on 767 768 #define RTC_STATE_V_LSB 0 769 #define RTC_STATE_V_MASK 0x00000007 770 #define RTC_STATE_ADDRESS 0x0000 771 #define PCIE_SOC_WAKE_V_MASK 0x00000001 772 #define PCIE_SOC_WAKE_ADDRESS 0x0004 773 #define PCIE_SOC_WAKE_RESET 0x00000000 774 #define SOC_GLOBAL_RESET_ADDRESS 0x0008 775 776 #define RTC_SOC_BASE_ADDRESS ar->regs->rtc_soc_base_address 777 #define RTC_WMAC_BASE_ADDRESS ar->regs->rtc_wmac_base_address 778 #define MAC_COEX_BASE_ADDRESS 0x00006000 779 #define BT_COEX_BASE_ADDRESS 0x00007000 780 #define SOC_PCIE_BASE_ADDRESS 0x00008000 781 #define SOC_CORE_BASE_ADDRESS ar->regs->soc_core_base_address 782 #define WLAN_UART_BASE_ADDRESS 0x0000c000 783 #define WLAN_SI_BASE_ADDRESS 0x00010000 784 #define WLAN_GPIO_BASE_ADDRESS 0x00014000 785 #define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000 786 #define WLAN_MAC_BASE_ADDRESS ar->regs->wlan_mac_base_address 787 #define EFUSE_BASE_ADDRESS 0x00030000 788 #define FPGA_REG_BASE_ADDRESS 0x00039000 789 #define WLAN_UART2_BASE_ADDRESS 0x00054c00 790 #define CE_WRAPPER_BASE_ADDRESS ar->regs->ce_wrapper_base_address 791 #define CE0_BASE_ADDRESS ar->regs->ce0_base_address 792 #define CE1_BASE_ADDRESS ar->regs->ce1_base_address 793 #define CE2_BASE_ADDRESS ar->regs->ce2_base_address 794 #define CE3_BASE_ADDRESS ar->regs->ce3_base_address 795 #define CE4_BASE_ADDRESS ar->regs->ce4_base_address 796 #define CE5_BASE_ADDRESS ar->regs->ce5_base_address 797 #define CE6_BASE_ADDRESS ar->regs->ce6_base_address 798 #define CE7_BASE_ADDRESS ar->regs->ce7_base_address 799 #define DBI_BASE_ADDRESS 0x00060000 800 #define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x0006c000 801 #define PCIE_LOCAL_BASE_ADDRESS ar->regs->pcie_local_base_address 802 803 #define SOC_RESET_CONTROL_ADDRESS 0x00000000 804 #define SOC_RESET_CONTROL_OFFSET 0x00000000 805 #define SOC_RESET_CONTROL_SI0_RST_MASK ar->regs->soc_reset_control_si0_rst_mask 806 #define SOC_RESET_CONTROL_CE_RST_MASK ar->regs->soc_reset_control_ce_rst_mask 807 #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040 808 #define SOC_CPU_CLOCK_OFFSET 0x00000020 809 #define SOC_CPU_CLOCK_STANDARD_LSB 0 810 #define SOC_CPU_CLOCK_STANDARD_MASK 0x00000003 811 #define SOC_CLOCK_CONTROL_OFFSET 0x00000028 812 #define SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001 813 #define SOC_SYSTEM_SLEEP_OFFSET 0x000000c4 814 #define SOC_LPO_CAL_OFFSET 0x000000e0 815 #define SOC_LPO_CAL_ENABLE_LSB 20 816 #define SOC_LPO_CAL_ENABLE_MASK 0x00100000 817 #define SOC_LF_TIMER_CONTROL0_ADDRESS 0x00000050 818 #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004 819 820 #define SOC_CHIP_ID_ADDRESS ar->regs->soc_chip_id_address 821 #define SOC_CHIP_ID_REV_LSB 8 822 #define SOC_CHIP_ID_REV_MASK 0x00000f00 823 824 #define WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000008 825 #define WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000004 826 #define WLAN_SYSTEM_SLEEP_DISABLE_LSB 0 827 #define WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001 828 829 #define WLAN_GPIO_PIN0_ADDRESS 0x00000028 830 #define WLAN_GPIO_PIN0_CONFIG_LSB 11 831 #define WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800 832 #define WLAN_GPIO_PIN0_PAD_PULL_LSB 5 833 #define WLAN_GPIO_PIN0_PAD_PULL_MASK 0x00000060 834 #define WLAN_GPIO_PIN1_ADDRESS 0x0000002c 835 #define WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800 836 #define WLAN_GPIO_PIN10_ADDRESS 0x00000050 837 #define WLAN_GPIO_PIN11_ADDRESS 0x00000054 838 #define WLAN_GPIO_PIN12_ADDRESS 0x00000058 839 #define WLAN_GPIO_PIN13_ADDRESS 0x0000005c 840 841 #define CLOCK_GPIO_OFFSET 0xffffffff 842 #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0 843 #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0 844 845 #define SI_CONFIG_OFFSET 0x00000000 846 #define SI_CONFIG_ERR_INT_LSB 19 847 #define SI_CONFIG_ERR_INT_MASK 0x00080000 848 #define SI_CONFIG_BIDIR_OD_DATA_LSB 18 849 #define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000 850 #define SI_CONFIG_I2C_LSB 16 851 #define SI_CONFIG_I2C_MASK 0x00010000 852 #define SI_CONFIG_POS_SAMPLE_LSB 7 853 #define SI_CONFIG_POS_SAMPLE_MASK 0x00000080 854 #define SI_CONFIG_INACTIVE_DATA_LSB 5 855 #define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020 856 #define SI_CONFIG_INACTIVE_CLK_LSB 4 857 #define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010 858 #define SI_CONFIG_DIVIDER_LSB 0 859 #define SI_CONFIG_DIVIDER_MASK 0x0000000f 860 #define SI_CS_OFFSET 0x00000004 861 #define SI_CS_DONE_ERR_LSB 10 862 #define SI_CS_DONE_ERR_MASK 0x00000400 863 #define SI_CS_DONE_INT_LSB 9 864 #define SI_CS_DONE_INT_MASK 0x00000200 865 #define SI_CS_START_LSB 8 866 #define SI_CS_START_MASK 0x00000100 867 #define SI_CS_RX_CNT_LSB 4 868 #define SI_CS_RX_CNT_MASK 0x000000f0 869 #define SI_CS_TX_CNT_LSB 0 870 #define SI_CS_TX_CNT_MASK 0x0000000f 871 872 #define SI_TX_DATA0_OFFSET 0x00000008 873 #define SI_TX_DATA1_OFFSET 0x0000000c 874 #define SI_RX_DATA0_OFFSET 0x00000010 875 #define SI_RX_DATA1_OFFSET 0x00000014 876 877 #define CORE_CTRL_CPU_INTR_MASK 0x00002000 878 #define CORE_CTRL_PCIE_REG_31_MASK 0x00000800 879 #define CORE_CTRL_ADDRESS 0x0000 880 #define PCIE_INTR_ENABLE_ADDRESS 0x0008 881 #define PCIE_INTR_CAUSE_ADDRESS 0x000c 882 #define PCIE_INTR_CLR_ADDRESS ar->regs->pcie_intr_clr_address 883 #define SCRATCH_3_ADDRESS ar->regs->scratch_3_address 884 #define CPU_INTR_ADDRESS 0x0010 885 886 #define CCNT_TO_MSEC(ar, x) ((x) / ar->hw_params.channel_counters_freq_hz) 887 888 /* Firmware indications to the Host via SCRATCH_3 register. */ 889 #define FW_INDICATOR_ADDRESS ar->regs->fw_indicator_address 890 #define FW_IND_EVENT_PENDING 1 891 #define FW_IND_INITIALIZED 2 892 #define FW_IND_HOST_READY 0x80000000 893 894 /* HOST_REG interrupt from firmware */ 895 #define PCIE_INTR_FIRMWARE_MASK ar->regs->pcie_intr_fw_mask 896 #define PCIE_INTR_CE_MASK_ALL ar->regs->pcie_intr_ce_mask_all 897 898 #define DRAM_BASE_ADDRESS 0x00400000 899 900 #define PCIE_BAR_REG_ADDRESS 0x40030 901 902 #define MISSING 0 903 904 #define SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET 905 #define WLAN_SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET 906 #define WLAN_RESET_CONTROL_OFFSET SOC_RESET_CONTROL_OFFSET 907 #define CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_OFFSET 908 #define CLOCK_CONTROL_SI0_CLK_MASK SOC_CLOCK_CONTROL_SI0_CLK_MASK 909 #define RESET_CONTROL_MBOX_RST_MASK MISSING 910 #define RESET_CONTROL_SI0_RST_MASK SOC_RESET_CONTROL_SI0_RST_MASK 911 #define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS 912 #define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_ADDRESS 913 #define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_ADDRESS 914 #define GPIO_PIN0_CONFIG_LSB WLAN_GPIO_PIN0_CONFIG_LSB 915 #define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK 916 #define GPIO_PIN0_PAD_PULL_LSB WLAN_GPIO_PIN0_PAD_PULL_LSB 917 #define GPIO_PIN0_PAD_PULL_MASK WLAN_GPIO_PIN0_PAD_PULL_MASK 918 #define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK 919 #define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS 920 #define SCRATCH_BASE_ADDRESS SOC_CORE_BASE_ADDRESS 921 #define LOCAL_SCRATCH_OFFSET 0x18 922 #define CPU_CLOCK_OFFSET SOC_CPU_CLOCK_OFFSET 923 #define LPO_CAL_OFFSET SOC_LPO_CAL_OFFSET 924 #define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_ADDRESS 925 #define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_ADDRESS 926 #define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_ADDRESS 927 #define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_ADDRESS 928 #define CPU_CLOCK_STANDARD_LSB SOC_CPU_CLOCK_STANDARD_LSB 929 #define CPU_CLOCK_STANDARD_MASK SOC_CPU_CLOCK_STANDARD_MASK 930 #define LPO_CAL_ENABLE_LSB SOC_LPO_CAL_ENABLE_LSB 931 #define LPO_CAL_ENABLE_MASK SOC_LPO_CAL_ENABLE_MASK 932 #define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS 933 #define MBOX_BASE_ADDRESS MISSING 934 #define INT_STATUS_ENABLE_ERROR_LSB MISSING 935 #define INT_STATUS_ENABLE_ERROR_MASK MISSING 936 #define INT_STATUS_ENABLE_CPU_LSB MISSING 937 #define INT_STATUS_ENABLE_CPU_MASK MISSING 938 #define INT_STATUS_ENABLE_COUNTER_LSB MISSING 939 #define INT_STATUS_ENABLE_COUNTER_MASK MISSING 940 #define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING 941 #define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING 942 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING 943 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING 944 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING 945 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING 946 #define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING 947 #define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING 948 #define INT_STATUS_ENABLE_ADDRESS MISSING 949 #define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING 950 #define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING 951 #define HOST_INT_STATUS_ADDRESS MISSING 952 #define CPU_INT_STATUS_ADDRESS MISSING 953 #define ERROR_INT_STATUS_ADDRESS MISSING 954 #define ERROR_INT_STATUS_WAKEUP_MASK MISSING 955 #define ERROR_INT_STATUS_WAKEUP_LSB MISSING 956 #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING 957 #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING 958 #define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING 959 #define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING 960 #define COUNT_DEC_ADDRESS MISSING 961 #define HOST_INT_STATUS_CPU_MASK MISSING 962 #define HOST_INT_STATUS_CPU_LSB MISSING 963 #define HOST_INT_STATUS_ERROR_MASK MISSING 964 #define HOST_INT_STATUS_ERROR_LSB MISSING 965 #define HOST_INT_STATUS_COUNTER_MASK MISSING 966 #define HOST_INT_STATUS_COUNTER_LSB MISSING 967 #define RX_LOOKAHEAD_VALID_ADDRESS MISSING 968 #define WINDOW_DATA_ADDRESS MISSING 969 #define WINDOW_READ_ADDR_ADDRESS MISSING 970 #define WINDOW_WRITE_ADDR_ADDRESS MISSING 971 972 #define QCA9887_1_0_I2C_SDA_GPIO_PIN 5 973 #define QCA9887_1_0_I2C_SDA_PIN_CONFIG 3 974 #define QCA9887_1_0_SI_CLK_GPIO_PIN 17 975 #define QCA9887_1_0_SI_CLK_PIN_CONFIG 3 976 #define QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS 0x00000010 977 978 #define QCA9887_EEPROM_SELECT_READ 0xa10000a0 979 #define QCA9887_EEPROM_ADDR_HI_MASK 0x0000ff00 980 #define QCA9887_EEPROM_ADDR_HI_LSB 8 981 #define QCA9887_EEPROM_ADDR_LO_MASK 0x00ff0000 982 #define QCA9887_EEPROM_ADDR_LO_LSB 16 983 984 #define MBOX_RESET_CONTROL_ADDRESS 0x00000000 985 #define MBOX_HOST_INT_STATUS_ADDRESS 0x00000800 986 #define MBOX_HOST_INT_STATUS_ERROR_LSB 7 987 #define MBOX_HOST_INT_STATUS_ERROR_MASK 0x00000080 988 #define MBOX_HOST_INT_STATUS_CPU_LSB 6 989 #define MBOX_HOST_INT_STATUS_CPU_MASK 0x00000040 990 #define MBOX_HOST_INT_STATUS_COUNTER_LSB 4 991 #define MBOX_HOST_INT_STATUS_COUNTER_MASK 0x00000010 992 #define MBOX_CPU_INT_STATUS_ADDRESS 0x00000801 993 #define MBOX_ERROR_INT_STATUS_ADDRESS 0x00000802 994 #define MBOX_ERROR_INT_STATUS_WAKEUP_LSB 2 995 #define MBOX_ERROR_INT_STATUS_WAKEUP_MASK 0x00000004 996 #define MBOX_ERROR_INT_STATUS_RX_UNDERFLOW_LSB 1 997 #define MBOX_ERROR_INT_STATUS_RX_UNDERFLOW_MASK 0x00000002 998 #define MBOX_ERROR_INT_STATUS_TX_OVERFLOW_LSB 0 999 #define MBOX_ERROR_INT_STATUS_TX_OVERFLOW_MASK 0x00000001 1000 #define MBOX_COUNTER_INT_STATUS_ADDRESS 0x00000803 1001 #define MBOX_COUNTER_INT_STATUS_COUNTER_LSB 0 1002 #define MBOX_COUNTER_INT_STATUS_COUNTER_MASK 0x000000ff 1003 #define MBOX_RX_LOOKAHEAD_VALID_ADDRESS 0x00000805 1004 #define MBOX_INT_STATUS_ENABLE_ADDRESS 0x00000828 1005 #define MBOX_INT_STATUS_ENABLE_ERROR_LSB 7 1006 #define MBOX_INT_STATUS_ENABLE_ERROR_MASK 0x00000080 1007 #define MBOX_INT_STATUS_ENABLE_CPU_LSB 6 1008 #define MBOX_INT_STATUS_ENABLE_CPU_MASK 0x00000040 1009 #define MBOX_INT_STATUS_ENABLE_INT_LSB 5 1010 #define MBOX_INT_STATUS_ENABLE_INT_MASK 0x00000020 1011 #define MBOX_INT_STATUS_ENABLE_COUNTER_LSB 4 1012 #define MBOX_INT_STATUS_ENABLE_COUNTER_MASK 0x00000010 1013 #define MBOX_INT_STATUS_ENABLE_MBOX_DATA_LSB 0 1014 #define MBOX_INT_STATUS_ENABLE_MBOX_DATA_MASK 0x0000000f 1015 #define MBOX_CPU_INT_STATUS_ENABLE_ADDRESS 0x00000819 1016 #define MBOX_CPU_INT_STATUS_ENABLE_BIT_LSB 0 1017 #define MBOX_CPU_INT_STATUS_ENABLE_BIT_MASK 0x000000ff 1018 #define MBOX_ERROR_STATUS_ENABLE_ADDRESS 0x0000081a 1019 #define MBOX_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB 1 1020 #define MBOX_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00000002 1021 #define MBOX_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB 0 1022 #define MBOX_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK 0x00000001 1023 #define MBOX_COUNTER_INT_STATUS_ENABLE_ADDRESS 0x0000081b 1024 #define MBOX_COUNTER_INT_STATUS_ENABLE_BIT_LSB 0 1025 #define MBOX_COUNTER_INT_STATUS_ENABLE_BIT_MASK 0x000000ff 1026 #define MBOX_COUNT_ADDRESS 0x00000820 1027 #define MBOX_COUNT_DEC_ADDRESS 0x00000840 1028 #define MBOX_WINDOW_DATA_ADDRESS 0x00000874 1029 #define MBOX_WINDOW_WRITE_ADDR_ADDRESS 0x00000878 1030 #define MBOX_WINDOW_READ_ADDR_ADDRESS 0x0000087c 1031 #define MBOX_CPU_DBG_SEL_ADDRESS 0x00000883 1032 #define MBOX_CPU_DBG_ADDRESS 0x00000884 1033 #define MBOX_RTC_BASE_ADDRESS 0x00000000 1034 #define MBOX_GPIO_BASE_ADDRESS 0x00005000 1035 #define MBOX_MBOX_BASE_ADDRESS 0x00008000 1036 1037 #define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB) 1038 1039 /* Register definitions for first generation ath10k cards. These cards include 1040 * a mac thich has a register allocation similar to ath9k and at least some 1041 * registers including the ones relevant for modifying the coverage class are 1042 * identical to the ath9k definitions. 1043 * These registers are usually managed by the ath10k firmware. However by 1044 * overriding them it is possible to support coverage class modifications. 1045 */ 1046 #define WAVE1_PCU_ACK_CTS_TIMEOUT 0x8014 1047 #define WAVE1_PCU_ACK_CTS_TIMEOUT_MAX 0x00003FFF 1048 #define WAVE1_PCU_ACK_CTS_TIMEOUT_ACK_MASK 0x00003FFF 1049 #define WAVE1_PCU_ACK_CTS_TIMEOUT_ACK_LSB 0 1050 #define WAVE1_PCU_ACK_CTS_TIMEOUT_CTS_MASK 0x3FFF0000 1051 #define WAVE1_PCU_ACK_CTS_TIMEOUT_CTS_LSB 16 1052 1053 #define WAVE1_PCU_GBL_IFS_SLOT 0x1070 1054 #define WAVE1_PCU_GBL_IFS_SLOT_MASK 0x0000FFFF 1055 #define WAVE1_PCU_GBL_IFS_SLOT_MAX 0x0000FFFF 1056 #define WAVE1_PCU_GBL_IFS_SLOT_LSB 0 1057 #define WAVE1_PCU_GBL_IFS_SLOT_RESV0 0xFFFF0000 1058 1059 #define WAVE1_PHYCLK 0x801C 1060 #define WAVE1_PHYCLK_USEC_MASK 0x0000007F 1061 #define WAVE1_PHYCLK_USEC_LSB 0 1062 1063 /* qca6174 PLL offset/mask */ 1064 #define SOC_CORE_CLK_CTRL_OFFSET 0x00000114 1065 #define SOC_CORE_CLK_CTRL_DIV_LSB 0 1066 #define SOC_CORE_CLK_CTRL_DIV_MASK 0x00000007 1067 1068 #define EFUSE_OFFSET 0x0000032c 1069 #define EFUSE_XTAL_SEL_LSB 8 1070 #define EFUSE_XTAL_SEL_MASK 0x00000700 1071 1072 #define BB_PLL_CONFIG_OFFSET 0x000002f4 1073 #define BB_PLL_CONFIG_FRAC_LSB 0 1074 #define BB_PLL_CONFIG_FRAC_MASK 0x0003ffff 1075 #define BB_PLL_CONFIG_OUTDIV_LSB 18 1076 #define BB_PLL_CONFIG_OUTDIV_MASK 0x001c0000 1077 1078 #define WLAN_PLL_SETTLE_OFFSET 0x0018 1079 #define WLAN_PLL_SETTLE_TIME_LSB 0 1080 #define WLAN_PLL_SETTLE_TIME_MASK 0x000007ff 1081 1082 #define WLAN_PLL_CONTROL_OFFSET 0x0014 1083 #define WLAN_PLL_CONTROL_DIV_LSB 0 1084 #define WLAN_PLL_CONTROL_DIV_MASK 0x000003ff 1085 #define WLAN_PLL_CONTROL_REFDIV_LSB 10 1086 #define WLAN_PLL_CONTROL_REFDIV_MASK 0x00003c00 1087 #define WLAN_PLL_CONTROL_BYPASS_LSB 16 1088 #define WLAN_PLL_CONTROL_BYPASS_MASK 0x00010000 1089 #define WLAN_PLL_CONTROL_NOPWD_LSB 18 1090 #define WLAN_PLL_CONTROL_NOPWD_MASK 0x00040000 1091 1092 #define RTC_SYNC_STATUS_OFFSET 0x0244 1093 #define RTC_SYNC_STATUS_PLL_CHANGING_LSB 5 1094 #define RTC_SYNC_STATUS_PLL_CHANGING_MASK 0x00000020 1095 /* qca6174 PLL offset/mask end */ 1096 1097 #endif /* _HW_H_ */ 1098