1 /* 2 * Copyright (c) 2005-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef _HW_H_ 19 #define _HW_H_ 20 21 #include "targaddrs.h" 22 23 #define ATH10K_FW_DIR "ath10k" 24 25 #define QCA988X_2_0_DEVICE_ID (0x003c) 26 #define QCA6164_2_1_DEVICE_ID (0x0041) 27 #define QCA6174_2_1_DEVICE_ID (0x003e) 28 #define QCA99X0_2_0_DEVICE_ID (0x0040) 29 #define QCA9888_2_0_DEVICE_ID (0x0056) 30 #define QCA9984_1_0_DEVICE_ID (0x0046) 31 #define QCA9377_1_0_DEVICE_ID (0x0042) 32 #define QCA9887_1_0_DEVICE_ID (0x0050) 33 34 /* QCA988X 1.0 definitions (unsupported) */ 35 #define QCA988X_HW_1_0_CHIP_ID_REV 0x0 36 37 /* QCA988X 2.0 definitions */ 38 #define QCA988X_HW_2_0_VERSION 0x4100016c 39 #define QCA988X_HW_2_0_CHIP_ID_REV 0x2 40 #define QCA988X_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA988X/hw2.0" 41 #define QCA988X_HW_2_0_BOARD_DATA_FILE "board.bin" 42 #define QCA988X_HW_2_0_PATCH_LOAD_ADDR 0x1234 43 44 /* QCA9887 1.0 definitions */ 45 #define QCA9887_HW_1_0_VERSION 0x4100016d 46 #define QCA9887_HW_1_0_CHIP_ID_REV 0 47 #define QCA9887_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9887/hw1.0" 48 #define QCA9887_HW_1_0_BOARD_DATA_FILE "board.bin" 49 #define QCA9887_HW_1_0_PATCH_LOAD_ADDR 0x1234 50 51 /* QCA6174 target BMI version signatures */ 52 #define QCA6174_HW_1_0_VERSION 0x05000000 53 #define QCA6174_HW_1_1_VERSION 0x05000001 54 #define QCA6174_HW_1_3_VERSION 0x05000003 55 #define QCA6174_HW_2_1_VERSION 0x05010000 56 #define QCA6174_HW_3_0_VERSION 0x05020000 57 #define QCA6174_HW_3_2_VERSION 0x05030000 58 59 /* QCA9377 target BMI version signatures */ 60 #define QCA9377_HW_1_0_DEV_VERSION 0x05020000 61 #define QCA9377_HW_1_1_DEV_VERSION 0x05020001 62 63 enum qca6174_pci_rev { 64 QCA6174_PCI_REV_1_1 = 0x11, 65 QCA6174_PCI_REV_1_3 = 0x13, 66 QCA6174_PCI_REV_2_0 = 0x20, 67 QCA6174_PCI_REV_3_0 = 0x30, 68 }; 69 70 enum qca6174_chip_id_rev { 71 QCA6174_HW_1_0_CHIP_ID_REV = 0, 72 QCA6174_HW_1_1_CHIP_ID_REV = 1, 73 QCA6174_HW_1_3_CHIP_ID_REV = 2, 74 QCA6174_HW_2_1_CHIP_ID_REV = 4, 75 QCA6174_HW_2_2_CHIP_ID_REV = 5, 76 QCA6174_HW_3_0_CHIP_ID_REV = 8, 77 QCA6174_HW_3_1_CHIP_ID_REV = 9, 78 QCA6174_HW_3_2_CHIP_ID_REV = 10, 79 }; 80 81 enum qca9377_chip_id_rev { 82 QCA9377_HW_1_0_CHIP_ID_REV = 0x0, 83 QCA9377_HW_1_1_CHIP_ID_REV = 0x1, 84 }; 85 86 #define QCA6174_HW_2_1_FW_DIR "ath10k/QCA6174/hw2.1" 87 #define QCA6174_HW_2_1_BOARD_DATA_FILE "board.bin" 88 #define QCA6174_HW_2_1_PATCH_LOAD_ADDR 0x1234 89 90 #define QCA6174_HW_3_0_FW_DIR "ath10k/QCA6174/hw3.0" 91 #define QCA6174_HW_3_0_BOARD_DATA_FILE "board.bin" 92 #define QCA6174_HW_3_0_PATCH_LOAD_ADDR 0x1234 93 94 /* QCA99X0 1.0 definitions (unsupported) */ 95 #define QCA99X0_HW_1_0_CHIP_ID_REV 0x0 96 97 /* QCA99X0 2.0 definitions */ 98 #define QCA99X0_HW_2_0_DEV_VERSION 0x01000000 99 #define QCA99X0_HW_2_0_CHIP_ID_REV 0x1 100 #define QCA99X0_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA99X0/hw2.0" 101 #define QCA99X0_HW_2_0_BOARD_DATA_FILE "board.bin" 102 #define QCA99X0_HW_2_0_PATCH_LOAD_ADDR 0x1234 103 104 /* QCA9984 1.0 defines */ 105 #define QCA9984_HW_1_0_DEV_VERSION 0x1000000 106 #define QCA9984_HW_DEV_TYPE 0xa 107 #define QCA9984_HW_1_0_CHIP_ID_REV 0x0 108 #define QCA9984_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9984/hw1.0" 109 #define QCA9984_HW_1_0_BOARD_DATA_FILE "board.bin" 110 #define QCA9984_HW_1_0_PATCH_LOAD_ADDR 0x1234 111 112 /* QCA9888 2.0 defines */ 113 #define QCA9888_HW_2_0_DEV_VERSION 0x1000000 114 #define QCA9888_HW_DEV_TYPE 0xc 115 #define QCA9888_HW_2_0_CHIP_ID_REV 0x0 116 #define QCA9888_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA9888/hw2.0" 117 #define QCA9888_HW_2_0_BOARD_DATA_FILE "board.bin" 118 #define QCA9888_HW_2_0_PATCH_LOAD_ADDR 0x1234 119 120 /* QCA9377 1.0 definitions */ 121 #define QCA9377_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9377/hw1.0" 122 #define QCA9377_HW_1_0_BOARD_DATA_FILE "board.bin" 123 #define QCA9377_HW_1_0_PATCH_LOAD_ADDR 0x1234 124 125 /* QCA4019 1.0 definitions */ 126 #define QCA4019_HW_1_0_DEV_VERSION 0x01000000 127 #define QCA4019_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA4019/hw1.0" 128 #define QCA4019_HW_1_0_BOARD_DATA_FILE "board.bin" 129 #define QCA4019_HW_1_0_PATCH_LOAD_ADDR 0x1234 130 131 #define ATH10K_FW_API2_FILE "firmware-2.bin" 132 #define ATH10K_FW_API3_FILE "firmware-3.bin" 133 134 /* added support for ATH10K_FW_IE_WMI_OP_VERSION */ 135 #define ATH10K_FW_API4_FILE "firmware-4.bin" 136 137 /* HTT id conflict fix for management frames over HTT */ 138 #define ATH10K_FW_API5_FILE "firmware-5.bin" 139 140 #define ATH10K_FW_UTF_FILE "utf.bin" 141 #define ATH10K_FW_UTF_API2_FILE "utf-2.bin" 142 143 /* includes also the null byte */ 144 #define ATH10K_FIRMWARE_MAGIC "QCA-ATH10K" 145 #define ATH10K_BOARD_MAGIC "QCA-ATH10K-BOARD" 146 147 #define ATH10K_BOARD_API2_FILE "board-2.bin" 148 149 #define REG_DUMP_COUNT_QCA988X 60 150 151 struct ath10k_fw_ie { 152 __le32 id; 153 __le32 len; 154 u8 data[0]; 155 }; 156 157 enum ath10k_fw_ie_type { 158 ATH10K_FW_IE_FW_VERSION = 0, 159 ATH10K_FW_IE_TIMESTAMP = 1, 160 ATH10K_FW_IE_FEATURES = 2, 161 ATH10K_FW_IE_FW_IMAGE = 3, 162 ATH10K_FW_IE_OTP_IMAGE = 4, 163 164 /* WMI "operations" interface version, 32 bit value. Supported from 165 * FW API 4 and above. 166 */ 167 ATH10K_FW_IE_WMI_OP_VERSION = 5, 168 169 /* HTT "operations" interface version, 32 bit value. Supported from 170 * FW API 5 and above. 171 */ 172 ATH10K_FW_IE_HTT_OP_VERSION = 6, 173 174 /* Code swap image for firmware binary */ 175 ATH10K_FW_IE_FW_CODE_SWAP_IMAGE = 7, 176 }; 177 178 enum ath10k_fw_wmi_op_version { 179 ATH10K_FW_WMI_OP_VERSION_UNSET = 0, 180 181 ATH10K_FW_WMI_OP_VERSION_MAIN = 1, 182 ATH10K_FW_WMI_OP_VERSION_10_1 = 2, 183 ATH10K_FW_WMI_OP_VERSION_10_2 = 3, 184 ATH10K_FW_WMI_OP_VERSION_TLV = 4, 185 ATH10K_FW_WMI_OP_VERSION_10_2_4 = 5, 186 ATH10K_FW_WMI_OP_VERSION_10_4 = 6, 187 188 /* keep last */ 189 ATH10K_FW_WMI_OP_VERSION_MAX, 190 }; 191 192 enum ath10k_fw_htt_op_version { 193 ATH10K_FW_HTT_OP_VERSION_UNSET = 0, 194 195 ATH10K_FW_HTT_OP_VERSION_MAIN = 1, 196 197 /* also used in 10.2 and 10.2.4 branches */ 198 ATH10K_FW_HTT_OP_VERSION_10_1 = 2, 199 200 ATH10K_FW_HTT_OP_VERSION_TLV = 3, 201 202 ATH10K_FW_HTT_OP_VERSION_10_4 = 4, 203 204 /* keep last */ 205 ATH10K_FW_HTT_OP_VERSION_MAX, 206 }; 207 208 enum ath10k_bd_ie_type { 209 /* contains sub IEs of enum ath10k_bd_ie_board_type */ 210 ATH10K_BD_IE_BOARD = 0, 211 }; 212 213 enum ath10k_bd_ie_board_type { 214 ATH10K_BD_IE_BOARD_NAME = 0, 215 ATH10K_BD_IE_BOARD_DATA = 1, 216 }; 217 218 enum ath10k_hw_rev { 219 ATH10K_HW_QCA988X, 220 ATH10K_HW_QCA6174, 221 ATH10K_HW_QCA99X0, 222 ATH10K_HW_QCA9888, 223 ATH10K_HW_QCA9984, 224 ATH10K_HW_QCA9377, 225 ATH10K_HW_QCA4019, 226 ATH10K_HW_QCA9887, 227 }; 228 229 struct ath10k_hw_regs { 230 u32 rtc_soc_base_address; 231 u32 rtc_wmac_base_address; 232 u32 soc_core_base_address; 233 u32 wlan_mac_base_address; 234 u32 ce_wrapper_base_address; 235 u32 ce0_base_address; 236 u32 ce1_base_address; 237 u32 ce2_base_address; 238 u32 ce3_base_address; 239 u32 ce4_base_address; 240 u32 ce5_base_address; 241 u32 ce6_base_address; 242 u32 ce7_base_address; 243 u32 soc_reset_control_si0_rst_mask; 244 u32 soc_reset_control_ce_rst_mask; 245 u32 soc_chip_id_address; 246 u32 scratch_3_address; 247 u32 fw_indicator_address; 248 u32 pcie_local_base_address; 249 u32 ce_wrap_intr_sum_host_msi_lsb; 250 u32 ce_wrap_intr_sum_host_msi_mask; 251 u32 pcie_intr_fw_mask; 252 u32 pcie_intr_ce_mask_all; 253 u32 pcie_intr_clr_address; 254 }; 255 256 extern const struct ath10k_hw_regs qca988x_regs; 257 extern const struct ath10k_hw_regs qca6174_regs; 258 extern const struct ath10k_hw_regs qca99x0_regs; 259 extern const struct ath10k_hw_regs qca4019_regs; 260 261 struct ath10k_hw_values { 262 u32 rtc_state_val_on; 263 u8 ce_count; 264 u8 msi_assign_ce_max; 265 u8 num_target_ce_config_wlan; 266 u16 ce_desc_meta_data_mask; 267 u8 ce_desc_meta_data_lsb; 268 }; 269 270 extern const struct ath10k_hw_values qca988x_values; 271 extern const struct ath10k_hw_values qca6174_values; 272 extern const struct ath10k_hw_values qca99x0_values; 273 extern const struct ath10k_hw_values qca9888_values; 274 extern const struct ath10k_hw_values qca4019_values; 275 276 void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey, 277 u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev); 278 279 #define QCA_REV_988X(ar) ((ar)->hw_rev == ATH10K_HW_QCA988X) 280 #define QCA_REV_9887(ar) ((ar)->hw_rev == ATH10K_HW_QCA9887) 281 #define QCA_REV_6174(ar) ((ar)->hw_rev == ATH10K_HW_QCA6174) 282 #define QCA_REV_99X0(ar) ((ar)->hw_rev == ATH10K_HW_QCA99X0) 283 #define QCA_REV_9888(ar) ((ar)->hw_rev == ATH10K_HW_QCA9888) 284 #define QCA_REV_9984(ar) ((ar)->hw_rev == ATH10K_HW_QCA9984) 285 #define QCA_REV_9377(ar) ((ar)->hw_rev == ATH10K_HW_QCA9377) 286 #define QCA_REV_40XX(ar) ((ar)->hw_rev == ATH10K_HW_QCA4019) 287 288 /* Known peculiarities: 289 * - raw appears in nwifi decap, raw and nwifi appear in ethernet decap 290 * - raw have FCS, nwifi doesn't 291 * - ethernet frames have 802.11 header decapped and parts (base hdr, cipher 292 * param, llc/snap) are aligned to 4byte boundaries each */ 293 enum ath10k_hw_txrx_mode { 294 ATH10K_HW_TXRX_RAW = 0, 295 296 /* Native Wifi decap mode is used to align IP frames to 4-byte 297 * boundaries and avoid a very expensive re-alignment in mac80211. 298 */ 299 ATH10K_HW_TXRX_NATIVE_WIFI = 1, 300 ATH10K_HW_TXRX_ETHERNET = 2, 301 302 /* Valid for HTT >= 3.0. Used for management frames in TX_FRM. */ 303 ATH10K_HW_TXRX_MGMT = 3, 304 }; 305 306 enum ath10k_mcast2ucast_mode { 307 ATH10K_MCAST2UCAST_DISABLED = 0, 308 ATH10K_MCAST2UCAST_ENABLED = 1, 309 }; 310 311 enum ath10k_hw_rate_ofdm { 312 ATH10K_HW_RATE_OFDM_48M = 0, 313 ATH10K_HW_RATE_OFDM_24M, 314 ATH10K_HW_RATE_OFDM_12M, 315 ATH10K_HW_RATE_OFDM_6M, 316 ATH10K_HW_RATE_OFDM_54M, 317 ATH10K_HW_RATE_OFDM_36M, 318 ATH10K_HW_RATE_OFDM_18M, 319 ATH10K_HW_RATE_OFDM_9M, 320 }; 321 322 enum ath10k_hw_rate_cck { 323 ATH10K_HW_RATE_CCK_LP_11M = 0, 324 ATH10K_HW_RATE_CCK_LP_5_5M, 325 ATH10K_HW_RATE_CCK_LP_2M, 326 ATH10K_HW_RATE_CCK_LP_1M, 327 ATH10K_HW_RATE_CCK_SP_11M, 328 ATH10K_HW_RATE_CCK_SP_5_5M, 329 ATH10K_HW_RATE_CCK_SP_2M, 330 }; 331 332 enum ath10k_hw_rate_rev2_cck { 333 ATH10K_HW_RATE_REV2_CCK_LP_1M = 1, 334 ATH10K_HW_RATE_REV2_CCK_LP_2M, 335 ATH10K_HW_RATE_REV2_CCK_LP_5_5M, 336 ATH10K_HW_RATE_REV2_CCK_LP_11M, 337 ATH10K_HW_RATE_REV2_CCK_SP_2M, 338 ATH10K_HW_RATE_REV2_CCK_SP_5_5M, 339 ATH10K_HW_RATE_REV2_CCK_SP_11M, 340 }; 341 342 enum ath10k_hw_cc_wraparound_type { 343 ATH10K_HW_CC_WRAP_DISABLED = 0, 344 345 /* This type is when the HW chip has a quirky Cycle Counter 346 * wraparound which resets to 0x7fffffff instead of 0. All 347 * other CC related counters (e.g. Rx Clear Count) are divided 348 * by 2 so they never wraparound themselves. 349 */ 350 ATH10K_HW_CC_WRAP_SHIFTED_ALL = 1, 351 352 /* Each hw counter wrapsaround independently. When the 353 * counter overflows the repestive counter is right shifted 354 * by 1, i.e reset to 0x7fffffff, and other counters will be 355 * running unaffected. In this type of wraparound, it should 356 * be possible to report accurate Rx busy time unlike the 357 * first type. 358 */ 359 ATH10K_HW_CC_WRAP_SHIFTED_EACH = 2, 360 }; 361 362 struct ath10k_hw_params { 363 u32 id; 364 u16 dev_id; 365 const char *name; 366 u32 patch_load_addr; 367 int uart_pin; 368 u32 otp_exe_param; 369 370 /* Type of hw cycle counter wraparound logic, for more info 371 * refer enum ath10k_hw_cc_wraparound_type. 372 */ 373 enum ath10k_hw_cc_wraparound_type cc_wraparound_type; 374 375 /* Some of chip expects fragment descriptor to be continuous 376 * memory for any TX operation. Set continuous_frag_desc flag 377 * for the hardware which have such requirement. 378 */ 379 bool continuous_frag_desc; 380 381 /* CCK hardware rate table mapping for the newer chipsets 382 * like QCA99X0, QCA4019 got revised. The CCK h/w rate values 383 * are in a proper order with respect to the rate/preamble 384 */ 385 bool cck_rate_map_rev2; 386 387 u32 channel_counters_freq_hz; 388 389 /* Mgmt tx descriptors threshold for limiting probe response 390 * frames. 391 */ 392 u32 max_probe_resp_desc_thres; 393 394 u32 tx_chain_mask; 395 u32 rx_chain_mask; 396 u32 max_spatial_stream; 397 u32 cal_data_len; 398 399 struct ath10k_hw_params_fw { 400 const char *dir; 401 const char *board; 402 size_t board_size; 403 size_t board_ext_size; 404 } fw; 405 406 /* qca99x0 family chips deliver broadcast/multicast management 407 * frames encrypted and expect software do decryption. 408 */ 409 bool sw_decrypt_mcast_mgmt; 410 411 const struct ath10k_hw_ops *hw_ops; 412 413 /* Number of bytes used for alignment in rx_hdr_status of rx desc. */ 414 int decap_align_bytes; 415 }; 416 417 struct htt_rx_desc; 418 419 /* Defines needed for Rx descriptor abstraction */ 420 struct ath10k_hw_ops { 421 int (*rx_desc_get_l3_pad_bytes)(struct htt_rx_desc *rxd); 422 void (*set_coverage_class)(struct ath10k *ar, s16 value); 423 }; 424 425 extern const struct ath10k_hw_ops qca988x_ops; 426 extern const struct ath10k_hw_ops qca99x0_ops; 427 428 static inline int 429 ath10k_rx_desc_get_l3_pad_bytes(struct ath10k_hw_params *hw, 430 struct htt_rx_desc *rxd) 431 { 432 if (hw->hw_ops->rx_desc_get_l3_pad_bytes) 433 return hw->hw_ops->rx_desc_get_l3_pad_bytes(rxd); 434 return 0; 435 } 436 437 /* Target specific defines for MAIN firmware */ 438 #define TARGET_NUM_VDEVS 8 439 #define TARGET_NUM_PEER_AST 2 440 #define TARGET_NUM_WDS_ENTRIES 32 441 #define TARGET_DMA_BURST_SIZE 0 442 #define TARGET_MAC_AGGR_DELIM 0 443 #define TARGET_AST_SKID_LIMIT 16 444 #define TARGET_NUM_STATIONS 16 445 #define TARGET_NUM_PEERS ((TARGET_NUM_STATIONS) + \ 446 (TARGET_NUM_VDEVS)) 447 #define TARGET_NUM_OFFLOAD_PEERS 0 448 #define TARGET_NUM_OFFLOAD_REORDER_BUFS 0 449 #define TARGET_NUM_PEER_KEYS 2 450 #define TARGET_NUM_TIDS ((TARGET_NUM_PEERS) * 2) 451 #define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 452 #define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 453 #define TARGET_RX_TIMEOUT_LO_PRI 100 454 #define TARGET_RX_TIMEOUT_HI_PRI 40 455 456 #define TARGET_SCAN_MAX_PENDING_REQS 4 457 #define TARGET_BMISS_OFFLOAD_MAX_VDEV 3 458 #define TARGET_ROAM_OFFLOAD_MAX_VDEV 3 459 #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8 460 #define TARGET_GTK_OFFLOAD_MAX_VDEV 3 461 #define TARGET_NUM_MCAST_GROUPS 0 462 #define TARGET_NUM_MCAST_TABLE_ELEMS 0 463 #define TARGET_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED 464 #define TARGET_TX_DBG_LOG_SIZE 1024 465 #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0 466 #define TARGET_VOW_CONFIG 0 467 #define TARGET_NUM_MSDU_DESC (1024 + 400) 468 #define TARGET_MAX_FRAG_ENTRIES 0 469 470 /* Target specific defines for 10.X firmware */ 471 #define TARGET_10X_NUM_VDEVS 16 472 #define TARGET_10X_NUM_PEER_AST 2 473 #define TARGET_10X_NUM_WDS_ENTRIES 32 474 #define TARGET_10X_DMA_BURST_SIZE 0 475 #define TARGET_10X_MAC_AGGR_DELIM 0 476 #define TARGET_10X_AST_SKID_LIMIT 128 477 #define TARGET_10X_NUM_STATIONS 128 478 #define TARGET_10X_TX_STATS_NUM_STATIONS 118 479 #define TARGET_10X_NUM_PEERS ((TARGET_10X_NUM_STATIONS) + \ 480 (TARGET_10X_NUM_VDEVS)) 481 #define TARGET_10X_TX_STATS_NUM_PEERS ((TARGET_10X_TX_STATS_NUM_STATIONS) + \ 482 (TARGET_10X_NUM_VDEVS)) 483 #define TARGET_10X_NUM_OFFLOAD_PEERS 0 484 #define TARGET_10X_NUM_OFFLOAD_REORDER_BUFS 0 485 #define TARGET_10X_NUM_PEER_KEYS 2 486 #define TARGET_10X_NUM_TIDS_MAX 256 487 #define TARGET_10X_NUM_TIDS min((TARGET_10X_NUM_TIDS_MAX), \ 488 (TARGET_10X_NUM_PEERS) * 2) 489 #define TARGET_10X_TX_STATS_NUM_TIDS min((TARGET_10X_NUM_TIDS_MAX), \ 490 (TARGET_10X_TX_STATS_NUM_PEERS) * 2) 491 #define TARGET_10X_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 492 #define TARGET_10X_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 493 #define TARGET_10X_RX_TIMEOUT_LO_PRI 100 494 #define TARGET_10X_RX_TIMEOUT_HI_PRI 40 495 #define TARGET_10X_SCAN_MAX_PENDING_REQS 4 496 #define TARGET_10X_BMISS_OFFLOAD_MAX_VDEV 2 497 #define TARGET_10X_ROAM_OFFLOAD_MAX_VDEV 2 498 #define TARGET_10X_ROAM_OFFLOAD_MAX_AP_PROFILES 8 499 #define TARGET_10X_GTK_OFFLOAD_MAX_VDEV 3 500 #define TARGET_10X_NUM_MCAST_GROUPS 0 501 #define TARGET_10X_NUM_MCAST_TABLE_ELEMS 0 502 #define TARGET_10X_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED 503 #define TARGET_10X_TX_DBG_LOG_SIZE 1024 504 #define TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1 505 #define TARGET_10X_VOW_CONFIG 0 506 #define TARGET_10X_NUM_MSDU_DESC (1024 + 400) 507 #define TARGET_10X_MAX_FRAG_ENTRIES 0 508 509 /* 10.2 parameters */ 510 #define TARGET_10_2_DMA_BURST_SIZE 0 511 512 /* Target specific defines for WMI-TLV firmware */ 513 #define TARGET_TLV_NUM_VDEVS 4 514 #define TARGET_TLV_NUM_STATIONS 32 515 #define TARGET_TLV_NUM_PEERS 35 516 #define TARGET_TLV_NUM_TDLS_VDEVS 1 517 #define TARGET_TLV_NUM_TIDS ((TARGET_TLV_NUM_PEERS) * 2) 518 #define TARGET_TLV_NUM_MSDU_DESC (1024 + 32) 519 #define TARGET_TLV_NUM_WOW_PATTERNS 22 520 521 /* Diagnostic Window */ 522 #define CE_DIAG_PIPE 7 523 524 #define NUM_TARGET_CE_CONFIG_WLAN ar->hw_values->num_target_ce_config_wlan 525 526 /* Target specific defines for 10.4 firmware */ 527 #define TARGET_10_4_NUM_VDEVS 16 528 #define TARGET_10_4_NUM_STATIONS 32 529 #define TARGET_10_4_NUM_PEERS ((TARGET_10_4_NUM_STATIONS) + \ 530 (TARGET_10_4_NUM_VDEVS)) 531 #define TARGET_10_4_ACTIVE_PEERS 0 532 533 #define TARGET_10_4_NUM_QCACHE_PEERS_MAX 512 534 #define TARGET_10_4_QCACHE_ACTIVE_PEERS 50 535 #define TARGET_10_4_QCACHE_ACTIVE_PEERS_PFC 35 536 #define TARGET_10_4_NUM_OFFLOAD_PEERS 0 537 #define TARGET_10_4_NUM_OFFLOAD_REORDER_BUFFS 0 538 #define TARGET_10_4_NUM_PEER_KEYS 2 539 #define TARGET_10_4_TGT_NUM_TIDS ((TARGET_10_4_NUM_PEERS) * 2) 540 #define TARGET_10_4_NUM_MSDU_DESC (1024 + 400) 541 #define TARGET_10_4_NUM_MSDU_DESC_PFC 2500 542 #define TARGET_10_4_AST_SKID_LIMIT 32 543 544 /* 100 ms for video, best-effort, and background */ 545 #define TARGET_10_4_RX_TIMEOUT_LO_PRI 100 546 547 /* 40 ms for voice */ 548 #define TARGET_10_4_RX_TIMEOUT_HI_PRI 40 549 550 #define TARGET_10_4_RX_DECAP_MODE ATH10K_HW_TXRX_NATIVE_WIFI 551 #define TARGET_10_4_SCAN_MAX_REQS 4 552 #define TARGET_10_4_BMISS_OFFLOAD_MAX_VDEV 3 553 #define TARGET_10_4_ROAM_OFFLOAD_MAX_VDEV 3 554 #define TARGET_10_4_ROAM_OFFLOAD_MAX_PROFILES 8 555 556 /* Note: mcast to ucast is disabled by default */ 557 #define TARGET_10_4_NUM_MCAST_GROUPS 0 558 #define TARGET_10_4_NUM_MCAST_TABLE_ELEMS 0 559 #define TARGET_10_4_MCAST2UCAST_MODE 0 560 561 #define TARGET_10_4_TX_DBG_LOG_SIZE 1024 562 #define TARGET_10_4_NUM_WDS_ENTRIES 32 563 #define TARGET_10_4_DMA_BURST_SIZE 0 564 #define TARGET_10_4_MAC_AGGR_DELIM 0 565 #define TARGET_10_4_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1 566 #define TARGET_10_4_VOW_CONFIG 0 567 #define TARGET_10_4_GTK_OFFLOAD_MAX_VDEV 3 568 #define TARGET_10_4_11AC_TX_MAX_FRAGS 2 569 #define TARGET_10_4_MAX_PEER_EXT_STATS 16 570 #define TARGET_10_4_SMART_ANT_CAP 0 571 #define TARGET_10_4_BK_MIN_FREE 0 572 #define TARGET_10_4_BE_MIN_FREE 0 573 #define TARGET_10_4_VI_MIN_FREE 0 574 #define TARGET_10_4_VO_MIN_FREE 0 575 #define TARGET_10_4_RX_BATCH_MODE 1 576 #define TARGET_10_4_THERMAL_THROTTLING_CONFIG 0 577 #define TARGET_10_4_ATF_CONFIG 0 578 #define TARGET_10_4_IPHDR_PAD_CONFIG 1 579 #define TARGET_10_4_QWRAP_CONFIG 0 580 581 /* Number of Copy Engines supported */ 582 #define CE_COUNT ar->hw_values->ce_count 583 584 /* 585 * Granted MSIs are assigned as follows: 586 * Firmware uses the first 587 * Remaining MSIs, if any, are used by Copy Engines 588 * This mapping is known to both Target firmware and Host software. 589 * It may be changed as long as Host and Target are kept in sync. 590 */ 591 /* MSI for firmware (errors, etc.) */ 592 #define MSI_ASSIGN_FW 0 593 594 /* MSIs for Copy Engines */ 595 #define MSI_ASSIGN_CE_INITIAL 1 596 #define MSI_ASSIGN_CE_MAX ar->hw_values->msi_assign_ce_max 597 598 /* as of IP3.7.1 */ 599 #define RTC_STATE_V_ON ar->hw_values->rtc_state_val_on 600 601 #define RTC_STATE_V_LSB 0 602 #define RTC_STATE_V_MASK 0x00000007 603 #define RTC_STATE_ADDRESS 0x0000 604 #define PCIE_SOC_WAKE_V_MASK 0x00000001 605 #define PCIE_SOC_WAKE_ADDRESS 0x0004 606 #define PCIE_SOC_WAKE_RESET 0x00000000 607 #define SOC_GLOBAL_RESET_ADDRESS 0x0008 608 609 #define RTC_SOC_BASE_ADDRESS ar->regs->rtc_soc_base_address 610 #define RTC_WMAC_BASE_ADDRESS ar->regs->rtc_wmac_base_address 611 #define MAC_COEX_BASE_ADDRESS 0x00006000 612 #define BT_COEX_BASE_ADDRESS 0x00007000 613 #define SOC_PCIE_BASE_ADDRESS 0x00008000 614 #define SOC_CORE_BASE_ADDRESS ar->regs->soc_core_base_address 615 #define WLAN_UART_BASE_ADDRESS 0x0000c000 616 #define WLAN_SI_BASE_ADDRESS 0x00010000 617 #define WLAN_GPIO_BASE_ADDRESS 0x00014000 618 #define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000 619 #define WLAN_MAC_BASE_ADDRESS ar->regs->wlan_mac_base_address 620 #define EFUSE_BASE_ADDRESS 0x00030000 621 #define FPGA_REG_BASE_ADDRESS 0x00039000 622 #define WLAN_UART2_BASE_ADDRESS 0x00054c00 623 #define CE_WRAPPER_BASE_ADDRESS ar->regs->ce_wrapper_base_address 624 #define CE0_BASE_ADDRESS ar->regs->ce0_base_address 625 #define CE1_BASE_ADDRESS ar->regs->ce1_base_address 626 #define CE2_BASE_ADDRESS ar->regs->ce2_base_address 627 #define CE3_BASE_ADDRESS ar->regs->ce3_base_address 628 #define CE4_BASE_ADDRESS ar->regs->ce4_base_address 629 #define CE5_BASE_ADDRESS ar->regs->ce5_base_address 630 #define CE6_BASE_ADDRESS ar->regs->ce6_base_address 631 #define CE7_BASE_ADDRESS ar->regs->ce7_base_address 632 #define DBI_BASE_ADDRESS 0x00060000 633 #define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x0006c000 634 #define PCIE_LOCAL_BASE_ADDRESS ar->regs->pcie_local_base_address 635 636 #define SOC_RESET_CONTROL_ADDRESS 0x00000000 637 #define SOC_RESET_CONTROL_OFFSET 0x00000000 638 #define SOC_RESET_CONTROL_SI0_RST_MASK ar->regs->soc_reset_control_si0_rst_mask 639 #define SOC_RESET_CONTROL_CE_RST_MASK ar->regs->soc_reset_control_ce_rst_mask 640 #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040 641 #define SOC_CPU_CLOCK_OFFSET 0x00000020 642 #define SOC_CPU_CLOCK_STANDARD_LSB 0 643 #define SOC_CPU_CLOCK_STANDARD_MASK 0x00000003 644 #define SOC_CLOCK_CONTROL_OFFSET 0x00000028 645 #define SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001 646 #define SOC_SYSTEM_SLEEP_OFFSET 0x000000c4 647 #define SOC_LPO_CAL_OFFSET 0x000000e0 648 #define SOC_LPO_CAL_ENABLE_LSB 20 649 #define SOC_LPO_CAL_ENABLE_MASK 0x00100000 650 #define SOC_LF_TIMER_CONTROL0_ADDRESS 0x00000050 651 #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004 652 653 #define SOC_CHIP_ID_ADDRESS ar->regs->soc_chip_id_address 654 #define SOC_CHIP_ID_REV_LSB 8 655 #define SOC_CHIP_ID_REV_MASK 0x00000f00 656 657 #define WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000008 658 #define WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000004 659 #define WLAN_SYSTEM_SLEEP_DISABLE_LSB 0 660 #define WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001 661 662 #define WLAN_GPIO_PIN0_ADDRESS 0x00000028 663 #define WLAN_GPIO_PIN0_CONFIG_LSB 11 664 #define WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800 665 #define WLAN_GPIO_PIN0_PAD_PULL_LSB 5 666 #define WLAN_GPIO_PIN0_PAD_PULL_MASK 0x00000060 667 #define WLAN_GPIO_PIN1_ADDRESS 0x0000002c 668 #define WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800 669 #define WLAN_GPIO_PIN10_ADDRESS 0x00000050 670 #define WLAN_GPIO_PIN11_ADDRESS 0x00000054 671 #define WLAN_GPIO_PIN12_ADDRESS 0x00000058 672 #define WLAN_GPIO_PIN13_ADDRESS 0x0000005c 673 674 #define CLOCK_GPIO_OFFSET 0xffffffff 675 #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0 676 #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0 677 678 #define SI_CONFIG_OFFSET 0x00000000 679 #define SI_CONFIG_ERR_INT_LSB 19 680 #define SI_CONFIG_ERR_INT_MASK 0x00080000 681 #define SI_CONFIG_BIDIR_OD_DATA_LSB 18 682 #define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000 683 #define SI_CONFIG_I2C_LSB 16 684 #define SI_CONFIG_I2C_MASK 0x00010000 685 #define SI_CONFIG_POS_SAMPLE_LSB 7 686 #define SI_CONFIG_POS_SAMPLE_MASK 0x00000080 687 #define SI_CONFIG_INACTIVE_DATA_LSB 5 688 #define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020 689 #define SI_CONFIG_INACTIVE_CLK_LSB 4 690 #define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010 691 #define SI_CONFIG_DIVIDER_LSB 0 692 #define SI_CONFIG_DIVIDER_MASK 0x0000000f 693 #define SI_CS_OFFSET 0x00000004 694 #define SI_CS_DONE_ERR_LSB 10 695 #define SI_CS_DONE_ERR_MASK 0x00000400 696 #define SI_CS_DONE_INT_LSB 9 697 #define SI_CS_DONE_INT_MASK 0x00000200 698 #define SI_CS_START_LSB 8 699 #define SI_CS_START_MASK 0x00000100 700 #define SI_CS_RX_CNT_LSB 4 701 #define SI_CS_RX_CNT_MASK 0x000000f0 702 #define SI_CS_TX_CNT_LSB 0 703 #define SI_CS_TX_CNT_MASK 0x0000000f 704 705 #define SI_TX_DATA0_OFFSET 0x00000008 706 #define SI_TX_DATA1_OFFSET 0x0000000c 707 #define SI_RX_DATA0_OFFSET 0x00000010 708 #define SI_RX_DATA1_OFFSET 0x00000014 709 710 #define CORE_CTRL_CPU_INTR_MASK 0x00002000 711 #define CORE_CTRL_PCIE_REG_31_MASK 0x00000800 712 #define CORE_CTRL_ADDRESS 0x0000 713 #define PCIE_INTR_ENABLE_ADDRESS 0x0008 714 #define PCIE_INTR_CAUSE_ADDRESS 0x000c 715 #define PCIE_INTR_CLR_ADDRESS ar->regs->pcie_intr_clr_address 716 #define SCRATCH_3_ADDRESS ar->regs->scratch_3_address 717 #define CPU_INTR_ADDRESS 0x0010 718 719 #define CCNT_TO_MSEC(ar, x) ((x) / ar->hw_params.channel_counters_freq_hz) 720 721 /* Firmware indications to the Host via SCRATCH_3 register. */ 722 #define FW_INDICATOR_ADDRESS ar->regs->fw_indicator_address 723 #define FW_IND_EVENT_PENDING 1 724 #define FW_IND_INITIALIZED 2 725 #define FW_IND_HOST_READY 0x80000000 726 727 /* HOST_REG interrupt from firmware */ 728 #define PCIE_INTR_FIRMWARE_MASK ar->regs->pcie_intr_fw_mask 729 #define PCIE_INTR_CE_MASK_ALL ar->regs->pcie_intr_ce_mask_all 730 731 #define DRAM_BASE_ADDRESS 0x00400000 732 733 #define PCIE_BAR_REG_ADDRESS 0x40030 734 735 #define MISSING 0 736 737 #define SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET 738 #define WLAN_SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET 739 #define WLAN_RESET_CONTROL_OFFSET SOC_RESET_CONTROL_OFFSET 740 #define CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_OFFSET 741 #define CLOCK_CONTROL_SI0_CLK_MASK SOC_CLOCK_CONTROL_SI0_CLK_MASK 742 #define RESET_CONTROL_MBOX_RST_MASK MISSING 743 #define RESET_CONTROL_SI0_RST_MASK SOC_RESET_CONTROL_SI0_RST_MASK 744 #define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS 745 #define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_ADDRESS 746 #define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_ADDRESS 747 #define GPIO_PIN0_CONFIG_LSB WLAN_GPIO_PIN0_CONFIG_LSB 748 #define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK 749 #define GPIO_PIN0_PAD_PULL_LSB WLAN_GPIO_PIN0_PAD_PULL_LSB 750 #define GPIO_PIN0_PAD_PULL_MASK WLAN_GPIO_PIN0_PAD_PULL_MASK 751 #define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK 752 #define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS 753 #define SCRATCH_BASE_ADDRESS SOC_CORE_BASE_ADDRESS 754 #define LOCAL_SCRATCH_OFFSET 0x18 755 #define CPU_CLOCK_OFFSET SOC_CPU_CLOCK_OFFSET 756 #define LPO_CAL_OFFSET SOC_LPO_CAL_OFFSET 757 #define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_ADDRESS 758 #define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_ADDRESS 759 #define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_ADDRESS 760 #define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_ADDRESS 761 #define CPU_CLOCK_STANDARD_LSB SOC_CPU_CLOCK_STANDARD_LSB 762 #define CPU_CLOCK_STANDARD_MASK SOC_CPU_CLOCK_STANDARD_MASK 763 #define LPO_CAL_ENABLE_LSB SOC_LPO_CAL_ENABLE_LSB 764 #define LPO_CAL_ENABLE_MASK SOC_LPO_CAL_ENABLE_MASK 765 #define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS 766 #define MBOX_BASE_ADDRESS MISSING 767 #define INT_STATUS_ENABLE_ERROR_LSB MISSING 768 #define INT_STATUS_ENABLE_ERROR_MASK MISSING 769 #define INT_STATUS_ENABLE_CPU_LSB MISSING 770 #define INT_STATUS_ENABLE_CPU_MASK MISSING 771 #define INT_STATUS_ENABLE_COUNTER_LSB MISSING 772 #define INT_STATUS_ENABLE_COUNTER_MASK MISSING 773 #define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING 774 #define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING 775 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING 776 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING 777 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING 778 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING 779 #define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING 780 #define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING 781 #define INT_STATUS_ENABLE_ADDRESS MISSING 782 #define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING 783 #define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING 784 #define HOST_INT_STATUS_ADDRESS MISSING 785 #define CPU_INT_STATUS_ADDRESS MISSING 786 #define ERROR_INT_STATUS_ADDRESS MISSING 787 #define ERROR_INT_STATUS_WAKEUP_MASK MISSING 788 #define ERROR_INT_STATUS_WAKEUP_LSB MISSING 789 #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING 790 #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING 791 #define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING 792 #define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING 793 #define COUNT_DEC_ADDRESS MISSING 794 #define HOST_INT_STATUS_CPU_MASK MISSING 795 #define HOST_INT_STATUS_CPU_LSB MISSING 796 #define HOST_INT_STATUS_ERROR_MASK MISSING 797 #define HOST_INT_STATUS_ERROR_LSB MISSING 798 #define HOST_INT_STATUS_COUNTER_MASK MISSING 799 #define HOST_INT_STATUS_COUNTER_LSB MISSING 800 #define RX_LOOKAHEAD_VALID_ADDRESS MISSING 801 #define WINDOW_DATA_ADDRESS MISSING 802 #define WINDOW_READ_ADDR_ADDRESS MISSING 803 #define WINDOW_WRITE_ADDR_ADDRESS MISSING 804 805 #define QCA9887_1_0_I2C_SDA_GPIO_PIN 5 806 #define QCA9887_1_0_I2C_SDA_PIN_CONFIG 3 807 #define QCA9887_1_0_SI_CLK_GPIO_PIN 17 808 #define QCA9887_1_0_SI_CLK_PIN_CONFIG 3 809 #define QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS 0x00000010 810 811 #define QCA9887_EEPROM_SELECT_READ 0xa10000a0 812 #define QCA9887_EEPROM_ADDR_HI_MASK 0x0000ff00 813 #define QCA9887_EEPROM_ADDR_HI_LSB 8 814 #define QCA9887_EEPROM_ADDR_LO_MASK 0x00ff0000 815 #define QCA9887_EEPROM_ADDR_LO_LSB 16 816 817 #define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB) 818 819 /* Register definitions for first generation ath10k cards. These cards include 820 * a mac thich has a register allocation similar to ath9k and at least some 821 * registers including the ones relevant for modifying the coverage class are 822 * identical to the ath9k definitions. 823 * These registers are usually managed by the ath10k firmware. However by 824 * overriding them it is possible to support coverage class modifications. 825 */ 826 #define WAVE1_PCU_ACK_CTS_TIMEOUT 0x8014 827 #define WAVE1_PCU_ACK_CTS_TIMEOUT_MAX 0x00003FFF 828 #define WAVE1_PCU_ACK_CTS_TIMEOUT_ACK_MASK 0x00003FFF 829 #define WAVE1_PCU_ACK_CTS_TIMEOUT_ACK_LSB 0 830 #define WAVE1_PCU_ACK_CTS_TIMEOUT_CTS_MASK 0x3FFF0000 831 #define WAVE1_PCU_ACK_CTS_TIMEOUT_CTS_LSB 16 832 833 #define WAVE1_PCU_GBL_IFS_SLOT 0x1070 834 #define WAVE1_PCU_GBL_IFS_SLOT_MASK 0x0000FFFF 835 #define WAVE1_PCU_GBL_IFS_SLOT_MAX 0x0000FFFF 836 #define WAVE1_PCU_GBL_IFS_SLOT_LSB 0 837 #define WAVE1_PCU_GBL_IFS_SLOT_RESV0 0xFFFF0000 838 839 #define WAVE1_PHYCLK 0x801C 840 #define WAVE1_PHYCLK_USEC_MASK 0x0000007F 841 #define WAVE1_PHYCLK_USEC_LSB 0 842 843 #endif /* _HW_H_ */ 844