1 /* 2 * Copyright (c) 2014-2015 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/types.h> 18 #include "core.h" 19 #include "hw.h" 20 21 const struct ath10k_hw_regs qca988x_regs = { 22 .rtc_state_cold_reset_mask = 0x00000400, 23 .rtc_soc_base_address = 0x00004000, 24 .rtc_wmac_base_address = 0x00005000, 25 .soc_core_base_address = 0x00009000, 26 .ce_wrapper_base_address = 0x00057000, 27 .ce0_base_address = 0x00057400, 28 .ce1_base_address = 0x00057800, 29 .ce2_base_address = 0x00057c00, 30 .ce3_base_address = 0x00058000, 31 .ce4_base_address = 0x00058400, 32 .ce5_base_address = 0x00058800, 33 .ce6_base_address = 0x00058c00, 34 .ce7_base_address = 0x00059000, 35 .soc_reset_control_si0_rst_mask = 0x00000001, 36 .soc_reset_control_ce_rst_mask = 0x00040000, 37 .soc_chip_id_address = 0x00ec, 38 .scratch_3_address = 0x0030, 39 }; 40 41 const struct ath10k_hw_regs qca6174_regs = { 42 .rtc_state_cold_reset_mask = 0x00002000, 43 .rtc_soc_base_address = 0x00000800, 44 .rtc_wmac_base_address = 0x00001000, 45 .soc_core_base_address = 0x0003a000, 46 .ce_wrapper_base_address = 0x00034000, 47 .ce0_base_address = 0x00034400, 48 .ce1_base_address = 0x00034800, 49 .ce2_base_address = 0x00034c00, 50 .ce3_base_address = 0x00035000, 51 .ce4_base_address = 0x00035400, 52 .ce5_base_address = 0x00035800, 53 .ce6_base_address = 0x00035c00, 54 .ce7_base_address = 0x00036000, 55 .soc_reset_control_si0_rst_mask = 0x00000000, 56 .soc_reset_control_ce_rst_mask = 0x00000001, 57 .soc_chip_id_address = 0x000f0, 58 .scratch_3_address = 0x0028, 59 }; 60 61 void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey, 62 u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev) 63 { 64 u32 cc_fix = 0; 65 66 survey->filled |= SURVEY_INFO_TIME | 67 SURVEY_INFO_TIME_BUSY; 68 69 if (ar->hw_params.has_shifted_cc_wraparound && cc < cc_prev) { 70 cc_fix = 0x7fffffff; 71 survey->filled &= ~SURVEY_INFO_TIME_BUSY; 72 } 73 74 cc -= cc_prev - cc_fix; 75 rcc -= rcc_prev; 76 77 survey->time = CCNT_TO_MSEC(cc); 78 survey->time_busy = CCNT_TO_MSEC(rcc); 79 } 80