1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (c) 2005-2011 Atheros Communications Inc. 4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. 5 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 6 */ 7 8 #include <linux/export.h> 9 #include <linux/etherdevice.h> 10 #include "htt.h" 11 #include "mac.h" 12 #include "hif.h" 13 #include "txrx.h" 14 #include "debug.h" 15 16 static u8 ath10k_htt_tx_txq_calc_size(size_t count) 17 { 18 int exp; 19 int factor; 20 21 exp = 0; 22 factor = count >> 7; 23 24 while (factor >= 64 && exp < 4) { 25 factor >>= 3; 26 exp++; 27 } 28 29 if (exp == 4) 30 return 0xff; 31 32 if (count > 0) 33 factor = max(1, factor); 34 35 return SM(exp, HTT_TX_Q_STATE_ENTRY_EXP) | 36 SM(factor, HTT_TX_Q_STATE_ENTRY_FACTOR); 37 } 38 39 static void __ath10k_htt_tx_txq_recalc(struct ieee80211_hw *hw, 40 struct ieee80211_txq *txq) 41 { 42 struct ath10k *ar = hw->priv; 43 struct ath10k_sta *arsta; 44 struct ath10k_vif *arvif = (void *)txq->vif->drv_priv; 45 unsigned long byte_cnt; 46 int idx; 47 u32 bit; 48 u16 peer_id; 49 u8 tid; 50 u8 count; 51 52 lockdep_assert_held(&ar->htt.tx_lock); 53 54 if (!ar->htt.tx_q_state.enabled) 55 return; 56 57 if (ar->htt.tx_q_state.mode != HTT_TX_MODE_SWITCH_PUSH_PULL) 58 return; 59 60 if (txq->sta) { 61 arsta = (void *)txq->sta->drv_priv; 62 peer_id = arsta->peer_id; 63 } else { 64 peer_id = arvif->peer_id; 65 } 66 67 tid = txq->tid; 68 bit = BIT(peer_id % 32); 69 idx = peer_id / 32; 70 71 ieee80211_txq_get_depth(txq, NULL, &byte_cnt); 72 count = ath10k_htt_tx_txq_calc_size(byte_cnt); 73 74 if (unlikely(peer_id >= ar->htt.tx_q_state.num_peers) || 75 unlikely(tid >= ar->htt.tx_q_state.num_tids)) { 76 ath10k_warn(ar, "refusing to update txq for peer_id %u tid %u due to out of bounds\n", 77 peer_id, tid); 78 return; 79 } 80 81 ar->htt.tx_q_state.vaddr->count[tid][peer_id] = count; 82 ar->htt.tx_q_state.vaddr->map[tid][idx] &= ~bit; 83 ar->htt.tx_q_state.vaddr->map[tid][idx] |= count ? bit : 0; 84 85 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx txq state update peer_id %u tid %u count %u\n", 86 peer_id, tid, count); 87 } 88 89 static void __ath10k_htt_tx_txq_sync(struct ath10k *ar) 90 { 91 u32 seq; 92 size_t size; 93 94 lockdep_assert_held(&ar->htt.tx_lock); 95 96 if (!ar->htt.tx_q_state.enabled) 97 return; 98 99 if (ar->htt.tx_q_state.mode != HTT_TX_MODE_SWITCH_PUSH_PULL) 100 return; 101 102 seq = le32_to_cpu(ar->htt.tx_q_state.vaddr->seq); 103 seq++; 104 ar->htt.tx_q_state.vaddr->seq = cpu_to_le32(seq); 105 106 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx txq state update commit seq %u\n", 107 seq); 108 109 size = sizeof(*ar->htt.tx_q_state.vaddr); 110 dma_sync_single_for_device(ar->dev, 111 ar->htt.tx_q_state.paddr, 112 size, 113 DMA_TO_DEVICE); 114 } 115 116 void ath10k_htt_tx_txq_recalc(struct ieee80211_hw *hw, 117 struct ieee80211_txq *txq) 118 { 119 struct ath10k *ar = hw->priv; 120 121 spin_lock_bh(&ar->htt.tx_lock); 122 __ath10k_htt_tx_txq_recalc(hw, txq); 123 spin_unlock_bh(&ar->htt.tx_lock); 124 } 125 126 void ath10k_htt_tx_txq_sync(struct ath10k *ar) 127 { 128 spin_lock_bh(&ar->htt.tx_lock); 129 __ath10k_htt_tx_txq_sync(ar); 130 spin_unlock_bh(&ar->htt.tx_lock); 131 } 132 133 void ath10k_htt_tx_txq_update(struct ieee80211_hw *hw, 134 struct ieee80211_txq *txq) 135 { 136 struct ath10k *ar = hw->priv; 137 138 spin_lock_bh(&ar->htt.tx_lock); 139 __ath10k_htt_tx_txq_recalc(hw, txq); 140 __ath10k_htt_tx_txq_sync(ar); 141 spin_unlock_bh(&ar->htt.tx_lock); 142 } 143 144 void ath10k_htt_tx_dec_pending(struct ath10k_htt *htt) 145 { 146 lockdep_assert_held(&htt->tx_lock); 147 148 htt->num_pending_tx--; 149 if (htt->num_pending_tx == htt->max_num_pending_tx - 1) 150 ath10k_mac_tx_unlock(htt->ar, ATH10K_TX_PAUSE_Q_FULL); 151 152 if (htt->num_pending_tx == 0) 153 wake_up(&htt->empty_tx_wq); 154 } 155 156 int ath10k_htt_tx_inc_pending(struct ath10k_htt *htt) 157 { 158 lockdep_assert_held(&htt->tx_lock); 159 160 if (htt->num_pending_tx >= htt->max_num_pending_tx) 161 return -EBUSY; 162 163 htt->num_pending_tx++; 164 if (htt->num_pending_tx == htt->max_num_pending_tx) 165 ath10k_mac_tx_lock(htt->ar, ATH10K_TX_PAUSE_Q_FULL); 166 167 return 0; 168 } 169 170 int ath10k_htt_tx_mgmt_inc_pending(struct ath10k_htt *htt, bool is_mgmt, 171 bool is_presp) 172 { 173 struct ath10k *ar = htt->ar; 174 175 lockdep_assert_held(&htt->tx_lock); 176 177 if (!is_mgmt || !ar->hw_params.max_probe_resp_desc_thres) 178 return 0; 179 180 if (is_presp && 181 ar->hw_params.max_probe_resp_desc_thres < htt->num_pending_mgmt_tx) 182 return -EBUSY; 183 184 htt->num_pending_mgmt_tx++; 185 186 return 0; 187 } 188 189 void ath10k_htt_tx_mgmt_dec_pending(struct ath10k_htt *htt) 190 { 191 lockdep_assert_held(&htt->tx_lock); 192 193 if (!htt->ar->hw_params.max_probe_resp_desc_thres) 194 return; 195 196 htt->num_pending_mgmt_tx--; 197 } 198 199 int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt, struct sk_buff *skb) 200 { 201 struct ath10k *ar = htt->ar; 202 int ret; 203 204 spin_lock_bh(&htt->tx_lock); 205 ret = idr_alloc(&htt->pending_tx, skb, 0, 206 htt->max_num_pending_tx, GFP_ATOMIC); 207 spin_unlock_bh(&htt->tx_lock); 208 209 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx alloc msdu_id %d\n", ret); 210 211 return ret; 212 } 213 214 void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id) 215 { 216 struct ath10k *ar = htt->ar; 217 218 lockdep_assert_held(&htt->tx_lock); 219 220 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx free msdu_id %u\n", msdu_id); 221 222 idr_remove(&htt->pending_tx, msdu_id); 223 } 224 225 static void ath10k_htt_tx_free_cont_txbuf_32(struct ath10k_htt *htt) 226 { 227 struct ath10k *ar = htt->ar; 228 size_t size; 229 230 if (!htt->txbuf.vaddr_txbuff_32) 231 return; 232 233 size = htt->txbuf.size; 234 dma_free_coherent(ar->dev, size, htt->txbuf.vaddr_txbuff_32, 235 htt->txbuf.paddr); 236 htt->txbuf.vaddr_txbuff_32 = NULL; 237 } 238 239 static int ath10k_htt_tx_alloc_cont_txbuf_32(struct ath10k_htt *htt) 240 { 241 struct ath10k *ar = htt->ar; 242 size_t size; 243 244 size = htt->max_num_pending_tx * 245 sizeof(struct ath10k_htt_txbuf_32); 246 247 htt->txbuf.vaddr_txbuff_32 = dma_alloc_coherent(ar->dev, size, 248 &htt->txbuf.paddr, 249 GFP_KERNEL); 250 if (!htt->txbuf.vaddr_txbuff_32) 251 return -ENOMEM; 252 253 htt->txbuf.size = size; 254 255 return 0; 256 } 257 258 static void ath10k_htt_tx_free_cont_txbuf_64(struct ath10k_htt *htt) 259 { 260 struct ath10k *ar = htt->ar; 261 size_t size; 262 263 if (!htt->txbuf.vaddr_txbuff_64) 264 return; 265 266 size = htt->txbuf.size; 267 dma_free_coherent(ar->dev, size, htt->txbuf.vaddr_txbuff_64, 268 htt->txbuf.paddr); 269 htt->txbuf.vaddr_txbuff_64 = NULL; 270 } 271 272 static int ath10k_htt_tx_alloc_cont_txbuf_64(struct ath10k_htt *htt) 273 { 274 struct ath10k *ar = htt->ar; 275 size_t size; 276 277 size = htt->max_num_pending_tx * 278 sizeof(struct ath10k_htt_txbuf_64); 279 280 htt->txbuf.vaddr_txbuff_64 = dma_alloc_coherent(ar->dev, size, 281 &htt->txbuf.paddr, 282 GFP_KERNEL); 283 if (!htt->txbuf.vaddr_txbuff_64) 284 return -ENOMEM; 285 286 htt->txbuf.size = size; 287 288 return 0; 289 } 290 291 static void ath10k_htt_tx_free_cont_frag_desc_32(struct ath10k_htt *htt) 292 { 293 size_t size; 294 295 if (!htt->frag_desc.vaddr_desc_32) 296 return; 297 298 size = htt->max_num_pending_tx * 299 sizeof(struct htt_msdu_ext_desc); 300 301 dma_free_coherent(htt->ar->dev, 302 size, 303 htt->frag_desc.vaddr_desc_32, 304 htt->frag_desc.paddr); 305 306 htt->frag_desc.vaddr_desc_32 = NULL; 307 } 308 309 static int ath10k_htt_tx_alloc_cont_frag_desc_32(struct ath10k_htt *htt) 310 { 311 struct ath10k *ar = htt->ar; 312 size_t size; 313 314 if (!ar->hw_params.continuous_frag_desc) 315 return 0; 316 317 size = htt->max_num_pending_tx * 318 sizeof(struct htt_msdu_ext_desc); 319 htt->frag_desc.vaddr_desc_32 = dma_alloc_coherent(ar->dev, size, 320 &htt->frag_desc.paddr, 321 GFP_KERNEL); 322 if (!htt->frag_desc.vaddr_desc_32) { 323 ath10k_err(ar, "failed to alloc fragment desc memory\n"); 324 return -ENOMEM; 325 } 326 htt->frag_desc.size = size; 327 328 return 0; 329 } 330 331 static void ath10k_htt_tx_free_cont_frag_desc_64(struct ath10k_htt *htt) 332 { 333 size_t size; 334 335 if (!htt->frag_desc.vaddr_desc_64) 336 return; 337 338 size = htt->max_num_pending_tx * 339 sizeof(struct htt_msdu_ext_desc_64); 340 341 dma_free_coherent(htt->ar->dev, 342 size, 343 htt->frag_desc.vaddr_desc_64, 344 htt->frag_desc.paddr); 345 346 htt->frag_desc.vaddr_desc_64 = NULL; 347 } 348 349 static int ath10k_htt_tx_alloc_cont_frag_desc_64(struct ath10k_htt *htt) 350 { 351 struct ath10k *ar = htt->ar; 352 size_t size; 353 354 if (!ar->hw_params.continuous_frag_desc) 355 return 0; 356 357 size = htt->max_num_pending_tx * 358 sizeof(struct htt_msdu_ext_desc_64); 359 360 htt->frag_desc.vaddr_desc_64 = dma_alloc_coherent(ar->dev, size, 361 &htt->frag_desc.paddr, 362 GFP_KERNEL); 363 if (!htt->frag_desc.vaddr_desc_64) { 364 ath10k_err(ar, "failed to alloc fragment desc memory\n"); 365 return -ENOMEM; 366 } 367 htt->frag_desc.size = size; 368 369 return 0; 370 } 371 372 static void ath10k_htt_tx_free_txq(struct ath10k_htt *htt) 373 { 374 struct ath10k *ar = htt->ar; 375 size_t size; 376 377 if (!test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, 378 ar->running_fw->fw_file.fw_features)) 379 return; 380 381 size = sizeof(*htt->tx_q_state.vaddr); 382 383 dma_unmap_single(ar->dev, htt->tx_q_state.paddr, size, DMA_TO_DEVICE); 384 kfree(htt->tx_q_state.vaddr); 385 } 386 387 static int ath10k_htt_tx_alloc_txq(struct ath10k_htt *htt) 388 { 389 struct ath10k *ar = htt->ar; 390 size_t size; 391 int ret; 392 393 if (!test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, 394 ar->running_fw->fw_file.fw_features)) 395 return 0; 396 397 htt->tx_q_state.num_peers = HTT_TX_Q_STATE_NUM_PEERS; 398 htt->tx_q_state.num_tids = HTT_TX_Q_STATE_NUM_TIDS; 399 htt->tx_q_state.type = HTT_Q_DEPTH_TYPE_BYTES; 400 401 size = sizeof(*htt->tx_q_state.vaddr); 402 htt->tx_q_state.vaddr = kzalloc(size, GFP_KERNEL); 403 if (!htt->tx_q_state.vaddr) 404 return -ENOMEM; 405 406 htt->tx_q_state.paddr = dma_map_single(ar->dev, htt->tx_q_state.vaddr, 407 size, DMA_TO_DEVICE); 408 ret = dma_mapping_error(ar->dev, htt->tx_q_state.paddr); 409 if (ret) { 410 ath10k_warn(ar, "failed to dma map tx_q_state: %d\n", ret); 411 kfree(htt->tx_q_state.vaddr); 412 return -EIO; 413 } 414 415 return 0; 416 } 417 418 static void ath10k_htt_tx_free_txdone_fifo(struct ath10k_htt *htt) 419 { 420 WARN_ON(!kfifo_is_empty(&htt->txdone_fifo)); 421 kfifo_free(&htt->txdone_fifo); 422 } 423 424 static int ath10k_htt_tx_alloc_txdone_fifo(struct ath10k_htt *htt) 425 { 426 int ret; 427 size_t size; 428 429 size = roundup_pow_of_two(htt->max_num_pending_tx); 430 ret = kfifo_alloc(&htt->txdone_fifo, size, GFP_KERNEL); 431 return ret; 432 } 433 434 static int ath10k_htt_tx_alloc_buf(struct ath10k_htt *htt) 435 { 436 struct ath10k *ar = htt->ar; 437 int ret; 438 439 ret = ath10k_htt_alloc_txbuff(htt); 440 if (ret) { 441 ath10k_err(ar, "failed to alloc cont tx buffer: %d\n", ret); 442 return ret; 443 } 444 445 ret = ath10k_htt_alloc_frag_desc(htt); 446 if (ret) { 447 ath10k_err(ar, "failed to alloc cont frag desc: %d\n", ret); 448 goto free_txbuf; 449 } 450 451 ret = ath10k_htt_tx_alloc_txq(htt); 452 if (ret) { 453 ath10k_err(ar, "failed to alloc txq: %d\n", ret); 454 goto free_frag_desc; 455 } 456 457 ret = ath10k_htt_tx_alloc_txdone_fifo(htt); 458 if (ret) { 459 ath10k_err(ar, "failed to alloc txdone fifo: %d\n", ret); 460 goto free_txq; 461 } 462 463 return 0; 464 465 free_txq: 466 ath10k_htt_tx_free_txq(htt); 467 468 free_frag_desc: 469 ath10k_htt_free_frag_desc(htt); 470 471 free_txbuf: 472 ath10k_htt_free_txbuff(htt); 473 474 return ret; 475 } 476 477 int ath10k_htt_tx_start(struct ath10k_htt *htt) 478 { 479 struct ath10k *ar = htt->ar; 480 int ret; 481 482 ath10k_dbg(ar, ATH10K_DBG_BOOT, "htt tx max num pending tx %d\n", 483 htt->max_num_pending_tx); 484 485 spin_lock_init(&htt->tx_lock); 486 idr_init(&htt->pending_tx); 487 488 if (htt->tx_mem_allocated) 489 return 0; 490 491 if (ar->bus_param.dev_type == ATH10K_DEV_TYPE_HL) 492 return 0; 493 494 ret = ath10k_htt_tx_alloc_buf(htt); 495 if (ret) 496 goto free_idr_pending_tx; 497 498 htt->tx_mem_allocated = true; 499 500 return 0; 501 502 free_idr_pending_tx: 503 idr_destroy(&htt->pending_tx); 504 505 return ret; 506 } 507 508 static void ath10k_htt_tx_clean_up_pending(int msdu_id, struct ath10k *ar) 509 { 510 struct ath10k_htt *htt = &ar->htt; 511 struct htt_tx_done tx_done = {}; 512 513 ath10k_dbg(ar, ATH10K_DBG_HTT, "force cleanup msdu_id %u\n", msdu_id); 514 515 tx_done.msdu_id = msdu_id; 516 tx_done.status = HTT_TX_COMPL_STATE_DISCARD; 517 518 ath10k_txrx_tx_unref(htt, &tx_done); 519 } 520 521 void ath10k_htt_tx_destroy(struct ath10k_htt *htt) 522 { 523 if (!htt->tx_mem_allocated) 524 return; 525 526 ath10k_htt_free_txbuff(htt); 527 ath10k_htt_tx_free_txq(htt); 528 ath10k_htt_free_frag_desc(htt); 529 ath10k_htt_tx_free_txdone_fifo(htt); 530 htt->tx_mem_allocated = false; 531 } 532 533 static void ath10k_htt_flush_tx_queue(struct ath10k_htt *htt) 534 { 535 struct sk_buff *msdu; 536 int msdu_id; 537 538 ath10k_htc_stop_hl(htt->ar); 539 540 idr_for_each_entry(&htt->pending_tx, msdu, msdu_id) 541 ath10k_htt_tx_clean_up_pending(msdu_id, htt->ar); 542 } 543 544 void ath10k_htt_tx_stop(struct ath10k_htt *htt) 545 { 546 ath10k_htt_flush_tx_queue(htt); 547 idr_destroy(&htt->pending_tx); 548 } 549 550 void ath10k_htt_tx_free(struct ath10k_htt *htt) 551 { 552 ath10k_htt_tx_stop(htt); 553 ath10k_htt_tx_destroy(htt); 554 } 555 556 void ath10k_htt_op_ep_tx_credits(struct ath10k *ar) 557 { 558 queue_work(ar->workqueue, &ar->bundle_tx_work); 559 } 560 561 void ath10k_htt_htc_tx_complete(struct ath10k *ar, struct sk_buff *skb) 562 { 563 struct ath10k_htt *htt = &ar->htt; 564 struct htt_tx_done tx_done = {}; 565 struct htt_cmd_hdr *htt_hdr; 566 struct htt_data_tx_desc *desc_hdr = NULL; 567 u16 flags1 = 0; 568 u8 msg_type = 0; 569 570 if (htt->disable_tx_comp) { 571 htt_hdr = (struct htt_cmd_hdr *)skb->data; 572 msg_type = htt_hdr->msg_type; 573 574 if (msg_type == HTT_H2T_MSG_TYPE_TX_FRM) { 575 desc_hdr = (struct htt_data_tx_desc *) 576 (skb->data + sizeof(*htt_hdr)); 577 flags1 = __le16_to_cpu(desc_hdr->flags1); 578 skb_pull(skb, sizeof(struct htt_cmd_hdr)); 579 skb_pull(skb, sizeof(struct htt_data_tx_desc)); 580 } 581 } 582 583 dev_kfree_skb_any(skb); 584 585 if ((!htt->disable_tx_comp) || (msg_type != HTT_H2T_MSG_TYPE_TX_FRM)) 586 return; 587 588 ath10k_dbg(ar, ATH10K_DBG_HTT, 589 "htt tx complete msdu id:%u ,flags1:%x\n", 590 __le16_to_cpu(desc_hdr->id), flags1); 591 592 if (flags1 & HTT_DATA_TX_DESC_FLAGS1_TX_COMPLETE) 593 return; 594 595 tx_done.status = HTT_TX_COMPL_STATE_ACK; 596 tx_done.msdu_id = __le16_to_cpu(desc_hdr->id); 597 ath10k_txrx_tx_unref(&ar->htt, &tx_done); 598 } 599 600 void ath10k_htt_hif_tx_complete(struct ath10k *ar, struct sk_buff *skb) 601 { 602 dev_kfree_skb_any(skb); 603 } 604 EXPORT_SYMBOL(ath10k_htt_hif_tx_complete); 605 606 int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt) 607 { 608 struct ath10k *ar = htt->ar; 609 struct sk_buff *skb; 610 struct htt_cmd *cmd; 611 int len = 0; 612 int ret; 613 614 len += sizeof(cmd->hdr); 615 len += sizeof(cmd->ver_req); 616 617 skb = ath10k_htc_alloc_skb(ar, len); 618 if (!skb) 619 return -ENOMEM; 620 621 skb_put(skb, len); 622 cmd = (struct htt_cmd *)skb->data; 623 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_VERSION_REQ; 624 625 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 626 if (ret) { 627 dev_kfree_skb_any(skb); 628 return ret; 629 } 630 631 return 0; 632 } 633 634 int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u32 mask, u32 reset_mask, 635 u64 cookie) 636 { 637 struct ath10k *ar = htt->ar; 638 struct htt_stats_req *req; 639 struct sk_buff *skb; 640 struct htt_cmd *cmd; 641 int len = 0, ret; 642 643 len += sizeof(cmd->hdr); 644 len += sizeof(cmd->stats_req); 645 646 skb = ath10k_htc_alloc_skb(ar, len); 647 if (!skb) 648 return -ENOMEM; 649 650 skb_put(skb, len); 651 cmd = (struct htt_cmd *)skb->data; 652 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_STATS_REQ; 653 654 req = &cmd->stats_req; 655 656 memset(req, 0, sizeof(*req)); 657 658 /* currently we support only max 24 bit masks so no need to worry 659 * about endian support 660 */ 661 memcpy(req->upload_types, &mask, 3); 662 memcpy(req->reset_types, &reset_mask, 3); 663 req->stat_type = HTT_STATS_REQ_CFG_STAT_TYPE_INVALID; 664 req->cookie_lsb = cpu_to_le32(cookie & 0xffffffff); 665 req->cookie_msb = cpu_to_le32((cookie & 0xffffffff00000000ULL) >> 32); 666 667 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 668 if (ret) { 669 ath10k_warn(ar, "failed to send htt type stats request: %d", 670 ret); 671 dev_kfree_skb_any(skb); 672 return ret; 673 } 674 675 return 0; 676 } 677 678 static int ath10k_htt_send_frag_desc_bank_cfg_32(struct ath10k_htt *htt) 679 { 680 struct ath10k *ar = htt->ar; 681 struct sk_buff *skb; 682 struct htt_cmd *cmd; 683 struct htt_frag_desc_bank_cfg32 *cfg; 684 int ret, size; 685 u8 info; 686 687 if (!ar->hw_params.continuous_frag_desc) 688 return 0; 689 690 if (!htt->frag_desc.paddr) { 691 ath10k_warn(ar, "invalid frag desc memory\n"); 692 return -EINVAL; 693 } 694 695 size = sizeof(cmd->hdr) + sizeof(cmd->frag_desc_bank_cfg32); 696 skb = ath10k_htc_alloc_skb(ar, size); 697 if (!skb) 698 return -ENOMEM; 699 700 skb_put(skb, size); 701 cmd = (struct htt_cmd *)skb->data; 702 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG; 703 704 info = 0; 705 info |= SM(htt->tx_q_state.type, 706 HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE); 707 708 if (test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, 709 ar->running_fw->fw_file.fw_features)) 710 info |= HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_VALID; 711 712 cfg = &cmd->frag_desc_bank_cfg32; 713 cfg->info = info; 714 cfg->num_banks = 1; 715 cfg->desc_size = sizeof(struct htt_msdu_ext_desc); 716 cfg->bank_base_addrs[0] = __cpu_to_le32(htt->frag_desc.paddr); 717 cfg->bank_id[0].bank_min_id = 0; 718 cfg->bank_id[0].bank_max_id = __cpu_to_le16(htt->max_num_pending_tx - 719 1); 720 721 cfg->q_state.paddr = cpu_to_le32(htt->tx_q_state.paddr); 722 cfg->q_state.num_peers = cpu_to_le16(htt->tx_q_state.num_peers); 723 cfg->q_state.num_tids = cpu_to_le16(htt->tx_q_state.num_tids); 724 cfg->q_state.record_size = HTT_TX_Q_STATE_ENTRY_SIZE; 725 cfg->q_state.record_multiplier = HTT_TX_Q_STATE_ENTRY_MULTIPLIER; 726 727 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt frag desc bank cmd\n"); 728 729 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 730 if (ret) { 731 ath10k_warn(ar, "failed to send frag desc bank cfg request: %d\n", 732 ret); 733 dev_kfree_skb_any(skb); 734 return ret; 735 } 736 737 return 0; 738 } 739 740 static int ath10k_htt_send_frag_desc_bank_cfg_64(struct ath10k_htt *htt) 741 { 742 struct ath10k *ar = htt->ar; 743 struct sk_buff *skb; 744 struct htt_cmd *cmd; 745 struct htt_frag_desc_bank_cfg64 *cfg; 746 int ret, size; 747 u8 info; 748 749 if (!ar->hw_params.continuous_frag_desc) 750 return 0; 751 752 if (!htt->frag_desc.paddr) { 753 ath10k_warn(ar, "invalid frag desc memory\n"); 754 return -EINVAL; 755 } 756 757 size = sizeof(cmd->hdr) + sizeof(cmd->frag_desc_bank_cfg64); 758 skb = ath10k_htc_alloc_skb(ar, size); 759 if (!skb) 760 return -ENOMEM; 761 762 skb_put(skb, size); 763 cmd = (struct htt_cmd *)skb->data; 764 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG; 765 766 info = 0; 767 info |= SM(htt->tx_q_state.type, 768 HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE); 769 770 if (test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, 771 ar->running_fw->fw_file.fw_features)) 772 info |= HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_VALID; 773 774 cfg = &cmd->frag_desc_bank_cfg64; 775 cfg->info = info; 776 cfg->num_banks = 1; 777 cfg->desc_size = sizeof(struct htt_msdu_ext_desc_64); 778 cfg->bank_base_addrs[0] = __cpu_to_le64(htt->frag_desc.paddr); 779 cfg->bank_id[0].bank_min_id = 0; 780 cfg->bank_id[0].bank_max_id = __cpu_to_le16(htt->max_num_pending_tx - 781 1); 782 783 cfg->q_state.paddr = cpu_to_le32(htt->tx_q_state.paddr); 784 cfg->q_state.num_peers = cpu_to_le16(htt->tx_q_state.num_peers); 785 cfg->q_state.num_tids = cpu_to_le16(htt->tx_q_state.num_tids); 786 cfg->q_state.record_size = HTT_TX_Q_STATE_ENTRY_SIZE; 787 cfg->q_state.record_multiplier = HTT_TX_Q_STATE_ENTRY_MULTIPLIER; 788 789 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt frag desc bank cmd\n"); 790 791 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 792 if (ret) { 793 ath10k_warn(ar, "failed to send frag desc bank cfg request: %d\n", 794 ret); 795 dev_kfree_skb_any(skb); 796 return ret; 797 } 798 799 return 0; 800 } 801 802 static void ath10k_htt_fill_rx_desc_offset_32(struct ath10k_hw_params *hw, 803 struct htt_rx_ring_setup_ring32 *rx_ring) 804 { 805 ath10k_htt_rx_desc_get_offsets(hw, &rx_ring->offsets); 806 } 807 808 static void ath10k_htt_fill_rx_desc_offset_64(struct ath10k_hw_params *hw, 809 struct htt_rx_ring_setup_ring64 *rx_ring) 810 { 811 ath10k_htt_rx_desc_get_offsets(hw, &rx_ring->offsets); 812 } 813 814 static int ath10k_htt_send_rx_ring_cfg_32(struct ath10k_htt *htt) 815 { 816 struct ath10k *ar = htt->ar; 817 struct ath10k_hw_params *hw = &ar->hw_params; 818 struct sk_buff *skb; 819 struct htt_cmd *cmd; 820 struct htt_rx_ring_setup_ring32 *ring; 821 const int num_rx_ring = 1; 822 u16 flags; 823 u32 fw_idx; 824 int len; 825 int ret; 826 827 /* 828 * the HW expects the buffer to be an integral number of 4-byte 829 * "words" 830 */ 831 BUILD_BUG_ON(!IS_ALIGNED(HTT_RX_BUF_SIZE, 4)); 832 BUILD_BUG_ON((HTT_RX_BUF_SIZE & HTT_MAX_CACHE_LINE_SIZE_MASK) != 0); 833 834 len = sizeof(cmd->hdr) + sizeof(cmd->rx_setup_32.hdr) 835 + (sizeof(*ring) * num_rx_ring); 836 skb = ath10k_htc_alloc_skb(ar, len); 837 if (!skb) 838 return -ENOMEM; 839 840 skb_put(skb, len); 841 842 cmd = (struct htt_cmd *)skb->data; 843 ring = &cmd->rx_setup_32.rings[0]; 844 845 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_RX_RING_CFG; 846 cmd->rx_setup_32.hdr.num_rings = 1; 847 848 /* FIXME: do we need all of this? */ 849 flags = 0; 850 flags |= HTT_RX_RING_FLAGS_MAC80211_HDR; 851 flags |= HTT_RX_RING_FLAGS_MSDU_PAYLOAD; 852 flags |= HTT_RX_RING_FLAGS_PPDU_START; 853 flags |= HTT_RX_RING_FLAGS_PPDU_END; 854 flags |= HTT_RX_RING_FLAGS_MPDU_START; 855 flags |= HTT_RX_RING_FLAGS_MPDU_END; 856 flags |= HTT_RX_RING_FLAGS_MSDU_START; 857 flags |= HTT_RX_RING_FLAGS_MSDU_END; 858 flags |= HTT_RX_RING_FLAGS_RX_ATTENTION; 859 flags |= HTT_RX_RING_FLAGS_FRAG_INFO; 860 flags |= HTT_RX_RING_FLAGS_UNICAST_RX; 861 flags |= HTT_RX_RING_FLAGS_MULTICAST_RX; 862 flags |= HTT_RX_RING_FLAGS_CTRL_RX; 863 flags |= HTT_RX_RING_FLAGS_MGMT_RX; 864 flags |= HTT_RX_RING_FLAGS_NULL_RX; 865 flags |= HTT_RX_RING_FLAGS_PHY_DATA_RX; 866 867 fw_idx = __le32_to_cpu(*htt->rx_ring.alloc_idx.vaddr); 868 869 ring->fw_idx_shadow_reg_paddr = 870 __cpu_to_le32(htt->rx_ring.alloc_idx.paddr); 871 ring->rx_ring_base_paddr = __cpu_to_le32(htt->rx_ring.base_paddr); 872 ring->rx_ring_len = __cpu_to_le16(htt->rx_ring.size); 873 ring->rx_ring_bufsize = __cpu_to_le16(HTT_RX_BUF_SIZE); 874 ring->flags = __cpu_to_le16(flags); 875 ring->fw_idx_init_val = __cpu_to_le16(fw_idx); 876 877 ath10k_htt_fill_rx_desc_offset_32(hw, ring); 878 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 879 if (ret) { 880 dev_kfree_skb_any(skb); 881 return ret; 882 } 883 884 return 0; 885 } 886 887 static int ath10k_htt_send_rx_ring_cfg_64(struct ath10k_htt *htt) 888 { 889 struct ath10k *ar = htt->ar; 890 struct ath10k_hw_params *hw = &ar->hw_params; 891 struct sk_buff *skb; 892 struct htt_cmd *cmd; 893 struct htt_rx_ring_setup_ring64 *ring; 894 const int num_rx_ring = 1; 895 u16 flags; 896 u32 fw_idx; 897 int len; 898 int ret; 899 900 /* HW expects the buffer to be an integral number of 4-byte 901 * "words" 902 */ 903 BUILD_BUG_ON(!IS_ALIGNED(HTT_RX_BUF_SIZE, 4)); 904 BUILD_BUG_ON((HTT_RX_BUF_SIZE & HTT_MAX_CACHE_LINE_SIZE_MASK) != 0); 905 906 len = sizeof(cmd->hdr) + sizeof(cmd->rx_setup_64.hdr) 907 + (sizeof(*ring) * num_rx_ring); 908 skb = ath10k_htc_alloc_skb(ar, len); 909 if (!skb) 910 return -ENOMEM; 911 912 skb_put(skb, len); 913 914 cmd = (struct htt_cmd *)skb->data; 915 ring = &cmd->rx_setup_64.rings[0]; 916 917 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_RX_RING_CFG; 918 cmd->rx_setup_64.hdr.num_rings = 1; 919 920 flags = 0; 921 flags |= HTT_RX_RING_FLAGS_MAC80211_HDR; 922 flags |= HTT_RX_RING_FLAGS_MSDU_PAYLOAD; 923 flags |= HTT_RX_RING_FLAGS_PPDU_START; 924 flags |= HTT_RX_RING_FLAGS_PPDU_END; 925 flags |= HTT_RX_RING_FLAGS_MPDU_START; 926 flags |= HTT_RX_RING_FLAGS_MPDU_END; 927 flags |= HTT_RX_RING_FLAGS_MSDU_START; 928 flags |= HTT_RX_RING_FLAGS_MSDU_END; 929 flags |= HTT_RX_RING_FLAGS_RX_ATTENTION; 930 flags |= HTT_RX_RING_FLAGS_FRAG_INFO; 931 flags |= HTT_RX_RING_FLAGS_UNICAST_RX; 932 flags |= HTT_RX_RING_FLAGS_MULTICAST_RX; 933 flags |= HTT_RX_RING_FLAGS_CTRL_RX; 934 flags |= HTT_RX_RING_FLAGS_MGMT_RX; 935 flags |= HTT_RX_RING_FLAGS_NULL_RX; 936 flags |= HTT_RX_RING_FLAGS_PHY_DATA_RX; 937 938 fw_idx = __le32_to_cpu(*htt->rx_ring.alloc_idx.vaddr); 939 940 ring->fw_idx_shadow_reg_paddr = __cpu_to_le64(htt->rx_ring.alloc_idx.paddr); 941 ring->rx_ring_base_paddr = __cpu_to_le64(htt->rx_ring.base_paddr); 942 ring->rx_ring_len = __cpu_to_le16(htt->rx_ring.size); 943 ring->rx_ring_bufsize = __cpu_to_le16(HTT_RX_BUF_SIZE); 944 ring->flags = __cpu_to_le16(flags); 945 ring->fw_idx_init_val = __cpu_to_le16(fw_idx); 946 947 ath10k_htt_fill_rx_desc_offset_64(hw, ring); 948 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 949 if (ret) { 950 dev_kfree_skb_any(skb); 951 return ret; 952 } 953 954 return 0; 955 } 956 957 static int ath10k_htt_send_rx_ring_cfg_hl(struct ath10k_htt *htt) 958 { 959 struct ath10k *ar = htt->ar; 960 struct sk_buff *skb; 961 struct htt_cmd *cmd; 962 struct htt_rx_ring_setup_ring32 *ring; 963 const int num_rx_ring = 1; 964 u16 flags; 965 int len; 966 int ret; 967 968 /* 969 * the HW expects the buffer to be an integral number of 4-byte 970 * "words" 971 */ 972 BUILD_BUG_ON(!IS_ALIGNED(HTT_RX_BUF_SIZE, 4)); 973 BUILD_BUG_ON((HTT_RX_BUF_SIZE & HTT_MAX_CACHE_LINE_SIZE_MASK) != 0); 974 975 len = sizeof(cmd->hdr) + sizeof(cmd->rx_setup_32.hdr) 976 + (sizeof(*ring) * num_rx_ring); 977 skb = ath10k_htc_alloc_skb(ar, len); 978 if (!skb) 979 return -ENOMEM; 980 981 skb_put(skb, len); 982 983 cmd = (struct htt_cmd *)skb->data; 984 ring = &cmd->rx_setup_32.rings[0]; 985 986 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_RX_RING_CFG; 987 cmd->rx_setup_32.hdr.num_rings = 1; 988 989 flags = 0; 990 flags |= HTT_RX_RING_FLAGS_MSDU_PAYLOAD; 991 flags |= HTT_RX_RING_FLAGS_UNICAST_RX; 992 flags |= HTT_RX_RING_FLAGS_MULTICAST_RX; 993 994 memset(ring, 0, sizeof(*ring)); 995 ring->rx_ring_len = __cpu_to_le16(HTT_RX_RING_SIZE_MIN); 996 ring->rx_ring_bufsize = __cpu_to_le16(HTT_RX_BUF_SIZE); 997 ring->flags = __cpu_to_le16(flags); 998 999 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 1000 if (ret) { 1001 dev_kfree_skb_any(skb); 1002 return ret; 1003 } 1004 1005 return 0; 1006 } 1007 1008 static int ath10k_htt_h2t_aggr_cfg_msg_32(struct ath10k_htt *htt, 1009 u8 max_subfrms_ampdu, 1010 u8 max_subfrms_amsdu) 1011 { 1012 struct ath10k *ar = htt->ar; 1013 struct htt_aggr_conf *aggr_conf; 1014 struct sk_buff *skb; 1015 struct htt_cmd *cmd; 1016 int len; 1017 int ret; 1018 1019 /* Firmware defaults are: amsdu = 3 and ampdu = 64 */ 1020 1021 if (max_subfrms_ampdu == 0 || max_subfrms_ampdu > 64) 1022 return -EINVAL; 1023 1024 if (max_subfrms_amsdu == 0 || max_subfrms_amsdu > 31) 1025 return -EINVAL; 1026 1027 len = sizeof(cmd->hdr); 1028 len += sizeof(cmd->aggr_conf); 1029 1030 skb = ath10k_htc_alloc_skb(ar, len); 1031 if (!skb) 1032 return -ENOMEM; 1033 1034 skb_put(skb, len); 1035 cmd = (struct htt_cmd *)skb->data; 1036 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_AGGR_CFG; 1037 1038 aggr_conf = &cmd->aggr_conf; 1039 aggr_conf->max_num_ampdu_subframes = max_subfrms_ampdu; 1040 aggr_conf->max_num_amsdu_subframes = max_subfrms_amsdu; 1041 1042 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt h2t aggr cfg msg amsdu %d ampdu %d", 1043 aggr_conf->max_num_amsdu_subframes, 1044 aggr_conf->max_num_ampdu_subframes); 1045 1046 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 1047 if (ret) { 1048 dev_kfree_skb_any(skb); 1049 return ret; 1050 } 1051 1052 return 0; 1053 } 1054 1055 static int ath10k_htt_h2t_aggr_cfg_msg_v2(struct ath10k_htt *htt, 1056 u8 max_subfrms_ampdu, 1057 u8 max_subfrms_amsdu) 1058 { 1059 struct ath10k *ar = htt->ar; 1060 struct htt_aggr_conf_v2 *aggr_conf; 1061 struct sk_buff *skb; 1062 struct htt_cmd *cmd; 1063 int len; 1064 int ret; 1065 1066 /* Firmware defaults are: amsdu = 3 and ampdu = 64 */ 1067 1068 if (max_subfrms_ampdu == 0 || max_subfrms_ampdu > 64) 1069 return -EINVAL; 1070 1071 if (max_subfrms_amsdu == 0 || max_subfrms_amsdu > 31) 1072 return -EINVAL; 1073 1074 len = sizeof(cmd->hdr); 1075 len += sizeof(cmd->aggr_conf_v2); 1076 1077 skb = ath10k_htc_alloc_skb(ar, len); 1078 if (!skb) 1079 return -ENOMEM; 1080 1081 skb_put(skb, len); 1082 cmd = (struct htt_cmd *)skb->data; 1083 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_AGGR_CFG; 1084 1085 aggr_conf = &cmd->aggr_conf_v2; 1086 aggr_conf->max_num_ampdu_subframes = max_subfrms_ampdu; 1087 aggr_conf->max_num_amsdu_subframes = max_subfrms_amsdu; 1088 1089 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt h2t aggr cfg msg amsdu %d ampdu %d", 1090 aggr_conf->max_num_amsdu_subframes, 1091 aggr_conf->max_num_ampdu_subframes); 1092 1093 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 1094 if (ret) { 1095 dev_kfree_skb_any(skb); 1096 return ret; 1097 } 1098 1099 return 0; 1100 } 1101 1102 int ath10k_htt_tx_fetch_resp(struct ath10k *ar, 1103 __le32 token, 1104 __le16 fetch_seq_num, 1105 struct htt_tx_fetch_record *records, 1106 size_t num_records) 1107 { 1108 struct sk_buff *skb; 1109 struct htt_cmd *cmd; 1110 const u16 resp_id = 0; 1111 int len = 0; 1112 int ret; 1113 1114 /* Response IDs are echo-ed back only for host driver convenience 1115 * purposes. They aren't used for anything in the driver yet so use 0. 1116 */ 1117 1118 len += sizeof(cmd->hdr); 1119 len += sizeof(cmd->tx_fetch_resp); 1120 len += sizeof(cmd->tx_fetch_resp.records[0]) * num_records; 1121 1122 skb = ath10k_htc_alloc_skb(ar, len); 1123 if (!skb) 1124 return -ENOMEM; 1125 1126 skb_put(skb, len); 1127 cmd = (struct htt_cmd *)skb->data; 1128 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_TX_FETCH_RESP; 1129 cmd->tx_fetch_resp.resp_id = cpu_to_le16(resp_id); 1130 cmd->tx_fetch_resp.fetch_seq_num = fetch_seq_num; 1131 cmd->tx_fetch_resp.num_records = cpu_to_le16(num_records); 1132 cmd->tx_fetch_resp.token = token; 1133 1134 memcpy(cmd->tx_fetch_resp.records, records, 1135 sizeof(records[0]) * num_records); 1136 1137 ret = ath10k_htc_send(&ar->htc, ar->htt.eid, skb); 1138 if (ret) { 1139 ath10k_warn(ar, "failed to submit htc command: %d\n", ret); 1140 goto err_free_skb; 1141 } 1142 1143 return 0; 1144 1145 err_free_skb: 1146 dev_kfree_skb_any(skb); 1147 1148 return ret; 1149 } 1150 1151 static u8 ath10k_htt_tx_get_vdev_id(struct ath10k *ar, struct sk_buff *skb) 1152 { 1153 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1154 struct ath10k_skb_cb *cb = ATH10K_SKB_CB(skb); 1155 struct ath10k_vif *arvif; 1156 1157 if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN) { 1158 return ar->scan.vdev_id; 1159 } else if (cb->vif) { 1160 arvif = (void *)cb->vif->drv_priv; 1161 return arvif->vdev_id; 1162 } else if (ar->monitor_started) { 1163 return ar->monitor_vdev_id; 1164 } else { 1165 return 0; 1166 } 1167 } 1168 1169 static u8 ath10k_htt_tx_get_tid(struct sk_buff *skb, bool is_eth) 1170 { 1171 struct ieee80211_hdr *hdr = (void *)skb->data; 1172 struct ath10k_skb_cb *cb = ATH10K_SKB_CB(skb); 1173 1174 if (!is_eth && ieee80211_is_mgmt(hdr->frame_control)) 1175 return HTT_DATA_TX_EXT_TID_MGMT; 1176 else if (cb->flags & ATH10K_SKB_F_QOS) 1177 return skb->priority & IEEE80211_QOS_CTL_TID_MASK; 1178 else 1179 return HTT_DATA_TX_EXT_TID_NON_QOS_MCAST_BCAST; 1180 } 1181 1182 int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *msdu) 1183 { 1184 struct ath10k *ar = htt->ar; 1185 struct device *dev = ar->dev; 1186 struct sk_buff *txdesc = NULL; 1187 struct htt_cmd *cmd; 1188 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu); 1189 u8 vdev_id = ath10k_htt_tx_get_vdev_id(ar, msdu); 1190 int len = 0; 1191 int msdu_id = -1; 1192 int res; 1193 const u8 *peer_addr; 1194 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data; 1195 1196 len += sizeof(cmd->hdr); 1197 len += sizeof(cmd->mgmt_tx); 1198 1199 res = ath10k_htt_tx_alloc_msdu_id(htt, msdu); 1200 if (res < 0) 1201 goto err; 1202 1203 msdu_id = res; 1204 1205 if ((ieee80211_is_action(hdr->frame_control) || 1206 ieee80211_is_deauth(hdr->frame_control) || 1207 ieee80211_is_disassoc(hdr->frame_control)) && 1208 ieee80211_has_protected(hdr->frame_control)) { 1209 peer_addr = hdr->addr1; 1210 if (is_multicast_ether_addr(peer_addr)) { 1211 skb_put(msdu, sizeof(struct ieee80211_mmie_16)); 1212 } else { 1213 if (skb_cb->ucast_cipher == WLAN_CIPHER_SUITE_GCMP || 1214 skb_cb->ucast_cipher == WLAN_CIPHER_SUITE_GCMP_256) 1215 skb_put(msdu, IEEE80211_GCMP_MIC_LEN); 1216 else 1217 skb_put(msdu, IEEE80211_CCMP_MIC_LEN); 1218 } 1219 } 1220 1221 txdesc = ath10k_htc_alloc_skb(ar, len); 1222 if (!txdesc) { 1223 res = -ENOMEM; 1224 goto err_free_msdu_id; 1225 } 1226 1227 skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len, 1228 DMA_TO_DEVICE); 1229 res = dma_mapping_error(dev, skb_cb->paddr); 1230 if (res) { 1231 res = -EIO; 1232 goto err_free_txdesc; 1233 } 1234 1235 skb_put(txdesc, len); 1236 cmd = (struct htt_cmd *)txdesc->data; 1237 memset(cmd, 0, len); 1238 1239 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_MGMT_TX; 1240 cmd->mgmt_tx.msdu_paddr = __cpu_to_le32(ATH10K_SKB_CB(msdu)->paddr); 1241 cmd->mgmt_tx.len = __cpu_to_le32(msdu->len); 1242 cmd->mgmt_tx.desc_id = __cpu_to_le32(msdu_id); 1243 cmd->mgmt_tx.vdev_id = __cpu_to_le32(vdev_id); 1244 memcpy(cmd->mgmt_tx.hdr, msdu->data, 1245 min_t(int, msdu->len, HTT_MGMT_FRM_HDR_DOWNLOAD_LEN)); 1246 1247 res = ath10k_htc_send(&htt->ar->htc, htt->eid, txdesc); 1248 if (res) 1249 goto err_unmap_msdu; 1250 1251 return 0; 1252 1253 err_unmap_msdu: 1254 if (ar->bus_param.dev_type != ATH10K_DEV_TYPE_HL) 1255 dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 1256 err_free_txdesc: 1257 dev_kfree_skb_any(txdesc); 1258 err_free_msdu_id: 1259 spin_lock_bh(&htt->tx_lock); 1260 ath10k_htt_tx_free_msdu_id(htt, msdu_id); 1261 spin_unlock_bh(&htt->tx_lock); 1262 err: 1263 return res; 1264 } 1265 1266 #define HTT_TX_HL_NEEDED_HEADROOM \ 1267 (unsigned int)(sizeof(struct htt_cmd_hdr) + \ 1268 sizeof(struct htt_data_tx_desc) + \ 1269 sizeof(struct ath10k_htc_hdr)) 1270 1271 static int ath10k_htt_tx_hl(struct ath10k_htt *htt, enum ath10k_hw_txrx_mode txmode, 1272 struct sk_buff *msdu) 1273 { 1274 struct ath10k *ar = htt->ar; 1275 int res, data_len; 1276 struct htt_cmd_hdr *cmd_hdr; 1277 struct htt_data_tx_desc *tx_desc; 1278 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu); 1279 struct sk_buff *tmp_skb; 1280 bool is_eth = (txmode == ATH10K_HW_TXRX_ETHERNET); 1281 u8 vdev_id = ath10k_htt_tx_get_vdev_id(ar, msdu); 1282 u8 tid = ath10k_htt_tx_get_tid(msdu, is_eth); 1283 u8 flags0 = 0; 1284 u16 flags1 = 0; 1285 u16 msdu_id = 0; 1286 1287 if (!is_eth) { 1288 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data; 1289 1290 if ((ieee80211_is_action(hdr->frame_control) || 1291 ieee80211_is_deauth(hdr->frame_control) || 1292 ieee80211_is_disassoc(hdr->frame_control)) && 1293 ieee80211_has_protected(hdr->frame_control)) { 1294 skb_put(msdu, IEEE80211_CCMP_MIC_LEN); 1295 } 1296 } 1297 1298 data_len = msdu->len; 1299 1300 switch (txmode) { 1301 case ATH10K_HW_TXRX_RAW: 1302 case ATH10K_HW_TXRX_NATIVE_WIFI: 1303 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT; 1304 fallthrough; 1305 case ATH10K_HW_TXRX_ETHERNET: 1306 flags0 |= SM(txmode, HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); 1307 break; 1308 case ATH10K_HW_TXRX_MGMT: 1309 flags0 |= SM(ATH10K_HW_TXRX_MGMT, 1310 HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); 1311 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT; 1312 1313 if (htt->disable_tx_comp) 1314 flags1 |= HTT_DATA_TX_DESC_FLAGS1_TX_COMPLETE; 1315 break; 1316 } 1317 1318 if (skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT) 1319 flags0 |= HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT; 1320 1321 flags1 |= SM((u16)vdev_id, HTT_DATA_TX_DESC_FLAGS1_VDEV_ID); 1322 flags1 |= SM((u16)tid, HTT_DATA_TX_DESC_FLAGS1_EXT_TID); 1323 if (msdu->ip_summed == CHECKSUM_PARTIAL && 1324 !test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) { 1325 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD; 1326 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD; 1327 } 1328 1329 /* Prepend the HTT header and TX desc struct to the data message 1330 * and realloc the skb if it does not have enough headroom. 1331 */ 1332 if (skb_headroom(msdu) < HTT_TX_HL_NEEDED_HEADROOM) { 1333 tmp_skb = msdu; 1334 1335 ath10k_dbg(htt->ar, ATH10K_DBG_HTT, 1336 "Not enough headroom in skb. Current headroom: %u, needed: %u. Reallocating...\n", 1337 skb_headroom(msdu), HTT_TX_HL_NEEDED_HEADROOM); 1338 msdu = skb_realloc_headroom(msdu, HTT_TX_HL_NEEDED_HEADROOM); 1339 kfree_skb(tmp_skb); 1340 if (!msdu) { 1341 ath10k_warn(htt->ar, "htt hl tx: Unable to realloc skb!\n"); 1342 res = -ENOMEM; 1343 goto out; 1344 } 1345 } 1346 1347 if (ar->bus_param.hl_msdu_ids) { 1348 flags1 |= HTT_DATA_TX_DESC_FLAGS1_POSTPONED; 1349 res = ath10k_htt_tx_alloc_msdu_id(htt, msdu); 1350 if (res < 0) { 1351 ath10k_err(ar, "msdu_id allocation failed %d\n", res); 1352 goto out; 1353 } 1354 msdu_id = res; 1355 } 1356 1357 /* As msdu is freed by mac80211 (in ieee80211_tx_status_skb()) and by 1358 * ath10k (in ath10k_htt_htc_tx_complete()) we have to increase 1359 * reference by one to avoid a use-after-free case and a double 1360 * free. 1361 */ 1362 skb_get(msdu); 1363 1364 skb_push(msdu, sizeof(*cmd_hdr)); 1365 skb_push(msdu, sizeof(*tx_desc)); 1366 cmd_hdr = (struct htt_cmd_hdr *)msdu->data; 1367 tx_desc = (struct htt_data_tx_desc *)(msdu->data + sizeof(*cmd_hdr)); 1368 1369 cmd_hdr->msg_type = HTT_H2T_MSG_TYPE_TX_FRM; 1370 tx_desc->flags0 = flags0; 1371 tx_desc->flags1 = __cpu_to_le16(flags1); 1372 tx_desc->len = __cpu_to_le16(data_len); 1373 tx_desc->id = __cpu_to_le16(msdu_id); 1374 tx_desc->frags_paddr = 0; /* always zero */ 1375 /* Initialize peer_id to INVALID_PEER because this is NOT 1376 * Reinjection path 1377 */ 1378 tx_desc->peerid = __cpu_to_le32(HTT_INVALID_PEERID); 1379 1380 res = ath10k_htc_send_hl(&htt->ar->htc, htt->eid, msdu); 1381 1382 out: 1383 return res; 1384 } 1385 1386 static int ath10k_htt_tx_32(struct ath10k_htt *htt, 1387 enum ath10k_hw_txrx_mode txmode, 1388 struct sk_buff *msdu) 1389 { 1390 struct ath10k *ar = htt->ar; 1391 struct device *dev = ar->dev; 1392 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(msdu); 1393 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu); 1394 struct ath10k_hif_sg_item sg_items[2]; 1395 struct ath10k_htt_txbuf_32 *txbuf; 1396 struct htt_data_tx_desc_frag *frags; 1397 bool is_eth = (txmode == ATH10K_HW_TXRX_ETHERNET); 1398 u8 vdev_id = ath10k_htt_tx_get_vdev_id(ar, msdu); 1399 u8 tid = ath10k_htt_tx_get_tid(msdu, is_eth); 1400 int prefetch_len; 1401 int res; 1402 u8 flags0 = 0; 1403 u16 msdu_id, flags1 = 0; 1404 u16 freq = 0; 1405 u32 frags_paddr = 0; 1406 u32 txbuf_paddr; 1407 struct htt_msdu_ext_desc *ext_desc = NULL; 1408 struct htt_msdu_ext_desc *ext_desc_t = NULL; 1409 1410 res = ath10k_htt_tx_alloc_msdu_id(htt, msdu); 1411 if (res < 0) 1412 goto err; 1413 1414 msdu_id = res; 1415 1416 prefetch_len = min(htt->prefetch_len, msdu->len); 1417 prefetch_len = roundup(prefetch_len, 4); 1418 1419 txbuf = htt->txbuf.vaddr_txbuff_32 + msdu_id; 1420 txbuf_paddr = htt->txbuf.paddr + 1421 (sizeof(struct ath10k_htt_txbuf_32) * msdu_id); 1422 1423 if (!is_eth) { 1424 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data; 1425 1426 if ((ieee80211_is_action(hdr->frame_control) || 1427 ieee80211_is_deauth(hdr->frame_control) || 1428 ieee80211_is_disassoc(hdr->frame_control)) && 1429 ieee80211_has_protected(hdr->frame_control)) { 1430 skb_put(msdu, IEEE80211_CCMP_MIC_LEN); 1431 } else if (!(skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT) && 1432 txmode == ATH10K_HW_TXRX_RAW && 1433 ieee80211_has_protected(hdr->frame_control)) { 1434 skb_put(msdu, IEEE80211_CCMP_MIC_LEN); 1435 } 1436 } 1437 1438 skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len, 1439 DMA_TO_DEVICE); 1440 res = dma_mapping_error(dev, skb_cb->paddr); 1441 if (res) { 1442 res = -EIO; 1443 goto err_free_msdu_id; 1444 } 1445 1446 if (unlikely(info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)) 1447 freq = ar->scan.roc_freq; 1448 1449 switch (txmode) { 1450 case ATH10K_HW_TXRX_RAW: 1451 case ATH10K_HW_TXRX_NATIVE_WIFI: 1452 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT; 1453 fallthrough; 1454 case ATH10K_HW_TXRX_ETHERNET: 1455 if (ar->hw_params.continuous_frag_desc) { 1456 ext_desc_t = htt->frag_desc.vaddr_desc_32; 1457 memset(&ext_desc_t[msdu_id], 0, 1458 sizeof(struct htt_msdu_ext_desc)); 1459 frags = (struct htt_data_tx_desc_frag *) 1460 &ext_desc_t[msdu_id].frags; 1461 ext_desc = &ext_desc_t[msdu_id]; 1462 frags[0].tword_addr.paddr_lo = 1463 __cpu_to_le32(skb_cb->paddr); 1464 frags[0].tword_addr.paddr_hi = 0; 1465 frags[0].tword_addr.len_16 = __cpu_to_le16(msdu->len); 1466 1467 frags_paddr = htt->frag_desc.paddr + 1468 (sizeof(struct htt_msdu_ext_desc) * msdu_id); 1469 } else { 1470 frags = txbuf->frags; 1471 frags[0].dword_addr.paddr = 1472 __cpu_to_le32(skb_cb->paddr); 1473 frags[0].dword_addr.len = __cpu_to_le32(msdu->len); 1474 frags[1].dword_addr.paddr = 0; 1475 frags[1].dword_addr.len = 0; 1476 1477 frags_paddr = txbuf_paddr; 1478 } 1479 flags0 |= SM(txmode, HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); 1480 break; 1481 case ATH10K_HW_TXRX_MGMT: 1482 flags0 |= SM(ATH10K_HW_TXRX_MGMT, 1483 HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); 1484 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT; 1485 1486 frags_paddr = skb_cb->paddr; 1487 break; 1488 } 1489 1490 /* Normally all commands go through HTC which manages tx credits for 1491 * each endpoint and notifies when tx is completed. 1492 * 1493 * HTT endpoint is creditless so there's no need to care about HTC 1494 * flags. In that case it is trivial to fill the HTC header here. 1495 * 1496 * MSDU transmission is considered completed upon HTT event. This 1497 * implies no relevant resources can be freed until after the event is 1498 * received. That's why HTC tx completion handler itself is ignored by 1499 * setting NULL to transfer_context for all sg items. 1500 * 1501 * There is simply no point in pushing HTT TX_FRM through HTC tx path 1502 * as it's a waste of resources. By bypassing HTC it is possible to 1503 * avoid extra memory allocations, compress data structures and thus 1504 * improve performance. 1505 */ 1506 1507 txbuf->htc_hdr.eid = htt->eid; 1508 txbuf->htc_hdr.len = __cpu_to_le16(sizeof(txbuf->cmd_hdr) + 1509 sizeof(txbuf->cmd_tx) + 1510 prefetch_len); 1511 txbuf->htc_hdr.flags = 0; 1512 1513 if (skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT) 1514 flags0 |= HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT; 1515 1516 flags1 |= SM((u16)vdev_id, HTT_DATA_TX_DESC_FLAGS1_VDEV_ID); 1517 flags1 |= SM((u16)tid, HTT_DATA_TX_DESC_FLAGS1_EXT_TID); 1518 if (msdu->ip_summed == CHECKSUM_PARTIAL && 1519 !test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) { 1520 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD; 1521 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD; 1522 if (ar->hw_params.continuous_frag_desc) 1523 ext_desc->flags |= HTT_MSDU_CHECKSUM_ENABLE; 1524 } 1525 1526 /* Prevent firmware from sending up tx inspection requests. There's 1527 * nothing ath10k can do with frames requested for inspection so force 1528 * it to simply rely a regular tx completion with discard status. 1529 */ 1530 flags1 |= HTT_DATA_TX_DESC_FLAGS1_POSTPONED; 1531 1532 txbuf->cmd_hdr.msg_type = HTT_H2T_MSG_TYPE_TX_FRM; 1533 txbuf->cmd_tx.flags0 = flags0; 1534 txbuf->cmd_tx.flags1 = __cpu_to_le16(flags1); 1535 txbuf->cmd_tx.len = __cpu_to_le16(msdu->len); 1536 txbuf->cmd_tx.id = __cpu_to_le16(msdu_id); 1537 txbuf->cmd_tx.frags_paddr = __cpu_to_le32(frags_paddr); 1538 if (ath10k_mac_tx_frm_has_freq(ar)) { 1539 txbuf->cmd_tx.offchan_tx.peerid = 1540 __cpu_to_le16(HTT_INVALID_PEERID); 1541 txbuf->cmd_tx.offchan_tx.freq = 1542 __cpu_to_le16(freq); 1543 } else { 1544 txbuf->cmd_tx.peerid = 1545 __cpu_to_le32(HTT_INVALID_PEERID); 1546 } 1547 1548 trace_ath10k_htt_tx(ar, msdu_id, msdu->len, vdev_id, tid); 1549 ath10k_dbg(ar, ATH10K_DBG_HTT, 1550 "htt tx flags0 %u flags1 %u len %d id %u frags_paddr %pad, msdu_paddr %pad vdev %u tid %u freq %u\n", 1551 flags0, flags1, msdu->len, msdu_id, &frags_paddr, 1552 &skb_cb->paddr, vdev_id, tid, freq); 1553 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt tx msdu: ", 1554 msdu->data, msdu->len); 1555 trace_ath10k_tx_hdr(ar, msdu->data, msdu->len); 1556 trace_ath10k_tx_payload(ar, msdu->data, msdu->len); 1557 1558 sg_items[0].transfer_id = 0; 1559 sg_items[0].transfer_context = NULL; 1560 sg_items[0].vaddr = &txbuf->htc_hdr; 1561 sg_items[0].paddr = txbuf_paddr + 1562 sizeof(txbuf->frags); 1563 sg_items[0].len = sizeof(txbuf->htc_hdr) + 1564 sizeof(txbuf->cmd_hdr) + 1565 sizeof(txbuf->cmd_tx); 1566 1567 sg_items[1].transfer_id = 0; 1568 sg_items[1].transfer_context = NULL; 1569 sg_items[1].vaddr = msdu->data; 1570 sg_items[1].paddr = skb_cb->paddr; 1571 sg_items[1].len = prefetch_len; 1572 1573 res = ath10k_hif_tx_sg(htt->ar, 1574 htt->ar->htc.endpoint[htt->eid].ul_pipe_id, 1575 sg_items, ARRAY_SIZE(sg_items)); 1576 if (res) 1577 goto err_unmap_msdu; 1578 1579 return 0; 1580 1581 err_unmap_msdu: 1582 dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 1583 err_free_msdu_id: 1584 spin_lock_bh(&htt->tx_lock); 1585 ath10k_htt_tx_free_msdu_id(htt, msdu_id); 1586 spin_unlock_bh(&htt->tx_lock); 1587 err: 1588 return res; 1589 } 1590 1591 static int ath10k_htt_tx_64(struct ath10k_htt *htt, 1592 enum ath10k_hw_txrx_mode txmode, 1593 struct sk_buff *msdu) 1594 { 1595 struct ath10k *ar = htt->ar; 1596 struct device *dev = ar->dev; 1597 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(msdu); 1598 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu); 1599 struct ath10k_hif_sg_item sg_items[2]; 1600 struct ath10k_htt_txbuf_64 *txbuf; 1601 struct htt_data_tx_desc_frag *frags; 1602 bool is_eth = (txmode == ATH10K_HW_TXRX_ETHERNET); 1603 u8 vdev_id = ath10k_htt_tx_get_vdev_id(ar, msdu); 1604 u8 tid = ath10k_htt_tx_get_tid(msdu, is_eth); 1605 int prefetch_len; 1606 int res; 1607 u8 flags0 = 0; 1608 u16 msdu_id, flags1 = 0; 1609 u16 freq = 0; 1610 dma_addr_t frags_paddr = 0; 1611 dma_addr_t txbuf_paddr; 1612 struct htt_msdu_ext_desc_64 *ext_desc = NULL; 1613 struct htt_msdu_ext_desc_64 *ext_desc_t = NULL; 1614 1615 res = ath10k_htt_tx_alloc_msdu_id(htt, msdu); 1616 if (res < 0) 1617 goto err; 1618 1619 msdu_id = res; 1620 1621 prefetch_len = min(htt->prefetch_len, msdu->len); 1622 prefetch_len = roundup(prefetch_len, 4); 1623 1624 txbuf = htt->txbuf.vaddr_txbuff_64 + msdu_id; 1625 txbuf_paddr = htt->txbuf.paddr + 1626 (sizeof(struct ath10k_htt_txbuf_64) * msdu_id); 1627 1628 if (!is_eth) { 1629 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data; 1630 1631 if ((ieee80211_is_action(hdr->frame_control) || 1632 ieee80211_is_deauth(hdr->frame_control) || 1633 ieee80211_is_disassoc(hdr->frame_control)) && 1634 ieee80211_has_protected(hdr->frame_control)) { 1635 skb_put(msdu, IEEE80211_CCMP_MIC_LEN); 1636 } else if (!(skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT) && 1637 txmode == ATH10K_HW_TXRX_RAW && 1638 ieee80211_has_protected(hdr->frame_control)) { 1639 skb_put(msdu, IEEE80211_CCMP_MIC_LEN); 1640 } 1641 } 1642 1643 skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len, 1644 DMA_TO_DEVICE); 1645 res = dma_mapping_error(dev, skb_cb->paddr); 1646 if (res) { 1647 res = -EIO; 1648 goto err_free_msdu_id; 1649 } 1650 1651 if (unlikely(info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)) 1652 freq = ar->scan.roc_freq; 1653 1654 switch (txmode) { 1655 case ATH10K_HW_TXRX_RAW: 1656 case ATH10K_HW_TXRX_NATIVE_WIFI: 1657 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT; 1658 fallthrough; 1659 case ATH10K_HW_TXRX_ETHERNET: 1660 if (ar->hw_params.continuous_frag_desc) { 1661 ext_desc_t = htt->frag_desc.vaddr_desc_64; 1662 memset(&ext_desc_t[msdu_id], 0, 1663 sizeof(struct htt_msdu_ext_desc_64)); 1664 frags = (struct htt_data_tx_desc_frag *) 1665 &ext_desc_t[msdu_id].frags; 1666 ext_desc = &ext_desc_t[msdu_id]; 1667 frags[0].tword_addr.paddr_lo = 1668 __cpu_to_le32(skb_cb->paddr); 1669 frags[0].tword_addr.paddr_hi = 1670 __cpu_to_le16(upper_32_bits(skb_cb->paddr)); 1671 frags[0].tword_addr.len_16 = __cpu_to_le16(msdu->len); 1672 1673 frags_paddr = htt->frag_desc.paddr + 1674 (sizeof(struct htt_msdu_ext_desc_64) * msdu_id); 1675 } else { 1676 frags = txbuf->frags; 1677 frags[0].tword_addr.paddr_lo = 1678 __cpu_to_le32(skb_cb->paddr); 1679 frags[0].tword_addr.paddr_hi = 1680 __cpu_to_le16(upper_32_bits(skb_cb->paddr)); 1681 frags[0].tword_addr.len_16 = __cpu_to_le16(msdu->len); 1682 frags[1].tword_addr.paddr_lo = 0; 1683 frags[1].tword_addr.paddr_hi = 0; 1684 frags[1].tword_addr.len_16 = 0; 1685 } 1686 flags0 |= SM(txmode, HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); 1687 break; 1688 case ATH10K_HW_TXRX_MGMT: 1689 flags0 |= SM(ATH10K_HW_TXRX_MGMT, 1690 HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); 1691 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT; 1692 1693 frags_paddr = skb_cb->paddr; 1694 break; 1695 } 1696 1697 /* Normally all commands go through HTC which manages tx credits for 1698 * each endpoint and notifies when tx is completed. 1699 * 1700 * HTT endpoint is creditless so there's no need to care about HTC 1701 * flags. In that case it is trivial to fill the HTC header here. 1702 * 1703 * MSDU transmission is considered completed upon HTT event. This 1704 * implies no relevant resources can be freed until after the event is 1705 * received. That's why HTC tx completion handler itself is ignored by 1706 * setting NULL to transfer_context for all sg items. 1707 * 1708 * There is simply no point in pushing HTT TX_FRM through HTC tx path 1709 * as it's a waste of resources. By bypassing HTC it is possible to 1710 * avoid extra memory allocations, compress data structures and thus 1711 * improve performance. 1712 */ 1713 1714 txbuf->htc_hdr.eid = htt->eid; 1715 txbuf->htc_hdr.len = __cpu_to_le16(sizeof(txbuf->cmd_hdr) + 1716 sizeof(txbuf->cmd_tx) + 1717 prefetch_len); 1718 txbuf->htc_hdr.flags = 0; 1719 1720 if (skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT) 1721 flags0 |= HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT; 1722 1723 flags1 |= SM((u16)vdev_id, HTT_DATA_TX_DESC_FLAGS1_VDEV_ID); 1724 flags1 |= SM((u16)tid, HTT_DATA_TX_DESC_FLAGS1_EXT_TID); 1725 if (msdu->ip_summed == CHECKSUM_PARTIAL && 1726 !test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) { 1727 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD; 1728 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD; 1729 if (ar->hw_params.continuous_frag_desc) { 1730 memset(ext_desc->tso_flag, 0, sizeof(ext_desc->tso_flag)); 1731 ext_desc->tso_flag[3] |= 1732 __cpu_to_le32(HTT_MSDU_CHECKSUM_ENABLE_64); 1733 } 1734 } 1735 1736 /* Prevent firmware from sending up tx inspection requests. There's 1737 * nothing ath10k can do with frames requested for inspection so force 1738 * it to simply rely a regular tx completion with discard status. 1739 */ 1740 flags1 |= HTT_DATA_TX_DESC_FLAGS1_POSTPONED; 1741 1742 txbuf->cmd_hdr.msg_type = HTT_H2T_MSG_TYPE_TX_FRM; 1743 txbuf->cmd_tx.flags0 = flags0; 1744 txbuf->cmd_tx.flags1 = __cpu_to_le16(flags1); 1745 txbuf->cmd_tx.len = __cpu_to_le16(msdu->len); 1746 txbuf->cmd_tx.id = __cpu_to_le16(msdu_id); 1747 1748 /* fill fragment descriptor */ 1749 txbuf->cmd_tx.frags_paddr = __cpu_to_le64(frags_paddr); 1750 if (ath10k_mac_tx_frm_has_freq(ar)) { 1751 txbuf->cmd_tx.offchan_tx.peerid = 1752 __cpu_to_le16(HTT_INVALID_PEERID); 1753 txbuf->cmd_tx.offchan_tx.freq = 1754 __cpu_to_le16(freq); 1755 } else { 1756 txbuf->cmd_tx.peerid = 1757 __cpu_to_le32(HTT_INVALID_PEERID); 1758 } 1759 1760 trace_ath10k_htt_tx(ar, msdu_id, msdu->len, vdev_id, tid); 1761 ath10k_dbg(ar, ATH10K_DBG_HTT, 1762 "htt tx flags0 %u flags1 %u len %d id %u frags_paddr %pad, msdu_paddr %pad vdev %u tid %u freq %u\n", 1763 flags0, flags1, msdu->len, msdu_id, &frags_paddr, 1764 &skb_cb->paddr, vdev_id, tid, freq); 1765 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt tx msdu: ", 1766 msdu->data, msdu->len); 1767 trace_ath10k_tx_hdr(ar, msdu->data, msdu->len); 1768 trace_ath10k_tx_payload(ar, msdu->data, msdu->len); 1769 1770 sg_items[0].transfer_id = 0; 1771 sg_items[0].transfer_context = NULL; 1772 sg_items[0].vaddr = &txbuf->htc_hdr; 1773 sg_items[0].paddr = txbuf_paddr + 1774 sizeof(txbuf->frags); 1775 sg_items[0].len = sizeof(txbuf->htc_hdr) + 1776 sizeof(txbuf->cmd_hdr) + 1777 sizeof(txbuf->cmd_tx); 1778 1779 sg_items[1].transfer_id = 0; 1780 sg_items[1].transfer_context = NULL; 1781 sg_items[1].vaddr = msdu->data; 1782 sg_items[1].paddr = skb_cb->paddr; 1783 sg_items[1].len = prefetch_len; 1784 1785 res = ath10k_hif_tx_sg(htt->ar, 1786 htt->ar->htc.endpoint[htt->eid].ul_pipe_id, 1787 sg_items, ARRAY_SIZE(sg_items)); 1788 if (res) 1789 goto err_unmap_msdu; 1790 1791 return 0; 1792 1793 err_unmap_msdu: 1794 dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 1795 err_free_msdu_id: 1796 spin_lock_bh(&htt->tx_lock); 1797 ath10k_htt_tx_free_msdu_id(htt, msdu_id); 1798 spin_unlock_bh(&htt->tx_lock); 1799 err: 1800 return res; 1801 } 1802 1803 static const struct ath10k_htt_tx_ops htt_tx_ops_32 = { 1804 .htt_send_rx_ring_cfg = ath10k_htt_send_rx_ring_cfg_32, 1805 .htt_send_frag_desc_bank_cfg = ath10k_htt_send_frag_desc_bank_cfg_32, 1806 .htt_alloc_frag_desc = ath10k_htt_tx_alloc_cont_frag_desc_32, 1807 .htt_free_frag_desc = ath10k_htt_tx_free_cont_frag_desc_32, 1808 .htt_tx = ath10k_htt_tx_32, 1809 .htt_alloc_txbuff = ath10k_htt_tx_alloc_cont_txbuf_32, 1810 .htt_free_txbuff = ath10k_htt_tx_free_cont_txbuf_32, 1811 .htt_h2t_aggr_cfg_msg = ath10k_htt_h2t_aggr_cfg_msg_32, 1812 }; 1813 1814 static const struct ath10k_htt_tx_ops htt_tx_ops_64 = { 1815 .htt_send_rx_ring_cfg = ath10k_htt_send_rx_ring_cfg_64, 1816 .htt_send_frag_desc_bank_cfg = ath10k_htt_send_frag_desc_bank_cfg_64, 1817 .htt_alloc_frag_desc = ath10k_htt_tx_alloc_cont_frag_desc_64, 1818 .htt_free_frag_desc = ath10k_htt_tx_free_cont_frag_desc_64, 1819 .htt_tx = ath10k_htt_tx_64, 1820 .htt_alloc_txbuff = ath10k_htt_tx_alloc_cont_txbuf_64, 1821 .htt_free_txbuff = ath10k_htt_tx_free_cont_txbuf_64, 1822 .htt_h2t_aggr_cfg_msg = ath10k_htt_h2t_aggr_cfg_msg_v2, 1823 }; 1824 1825 static const struct ath10k_htt_tx_ops htt_tx_ops_hl = { 1826 .htt_send_rx_ring_cfg = ath10k_htt_send_rx_ring_cfg_hl, 1827 .htt_send_frag_desc_bank_cfg = ath10k_htt_send_frag_desc_bank_cfg_32, 1828 .htt_tx = ath10k_htt_tx_hl, 1829 .htt_h2t_aggr_cfg_msg = ath10k_htt_h2t_aggr_cfg_msg_32, 1830 .htt_flush_tx = ath10k_htt_flush_tx_queue, 1831 }; 1832 1833 void ath10k_htt_set_tx_ops(struct ath10k_htt *htt) 1834 { 1835 struct ath10k *ar = htt->ar; 1836 1837 if (ar->bus_param.dev_type == ATH10K_DEV_TYPE_HL) 1838 htt->tx_ops = &htt_tx_ops_hl; 1839 else if (ar->hw_params.target_64bit) 1840 htt->tx_ops = &htt_tx_ops_64; 1841 else 1842 htt->tx_ops = &htt_tx_ops_32; 1843 } 1844