1 /* 2 * Copyright (c) 2005-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef _HTT_H_ 19 #define _HTT_H_ 20 21 #include <linux/bug.h> 22 #include <linux/interrupt.h> 23 #include <linux/dmapool.h> 24 #include <linux/hashtable.h> 25 #include <linux/kfifo.h> 26 #include <net/mac80211.h> 27 28 #include "htc.h" 29 #include "hw.h" 30 #include "rx_desc.h" 31 #include "hw.h" 32 33 enum htt_dbg_stats_type { 34 HTT_DBG_STATS_WAL_PDEV_TXRX = 1 << 0, 35 HTT_DBG_STATS_RX_REORDER = 1 << 1, 36 HTT_DBG_STATS_RX_RATE_INFO = 1 << 2, 37 HTT_DBG_STATS_TX_PPDU_LOG = 1 << 3, 38 HTT_DBG_STATS_TX_RATE_INFO = 1 << 4, 39 /* bits 5-23 currently reserved */ 40 41 HTT_DBG_NUM_STATS /* keep this last */ 42 }; 43 44 enum htt_h2t_msg_type { /* host-to-target */ 45 HTT_H2T_MSG_TYPE_VERSION_REQ = 0, 46 HTT_H2T_MSG_TYPE_TX_FRM = 1, 47 HTT_H2T_MSG_TYPE_RX_RING_CFG = 2, 48 HTT_H2T_MSG_TYPE_STATS_REQ = 3, 49 HTT_H2T_MSG_TYPE_SYNC = 4, 50 HTT_H2T_MSG_TYPE_AGGR_CFG = 5, 51 HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG = 6, 52 53 /* This command is used for sending management frames in HTT < 3.0. 54 * HTT >= 3.0 uses TX_FRM for everything. */ 55 HTT_H2T_MSG_TYPE_MGMT_TX = 7, 56 HTT_H2T_MSG_TYPE_TX_FETCH_RESP = 11, 57 58 HTT_H2T_NUM_MSGS /* keep this last */ 59 }; 60 61 struct htt_cmd_hdr { 62 u8 msg_type; 63 } __packed; 64 65 struct htt_ver_req { 66 u8 pad[sizeof(u32) - sizeof(struct htt_cmd_hdr)]; 67 } __packed; 68 69 /* 70 * HTT tx MSDU descriptor 71 * 72 * The HTT tx MSDU descriptor is created by the host HTT SW for each 73 * tx MSDU. The HTT tx MSDU descriptor contains the information that 74 * the target firmware needs for the FW's tx processing, particularly 75 * for creating the HW msdu descriptor. 76 * The same HTT tx descriptor is used for HL and LL systems, though 77 * a few fields within the tx descriptor are used only by LL or 78 * only by HL. 79 * The HTT tx descriptor is defined in two manners: by a struct with 80 * bitfields, and by a series of [dword offset, bit mask, bit shift] 81 * definitions. 82 * The target should use the struct def, for simplicitly and clarity, 83 * but the host shall use the bit-mast + bit-shift defs, to be endian- 84 * neutral. Specifically, the host shall use the get/set macros built 85 * around the mask + shift defs. 86 */ 87 struct htt_data_tx_desc_frag { 88 union { 89 struct double_word_addr { 90 __le32 paddr; 91 __le32 len; 92 } __packed dword_addr; 93 struct triple_word_addr { 94 __le32 paddr_lo; 95 __le16 paddr_hi; 96 __le16 len_16; 97 } __packed tword_addr; 98 } __packed; 99 } __packed; 100 101 struct htt_msdu_ext_desc { 102 __le32 tso_flag[3]; 103 __le16 ip_identification; 104 u8 flags; 105 u8 reserved; 106 struct htt_data_tx_desc_frag frags[6]; 107 }; 108 109 #define HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE BIT(0) 110 #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE BIT(1) 111 #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE BIT(2) 112 #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE BIT(3) 113 #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE BIT(4) 114 115 #define HTT_MSDU_CHECKSUM_ENABLE (HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE \ 116 | HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE \ 117 | HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE \ 118 | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE \ 119 | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE) 120 121 enum htt_data_tx_desc_flags0 { 122 HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT = 1 << 0, 123 HTT_DATA_TX_DESC_FLAGS0_NO_AGGR = 1 << 1, 124 HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT = 1 << 2, 125 HTT_DATA_TX_DESC_FLAGS0_NO_CLASSIFY = 1 << 3, 126 HTT_DATA_TX_DESC_FLAGS0_RSVD0 = 1 << 4 127 #define HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE_MASK 0xE0 128 #define HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE_LSB 5 129 }; 130 131 enum htt_data_tx_desc_flags1 { 132 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_BITS 6 133 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_MASK 0x003F 134 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_LSB 0 135 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_BITS 5 136 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_MASK 0x07C0 137 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_LSB 6 138 HTT_DATA_TX_DESC_FLAGS1_POSTPONED = 1 << 11, 139 HTT_DATA_TX_DESC_FLAGS1_MORE_IN_BATCH = 1 << 12, 140 HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD = 1 << 13, 141 HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD = 1 << 14, 142 HTT_DATA_TX_DESC_FLAGS1_RSVD1 = 1 << 15 143 }; 144 145 enum htt_data_tx_ext_tid { 146 HTT_DATA_TX_EXT_TID_NON_QOS_MCAST_BCAST = 16, 147 HTT_DATA_TX_EXT_TID_MGMT = 17, 148 HTT_DATA_TX_EXT_TID_INVALID = 31 149 }; 150 151 #define HTT_INVALID_PEERID 0xFFFF 152 153 /* 154 * htt_data_tx_desc - used for data tx path 155 * 156 * Note: vdev_id irrelevant for pkt_type == raw and no_classify == 1. 157 * ext_tid: for qos-data frames (0-15), see %HTT_DATA_TX_EXT_TID_ 158 * for special kinds of tids 159 * postponed: only for HL hosts. indicates if this is a resend 160 * (HL hosts manage queues on the host ) 161 * more_in_batch: only for HL hosts. indicates if more packets are 162 * pending. this allows target to wait and aggregate 163 * freq: 0 means home channel of given vdev. intended for offchannel 164 */ 165 struct htt_data_tx_desc { 166 u8 flags0; /* %HTT_DATA_TX_DESC_FLAGS0_ */ 167 __le16 flags1; /* %HTT_DATA_TX_DESC_FLAGS1_ */ 168 __le16 len; 169 __le16 id; 170 __le32 frags_paddr; 171 union { 172 __le32 peerid; 173 struct { 174 __le16 peerid; 175 __le16 freq; 176 } __packed offchan_tx; 177 } __packed; 178 u8 prefetch[0]; /* start of frame, for FW classification engine */ 179 } __packed; 180 181 enum htt_rx_ring_flags { 182 HTT_RX_RING_FLAGS_MAC80211_HDR = 1 << 0, 183 HTT_RX_RING_FLAGS_MSDU_PAYLOAD = 1 << 1, 184 HTT_RX_RING_FLAGS_PPDU_START = 1 << 2, 185 HTT_RX_RING_FLAGS_PPDU_END = 1 << 3, 186 HTT_RX_RING_FLAGS_MPDU_START = 1 << 4, 187 HTT_RX_RING_FLAGS_MPDU_END = 1 << 5, 188 HTT_RX_RING_FLAGS_MSDU_START = 1 << 6, 189 HTT_RX_RING_FLAGS_MSDU_END = 1 << 7, 190 HTT_RX_RING_FLAGS_RX_ATTENTION = 1 << 8, 191 HTT_RX_RING_FLAGS_FRAG_INFO = 1 << 9, 192 HTT_RX_RING_FLAGS_UNICAST_RX = 1 << 10, 193 HTT_RX_RING_FLAGS_MULTICAST_RX = 1 << 11, 194 HTT_RX_RING_FLAGS_CTRL_RX = 1 << 12, 195 HTT_RX_RING_FLAGS_MGMT_RX = 1 << 13, 196 HTT_RX_RING_FLAGS_NULL_RX = 1 << 14, 197 HTT_RX_RING_FLAGS_PHY_DATA_RX = 1 << 15 198 }; 199 200 #define HTT_RX_RING_SIZE_MIN 128 201 #define HTT_RX_RING_SIZE_MAX 2048 202 203 struct htt_rx_ring_setup_ring { 204 __le32 fw_idx_shadow_reg_paddr; 205 __le32 rx_ring_base_paddr; 206 __le16 rx_ring_len; /* in 4-byte words */ 207 __le16 rx_ring_bufsize; /* rx skb size - in bytes */ 208 __le16 flags; /* %HTT_RX_RING_FLAGS_ */ 209 __le16 fw_idx_init_val; 210 211 /* the following offsets are in 4-byte units */ 212 __le16 mac80211_hdr_offset; 213 __le16 msdu_payload_offset; 214 __le16 ppdu_start_offset; 215 __le16 ppdu_end_offset; 216 __le16 mpdu_start_offset; 217 __le16 mpdu_end_offset; 218 __le16 msdu_start_offset; 219 __le16 msdu_end_offset; 220 __le16 rx_attention_offset; 221 __le16 frag_info_offset; 222 } __packed; 223 224 struct htt_rx_ring_setup_hdr { 225 u8 num_rings; /* supported values: 1, 2 */ 226 __le16 rsvd0; 227 } __packed; 228 229 struct htt_rx_ring_setup { 230 struct htt_rx_ring_setup_hdr hdr; 231 struct htt_rx_ring_setup_ring rings[0]; 232 } __packed; 233 234 /* 235 * htt_stats_req - request target to send specified statistics 236 * 237 * @msg_type: hardcoded %HTT_H2T_MSG_TYPE_STATS_REQ 238 * @upload_types: see %htt_dbg_stats_type. this is 24bit field actually 239 * so make sure its little-endian. 240 * @reset_types: see %htt_dbg_stats_type. this is 24bit field actually 241 * so make sure its little-endian. 242 * @cfg_val: stat_type specific configuration 243 * @stat_type: see %htt_dbg_stats_type 244 * @cookie_lsb: used for confirmation message from target->host 245 * @cookie_msb: ditto as %cookie 246 */ 247 struct htt_stats_req { 248 u8 upload_types[3]; 249 u8 rsvd0; 250 u8 reset_types[3]; 251 struct { 252 u8 mpdu_bytes; 253 u8 mpdu_num_msdus; 254 u8 msdu_bytes; 255 } __packed; 256 u8 stat_type; 257 __le32 cookie_lsb; 258 __le32 cookie_msb; 259 } __packed; 260 261 #define HTT_STATS_REQ_CFG_STAT_TYPE_INVALID 0xff 262 263 /* 264 * htt_oob_sync_req - request out-of-band sync 265 * 266 * The HTT SYNC tells the target to suspend processing of subsequent 267 * HTT host-to-target messages until some other target agent locally 268 * informs the target HTT FW that the current sync counter is equal to 269 * or greater than (in a modulo sense) the sync counter specified in 270 * the SYNC message. 271 * 272 * This allows other host-target components to synchronize their operation 273 * with HTT, e.g. to ensure that tx frames don't get transmitted until a 274 * security key has been downloaded to and activated by the target. 275 * In the absence of any explicit synchronization counter value 276 * specification, the target HTT FW will use zero as the default current 277 * sync value. 278 * 279 * The HTT target FW will suspend its host->target message processing as long 280 * as 0 < (in-band sync counter - out-of-band sync counter) & 0xff < 128. 281 */ 282 struct htt_oob_sync_req { 283 u8 sync_count; 284 __le16 rsvd0; 285 } __packed; 286 287 struct htt_aggr_conf { 288 u8 max_num_ampdu_subframes; 289 /* amsdu_subframes is limited by 0x1F mask */ 290 u8 max_num_amsdu_subframes; 291 } __packed; 292 293 #define HTT_MGMT_FRM_HDR_DOWNLOAD_LEN 32 294 struct htt_mgmt_tx_desc_qca99x0 { 295 __le32 rate; 296 } __packed; 297 298 struct htt_mgmt_tx_desc { 299 u8 pad[sizeof(u32) - sizeof(struct htt_cmd_hdr)]; 300 __le32 msdu_paddr; 301 __le32 desc_id; 302 __le32 len; 303 __le32 vdev_id; 304 u8 hdr[HTT_MGMT_FRM_HDR_DOWNLOAD_LEN]; 305 union { 306 struct htt_mgmt_tx_desc_qca99x0 qca99x0; 307 } __packed; 308 } __packed; 309 310 enum htt_mgmt_tx_status { 311 HTT_MGMT_TX_STATUS_OK = 0, 312 HTT_MGMT_TX_STATUS_RETRY = 1, 313 HTT_MGMT_TX_STATUS_DROP = 2 314 }; 315 316 /*=== target -> host messages ===============================================*/ 317 318 enum htt_main_t2h_msg_type { 319 HTT_MAIN_T2H_MSG_TYPE_VERSION_CONF = 0x0, 320 HTT_MAIN_T2H_MSG_TYPE_RX_IND = 0x1, 321 HTT_MAIN_T2H_MSG_TYPE_RX_FLUSH = 0x2, 322 HTT_MAIN_T2H_MSG_TYPE_PEER_MAP = 0x3, 323 HTT_MAIN_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 324 HTT_MAIN_T2H_MSG_TYPE_RX_ADDBA = 0x5, 325 HTT_MAIN_T2H_MSG_TYPE_RX_DELBA = 0x6, 326 HTT_MAIN_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 327 HTT_MAIN_T2H_MSG_TYPE_PKTLOG = 0x8, 328 HTT_MAIN_T2H_MSG_TYPE_STATS_CONF = 0x9, 329 HTT_MAIN_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 330 HTT_MAIN_T2H_MSG_TYPE_SEC_IND = 0xb, 331 HTT_MAIN_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 332 HTT_MAIN_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe, 333 HTT_MAIN_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0xf, 334 HTT_MAIN_T2H_MSG_TYPE_RX_PN_IND = 0x10, 335 HTT_MAIN_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x11, 336 HTT_MAIN_T2H_MSG_TYPE_TEST, 337 /* keep this last */ 338 HTT_MAIN_T2H_NUM_MSGS 339 }; 340 341 enum htt_10x_t2h_msg_type { 342 HTT_10X_T2H_MSG_TYPE_VERSION_CONF = 0x0, 343 HTT_10X_T2H_MSG_TYPE_RX_IND = 0x1, 344 HTT_10X_T2H_MSG_TYPE_RX_FLUSH = 0x2, 345 HTT_10X_T2H_MSG_TYPE_PEER_MAP = 0x3, 346 HTT_10X_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 347 HTT_10X_T2H_MSG_TYPE_RX_ADDBA = 0x5, 348 HTT_10X_T2H_MSG_TYPE_RX_DELBA = 0x6, 349 HTT_10X_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 350 HTT_10X_T2H_MSG_TYPE_PKTLOG = 0x8, 351 HTT_10X_T2H_MSG_TYPE_STATS_CONF = 0x9, 352 HTT_10X_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 353 HTT_10X_T2H_MSG_TYPE_SEC_IND = 0xb, 354 HTT_10X_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc, 355 HTT_10X_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 356 HTT_10X_T2H_MSG_TYPE_TEST = 0xe, 357 HTT_10X_T2H_MSG_TYPE_CHAN_CHANGE = 0xf, 358 HTT_10X_T2H_MSG_TYPE_AGGR_CONF = 0x11, 359 HTT_10X_T2H_MSG_TYPE_STATS_NOUPLOAD = 0x12, 360 HTT_10X_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0x13, 361 /* keep this last */ 362 HTT_10X_T2H_NUM_MSGS 363 }; 364 365 enum htt_tlv_t2h_msg_type { 366 HTT_TLV_T2H_MSG_TYPE_VERSION_CONF = 0x0, 367 HTT_TLV_T2H_MSG_TYPE_RX_IND = 0x1, 368 HTT_TLV_T2H_MSG_TYPE_RX_FLUSH = 0x2, 369 HTT_TLV_T2H_MSG_TYPE_PEER_MAP = 0x3, 370 HTT_TLV_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 371 HTT_TLV_T2H_MSG_TYPE_RX_ADDBA = 0x5, 372 HTT_TLV_T2H_MSG_TYPE_RX_DELBA = 0x6, 373 HTT_TLV_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 374 HTT_TLV_T2H_MSG_TYPE_PKTLOG = 0x8, 375 HTT_TLV_T2H_MSG_TYPE_STATS_CONF = 0x9, 376 HTT_TLV_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 377 HTT_TLV_T2H_MSG_TYPE_SEC_IND = 0xb, 378 HTT_TLV_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc, /* deprecated */ 379 HTT_TLV_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 380 HTT_TLV_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe, 381 HTT_TLV_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0xf, 382 HTT_TLV_T2H_MSG_TYPE_RX_PN_IND = 0x10, 383 HTT_TLV_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x11, 384 HTT_TLV_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND = 0x12, 385 /* 0x13 reservd */ 386 HTT_TLV_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE = 0x14, 387 HTT_TLV_T2H_MSG_TYPE_CHAN_CHANGE = 0x15, 388 HTT_TLV_T2H_MSG_TYPE_RX_OFLD_PKT_ERR = 0x16, 389 HTT_TLV_T2H_MSG_TYPE_TEST, 390 /* keep this last */ 391 HTT_TLV_T2H_NUM_MSGS 392 }; 393 394 enum htt_10_4_t2h_msg_type { 395 HTT_10_4_T2H_MSG_TYPE_VERSION_CONF = 0x0, 396 HTT_10_4_T2H_MSG_TYPE_RX_IND = 0x1, 397 HTT_10_4_T2H_MSG_TYPE_RX_FLUSH = 0x2, 398 HTT_10_4_T2H_MSG_TYPE_PEER_MAP = 0x3, 399 HTT_10_4_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 400 HTT_10_4_T2H_MSG_TYPE_RX_ADDBA = 0x5, 401 HTT_10_4_T2H_MSG_TYPE_RX_DELBA = 0x6, 402 HTT_10_4_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 403 HTT_10_4_T2H_MSG_TYPE_PKTLOG = 0x8, 404 HTT_10_4_T2H_MSG_TYPE_STATS_CONF = 0x9, 405 HTT_10_4_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 406 HTT_10_4_T2H_MSG_TYPE_SEC_IND = 0xb, 407 HTT_10_4_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc, 408 HTT_10_4_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 409 HTT_10_4_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe, 410 HTT_10_4_T2H_MSG_TYPE_CHAN_CHANGE = 0xf, 411 HTT_10_4_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0x10, 412 HTT_10_4_T2H_MSG_TYPE_RX_PN_IND = 0x11, 413 HTT_10_4_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x12, 414 HTT_10_4_T2H_MSG_TYPE_TEST = 0x13, 415 HTT_10_4_T2H_MSG_TYPE_EN_STATS = 0x14, 416 HTT_10_4_T2H_MSG_TYPE_AGGR_CONF = 0x15, 417 HTT_10_4_T2H_MSG_TYPE_TX_FETCH_IND = 0x16, 418 HTT_10_4_T2H_MSG_TYPE_TX_FETCH_CONFIRM = 0x17, 419 HTT_10_4_T2H_MSG_TYPE_STATS_NOUPLOAD = 0x18, 420 /* 0x19 to 0x2f are reserved */ 421 HTT_10_4_T2H_MSG_TYPE_TX_MODE_SWITCH_IND = 0x30, 422 HTT_10_4_T2H_MSG_TYPE_PEER_STATS = 0x31, 423 /* keep this last */ 424 HTT_10_4_T2H_NUM_MSGS 425 }; 426 427 enum htt_t2h_msg_type { 428 HTT_T2H_MSG_TYPE_VERSION_CONF, 429 HTT_T2H_MSG_TYPE_RX_IND, 430 HTT_T2H_MSG_TYPE_RX_FLUSH, 431 HTT_T2H_MSG_TYPE_PEER_MAP, 432 HTT_T2H_MSG_TYPE_PEER_UNMAP, 433 HTT_T2H_MSG_TYPE_RX_ADDBA, 434 HTT_T2H_MSG_TYPE_RX_DELBA, 435 HTT_T2H_MSG_TYPE_TX_COMPL_IND, 436 HTT_T2H_MSG_TYPE_PKTLOG, 437 HTT_T2H_MSG_TYPE_STATS_CONF, 438 HTT_T2H_MSG_TYPE_RX_FRAG_IND, 439 HTT_T2H_MSG_TYPE_SEC_IND, 440 HTT_T2H_MSG_TYPE_RC_UPDATE_IND, 441 HTT_T2H_MSG_TYPE_TX_INSPECT_IND, 442 HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION, 443 HTT_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND, 444 HTT_T2H_MSG_TYPE_RX_PN_IND, 445 HTT_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND, 446 HTT_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND, 447 HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE, 448 HTT_T2H_MSG_TYPE_CHAN_CHANGE, 449 HTT_T2H_MSG_TYPE_RX_OFLD_PKT_ERR, 450 HTT_T2H_MSG_TYPE_AGGR_CONF, 451 HTT_T2H_MSG_TYPE_STATS_NOUPLOAD, 452 HTT_T2H_MSG_TYPE_TEST, 453 HTT_T2H_MSG_TYPE_EN_STATS, 454 HTT_T2H_MSG_TYPE_TX_FETCH_IND, 455 HTT_T2H_MSG_TYPE_TX_FETCH_CONFIRM, 456 HTT_T2H_MSG_TYPE_TX_MODE_SWITCH_IND, 457 HTT_T2H_MSG_TYPE_PEER_STATS, 458 /* keep this last */ 459 HTT_T2H_NUM_MSGS 460 }; 461 462 /* 463 * htt_resp_hdr - header for target-to-host messages 464 * 465 * msg_type: see htt_t2h_msg_type 466 */ 467 struct htt_resp_hdr { 468 u8 msg_type; 469 } __packed; 470 471 #define HTT_RESP_HDR_MSG_TYPE_OFFSET 0 472 #define HTT_RESP_HDR_MSG_TYPE_MASK 0xff 473 #define HTT_RESP_HDR_MSG_TYPE_LSB 0 474 475 /* htt_ver_resp - response sent for htt_ver_req */ 476 struct htt_ver_resp { 477 u8 minor; 478 u8 major; 479 u8 rsvd0; 480 } __packed; 481 482 struct htt_mgmt_tx_completion { 483 u8 rsvd0; 484 u8 rsvd1; 485 u8 rsvd2; 486 __le32 desc_id; 487 __le32 status; 488 } __packed; 489 490 #define HTT_RX_INDICATION_INFO0_EXT_TID_MASK (0x1F) 491 #define HTT_RX_INDICATION_INFO0_EXT_TID_LSB (0) 492 #define HTT_RX_INDICATION_INFO0_FLUSH_VALID (1 << 5) 493 #define HTT_RX_INDICATION_INFO0_RELEASE_VALID (1 << 6) 494 495 #define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_MASK 0x0000003F 496 #define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_LSB 0 497 #define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_MASK 0x00000FC0 498 #define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_LSB 6 499 #define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_MASK 0x0003F000 500 #define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_LSB 12 501 #define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_MASK 0x00FC0000 502 #define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_LSB 18 503 #define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_MASK 0xFF000000 504 #define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_LSB 24 505 506 struct htt_rx_indication_hdr { 507 u8 info0; /* %HTT_RX_INDICATION_INFO0_ */ 508 __le16 peer_id; 509 __le32 info1; /* %HTT_RX_INDICATION_INFO1_ */ 510 } __packed; 511 512 #define HTT_RX_INDICATION_INFO0_PHY_ERR_VALID (1 << 0) 513 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_MASK (0x1E) 514 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_LSB (1) 515 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_CCK (1 << 5) 516 #define HTT_RX_INDICATION_INFO0_END_VALID (1 << 6) 517 #define HTT_RX_INDICATION_INFO0_START_VALID (1 << 7) 518 519 #define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_MASK 0x00FFFFFF 520 #define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_LSB 0 521 #define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_MASK 0xFF000000 522 #define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_LSB 24 523 524 #define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_MASK 0x00FFFFFF 525 #define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_LSB 0 526 #define HTT_RX_INDICATION_INFO2_SERVICE_MASK 0xFF000000 527 #define HTT_RX_INDICATION_INFO2_SERVICE_LSB 24 528 529 enum htt_rx_legacy_rate { 530 HTT_RX_OFDM_48 = 0, 531 HTT_RX_OFDM_24 = 1, 532 HTT_RX_OFDM_12, 533 HTT_RX_OFDM_6, 534 HTT_RX_OFDM_54, 535 HTT_RX_OFDM_36, 536 HTT_RX_OFDM_18, 537 HTT_RX_OFDM_9, 538 539 /* long preamble */ 540 HTT_RX_CCK_11_LP = 0, 541 HTT_RX_CCK_5_5_LP = 1, 542 HTT_RX_CCK_2_LP, 543 HTT_RX_CCK_1_LP, 544 /* short preamble */ 545 HTT_RX_CCK_11_SP, 546 HTT_RX_CCK_5_5_SP, 547 HTT_RX_CCK_2_SP 548 }; 549 550 enum htt_rx_legacy_rate_type { 551 HTT_RX_LEGACY_RATE_OFDM = 0, 552 HTT_RX_LEGACY_RATE_CCK 553 }; 554 555 enum htt_rx_preamble_type { 556 HTT_RX_LEGACY = 0x4, 557 HTT_RX_HT = 0x8, 558 HTT_RX_HT_WITH_TXBF = 0x9, 559 HTT_RX_VHT = 0xC, 560 HTT_RX_VHT_WITH_TXBF = 0xD, 561 }; 562 563 /* 564 * Fields: phy_err_valid, phy_err_code, tsf, 565 * usec_timestamp, sub_usec_timestamp 566 * ..are valid only if end_valid == 1. 567 * 568 * Fields: rssi_chains, legacy_rate_type, 569 * legacy_rate_cck, preamble_type, service, 570 * vht_sig_* 571 * ..are valid only if start_valid == 1; 572 */ 573 struct htt_rx_indication_ppdu { 574 u8 combined_rssi; 575 u8 sub_usec_timestamp; 576 u8 phy_err_code; 577 u8 info0; /* HTT_RX_INDICATION_INFO0_ */ 578 struct { 579 u8 pri20_db; 580 u8 ext20_db; 581 u8 ext40_db; 582 u8 ext80_db; 583 } __packed rssi_chains[4]; 584 __le32 tsf; 585 __le32 usec_timestamp; 586 __le32 info1; /* HTT_RX_INDICATION_INFO1_ */ 587 __le32 info2; /* HTT_RX_INDICATION_INFO2_ */ 588 } __packed; 589 590 enum htt_rx_mpdu_status { 591 HTT_RX_IND_MPDU_STATUS_UNKNOWN = 0x0, 592 HTT_RX_IND_MPDU_STATUS_OK, 593 HTT_RX_IND_MPDU_STATUS_ERR_FCS, 594 HTT_RX_IND_MPDU_STATUS_ERR_DUP, 595 HTT_RX_IND_MPDU_STATUS_ERR_REPLAY, 596 HTT_RX_IND_MPDU_STATUS_ERR_INV_PEER, 597 /* only accept EAPOL frames */ 598 HTT_RX_IND_MPDU_STATUS_UNAUTH_PEER, 599 HTT_RX_IND_MPDU_STATUS_OUT_OF_SYNC, 600 /* Non-data in promiscuous mode */ 601 HTT_RX_IND_MPDU_STATUS_MGMT_CTRL, 602 HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR, 603 HTT_RX_IND_MPDU_STATUS_DECRYPT_ERR, 604 HTT_RX_IND_MPDU_STATUS_MPDU_LENGTH_ERR, 605 HTT_RX_IND_MPDU_STATUS_ENCRYPT_REQUIRED_ERR, 606 HTT_RX_IND_MPDU_STATUS_PRIVACY_ERR, 607 608 /* 609 * MISC: discard for unspecified reasons. 610 * Leave this enum value last. 611 */ 612 HTT_RX_IND_MPDU_STATUS_ERR_MISC = 0xFF 613 }; 614 615 struct htt_rx_indication_mpdu_range { 616 u8 mpdu_count; 617 u8 mpdu_range_status; /* %htt_rx_mpdu_status */ 618 u8 pad0; 619 u8 pad1; 620 } __packed; 621 622 struct htt_rx_indication_prefix { 623 __le16 fw_rx_desc_bytes; 624 u8 pad0; 625 u8 pad1; 626 }; 627 628 struct htt_rx_indication { 629 struct htt_rx_indication_hdr hdr; 630 struct htt_rx_indication_ppdu ppdu; 631 struct htt_rx_indication_prefix prefix; 632 633 /* 634 * the following fields are both dynamically sized, so 635 * take care addressing them 636 */ 637 638 /* the size of this is %fw_rx_desc_bytes */ 639 struct fw_rx_desc_base fw_desc; 640 641 /* 642 * %mpdu_ranges starts after &%prefix + roundup(%fw_rx_desc_bytes, 4) 643 * and has %num_mpdu_ranges elements. 644 */ 645 struct htt_rx_indication_mpdu_range mpdu_ranges[0]; 646 } __packed; 647 648 static inline struct htt_rx_indication_mpdu_range * 649 htt_rx_ind_get_mpdu_ranges(struct htt_rx_indication *rx_ind) 650 { 651 void *ptr = rx_ind; 652 653 ptr += sizeof(rx_ind->hdr) 654 + sizeof(rx_ind->ppdu) 655 + sizeof(rx_ind->prefix) 656 + roundup(__le16_to_cpu(rx_ind->prefix.fw_rx_desc_bytes), 4); 657 return ptr; 658 } 659 660 enum htt_rx_flush_mpdu_status { 661 HTT_RX_FLUSH_MPDU_DISCARD = 0, 662 HTT_RX_FLUSH_MPDU_REORDER = 1, 663 }; 664 665 /* 666 * htt_rx_flush - discard or reorder given range of mpdus 667 * 668 * Note: host must check if all sequence numbers between 669 * [seq_num_start, seq_num_end-1] are valid. 670 */ 671 struct htt_rx_flush { 672 __le16 peer_id; 673 u8 tid; 674 u8 rsvd0; 675 u8 mpdu_status; /* %htt_rx_flush_mpdu_status */ 676 u8 seq_num_start; /* it is 6 LSBs of 802.11 seq no */ 677 u8 seq_num_end; /* it is 6 LSBs of 802.11 seq no */ 678 }; 679 680 struct htt_rx_peer_map { 681 u8 vdev_id; 682 __le16 peer_id; 683 u8 addr[6]; 684 u8 rsvd0; 685 u8 rsvd1; 686 } __packed; 687 688 struct htt_rx_peer_unmap { 689 u8 rsvd0; 690 __le16 peer_id; 691 } __packed; 692 693 enum htt_security_types { 694 HTT_SECURITY_NONE, 695 HTT_SECURITY_WEP128, 696 HTT_SECURITY_WEP104, 697 HTT_SECURITY_WEP40, 698 HTT_SECURITY_TKIP, 699 HTT_SECURITY_TKIP_NOMIC, 700 HTT_SECURITY_AES_CCMP, 701 HTT_SECURITY_WAPI, 702 703 HTT_NUM_SECURITY_TYPES /* keep this last! */ 704 }; 705 706 enum htt_security_flags { 707 #define HTT_SECURITY_TYPE_MASK 0x7F 708 #define HTT_SECURITY_TYPE_LSB 0 709 HTT_SECURITY_IS_UNICAST = 1 << 7 710 }; 711 712 struct htt_security_indication { 713 union { 714 /* dont use bitfields; undefined behaviour */ 715 u8 flags; /* %htt_security_flags */ 716 struct { 717 u8 security_type:7, /* %htt_security_types */ 718 is_unicast:1; 719 } __packed; 720 } __packed; 721 __le16 peer_id; 722 u8 michael_key[8]; 723 u8 wapi_rsc[16]; 724 } __packed; 725 726 #define HTT_RX_BA_INFO0_TID_MASK 0x000F 727 #define HTT_RX_BA_INFO0_TID_LSB 0 728 #define HTT_RX_BA_INFO0_PEER_ID_MASK 0xFFF0 729 #define HTT_RX_BA_INFO0_PEER_ID_LSB 4 730 731 struct htt_rx_addba { 732 u8 window_size; 733 __le16 info0; /* %HTT_RX_BA_INFO0_ */ 734 } __packed; 735 736 struct htt_rx_delba { 737 u8 rsvd0; 738 __le16 info0; /* %HTT_RX_BA_INFO0_ */ 739 } __packed; 740 741 enum htt_data_tx_status { 742 HTT_DATA_TX_STATUS_OK = 0, 743 HTT_DATA_TX_STATUS_DISCARD = 1, 744 HTT_DATA_TX_STATUS_NO_ACK = 2, 745 HTT_DATA_TX_STATUS_POSTPONE = 3, /* HL only */ 746 HTT_DATA_TX_STATUS_DOWNLOAD_FAIL = 128 747 }; 748 749 enum htt_data_tx_flags { 750 #define HTT_DATA_TX_STATUS_MASK 0x07 751 #define HTT_DATA_TX_STATUS_LSB 0 752 #define HTT_DATA_TX_TID_MASK 0x78 753 #define HTT_DATA_TX_TID_LSB 3 754 HTT_DATA_TX_TID_INVALID = 1 << 7 755 }; 756 757 #define HTT_TX_COMPL_INV_MSDU_ID 0xFFFF 758 759 struct htt_data_tx_completion { 760 union { 761 u8 flags; 762 struct { 763 u8 status:3, 764 tid:4, 765 tid_invalid:1; 766 } __packed; 767 } __packed; 768 u8 num_msdus; 769 u8 rsvd0; 770 __le16 msdus[0]; /* variable length based on %num_msdus */ 771 } __packed; 772 773 struct htt_tx_compl_ind_base { 774 u32 hdr; 775 u16 payload[1/*or more*/]; 776 } __packed; 777 778 struct htt_rc_tx_done_params { 779 u32 rate_code; 780 u32 rate_code_flags; 781 u32 flags; 782 u32 num_enqued; /* 1 for non-AMPDU */ 783 u32 num_retries; 784 u32 num_failed; /* for AMPDU */ 785 u32 ack_rssi; 786 u32 time_stamp; 787 u32 is_probe; 788 }; 789 790 struct htt_rc_update { 791 u8 vdev_id; 792 __le16 peer_id; 793 u8 addr[6]; 794 u8 num_elems; 795 u8 rsvd0; 796 struct htt_rc_tx_done_params params[0]; /* variable length %num_elems */ 797 } __packed; 798 799 /* see htt_rx_indication for similar fields and descriptions */ 800 struct htt_rx_fragment_indication { 801 union { 802 u8 info0; /* %HTT_RX_FRAG_IND_INFO0_ */ 803 struct { 804 u8 ext_tid:5, 805 flush_valid:1; 806 } __packed; 807 } __packed; 808 __le16 peer_id; 809 __le32 info1; /* %HTT_RX_FRAG_IND_INFO1_ */ 810 __le16 fw_rx_desc_bytes; 811 __le16 rsvd0; 812 813 u8 fw_msdu_rx_desc[0]; 814 } __packed; 815 816 #define HTT_RX_FRAG_IND_INFO0_EXT_TID_MASK 0x1F 817 #define HTT_RX_FRAG_IND_INFO0_EXT_TID_LSB 0 818 #define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_MASK 0x20 819 #define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_LSB 5 820 821 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_MASK 0x0000003F 822 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_LSB 0 823 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_MASK 0x00000FC0 824 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_LSB 6 825 826 struct htt_rx_pn_ind { 827 __le16 peer_id; 828 u8 tid; 829 u8 seqno_start; 830 u8 seqno_end; 831 u8 pn_ie_count; 832 u8 reserved; 833 u8 pn_ies[0]; 834 } __packed; 835 836 struct htt_rx_offload_msdu { 837 __le16 msdu_len; 838 __le16 peer_id; 839 u8 vdev_id; 840 u8 tid; 841 u8 fw_desc; 842 u8 payload[0]; 843 } __packed; 844 845 struct htt_rx_offload_ind { 846 u8 reserved; 847 __le16 msdu_count; 848 } __packed; 849 850 struct htt_rx_in_ord_msdu_desc { 851 __le32 msdu_paddr; 852 __le16 msdu_len; 853 u8 fw_desc; 854 u8 reserved; 855 } __packed; 856 857 struct htt_rx_in_ord_ind { 858 u8 info; 859 __le16 peer_id; 860 u8 vdev_id; 861 u8 reserved; 862 __le16 msdu_count; 863 struct htt_rx_in_ord_msdu_desc msdu_descs[0]; 864 } __packed; 865 866 #define HTT_RX_IN_ORD_IND_INFO_TID_MASK 0x0000001f 867 #define HTT_RX_IN_ORD_IND_INFO_TID_LSB 0 868 #define HTT_RX_IN_ORD_IND_INFO_OFFLOAD_MASK 0x00000020 869 #define HTT_RX_IN_ORD_IND_INFO_OFFLOAD_LSB 5 870 #define HTT_RX_IN_ORD_IND_INFO_FRAG_MASK 0x00000040 871 #define HTT_RX_IN_ORD_IND_INFO_FRAG_LSB 6 872 873 /* 874 * target -> host test message definition 875 * 876 * The following field definitions describe the format of the test 877 * message sent from the target to the host. 878 * The message consists of a 4-octet header, followed by a variable 879 * number of 32-bit integer values, followed by a variable number 880 * of 8-bit character values. 881 * 882 * |31 16|15 8|7 0| 883 * |-----------------------------------------------------------| 884 * | num chars | num ints | msg type | 885 * |-----------------------------------------------------------| 886 * | int 0 | 887 * |-----------------------------------------------------------| 888 * | int 1 | 889 * |-----------------------------------------------------------| 890 * | ... | 891 * |-----------------------------------------------------------| 892 * | char 3 | char 2 | char 1 | char 0 | 893 * |-----------------------------------------------------------| 894 * | | | ... | char 4 | 895 * |-----------------------------------------------------------| 896 * - MSG_TYPE 897 * Bits 7:0 898 * Purpose: identifies this as a test message 899 * Value: HTT_MSG_TYPE_TEST 900 * - NUM_INTS 901 * Bits 15:8 902 * Purpose: indicate how many 32-bit integers follow the message header 903 * - NUM_CHARS 904 * Bits 31:16 905 * Purpose: indicate how many 8-bit characters follow the series of integers 906 */ 907 struct htt_rx_test { 908 u8 num_ints; 909 __le16 num_chars; 910 911 /* payload consists of 2 lists: 912 * a) num_ints * sizeof(__le32) 913 * b) num_chars * sizeof(u8) aligned to 4bytes */ 914 u8 payload[0]; 915 } __packed; 916 917 static inline __le32 *htt_rx_test_get_ints(struct htt_rx_test *rx_test) 918 { 919 return (__le32 *)rx_test->payload; 920 } 921 922 static inline u8 *htt_rx_test_get_chars(struct htt_rx_test *rx_test) 923 { 924 return rx_test->payload + (rx_test->num_ints * sizeof(__le32)); 925 } 926 927 /* 928 * target -> host packet log message 929 * 930 * The following field definitions describe the format of the packet log 931 * message sent from the target to the host. 932 * The message consists of a 4-octet header,followed by a variable number 933 * of 32-bit character values. 934 * 935 * |31 24|23 16|15 8|7 0| 936 * |-----------------------------------------------------------| 937 * | | | | msg type | 938 * |-----------------------------------------------------------| 939 * | payload | 940 * |-----------------------------------------------------------| 941 * - MSG_TYPE 942 * Bits 7:0 943 * Purpose: identifies this as a test message 944 * Value: HTT_MSG_TYPE_PACKETLOG 945 */ 946 struct htt_pktlog_msg { 947 u8 pad[3]; 948 u8 payload[0]; 949 } __packed; 950 951 struct htt_dbg_stats_rx_reorder_stats { 952 /* Non QoS MPDUs received */ 953 __le32 deliver_non_qos; 954 955 /* MPDUs received in-order */ 956 __le32 deliver_in_order; 957 958 /* Flush due to reorder timer expired */ 959 __le32 deliver_flush_timeout; 960 961 /* Flush due to move out of window */ 962 __le32 deliver_flush_oow; 963 964 /* Flush due to DELBA */ 965 __le32 deliver_flush_delba; 966 967 /* MPDUs dropped due to FCS error */ 968 __le32 fcs_error; 969 970 /* MPDUs dropped due to monitor mode non-data packet */ 971 __le32 mgmt_ctrl; 972 973 /* MPDUs dropped due to invalid peer */ 974 __le32 invalid_peer; 975 976 /* MPDUs dropped due to duplication (non aggregation) */ 977 __le32 dup_non_aggr; 978 979 /* MPDUs dropped due to processed before */ 980 __le32 dup_past; 981 982 /* MPDUs dropped due to duplicate in reorder queue */ 983 __le32 dup_in_reorder; 984 985 /* Reorder timeout happened */ 986 __le32 reorder_timeout; 987 988 /* invalid bar ssn */ 989 __le32 invalid_bar_ssn; 990 991 /* reorder reset due to bar ssn */ 992 __le32 ssn_reset; 993 }; 994 995 struct htt_dbg_stats_wal_tx_stats { 996 /* Num HTT cookies queued to dispatch list */ 997 __le32 comp_queued; 998 999 /* Num HTT cookies dispatched */ 1000 __le32 comp_delivered; 1001 1002 /* Num MSDU queued to WAL */ 1003 __le32 msdu_enqued; 1004 1005 /* Num MPDU queue to WAL */ 1006 __le32 mpdu_enqued; 1007 1008 /* Num MSDUs dropped by WMM limit */ 1009 __le32 wmm_drop; 1010 1011 /* Num Local frames queued */ 1012 __le32 local_enqued; 1013 1014 /* Num Local frames done */ 1015 __le32 local_freed; 1016 1017 /* Num queued to HW */ 1018 __le32 hw_queued; 1019 1020 /* Num PPDU reaped from HW */ 1021 __le32 hw_reaped; 1022 1023 /* Num underruns */ 1024 __le32 underrun; 1025 1026 /* Num PPDUs cleaned up in TX abort */ 1027 __le32 tx_abort; 1028 1029 /* Num MPDUs requed by SW */ 1030 __le32 mpdus_requed; 1031 1032 /* excessive retries */ 1033 __le32 tx_ko; 1034 1035 /* data hw rate code */ 1036 __le32 data_rc; 1037 1038 /* Scheduler self triggers */ 1039 __le32 self_triggers; 1040 1041 /* frames dropped due to excessive sw retries */ 1042 __le32 sw_retry_failure; 1043 1044 /* illegal rate phy errors */ 1045 __le32 illgl_rate_phy_err; 1046 1047 /* wal pdev continuous xretry */ 1048 __le32 pdev_cont_xretry; 1049 1050 /* wal pdev continuous xretry */ 1051 __le32 pdev_tx_timeout; 1052 1053 /* wal pdev resets */ 1054 __le32 pdev_resets; 1055 1056 __le32 phy_underrun; 1057 1058 /* MPDU is more than txop limit */ 1059 __le32 txop_ovf; 1060 } __packed; 1061 1062 struct htt_dbg_stats_wal_rx_stats { 1063 /* Cnts any change in ring routing mid-ppdu */ 1064 __le32 mid_ppdu_route_change; 1065 1066 /* Total number of statuses processed */ 1067 __le32 status_rcvd; 1068 1069 /* Extra frags on rings 0-3 */ 1070 __le32 r0_frags; 1071 __le32 r1_frags; 1072 __le32 r2_frags; 1073 __le32 r3_frags; 1074 1075 /* MSDUs / MPDUs delivered to HTT */ 1076 __le32 htt_msdus; 1077 __le32 htt_mpdus; 1078 1079 /* MSDUs / MPDUs delivered to local stack */ 1080 __le32 loc_msdus; 1081 __le32 loc_mpdus; 1082 1083 /* AMSDUs that have more MSDUs than the status ring size */ 1084 __le32 oversize_amsdu; 1085 1086 /* Number of PHY errors */ 1087 __le32 phy_errs; 1088 1089 /* Number of PHY errors drops */ 1090 __le32 phy_err_drop; 1091 1092 /* Number of mpdu errors - FCS, MIC, ENC etc. */ 1093 __le32 mpdu_errs; 1094 } __packed; 1095 1096 struct htt_dbg_stats_wal_peer_stats { 1097 __le32 dummy; /* REMOVE THIS ONCE REAL PEER STAT COUNTERS ARE ADDED */ 1098 } __packed; 1099 1100 struct htt_dbg_stats_wal_pdev_txrx { 1101 struct htt_dbg_stats_wal_tx_stats tx_stats; 1102 struct htt_dbg_stats_wal_rx_stats rx_stats; 1103 struct htt_dbg_stats_wal_peer_stats peer_stats; 1104 } __packed; 1105 1106 struct htt_dbg_stats_rx_rate_info { 1107 __le32 mcs[10]; 1108 __le32 sgi[10]; 1109 __le32 nss[4]; 1110 __le32 stbc[10]; 1111 __le32 bw[3]; 1112 __le32 pream[6]; 1113 __le32 ldpc; 1114 __le32 txbf; 1115 }; 1116 1117 /* 1118 * htt_dbg_stats_status - 1119 * present - The requested stats have been delivered in full. 1120 * This indicates that either the stats information was contained 1121 * in its entirety within this message, or else this message 1122 * completes the delivery of the requested stats info that was 1123 * partially delivered through earlier STATS_CONF messages. 1124 * partial - The requested stats have been delivered in part. 1125 * One or more subsequent STATS_CONF messages with the same 1126 * cookie value will be sent to deliver the remainder of the 1127 * information. 1128 * error - The requested stats could not be delivered, for example due 1129 * to a shortage of memory to construct a message holding the 1130 * requested stats. 1131 * invalid - The requested stat type is either not recognized, or the 1132 * target is configured to not gather the stats type in question. 1133 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1134 * series_done - This special value indicates that no further stats info 1135 * elements are present within a series of stats info elems 1136 * (within a stats upload confirmation message). 1137 */ 1138 enum htt_dbg_stats_status { 1139 HTT_DBG_STATS_STATUS_PRESENT = 0, 1140 HTT_DBG_STATS_STATUS_PARTIAL = 1, 1141 HTT_DBG_STATS_STATUS_ERROR = 2, 1142 HTT_DBG_STATS_STATUS_INVALID = 3, 1143 HTT_DBG_STATS_STATUS_SERIES_DONE = 7 1144 }; 1145 1146 /* 1147 * target -> host statistics upload 1148 * 1149 * The following field definitions describe the format of the HTT target 1150 * to host stats upload confirmation message. 1151 * The message contains a cookie echoed from the HTT host->target stats 1152 * upload request, which identifies which request the confirmation is 1153 * for, and a series of tag-length-value stats information elements. 1154 * The tag-length header for each stats info element also includes a 1155 * status field, to indicate whether the request for the stat type in 1156 * question was fully met, partially met, unable to be met, or invalid 1157 * (if the stat type in question is disabled in the target). 1158 * A special value of all 1's in this status field is used to indicate 1159 * the end of the series of stats info elements. 1160 * 1161 * 1162 * |31 16|15 8|7 5|4 0| 1163 * |------------------------------------------------------------| 1164 * | reserved | msg type | 1165 * |------------------------------------------------------------| 1166 * | cookie LSBs | 1167 * |------------------------------------------------------------| 1168 * | cookie MSBs | 1169 * |------------------------------------------------------------| 1170 * | stats entry length | reserved | S |stat type| 1171 * |------------------------------------------------------------| 1172 * | | 1173 * | type-specific stats info | 1174 * | | 1175 * |------------------------------------------------------------| 1176 * | stats entry length | reserved | S |stat type| 1177 * |------------------------------------------------------------| 1178 * | | 1179 * | type-specific stats info | 1180 * | | 1181 * |------------------------------------------------------------| 1182 * | n/a | reserved | 111 | n/a | 1183 * |------------------------------------------------------------| 1184 * Header fields: 1185 * - MSG_TYPE 1186 * Bits 7:0 1187 * Purpose: identifies this is a statistics upload confirmation message 1188 * Value: 0x9 1189 * - COOKIE_LSBS 1190 * Bits 31:0 1191 * Purpose: Provide a mechanism to match a target->host stats confirmation 1192 * message with its preceding host->target stats request message. 1193 * Value: LSBs of the opaque cookie specified by the host-side requestor 1194 * - COOKIE_MSBS 1195 * Bits 31:0 1196 * Purpose: Provide a mechanism to match a target->host stats confirmation 1197 * message with its preceding host->target stats request message. 1198 * Value: MSBs of the opaque cookie specified by the host-side requestor 1199 * 1200 * Stats Information Element tag-length header fields: 1201 * - STAT_TYPE 1202 * Bits 4:0 1203 * Purpose: identifies the type of statistics info held in the 1204 * following information element 1205 * Value: htt_dbg_stats_type 1206 * - STATUS 1207 * Bits 7:5 1208 * Purpose: indicate whether the requested stats are present 1209 * Value: htt_dbg_stats_status, including a special value (0x7) to mark 1210 * the completion of the stats entry series 1211 * - LENGTH 1212 * Bits 31:16 1213 * Purpose: indicate the stats information size 1214 * Value: This field specifies the number of bytes of stats information 1215 * that follows the element tag-length header. 1216 * It is expected but not required that this length is a multiple of 1217 * 4 bytes. Even if the length is not an integer multiple of 4, the 1218 * subsequent stats entry header will begin on a 4-byte aligned 1219 * boundary. 1220 */ 1221 1222 #define HTT_STATS_CONF_ITEM_INFO_STAT_TYPE_MASK 0x1F 1223 #define HTT_STATS_CONF_ITEM_INFO_STAT_TYPE_LSB 0 1224 #define HTT_STATS_CONF_ITEM_INFO_STATUS_MASK 0xE0 1225 #define HTT_STATS_CONF_ITEM_INFO_STATUS_LSB 5 1226 1227 struct htt_stats_conf_item { 1228 union { 1229 u8 info; 1230 struct { 1231 u8 stat_type:5; /* %HTT_DBG_STATS_ */ 1232 u8 status:3; /* %HTT_DBG_STATS_STATUS_ */ 1233 } __packed; 1234 } __packed; 1235 u8 pad; 1236 __le16 length; 1237 u8 payload[0]; /* roundup(length, 4) long */ 1238 } __packed; 1239 1240 struct htt_stats_conf { 1241 u8 pad[3]; 1242 __le32 cookie_lsb; 1243 __le32 cookie_msb; 1244 1245 /* each item has variable length! */ 1246 struct htt_stats_conf_item items[0]; 1247 } __packed; 1248 1249 static inline struct htt_stats_conf_item *htt_stats_conf_next_item( 1250 const struct htt_stats_conf_item *item) 1251 { 1252 return (void *)item + sizeof(*item) + roundup(item->length, 4); 1253 } 1254 1255 /* 1256 * host -> target FRAG DESCRIPTOR/MSDU_EXT DESC bank 1257 * 1258 * The following field definitions describe the format of the HTT host 1259 * to target frag_desc/msdu_ext bank configuration message. 1260 * The message contains the based address and the min and max id of the 1261 * MSDU_EXT/FRAG_DESC that will be used by the HTT to map MSDU DESC and 1262 * MSDU_EXT/FRAG_DESC. 1263 * HTT will use id in HTT descriptor instead sending the frag_desc_ptr. 1264 * For QCA988X HW the firmware will use fragment_desc_ptr but in WIFI2.0 1265 * the hardware does the mapping/translation. 1266 * 1267 * Total banks that can be configured is configured to 16. 1268 * 1269 * This should be called before any TX has be initiated by the HTT 1270 * 1271 * |31 16|15 8|7 5|4 0| 1272 * |------------------------------------------------------------| 1273 * | DESC_SIZE | NUM_BANKS | RES |SWP|pdev| msg type | 1274 * |------------------------------------------------------------| 1275 * | BANK0_BASE_ADDRESS | 1276 * |------------------------------------------------------------| 1277 * | ... | 1278 * |------------------------------------------------------------| 1279 * | BANK15_BASE_ADDRESS | 1280 * |------------------------------------------------------------| 1281 * | BANK0_MAX_ID | BANK0_MIN_ID | 1282 * |------------------------------------------------------------| 1283 * | ... | 1284 * |------------------------------------------------------------| 1285 * | BANK15_MAX_ID | BANK15_MIN_ID | 1286 * |------------------------------------------------------------| 1287 * Header fields: 1288 * - MSG_TYPE 1289 * Bits 7:0 1290 * Value: 0x6 1291 * - BANKx_BASE_ADDRESS 1292 * Bits 31:0 1293 * Purpose: Provide a mechanism to specify the base address of the MSDU_EXT 1294 * bank physical/bus address. 1295 * - BANKx_MIN_ID 1296 * Bits 15:0 1297 * Purpose: Provide a mechanism to specify the min index that needs to 1298 * mapped. 1299 * - BANKx_MAX_ID 1300 * Bits 31:16 1301 * Purpose: Provide a mechanism to specify the max index that needs to 1302 * 1303 */ 1304 struct htt_frag_desc_bank_id { 1305 __le16 bank_min_id; 1306 __le16 bank_max_id; 1307 } __packed; 1308 1309 /* real is 16 but it wouldn't fit in the max htt message size 1310 * so we use a conservatively safe value for now */ 1311 #define HTT_FRAG_DESC_BANK_MAX 4 1312 1313 #define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_MASK 0x03 1314 #define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_LSB 0 1315 #define HTT_FRAG_DESC_BANK_CFG_INFO_SWAP BIT(2) 1316 #define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_VALID BIT(3) 1317 #define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE_MASK BIT(4) 1318 #define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE_LSB 4 1319 1320 enum htt_q_depth_type { 1321 HTT_Q_DEPTH_TYPE_BYTES = 0, 1322 HTT_Q_DEPTH_TYPE_MSDUS = 1, 1323 }; 1324 1325 #define HTT_TX_Q_STATE_NUM_PEERS (TARGET_10_4_NUM_QCACHE_PEERS_MAX + \ 1326 TARGET_10_4_NUM_VDEVS) 1327 #define HTT_TX_Q_STATE_NUM_TIDS 8 1328 #define HTT_TX_Q_STATE_ENTRY_SIZE 1 1329 #define HTT_TX_Q_STATE_ENTRY_MULTIPLIER 0 1330 1331 /** 1332 * htt_q_state_conf - part of htt_frag_desc_bank_cfg for host q state config 1333 * 1334 * Defines host q state format and behavior. See htt_q_state. 1335 * 1336 * @record_size: Defines the size of each host q entry in bytes. In practice 1337 * however firmware (at least 10.4.3-00191) ignores this host 1338 * configuration value and uses hardcoded value of 1. 1339 * @record_multiplier: This is valid only when q depth type is MSDUs. It 1340 * defines the exponent for the power of 2 multiplication. 1341 */ 1342 struct htt_q_state_conf { 1343 __le32 paddr; 1344 __le16 num_peers; 1345 __le16 num_tids; 1346 u8 record_size; 1347 u8 record_multiplier; 1348 u8 pad[2]; 1349 } __packed; 1350 1351 struct htt_frag_desc_bank_cfg { 1352 u8 info; /* HTT_FRAG_DESC_BANK_CFG_INFO_ */ 1353 u8 num_banks; 1354 u8 desc_size; 1355 __le32 bank_base_addrs[HTT_FRAG_DESC_BANK_MAX]; 1356 struct htt_frag_desc_bank_id bank_id[HTT_FRAG_DESC_BANK_MAX]; 1357 struct htt_q_state_conf q_state; 1358 } __packed; 1359 1360 #define HTT_TX_Q_STATE_ENTRY_COEFFICIENT 128 1361 #define HTT_TX_Q_STATE_ENTRY_FACTOR_MASK 0x3f 1362 #define HTT_TX_Q_STATE_ENTRY_FACTOR_LSB 0 1363 #define HTT_TX_Q_STATE_ENTRY_EXP_MASK 0xc0 1364 #define HTT_TX_Q_STATE_ENTRY_EXP_LSB 6 1365 1366 /** 1367 * htt_q_state - shared between host and firmware via DMA 1368 * 1369 * This structure is used for the host to expose it's software queue state to 1370 * firmware so that its rate control can schedule fetch requests for optimized 1371 * performance. This is most notably used for MU-MIMO aggregation when multiple 1372 * MU clients are connected. 1373 * 1374 * @count: Each element defines the host queue depth. When q depth type was 1375 * configured as HTT_Q_DEPTH_TYPE_BYTES then each entry is defined as: 1376 * FACTOR * 128 * 8^EXP (see HTT_TX_Q_STATE_ENTRY_FACTOR_MASK and 1377 * HTT_TX_Q_STATE_ENTRY_EXP_MASK). When q depth type was configured as 1378 * HTT_Q_DEPTH_TYPE_MSDUS the number of packets is scaled by 2 ** 1379 * record_multiplier (see htt_q_state_conf). 1380 * @map: Used by firmware to quickly check which host queues are not empty. It 1381 * is a bitmap simply saying. 1382 * @seq: Used by firmware to quickly check if the host queues were updated 1383 * since it last checked. 1384 * 1385 * FIXME: Is the q_state map[] size calculation really correct? 1386 */ 1387 struct htt_q_state { 1388 u8 count[HTT_TX_Q_STATE_NUM_TIDS][HTT_TX_Q_STATE_NUM_PEERS]; 1389 u32 map[HTT_TX_Q_STATE_NUM_TIDS][(HTT_TX_Q_STATE_NUM_PEERS + 31) / 32]; 1390 __le32 seq; 1391 } __packed; 1392 1393 #define HTT_TX_FETCH_RECORD_INFO_PEER_ID_MASK 0x0fff 1394 #define HTT_TX_FETCH_RECORD_INFO_PEER_ID_LSB 0 1395 #define HTT_TX_FETCH_RECORD_INFO_TID_MASK 0xf000 1396 #define HTT_TX_FETCH_RECORD_INFO_TID_LSB 12 1397 1398 struct htt_tx_fetch_record { 1399 __le16 info; /* HTT_TX_FETCH_IND_RECORD_INFO_ */ 1400 __le16 num_msdus; 1401 __le32 num_bytes; 1402 } __packed; 1403 1404 struct htt_tx_fetch_ind { 1405 u8 pad0; 1406 __le16 fetch_seq_num; 1407 __le32 token; 1408 __le16 num_resp_ids; 1409 __le16 num_records; 1410 struct htt_tx_fetch_record records[0]; 1411 __le32 resp_ids[0]; /* ath10k_htt_get_tx_fetch_ind_resp_ids() */ 1412 } __packed; 1413 1414 static inline void * 1415 ath10k_htt_get_tx_fetch_ind_resp_ids(struct htt_tx_fetch_ind *ind) 1416 { 1417 return (void *)&ind->records[le16_to_cpu(ind->num_records)]; 1418 } 1419 1420 struct htt_tx_fetch_resp { 1421 u8 pad0; 1422 __le16 resp_id; 1423 __le16 fetch_seq_num; 1424 __le16 num_records; 1425 __le32 token; 1426 struct htt_tx_fetch_record records[0]; 1427 } __packed; 1428 1429 struct htt_tx_fetch_confirm { 1430 u8 pad0; 1431 __le16 num_resp_ids; 1432 __le32 resp_ids[0]; 1433 } __packed; 1434 1435 enum htt_tx_mode_switch_mode { 1436 HTT_TX_MODE_SWITCH_PUSH = 0, 1437 HTT_TX_MODE_SWITCH_PUSH_PULL = 1, 1438 }; 1439 1440 #define HTT_TX_MODE_SWITCH_IND_INFO0_ENABLE BIT(0) 1441 #define HTT_TX_MODE_SWITCH_IND_INFO0_NUM_RECORDS_MASK 0xfffe 1442 #define HTT_TX_MODE_SWITCH_IND_INFO0_NUM_RECORDS_LSB 1 1443 1444 #define HTT_TX_MODE_SWITCH_IND_INFO1_MODE_MASK 0x0003 1445 #define HTT_TX_MODE_SWITCH_IND_INFO1_MODE_LSB 0 1446 #define HTT_TX_MODE_SWITCH_IND_INFO1_THRESHOLD_MASK 0xfffc 1447 #define HTT_TX_MODE_SWITCH_IND_INFO1_THRESHOLD_LSB 2 1448 1449 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_PEER_ID_MASK 0x0fff 1450 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_PEER_ID_LSB 0 1451 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_TID_MASK 0xf000 1452 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_TID_LSB 12 1453 1454 struct htt_tx_mode_switch_record { 1455 __le16 info0; /* HTT_TX_MODE_SWITCH_RECORD_INFO0_ */ 1456 __le16 num_max_msdus; 1457 } __packed; 1458 1459 struct htt_tx_mode_switch_ind { 1460 u8 pad0; 1461 __le16 info0; /* HTT_TX_MODE_SWITCH_IND_INFO0_ */ 1462 __le16 info1; /* HTT_TX_MODE_SWITCH_IND_INFO1_ */ 1463 u8 pad1[2]; 1464 struct htt_tx_mode_switch_record records[0]; 1465 } __packed; 1466 1467 struct htt_channel_change { 1468 u8 pad[3]; 1469 __le32 freq; 1470 __le32 center_freq1; 1471 __le32 center_freq2; 1472 __le32 phymode; 1473 } __packed; 1474 1475 struct htt_per_peer_tx_stats_ind { 1476 __le32 succ_bytes; 1477 __le32 retry_bytes; 1478 __le32 failed_bytes; 1479 u8 ratecode; 1480 u8 flags; 1481 __le16 peer_id; 1482 __le16 succ_pkts; 1483 __le16 retry_pkts; 1484 __le16 failed_pkts; 1485 __le16 tx_duration; 1486 __le32 reserved1; 1487 __le32 reserved2; 1488 } __packed; 1489 1490 struct htt_peer_tx_stats { 1491 u8 num_ppdu; 1492 u8 ppdu_len; 1493 u8 version; 1494 u8 payload[0]; 1495 } __packed; 1496 1497 union htt_rx_pn_t { 1498 /* WEP: 24-bit PN */ 1499 u32 pn24; 1500 1501 /* TKIP or CCMP: 48-bit PN */ 1502 u64 pn48; 1503 1504 /* WAPI: 128-bit PN */ 1505 u64 pn128[2]; 1506 }; 1507 1508 struct htt_cmd { 1509 struct htt_cmd_hdr hdr; 1510 union { 1511 struct htt_ver_req ver_req; 1512 struct htt_mgmt_tx_desc mgmt_tx; 1513 struct htt_data_tx_desc data_tx; 1514 struct htt_rx_ring_setup rx_setup; 1515 struct htt_stats_req stats_req; 1516 struct htt_oob_sync_req oob_sync_req; 1517 struct htt_aggr_conf aggr_conf; 1518 struct htt_frag_desc_bank_cfg frag_desc_bank_cfg; 1519 struct htt_tx_fetch_resp tx_fetch_resp; 1520 }; 1521 } __packed; 1522 1523 struct htt_resp { 1524 struct htt_resp_hdr hdr; 1525 union { 1526 struct htt_ver_resp ver_resp; 1527 struct htt_mgmt_tx_completion mgmt_tx_completion; 1528 struct htt_data_tx_completion data_tx_completion; 1529 struct htt_rx_indication rx_ind; 1530 struct htt_rx_fragment_indication rx_frag_ind; 1531 struct htt_rx_peer_map peer_map; 1532 struct htt_rx_peer_unmap peer_unmap; 1533 struct htt_rx_flush rx_flush; 1534 struct htt_rx_addba rx_addba; 1535 struct htt_rx_delba rx_delba; 1536 struct htt_security_indication security_indication; 1537 struct htt_rc_update rc_update; 1538 struct htt_rx_test rx_test; 1539 struct htt_pktlog_msg pktlog_msg; 1540 struct htt_stats_conf stats_conf; 1541 struct htt_rx_pn_ind rx_pn_ind; 1542 struct htt_rx_offload_ind rx_offload_ind; 1543 struct htt_rx_in_ord_ind rx_in_ord_ind; 1544 struct htt_tx_fetch_ind tx_fetch_ind; 1545 struct htt_tx_fetch_confirm tx_fetch_confirm; 1546 struct htt_tx_mode_switch_ind tx_mode_switch_ind; 1547 struct htt_channel_change chan_change; 1548 struct htt_peer_tx_stats peer_tx_stats; 1549 }; 1550 } __packed; 1551 1552 /*** host side structures follow ***/ 1553 1554 struct htt_tx_done { 1555 u16 msdu_id; 1556 u16 status; 1557 }; 1558 1559 enum htt_tx_compl_state { 1560 HTT_TX_COMPL_STATE_NONE, 1561 HTT_TX_COMPL_STATE_ACK, 1562 HTT_TX_COMPL_STATE_NOACK, 1563 HTT_TX_COMPL_STATE_DISCARD, 1564 }; 1565 1566 struct htt_peer_map_event { 1567 u8 vdev_id; 1568 u16 peer_id; 1569 u8 addr[ETH_ALEN]; 1570 }; 1571 1572 struct htt_peer_unmap_event { 1573 u16 peer_id; 1574 }; 1575 1576 struct ath10k_htt_txbuf { 1577 struct htt_data_tx_desc_frag frags[2]; 1578 struct ath10k_htc_hdr htc_hdr; 1579 struct htt_cmd_hdr cmd_hdr; 1580 struct htt_data_tx_desc cmd_tx; 1581 } __packed; 1582 1583 struct ath10k_htt { 1584 struct ath10k *ar; 1585 enum ath10k_htc_ep_id eid; 1586 1587 u8 target_version_major; 1588 u8 target_version_minor; 1589 struct completion target_version_received; 1590 u8 max_num_amsdu; 1591 u8 max_num_ampdu; 1592 1593 const enum htt_t2h_msg_type *t2h_msg_types; 1594 u32 t2h_msg_types_max; 1595 1596 struct { 1597 /* 1598 * Ring of network buffer objects - This ring is 1599 * used exclusively by the host SW. This ring 1600 * mirrors the dev_addrs_ring that is shared 1601 * between the host SW and the MAC HW. The host SW 1602 * uses this netbufs ring to locate the network 1603 * buffer objects whose data buffers the HW has 1604 * filled. 1605 */ 1606 struct sk_buff **netbufs_ring; 1607 1608 /* This is used only with firmware supporting IN_ORD_IND. 1609 * 1610 * With Full Rx Reorder the HTT Rx Ring is more of a temporary 1611 * buffer ring from which buffer addresses are copied by the 1612 * firmware to MAC Rx ring. Firmware then delivers IN_ORD_IND 1613 * pointing to specific (re-ordered) buffers. 1614 * 1615 * FIXME: With kernel generic hashing functions there's a lot 1616 * of hash collisions for sk_buffs. 1617 */ 1618 bool in_ord_rx; 1619 DECLARE_HASHTABLE(skb_table, 4); 1620 1621 /* 1622 * Ring of buffer addresses - 1623 * This ring holds the "physical" device address of the 1624 * rx buffers the host SW provides for the MAC HW to 1625 * fill. 1626 */ 1627 __le32 *paddrs_ring; 1628 1629 /* 1630 * Base address of ring, as a "physical" device address 1631 * rather than a CPU address. 1632 */ 1633 dma_addr_t base_paddr; 1634 1635 /* how many elems in the ring (power of 2) */ 1636 int size; 1637 1638 /* size - 1 */ 1639 unsigned int size_mask; 1640 1641 /* how many rx buffers to keep in the ring */ 1642 int fill_level; 1643 1644 /* how many rx buffers (full+empty) are in the ring */ 1645 int fill_cnt; 1646 1647 /* 1648 * alloc_idx - where HTT SW has deposited empty buffers 1649 * This is allocated in consistent mem, so that the FW can 1650 * read this variable, and program the HW's FW_IDX reg with 1651 * the value of this shadow register. 1652 */ 1653 struct { 1654 __le32 *vaddr; 1655 dma_addr_t paddr; 1656 } alloc_idx; 1657 1658 /* where HTT SW has processed bufs filled by rx MAC DMA */ 1659 struct { 1660 unsigned int msdu_payld; 1661 } sw_rd_idx; 1662 1663 /* 1664 * refill_retry_timer - timer triggered when the ring is 1665 * not refilled to the level expected 1666 */ 1667 struct timer_list refill_retry_timer; 1668 1669 /* Protects access to all rx ring buffer state variables */ 1670 spinlock_t lock; 1671 } rx_ring; 1672 1673 unsigned int prefetch_len; 1674 1675 /* Protects access to pending_tx, num_pending_tx */ 1676 spinlock_t tx_lock; 1677 int max_num_pending_tx; 1678 int num_pending_tx; 1679 int num_pending_mgmt_tx; 1680 struct idr pending_tx; 1681 wait_queue_head_t empty_tx_wq; 1682 1683 /* FIFO for storing tx done status {ack, no-ack, discard} and msdu id */ 1684 DECLARE_KFIFO_PTR(txdone_fifo, struct htt_tx_done); 1685 1686 /* set if host-fw communication goes haywire 1687 * used to avoid further failures */ 1688 bool rx_confused; 1689 atomic_t num_mpdus_ready; 1690 1691 /* This is used to group tx/rx completions separately and process them 1692 * in batches to reduce cache stalls */ 1693 struct sk_buff_head rx_compl_q; 1694 struct sk_buff_head rx_in_ord_compl_q; 1695 struct sk_buff_head tx_fetch_ind_q; 1696 1697 /* rx_status template */ 1698 struct ieee80211_rx_status rx_status; 1699 1700 struct { 1701 dma_addr_t paddr; 1702 struct htt_msdu_ext_desc *vaddr; 1703 } frag_desc; 1704 1705 struct { 1706 dma_addr_t paddr; 1707 struct ath10k_htt_txbuf *vaddr; 1708 } txbuf; 1709 1710 struct { 1711 bool enabled; 1712 struct htt_q_state *vaddr; 1713 dma_addr_t paddr; 1714 u16 num_push_allowed; 1715 u16 num_peers; 1716 u16 num_tids; 1717 enum htt_tx_mode_switch_mode mode; 1718 enum htt_q_depth_type type; 1719 } tx_q_state; 1720 1721 bool tx_mem_allocated; 1722 }; 1723 1724 #define RX_HTT_HDR_STATUS_LEN 64 1725 1726 /* This structure layout is programmed via rx ring setup 1727 * so that FW knows how to transfer the rx descriptor to the host. 1728 * Buffers like this are placed on the rx ring. */ 1729 struct htt_rx_desc { 1730 union { 1731 /* This field is filled on the host using the msdu buffer 1732 * from htt_rx_indication */ 1733 struct fw_rx_desc_base fw_desc; 1734 u32 pad; 1735 } __packed; 1736 struct { 1737 struct rx_attention attention; 1738 struct rx_frag_info frag_info; 1739 struct rx_mpdu_start mpdu_start; 1740 struct rx_msdu_start msdu_start; 1741 struct rx_msdu_end msdu_end; 1742 struct rx_mpdu_end mpdu_end; 1743 struct rx_ppdu_start ppdu_start; 1744 struct rx_ppdu_end ppdu_end; 1745 } __packed; 1746 u8 rx_hdr_status[RX_HTT_HDR_STATUS_LEN]; 1747 u8 msdu_payload[0]; 1748 }; 1749 1750 #define HTT_RX_DESC_ALIGN 8 1751 1752 #define HTT_MAC_ADDR_LEN 6 1753 1754 /* 1755 * FIX THIS 1756 * Should be: sizeof(struct htt_host_rx_desc) + max rx MSDU size, 1757 * rounded up to a cache line size. 1758 */ 1759 #define HTT_RX_BUF_SIZE 1920 1760 #define HTT_RX_MSDU_SIZE (HTT_RX_BUF_SIZE - (int)sizeof(struct htt_rx_desc)) 1761 1762 /* Refill a bunch of RX buffers for each refill round so that FW/HW can handle 1763 * aggregated traffic more nicely. */ 1764 #define ATH10K_HTT_MAX_NUM_REFILL 100 1765 1766 /* 1767 * DMA_MAP expects the buffer to be an integral number of cache lines. 1768 * Rather than checking the actual cache line size, this code makes a 1769 * conservative estimate of what the cache line size could be. 1770 */ 1771 #define HTT_LOG2_MAX_CACHE_LINE_SIZE 7 /* 2^7 = 128 */ 1772 #define HTT_MAX_CACHE_LINE_SIZE_MASK ((1 << HTT_LOG2_MAX_CACHE_LINE_SIZE) - 1) 1773 1774 /* These values are default in most firmware revisions and apparently are a 1775 * sweet spot performance wise. 1776 */ 1777 #define ATH10K_HTT_MAX_NUM_AMSDU_DEFAULT 3 1778 #define ATH10K_HTT_MAX_NUM_AMPDU_DEFAULT 64 1779 1780 int ath10k_htt_connect(struct ath10k_htt *htt); 1781 int ath10k_htt_init(struct ath10k *ar); 1782 int ath10k_htt_setup(struct ath10k_htt *htt); 1783 1784 int ath10k_htt_tx_start(struct ath10k_htt *htt); 1785 void ath10k_htt_tx_stop(struct ath10k_htt *htt); 1786 void ath10k_htt_tx_destroy(struct ath10k_htt *htt); 1787 void ath10k_htt_tx_free(struct ath10k_htt *htt); 1788 1789 int ath10k_htt_rx_alloc(struct ath10k_htt *htt); 1790 int ath10k_htt_rx_ring_refill(struct ath10k *ar); 1791 void ath10k_htt_rx_free(struct ath10k_htt *htt); 1792 1793 void ath10k_htt_htc_tx_complete(struct ath10k *ar, struct sk_buff *skb); 1794 void ath10k_htt_htc_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb); 1795 bool ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb); 1796 int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt); 1797 int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u8 mask, u64 cookie); 1798 int ath10k_htt_send_frag_desc_bank_cfg(struct ath10k_htt *htt); 1799 int ath10k_htt_send_rx_ring_cfg_ll(struct ath10k_htt *htt); 1800 int ath10k_htt_h2t_aggr_cfg_msg(struct ath10k_htt *htt, 1801 u8 max_subfrms_ampdu, 1802 u8 max_subfrms_amsdu); 1803 void ath10k_htt_hif_tx_complete(struct ath10k *ar, struct sk_buff *skb); 1804 int ath10k_htt_tx_fetch_resp(struct ath10k *ar, 1805 __le32 token, 1806 __le16 fetch_seq_num, 1807 struct htt_tx_fetch_record *records, 1808 size_t num_records); 1809 1810 void ath10k_htt_tx_txq_update(struct ieee80211_hw *hw, 1811 struct ieee80211_txq *txq); 1812 void ath10k_htt_tx_txq_recalc(struct ieee80211_hw *hw, 1813 struct ieee80211_txq *txq); 1814 void ath10k_htt_tx_txq_sync(struct ath10k *ar); 1815 void ath10k_htt_tx_dec_pending(struct ath10k_htt *htt); 1816 int ath10k_htt_tx_inc_pending(struct ath10k_htt *htt); 1817 void ath10k_htt_tx_mgmt_dec_pending(struct ath10k_htt *htt); 1818 int ath10k_htt_tx_mgmt_inc_pending(struct ath10k_htt *htt, bool is_mgmt, 1819 bool is_presp); 1820 1821 int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt, struct sk_buff *skb); 1822 void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id); 1823 int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *msdu); 1824 int ath10k_htt_tx(struct ath10k_htt *htt, 1825 enum ath10k_hw_txrx_mode txmode, 1826 struct sk_buff *msdu); 1827 void ath10k_htt_rx_pktlog_completion_handler(struct ath10k *ar, 1828 struct sk_buff *skb); 1829 int ath10k_htt_txrx_compl_task(struct ath10k *ar, int budget); 1830 1831 #endif 1832