1 /* 2 * Copyright (c) 2005-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef _HTT_H_ 19 #define _HTT_H_ 20 21 #include <linux/bug.h> 22 #include <linux/interrupt.h> 23 #include <linux/dmapool.h> 24 25 #include "htc.h" 26 #include "rx_desc.h" 27 28 enum htt_dbg_stats_type { 29 HTT_DBG_STATS_WAL_PDEV_TXRX = 1 << 0, 30 HTT_DBG_STATS_RX_REORDER = 1 << 1, 31 HTT_DBG_STATS_RX_RATE_INFO = 1 << 2, 32 HTT_DBG_STATS_TX_PPDU_LOG = 1 << 3, 33 HTT_DBG_STATS_TX_RATE_INFO = 1 << 4, 34 /* bits 5-23 currently reserved */ 35 36 HTT_DBG_NUM_STATS /* keep this last */ 37 }; 38 39 enum htt_h2t_msg_type { /* host-to-target */ 40 HTT_H2T_MSG_TYPE_VERSION_REQ = 0, 41 HTT_H2T_MSG_TYPE_TX_FRM = 1, 42 HTT_H2T_MSG_TYPE_RX_RING_CFG = 2, 43 HTT_H2T_MSG_TYPE_STATS_REQ = 3, 44 HTT_H2T_MSG_TYPE_SYNC = 4, 45 HTT_H2T_MSG_TYPE_AGGR_CFG = 5, 46 HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG = 6, 47 48 /* This command is used for sending management frames in HTT < 3.0. 49 * HTT >= 3.0 uses TX_FRM for everything. */ 50 HTT_H2T_MSG_TYPE_MGMT_TX = 7, 51 52 HTT_H2T_NUM_MSGS /* keep this last */ 53 }; 54 55 struct htt_cmd_hdr { 56 u8 msg_type; 57 } __packed; 58 59 struct htt_ver_req { 60 u8 pad[sizeof(u32) - sizeof(struct htt_cmd_hdr)]; 61 } __packed; 62 63 /* 64 * HTT tx MSDU descriptor 65 * 66 * The HTT tx MSDU descriptor is created by the host HTT SW for each 67 * tx MSDU. The HTT tx MSDU descriptor contains the information that 68 * the target firmware needs for the FW's tx processing, particularly 69 * for creating the HW msdu descriptor. 70 * The same HTT tx descriptor is used for HL and LL systems, though 71 * a few fields within the tx descriptor are used only by LL or 72 * only by HL. 73 * The HTT tx descriptor is defined in two manners: by a struct with 74 * bitfields, and by a series of [dword offset, bit mask, bit shift] 75 * definitions. 76 * The target should use the struct def, for simplicitly and clarity, 77 * but the host shall use the bit-mast + bit-shift defs, to be endian- 78 * neutral. Specifically, the host shall use the get/set macros built 79 * around the mask + shift defs. 80 */ 81 struct htt_data_tx_desc_frag { 82 __le32 paddr; 83 __le32 len; 84 } __packed; 85 86 enum htt_data_tx_desc_flags0 { 87 HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT = 1 << 0, 88 HTT_DATA_TX_DESC_FLAGS0_NO_AGGR = 1 << 1, 89 HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT = 1 << 2, 90 HTT_DATA_TX_DESC_FLAGS0_NO_CLASSIFY = 1 << 3, 91 HTT_DATA_TX_DESC_FLAGS0_RSVD0 = 1 << 4 92 #define HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE_MASK 0xE0 93 #define HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE_LSB 5 94 }; 95 96 enum htt_data_tx_desc_flags1 { 97 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_BITS 6 98 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_MASK 0x003F 99 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_LSB 0 100 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_BITS 5 101 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_MASK 0x07C0 102 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_LSB 6 103 HTT_DATA_TX_DESC_FLAGS1_POSTPONED = 1 << 11, 104 HTT_DATA_TX_DESC_FLAGS1_MORE_IN_BATCH = 1 << 12, 105 HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD = 1 << 13, 106 HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD = 1 << 14, 107 HTT_DATA_TX_DESC_FLAGS1_RSVD1 = 1 << 15 108 }; 109 110 enum htt_data_tx_ext_tid { 111 HTT_DATA_TX_EXT_TID_NON_QOS_MCAST_BCAST = 16, 112 HTT_DATA_TX_EXT_TID_MGMT = 17, 113 HTT_DATA_TX_EXT_TID_INVALID = 31 114 }; 115 116 #define HTT_INVALID_PEERID 0xFFFF 117 118 /* 119 * htt_data_tx_desc - used for data tx path 120 * 121 * Note: vdev_id irrelevant for pkt_type == raw and no_classify == 1. 122 * ext_tid: for qos-data frames (0-15), see %HTT_DATA_TX_EXT_TID_ 123 * for special kinds of tids 124 * postponed: only for HL hosts. indicates if this is a resend 125 * (HL hosts manage queues on the host ) 126 * more_in_batch: only for HL hosts. indicates if more packets are 127 * pending. this allows target to wait and aggregate 128 */ 129 struct htt_data_tx_desc { 130 u8 flags0; /* %HTT_DATA_TX_DESC_FLAGS0_ */ 131 __le16 flags1; /* %HTT_DATA_TX_DESC_FLAGS1_ */ 132 __le16 len; 133 __le16 id; 134 __le32 frags_paddr; 135 __le32 peerid; 136 u8 prefetch[0]; /* start of frame, for FW classification engine */ 137 } __packed; 138 139 enum htt_rx_ring_flags { 140 HTT_RX_RING_FLAGS_MAC80211_HDR = 1 << 0, 141 HTT_RX_RING_FLAGS_MSDU_PAYLOAD = 1 << 1, 142 HTT_RX_RING_FLAGS_PPDU_START = 1 << 2, 143 HTT_RX_RING_FLAGS_PPDU_END = 1 << 3, 144 HTT_RX_RING_FLAGS_MPDU_START = 1 << 4, 145 HTT_RX_RING_FLAGS_MPDU_END = 1 << 5, 146 HTT_RX_RING_FLAGS_MSDU_START = 1 << 6, 147 HTT_RX_RING_FLAGS_MSDU_END = 1 << 7, 148 HTT_RX_RING_FLAGS_RX_ATTENTION = 1 << 8, 149 HTT_RX_RING_FLAGS_FRAG_INFO = 1 << 9, 150 HTT_RX_RING_FLAGS_UNICAST_RX = 1 << 10, 151 HTT_RX_RING_FLAGS_MULTICAST_RX = 1 << 11, 152 HTT_RX_RING_FLAGS_CTRL_RX = 1 << 12, 153 HTT_RX_RING_FLAGS_MGMT_RX = 1 << 13, 154 HTT_RX_RING_FLAGS_NULL_RX = 1 << 14, 155 HTT_RX_RING_FLAGS_PHY_DATA_RX = 1 << 15 156 }; 157 158 struct htt_rx_ring_setup_ring { 159 __le32 fw_idx_shadow_reg_paddr; 160 __le32 rx_ring_base_paddr; 161 __le16 rx_ring_len; /* in 4-byte words */ 162 __le16 rx_ring_bufsize; /* rx skb size - in bytes */ 163 __le16 flags; /* %HTT_RX_RING_FLAGS_ */ 164 __le16 fw_idx_init_val; 165 166 /* the following offsets are in 4-byte units */ 167 __le16 mac80211_hdr_offset; 168 __le16 msdu_payload_offset; 169 __le16 ppdu_start_offset; 170 __le16 ppdu_end_offset; 171 __le16 mpdu_start_offset; 172 __le16 mpdu_end_offset; 173 __le16 msdu_start_offset; 174 __le16 msdu_end_offset; 175 __le16 rx_attention_offset; 176 __le16 frag_info_offset; 177 } __packed; 178 179 struct htt_rx_ring_setup_hdr { 180 u8 num_rings; /* supported values: 1, 2 */ 181 __le16 rsvd0; 182 } __packed; 183 184 struct htt_rx_ring_setup { 185 struct htt_rx_ring_setup_hdr hdr; 186 struct htt_rx_ring_setup_ring rings[0]; 187 } __packed; 188 189 /* 190 * htt_stats_req - request target to send specified statistics 191 * 192 * @msg_type: hardcoded %HTT_H2T_MSG_TYPE_STATS_REQ 193 * @upload_types: see %htt_dbg_stats_type. this is 24bit field actually 194 * so make sure its little-endian. 195 * @reset_types: see %htt_dbg_stats_type. this is 24bit field actually 196 * so make sure its little-endian. 197 * @cfg_val: stat_type specific configuration 198 * @stat_type: see %htt_dbg_stats_type 199 * @cookie_lsb: used for confirmation message from target->host 200 * @cookie_msb: ditto as %cookie 201 */ 202 struct htt_stats_req { 203 u8 upload_types[3]; 204 u8 rsvd0; 205 u8 reset_types[3]; 206 struct { 207 u8 mpdu_bytes; 208 u8 mpdu_num_msdus; 209 u8 msdu_bytes; 210 } __packed; 211 u8 stat_type; 212 __le32 cookie_lsb; 213 __le32 cookie_msb; 214 } __packed; 215 216 #define HTT_STATS_REQ_CFG_STAT_TYPE_INVALID 0xff 217 218 /* 219 * htt_oob_sync_req - request out-of-band sync 220 * 221 * The HTT SYNC tells the target to suspend processing of subsequent 222 * HTT host-to-target messages until some other target agent locally 223 * informs the target HTT FW that the current sync counter is equal to 224 * or greater than (in a modulo sense) the sync counter specified in 225 * the SYNC message. 226 * 227 * This allows other host-target components to synchronize their operation 228 * with HTT, e.g. to ensure that tx frames don't get transmitted until a 229 * security key has been downloaded to and activated by the target. 230 * In the absence of any explicit synchronization counter value 231 * specification, the target HTT FW will use zero as the default current 232 * sync value. 233 * 234 * The HTT target FW will suspend its host->target message processing as long 235 * as 0 < (in-band sync counter - out-of-band sync counter) & 0xff < 128. 236 */ 237 struct htt_oob_sync_req { 238 u8 sync_count; 239 __le16 rsvd0; 240 } __packed; 241 242 #define HTT_AGGR_CONF_MAX_NUM_AMSDU_SUBFRAMES_MASK 0x1F 243 #define HTT_AGGR_CONF_MAX_NUM_AMSDU_SUBFRAMES_LSB 0 244 245 struct htt_aggr_conf { 246 u8 max_num_ampdu_subframes; 247 union { 248 /* dont use bitfields; undefined behaviour */ 249 u8 flags; /* see %HTT_AGGR_CONF_MAX_NUM_AMSDU_SUBFRAMES_ */ 250 u8 max_num_amsdu_subframes:5; 251 } __packed; 252 } __packed; 253 254 #define HTT_MGMT_FRM_HDR_DOWNLOAD_LEN 32 255 256 struct htt_mgmt_tx_desc { 257 u8 pad[sizeof(u32) - sizeof(struct htt_cmd_hdr)]; 258 __le32 msdu_paddr; 259 __le32 desc_id; 260 __le32 len; 261 __le32 vdev_id; 262 u8 hdr[HTT_MGMT_FRM_HDR_DOWNLOAD_LEN]; 263 } __packed; 264 265 enum htt_mgmt_tx_status { 266 HTT_MGMT_TX_STATUS_OK = 0, 267 HTT_MGMT_TX_STATUS_RETRY = 1, 268 HTT_MGMT_TX_STATUS_DROP = 2 269 }; 270 271 /*=== target -> host messages ===============================================*/ 272 273 274 enum htt_t2h_msg_type { 275 HTT_T2H_MSG_TYPE_VERSION_CONF = 0x0, 276 HTT_T2H_MSG_TYPE_RX_IND = 0x1, 277 HTT_T2H_MSG_TYPE_RX_FLUSH = 0x2, 278 HTT_T2H_MSG_TYPE_PEER_MAP = 0x3, 279 HTT_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 280 HTT_T2H_MSG_TYPE_RX_ADDBA = 0x5, 281 HTT_T2H_MSG_TYPE_RX_DELBA = 0x6, 282 HTT_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 283 HTT_T2H_MSG_TYPE_PKTLOG = 0x8, 284 HTT_T2H_MSG_TYPE_STATS_CONF = 0x9, 285 HTT_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 286 HTT_T2H_MSG_TYPE_SEC_IND = 0xb, 287 HTT_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc, 288 HTT_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 289 HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION = 0xe, 290 HTT_T2H_MSG_TYPE_TEST, 291 /* keep this last */ 292 HTT_T2H_NUM_MSGS 293 }; 294 295 /* 296 * htt_resp_hdr - header for target-to-host messages 297 * 298 * msg_type: see htt_t2h_msg_type 299 */ 300 struct htt_resp_hdr { 301 u8 msg_type; 302 } __packed; 303 304 #define HTT_RESP_HDR_MSG_TYPE_OFFSET 0 305 #define HTT_RESP_HDR_MSG_TYPE_MASK 0xff 306 #define HTT_RESP_HDR_MSG_TYPE_LSB 0 307 308 /* htt_ver_resp - response sent for htt_ver_req */ 309 struct htt_ver_resp { 310 u8 minor; 311 u8 major; 312 u8 rsvd0; 313 } __packed; 314 315 struct htt_mgmt_tx_completion { 316 u8 rsvd0; 317 u8 rsvd1; 318 u8 rsvd2; 319 __le32 desc_id; 320 __le32 status; 321 } __packed; 322 323 #define HTT_RX_INDICATION_INFO0_EXT_TID_MASK (0x3F) 324 #define HTT_RX_INDICATION_INFO0_EXT_TID_LSB (0) 325 #define HTT_RX_INDICATION_INFO0_FLUSH_VALID (1 << 6) 326 #define HTT_RX_INDICATION_INFO0_RELEASE_VALID (1 << 7) 327 328 #define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_MASK 0x0000003F 329 #define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_LSB 0 330 #define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_MASK 0x00000FC0 331 #define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_LSB 6 332 #define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_MASK 0x0003F000 333 #define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_LSB 12 334 #define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_MASK 0x00FC0000 335 #define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_LSB 18 336 #define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_MASK 0xFF000000 337 #define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_LSB 24 338 339 struct htt_rx_indication_hdr { 340 u8 info0; /* %HTT_RX_INDICATION_INFO0_ */ 341 __le16 peer_id; 342 __le32 info1; /* %HTT_RX_INDICATION_INFO1_ */ 343 } __packed; 344 345 #define HTT_RX_INDICATION_INFO0_PHY_ERR_VALID (1 << 0) 346 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_MASK (0x1E) 347 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_LSB (1) 348 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_CCK (1 << 5) 349 #define HTT_RX_INDICATION_INFO0_END_VALID (1 << 6) 350 #define HTT_RX_INDICATION_INFO0_START_VALID (1 << 7) 351 352 #define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_MASK 0x00FFFFFF 353 #define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_LSB 0 354 #define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_MASK 0xFF000000 355 #define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_LSB 24 356 357 #define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_MASK 0x00FFFFFF 358 #define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_LSB 0 359 #define HTT_RX_INDICATION_INFO2_SERVICE_MASK 0xFF000000 360 #define HTT_RX_INDICATION_INFO2_SERVICE_LSB 24 361 362 enum htt_rx_legacy_rate { 363 HTT_RX_OFDM_48 = 0, 364 HTT_RX_OFDM_24 = 1, 365 HTT_RX_OFDM_12, 366 HTT_RX_OFDM_6, 367 HTT_RX_OFDM_54, 368 HTT_RX_OFDM_36, 369 HTT_RX_OFDM_18, 370 HTT_RX_OFDM_9, 371 372 /* long preamble */ 373 HTT_RX_CCK_11_LP = 0, 374 HTT_RX_CCK_5_5_LP = 1, 375 HTT_RX_CCK_2_LP, 376 HTT_RX_CCK_1_LP, 377 /* short preamble */ 378 HTT_RX_CCK_11_SP, 379 HTT_RX_CCK_5_5_SP, 380 HTT_RX_CCK_2_SP 381 }; 382 383 enum htt_rx_legacy_rate_type { 384 HTT_RX_LEGACY_RATE_OFDM = 0, 385 HTT_RX_LEGACY_RATE_CCK 386 }; 387 388 enum htt_rx_preamble_type { 389 HTT_RX_LEGACY = 0x4, 390 HTT_RX_HT = 0x8, 391 HTT_RX_HT_WITH_TXBF = 0x9, 392 HTT_RX_VHT = 0xC, 393 HTT_RX_VHT_WITH_TXBF = 0xD, 394 }; 395 396 /* 397 * Fields: phy_err_valid, phy_err_code, tsf, 398 * usec_timestamp, sub_usec_timestamp 399 * ..are valid only if end_valid == 1. 400 * 401 * Fields: rssi_chains, legacy_rate_type, 402 * legacy_rate_cck, preamble_type, service, 403 * vht_sig_* 404 * ..are valid only if start_valid == 1; 405 */ 406 struct htt_rx_indication_ppdu { 407 u8 combined_rssi; 408 u8 sub_usec_timestamp; 409 u8 phy_err_code; 410 u8 info0; /* HTT_RX_INDICATION_INFO0_ */ 411 struct { 412 u8 pri20_db; 413 u8 ext20_db; 414 u8 ext40_db; 415 u8 ext80_db; 416 } __packed rssi_chains[4]; 417 __le32 tsf; 418 __le32 usec_timestamp; 419 __le32 info1; /* HTT_RX_INDICATION_INFO1_ */ 420 __le32 info2; /* HTT_RX_INDICATION_INFO2_ */ 421 } __packed; 422 423 enum htt_rx_mpdu_status { 424 HTT_RX_IND_MPDU_STATUS_UNKNOWN = 0x0, 425 HTT_RX_IND_MPDU_STATUS_OK, 426 HTT_RX_IND_MPDU_STATUS_ERR_FCS, 427 HTT_RX_IND_MPDU_STATUS_ERR_DUP, 428 HTT_RX_IND_MPDU_STATUS_ERR_REPLAY, 429 HTT_RX_IND_MPDU_STATUS_ERR_INV_PEER, 430 /* only accept EAPOL frames */ 431 HTT_RX_IND_MPDU_STATUS_UNAUTH_PEER, 432 HTT_RX_IND_MPDU_STATUS_OUT_OF_SYNC, 433 /* Non-data in promiscous mode */ 434 HTT_RX_IND_MPDU_STATUS_MGMT_CTRL, 435 HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR, 436 HTT_RX_IND_MPDU_STATUS_DECRYPT_ERR, 437 HTT_RX_IND_MPDU_STATUS_MPDU_LENGTH_ERR, 438 HTT_RX_IND_MPDU_STATUS_ENCRYPT_REQUIRED_ERR, 439 HTT_RX_IND_MPDU_STATUS_PRIVACY_ERR, 440 441 /* 442 * MISC: discard for unspecified reasons. 443 * Leave this enum value last. 444 */ 445 HTT_RX_IND_MPDU_STATUS_ERR_MISC = 0xFF 446 }; 447 448 struct htt_rx_indication_mpdu_range { 449 u8 mpdu_count; 450 u8 mpdu_range_status; /* %htt_rx_mpdu_status */ 451 u8 pad0; 452 u8 pad1; 453 } __packed; 454 455 struct htt_rx_indication_prefix { 456 __le16 fw_rx_desc_bytes; 457 u8 pad0; 458 u8 pad1; 459 }; 460 461 struct htt_rx_indication { 462 struct htt_rx_indication_hdr hdr; 463 struct htt_rx_indication_ppdu ppdu; 464 struct htt_rx_indication_prefix prefix; 465 466 /* 467 * the following fields are both dynamically sized, so 468 * take care addressing them 469 */ 470 471 /* the size of this is %fw_rx_desc_bytes */ 472 struct fw_rx_desc_base fw_desc; 473 474 /* 475 * %mpdu_ranges starts after &%prefix + roundup(%fw_rx_desc_bytes, 4) 476 * and has %num_mpdu_ranges elements. 477 */ 478 struct htt_rx_indication_mpdu_range mpdu_ranges[0]; 479 } __packed; 480 481 static inline struct htt_rx_indication_mpdu_range * 482 htt_rx_ind_get_mpdu_ranges(struct htt_rx_indication *rx_ind) 483 { 484 void *ptr = rx_ind; 485 486 ptr += sizeof(rx_ind->hdr) 487 + sizeof(rx_ind->ppdu) 488 + sizeof(rx_ind->prefix) 489 + roundup(__le16_to_cpu(rx_ind->prefix.fw_rx_desc_bytes), 4); 490 return ptr; 491 } 492 493 enum htt_rx_flush_mpdu_status { 494 HTT_RX_FLUSH_MPDU_DISCARD = 0, 495 HTT_RX_FLUSH_MPDU_REORDER = 1, 496 }; 497 498 /* 499 * htt_rx_flush - discard or reorder given range of mpdus 500 * 501 * Note: host must check if all sequence numbers between 502 * [seq_num_start, seq_num_end-1] are valid. 503 */ 504 struct htt_rx_flush { 505 __le16 peer_id; 506 u8 tid; 507 u8 rsvd0; 508 u8 mpdu_status; /* %htt_rx_flush_mpdu_status */ 509 u8 seq_num_start; /* it is 6 LSBs of 802.11 seq no */ 510 u8 seq_num_end; /* it is 6 LSBs of 802.11 seq no */ 511 }; 512 513 struct htt_rx_peer_map { 514 u8 vdev_id; 515 __le16 peer_id; 516 u8 addr[6]; 517 u8 rsvd0; 518 u8 rsvd1; 519 } __packed; 520 521 struct htt_rx_peer_unmap { 522 u8 rsvd0; 523 __le16 peer_id; 524 } __packed; 525 526 enum htt_security_types { 527 HTT_SECURITY_NONE, 528 HTT_SECURITY_WEP128, 529 HTT_SECURITY_WEP104, 530 HTT_SECURITY_WEP40, 531 HTT_SECURITY_TKIP, 532 HTT_SECURITY_TKIP_NOMIC, 533 HTT_SECURITY_AES_CCMP, 534 HTT_SECURITY_WAPI, 535 536 HTT_NUM_SECURITY_TYPES /* keep this last! */ 537 }; 538 539 enum htt_security_flags { 540 #define HTT_SECURITY_TYPE_MASK 0x7F 541 #define HTT_SECURITY_TYPE_LSB 0 542 HTT_SECURITY_IS_UNICAST = 1 << 7 543 }; 544 545 struct htt_security_indication { 546 union { 547 /* dont use bitfields; undefined behaviour */ 548 u8 flags; /* %htt_security_flags */ 549 struct { 550 u8 security_type:7, /* %htt_security_types */ 551 is_unicast:1; 552 } __packed; 553 } __packed; 554 __le16 peer_id; 555 u8 michael_key[8]; 556 u8 wapi_rsc[16]; 557 } __packed; 558 559 #define HTT_RX_BA_INFO0_TID_MASK 0x000F 560 #define HTT_RX_BA_INFO0_TID_LSB 0 561 #define HTT_RX_BA_INFO0_PEER_ID_MASK 0xFFF0 562 #define HTT_RX_BA_INFO0_PEER_ID_LSB 4 563 564 struct htt_rx_addba { 565 u8 window_size; 566 __le16 info0; /* %HTT_RX_BA_INFO0_ */ 567 } __packed; 568 569 struct htt_rx_delba { 570 u8 rsvd0; 571 __le16 info0; /* %HTT_RX_BA_INFO0_ */ 572 } __packed; 573 574 enum htt_data_tx_status { 575 HTT_DATA_TX_STATUS_OK = 0, 576 HTT_DATA_TX_STATUS_DISCARD = 1, 577 HTT_DATA_TX_STATUS_NO_ACK = 2, 578 HTT_DATA_TX_STATUS_POSTPONE = 3, /* HL only */ 579 HTT_DATA_TX_STATUS_DOWNLOAD_FAIL = 128 580 }; 581 582 enum htt_data_tx_flags { 583 #define HTT_DATA_TX_STATUS_MASK 0x07 584 #define HTT_DATA_TX_STATUS_LSB 0 585 #define HTT_DATA_TX_TID_MASK 0x78 586 #define HTT_DATA_TX_TID_LSB 3 587 HTT_DATA_TX_TID_INVALID = 1 << 7 588 }; 589 590 #define HTT_TX_COMPL_INV_MSDU_ID 0xFFFF 591 592 struct htt_data_tx_completion { 593 union { 594 u8 flags; 595 struct { 596 u8 status:3, 597 tid:4, 598 tid_invalid:1; 599 } __packed; 600 } __packed; 601 u8 num_msdus; 602 u8 rsvd0; 603 __le16 msdus[0]; /* variable length based on %num_msdus */ 604 } __packed; 605 606 struct htt_tx_compl_ind_base { 607 u32 hdr; 608 u16 payload[1/*or more*/]; 609 } __packed; 610 611 struct htt_rc_tx_done_params { 612 u32 rate_code; 613 u32 rate_code_flags; 614 u32 flags; 615 u32 num_enqued; /* 1 for non-AMPDU */ 616 u32 num_retries; 617 u32 num_failed; /* for AMPDU */ 618 u32 ack_rssi; 619 u32 time_stamp; 620 u32 is_probe; 621 }; 622 623 struct htt_rc_update { 624 u8 vdev_id; 625 __le16 peer_id; 626 u8 addr[6]; 627 u8 num_elems; 628 u8 rsvd0; 629 struct htt_rc_tx_done_params params[0]; /* variable length %num_elems */ 630 } __packed; 631 632 /* see htt_rx_indication for similar fields and descriptions */ 633 struct htt_rx_fragment_indication { 634 union { 635 u8 info0; /* %HTT_RX_FRAG_IND_INFO0_ */ 636 struct { 637 u8 ext_tid:5, 638 flush_valid:1; 639 } __packed; 640 } __packed; 641 __le16 peer_id; 642 __le32 info1; /* %HTT_RX_FRAG_IND_INFO1_ */ 643 __le16 fw_rx_desc_bytes; 644 __le16 rsvd0; 645 646 u8 fw_msdu_rx_desc[0]; 647 } __packed; 648 649 #define HTT_RX_FRAG_IND_INFO0_EXT_TID_MASK 0x1F 650 #define HTT_RX_FRAG_IND_INFO0_EXT_TID_LSB 0 651 #define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_MASK 0x20 652 #define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_LSB 5 653 654 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_MASK 0x0000003F 655 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_LSB 0 656 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_MASK 0x00000FC0 657 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_LSB 6 658 659 /* 660 * target -> host test message definition 661 * 662 * The following field definitions describe the format of the test 663 * message sent from the target to the host. 664 * The message consists of a 4-octet header, followed by a variable 665 * number of 32-bit integer values, followed by a variable number 666 * of 8-bit character values. 667 * 668 * |31 16|15 8|7 0| 669 * |-----------------------------------------------------------| 670 * | num chars | num ints | msg type | 671 * |-----------------------------------------------------------| 672 * | int 0 | 673 * |-----------------------------------------------------------| 674 * | int 1 | 675 * |-----------------------------------------------------------| 676 * | ... | 677 * |-----------------------------------------------------------| 678 * | char 3 | char 2 | char 1 | char 0 | 679 * |-----------------------------------------------------------| 680 * | | | ... | char 4 | 681 * |-----------------------------------------------------------| 682 * - MSG_TYPE 683 * Bits 7:0 684 * Purpose: identifies this as a test message 685 * Value: HTT_MSG_TYPE_TEST 686 * - NUM_INTS 687 * Bits 15:8 688 * Purpose: indicate how many 32-bit integers follow the message header 689 * - NUM_CHARS 690 * Bits 31:16 691 * Purpose: indicate how many 8-bit charaters follow the series of integers 692 */ 693 struct htt_rx_test { 694 u8 num_ints; 695 __le16 num_chars; 696 697 /* payload consists of 2 lists: 698 * a) num_ints * sizeof(__le32) 699 * b) num_chars * sizeof(u8) aligned to 4bytes */ 700 u8 payload[0]; 701 } __packed; 702 703 static inline __le32 *htt_rx_test_get_ints(struct htt_rx_test *rx_test) 704 { 705 return (__le32 *)rx_test->payload; 706 } 707 708 static inline u8 *htt_rx_test_get_chars(struct htt_rx_test *rx_test) 709 { 710 return rx_test->payload + (rx_test->num_ints * sizeof(__le32)); 711 } 712 713 /* 714 * target -> host packet log message 715 * 716 * The following field definitions describe the format of the packet log 717 * message sent from the target to the host. 718 * The message consists of a 4-octet header,followed by a variable number 719 * of 32-bit character values. 720 * 721 * |31 24|23 16|15 8|7 0| 722 * |-----------------------------------------------------------| 723 * | | | | msg type | 724 * |-----------------------------------------------------------| 725 * | payload | 726 * |-----------------------------------------------------------| 727 * - MSG_TYPE 728 * Bits 7:0 729 * Purpose: identifies this as a test message 730 * Value: HTT_MSG_TYPE_PACKETLOG 731 */ 732 struct htt_pktlog_msg { 733 u8 pad[3]; 734 __le32 payload[1 /* or more */]; 735 } __packed; 736 737 struct htt_dbg_stats_rx_reorder_stats { 738 /* Non QoS MPDUs received */ 739 __le32 deliver_non_qos; 740 741 /* MPDUs received in-order */ 742 __le32 deliver_in_order; 743 744 /* Flush due to reorder timer expired */ 745 __le32 deliver_flush_timeout; 746 747 /* Flush due to move out of window */ 748 __le32 deliver_flush_oow; 749 750 /* Flush due to DELBA */ 751 __le32 deliver_flush_delba; 752 753 /* MPDUs dropped due to FCS error */ 754 __le32 fcs_error; 755 756 /* MPDUs dropped due to monitor mode non-data packet */ 757 __le32 mgmt_ctrl; 758 759 /* MPDUs dropped due to invalid peer */ 760 __le32 invalid_peer; 761 762 /* MPDUs dropped due to duplication (non aggregation) */ 763 __le32 dup_non_aggr; 764 765 /* MPDUs dropped due to processed before */ 766 __le32 dup_past; 767 768 /* MPDUs dropped due to duplicate in reorder queue */ 769 __le32 dup_in_reorder; 770 771 /* Reorder timeout happened */ 772 __le32 reorder_timeout; 773 774 /* invalid bar ssn */ 775 __le32 invalid_bar_ssn; 776 777 /* reorder reset due to bar ssn */ 778 __le32 ssn_reset; 779 }; 780 781 struct htt_dbg_stats_wal_tx_stats { 782 /* Num HTT cookies queued to dispatch list */ 783 __le32 comp_queued; 784 785 /* Num HTT cookies dispatched */ 786 __le32 comp_delivered; 787 788 /* Num MSDU queued to WAL */ 789 __le32 msdu_enqued; 790 791 /* Num MPDU queue to WAL */ 792 __le32 mpdu_enqued; 793 794 /* Num MSDUs dropped by WMM limit */ 795 __le32 wmm_drop; 796 797 /* Num Local frames queued */ 798 __le32 local_enqued; 799 800 /* Num Local frames done */ 801 __le32 local_freed; 802 803 /* Num queued to HW */ 804 __le32 hw_queued; 805 806 /* Num PPDU reaped from HW */ 807 __le32 hw_reaped; 808 809 /* Num underruns */ 810 __le32 underrun; 811 812 /* Num PPDUs cleaned up in TX abort */ 813 __le32 tx_abort; 814 815 /* Num MPDUs requed by SW */ 816 __le32 mpdus_requed; 817 818 /* excessive retries */ 819 __le32 tx_ko; 820 821 /* data hw rate code */ 822 __le32 data_rc; 823 824 /* Scheduler self triggers */ 825 __le32 self_triggers; 826 827 /* frames dropped due to excessive sw retries */ 828 __le32 sw_retry_failure; 829 830 /* illegal rate phy errors */ 831 __le32 illgl_rate_phy_err; 832 833 /* wal pdev continous xretry */ 834 __le32 pdev_cont_xretry; 835 836 /* wal pdev continous xretry */ 837 __le32 pdev_tx_timeout; 838 839 /* wal pdev resets */ 840 __le32 pdev_resets; 841 842 __le32 phy_underrun; 843 844 /* MPDU is more than txop limit */ 845 __le32 txop_ovf; 846 } __packed; 847 848 struct htt_dbg_stats_wal_rx_stats { 849 /* Cnts any change in ring routing mid-ppdu */ 850 __le32 mid_ppdu_route_change; 851 852 /* Total number of statuses processed */ 853 __le32 status_rcvd; 854 855 /* Extra frags on rings 0-3 */ 856 __le32 r0_frags; 857 __le32 r1_frags; 858 __le32 r2_frags; 859 __le32 r3_frags; 860 861 /* MSDUs / MPDUs delivered to HTT */ 862 __le32 htt_msdus; 863 __le32 htt_mpdus; 864 865 /* MSDUs / MPDUs delivered to local stack */ 866 __le32 loc_msdus; 867 __le32 loc_mpdus; 868 869 /* AMSDUs that have more MSDUs than the status ring size */ 870 __le32 oversize_amsdu; 871 872 /* Number of PHY errors */ 873 __le32 phy_errs; 874 875 /* Number of PHY errors drops */ 876 __le32 phy_err_drop; 877 878 /* Number of mpdu errors - FCS, MIC, ENC etc. */ 879 __le32 mpdu_errs; 880 } __packed; 881 882 struct htt_dbg_stats_wal_peer_stats { 883 __le32 dummy; /* REMOVE THIS ONCE REAL PEER STAT COUNTERS ARE ADDED */ 884 } __packed; 885 886 struct htt_dbg_stats_wal_pdev_txrx { 887 struct htt_dbg_stats_wal_tx_stats tx_stats; 888 struct htt_dbg_stats_wal_rx_stats rx_stats; 889 struct htt_dbg_stats_wal_peer_stats peer_stats; 890 } __packed; 891 892 struct htt_dbg_stats_rx_rate_info { 893 __le32 mcs[10]; 894 __le32 sgi[10]; 895 __le32 nss[4]; 896 __le32 stbc[10]; 897 __le32 bw[3]; 898 __le32 pream[6]; 899 __le32 ldpc; 900 __le32 txbf; 901 }; 902 903 /* 904 * htt_dbg_stats_status - 905 * present - The requested stats have been delivered in full. 906 * This indicates that either the stats information was contained 907 * in its entirety within this message, or else this message 908 * completes the delivery of the requested stats info that was 909 * partially delivered through earlier STATS_CONF messages. 910 * partial - The requested stats have been delivered in part. 911 * One or more subsequent STATS_CONF messages with the same 912 * cookie value will be sent to deliver the remainder of the 913 * information. 914 * error - The requested stats could not be delivered, for example due 915 * to a shortage of memory to construct a message holding the 916 * requested stats. 917 * invalid - The requested stat type is either not recognized, or the 918 * target is configured to not gather the stats type in question. 919 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 920 * series_done - This special value indicates that no further stats info 921 * elements are present within a series of stats info elems 922 * (within a stats upload confirmation message). 923 */ 924 enum htt_dbg_stats_status { 925 HTT_DBG_STATS_STATUS_PRESENT = 0, 926 HTT_DBG_STATS_STATUS_PARTIAL = 1, 927 HTT_DBG_STATS_STATUS_ERROR = 2, 928 HTT_DBG_STATS_STATUS_INVALID = 3, 929 HTT_DBG_STATS_STATUS_SERIES_DONE = 7 930 }; 931 932 /* 933 * target -> host statistics upload 934 * 935 * The following field definitions describe the format of the HTT target 936 * to host stats upload confirmation message. 937 * The message contains a cookie echoed from the HTT host->target stats 938 * upload request, which identifies which request the confirmation is 939 * for, and a series of tag-length-value stats information elements. 940 * The tag-length header for each stats info element also includes a 941 * status field, to indicate whether the request for the stat type in 942 * question was fully met, partially met, unable to be met, or invalid 943 * (if the stat type in question is disabled in the target). 944 * A special value of all 1's in this status field is used to indicate 945 * the end of the series of stats info elements. 946 * 947 * 948 * |31 16|15 8|7 5|4 0| 949 * |------------------------------------------------------------| 950 * | reserved | msg type | 951 * |------------------------------------------------------------| 952 * | cookie LSBs | 953 * |------------------------------------------------------------| 954 * | cookie MSBs | 955 * |------------------------------------------------------------| 956 * | stats entry length | reserved | S |stat type| 957 * |------------------------------------------------------------| 958 * | | 959 * | type-specific stats info | 960 * | | 961 * |------------------------------------------------------------| 962 * | stats entry length | reserved | S |stat type| 963 * |------------------------------------------------------------| 964 * | | 965 * | type-specific stats info | 966 * | | 967 * |------------------------------------------------------------| 968 * | n/a | reserved | 111 | n/a | 969 * |------------------------------------------------------------| 970 * Header fields: 971 * - MSG_TYPE 972 * Bits 7:0 973 * Purpose: identifies this is a statistics upload confirmation message 974 * Value: 0x9 975 * - COOKIE_LSBS 976 * Bits 31:0 977 * Purpose: Provide a mechanism to match a target->host stats confirmation 978 * message with its preceding host->target stats request message. 979 * Value: LSBs of the opaque cookie specified by the host-side requestor 980 * - COOKIE_MSBS 981 * Bits 31:0 982 * Purpose: Provide a mechanism to match a target->host stats confirmation 983 * message with its preceding host->target stats request message. 984 * Value: MSBs of the opaque cookie specified by the host-side requestor 985 * 986 * Stats Information Element tag-length header fields: 987 * - STAT_TYPE 988 * Bits 4:0 989 * Purpose: identifies the type of statistics info held in the 990 * following information element 991 * Value: htt_dbg_stats_type 992 * - STATUS 993 * Bits 7:5 994 * Purpose: indicate whether the requested stats are present 995 * Value: htt_dbg_stats_status, including a special value (0x7) to mark 996 * the completion of the stats entry series 997 * - LENGTH 998 * Bits 31:16 999 * Purpose: indicate the stats information size 1000 * Value: This field specifies the number of bytes of stats information 1001 * that follows the element tag-length header. 1002 * It is expected but not required that this length is a multiple of 1003 * 4 bytes. Even if the length is not an integer multiple of 4, the 1004 * subsequent stats entry header will begin on a 4-byte aligned 1005 * boundary. 1006 */ 1007 1008 #define HTT_STATS_CONF_ITEM_INFO_STAT_TYPE_MASK 0x1F 1009 #define HTT_STATS_CONF_ITEM_INFO_STAT_TYPE_LSB 0 1010 #define HTT_STATS_CONF_ITEM_INFO_STATUS_MASK 0xE0 1011 #define HTT_STATS_CONF_ITEM_INFO_STATUS_LSB 5 1012 1013 struct htt_stats_conf_item { 1014 union { 1015 u8 info; 1016 struct { 1017 u8 stat_type:5; /* %HTT_DBG_STATS_ */ 1018 u8 status:3; /* %HTT_DBG_STATS_STATUS_ */ 1019 } __packed; 1020 } __packed; 1021 u8 pad; 1022 __le16 length; 1023 u8 payload[0]; /* roundup(length, 4) long */ 1024 } __packed; 1025 1026 struct htt_stats_conf { 1027 u8 pad[3]; 1028 __le32 cookie_lsb; 1029 __le32 cookie_msb; 1030 1031 /* each item has variable length! */ 1032 struct htt_stats_conf_item items[0]; 1033 } __packed; 1034 1035 static inline struct htt_stats_conf_item *htt_stats_conf_next_item( 1036 const struct htt_stats_conf_item *item) 1037 { 1038 return (void *)item + sizeof(*item) + roundup(item->length, 4); 1039 } 1040 /* 1041 * host -> target FRAG DESCRIPTOR/MSDU_EXT DESC bank 1042 * 1043 * The following field definitions describe the format of the HTT host 1044 * to target frag_desc/msdu_ext bank configuration message. 1045 * The message contains the based address and the min and max id of the 1046 * MSDU_EXT/FRAG_DESC that will be used by the HTT to map MSDU DESC and 1047 * MSDU_EXT/FRAG_DESC. 1048 * HTT will use id in HTT descriptor instead sending the frag_desc_ptr. 1049 * For QCA988X HW the firmware will use fragment_desc_ptr but in WIFI2.0 1050 * the hardware does the mapping/translation. 1051 * 1052 * Total banks that can be configured is configured to 16. 1053 * 1054 * This should be called before any TX has be initiated by the HTT 1055 * 1056 * |31 16|15 8|7 5|4 0| 1057 * |------------------------------------------------------------| 1058 * | DESC_SIZE | NUM_BANKS | RES |SWP|pdev| msg type | 1059 * |------------------------------------------------------------| 1060 * | BANK0_BASE_ADDRESS | 1061 * |------------------------------------------------------------| 1062 * | ... | 1063 * |------------------------------------------------------------| 1064 * | BANK15_BASE_ADDRESS | 1065 * |------------------------------------------------------------| 1066 * | BANK0_MAX_ID | BANK0_MIN_ID | 1067 * |------------------------------------------------------------| 1068 * | ... | 1069 * |------------------------------------------------------------| 1070 * | BANK15_MAX_ID | BANK15_MIN_ID | 1071 * |------------------------------------------------------------| 1072 * Header fields: 1073 * - MSG_TYPE 1074 * Bits 7:0 1075 * Value: 0x6 1076 * - BANKx_BASE_ADDRESS 1077 * Bits 31:0 1078 * Purpose: Provide a mechanism to specify the base address of the MSDU_EXT 1079 * bank physical/bus address. 1080 * - BANKx_MIN_ID 1081 * Bits 15:0 1082 * Purpose: Provide a mechanism to specify the min index that needs to 1083 * mapped. 1084 * - BANKx_MAX_ID 1085 * Bits 31:16 1086 * Purpose: Provide a mechanism to specify the max index that needs to 1087 * 1088 */ 1089 struct htt_frag_desc_bank_id { 1090 __le16 bank_min_id; 1091 __le16 bank_max_id; 1092 } __packed; 1093 1094 /* real is 16 but it wouldn't fit in the max htt message size 1095 * so we use a conservatively safe value for now */ 1096 #define HTT_FRAG_DESC_BANK_MAX 4 1097 1098 #define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_MASK 0x03 1099 #define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_LSB 0 1100 #define HTT_FRAG_DESC_BANK_CFG_INFO_SWAP (1 << 2) 1101 1102 struct htt_frag_desc_bank_cfg { 1103 u8 info; /* HTT_FRAG_DESC_BANK_CFG_INFO_ */ 1104 u8 num_banks; 1105 u8 desc_size; 1106 __le32 bank_base_addrs[HTT_FRAG_DESC_BANK_MAX]; 1107 struct htt_frag_desc_bank_id bank_id[HTT_FRAG_DESC_BANK_MAX]; 1108 } __packed; 1109 1110 union htt_rx_pn_t { 1111 /* WEP: 24-bit PN */ 1112 u32 pn24; 1113 1114 /* TKIP or CCMP: 48-bit PN */ 1115 u_int64_t pn48; 1116 1117 /* WAPI: 128-bit PN */ 1118 u_int64_t pn128[2]; 1119 }; 1120 1121 struct htt_cmd { 1122 struct htt_cmd_hdr hdr; 1123 union { 1124 struct htt_ver_req ver_req; 1125 struct htt_mgmt_tx_desc mgmt_tx; 1126 struct htt_data_tx_desc data_tx; 1127 struct htt_rx_ring_setup rx_setup; 1128 struct htt_stats_req stats_req; 1129 struct htt_oob_sync_req oob_sync_req; 1130 struct htt_aggr_conf aggr_conf; 1131 struct htt_frag_desc_bank_cfg frag_desc_bank_cfg; 1132 }; 1133 } __packed; 1134 1135 struct htt_resp { 1136 struct htt_resp_hdr hdr; 1137 union { 1138 struct htt_ver_resp ver_resp; 1139 struct htt_mgmt_tx_completion mgmt_tx_completion; 1140 struct htt_data_tx_completion data_tx_completion; 1141 struct htt_rx_indication rx_ind; 1142 struct htt_rx_fragment_indication rx_frag_ind; 1143 struct htt_rx_peer_map peer_map; 1144 struct htt_rx_peer_unmap peer_unmap; 1145 struct htt_rx_flush rx_flush; 1146 struct htt_rx_addba rx_addba; 1147 struct htt_rx_delba rx_delba; 1148 struct htt_security_indication security_indication; 1149 struct htt_rc_update rc_update; 1150 struct htt_rx_test rx_test; 1151 struct htt_pktlog_msg pktlog_msg; 1152 struct htt_stats_conf stats_conf; 1153 }; 1154 } __packed; 1155 1156 1157 /*** host side structures follow ***/ 1158 1159 struct htt_tx_done { 1160 u32 msdu_id; 1161 bool discard; 1162 bool no_ack; 1163 }; 1164 1165 struct htt_peer_map_event { 1166 u8 vdev_id; 1167 u16 peer_id; 1168 u8 addr[ETH_ALEN]; 1169 }; 1170 1171 struct htt_peer_unmap_event { 1172 u16 peer_id; 1173 }; 1174 1175 struct htt_rx_info { 1176 struct sk_buff *skb; 1177 enum htt_rx_mpdu_status status; 1178 enum htt_rx_mpdu_encrypt_type encrypt_type; 1179 s8 signal; 1180 struct { 1181 u8 info0; 1182 u32 info1; 1183 u32 info2; 1184 } rate; 1185 1186 u32 tsf; 1187 bool fcs_err; 1188 bool amsdu_more; 1189 bool mic_err; 1190 }; 1191 1192 struct ath10k_htt_txbuf { 1193 struct htt_data_tx_desc_frag frags[2]; 1194 struct ath10k_htc_hdr htc_hdr; 1195 struct htt_cmd_hdr cmd_hdr; 1196 struct htt_data_tx_desc cmd_tx; 1197 } __packed; 1198 1199 struct ath10k_htt { 1200 struct ath10k *ar; 1201 enum ath10k_htc_ep_id eid; 1202 1203 int max_throughput_mbps; 1204 u8 target_version_major; 1205 u8 target_version_minor; 1206 struct completion target_version_received; 1207 1208 struct { 1209 /* 1210 * Ring of network buffer objects - This ring is 1211 * used exclusively by the host SW. This ring 1212 * mirrors the dev_addrs_ring that is shared 1213 * between the host SW and the MAC HW. The host SW 1214 * uses this netbufs ring to locate the network 1215 * buffer objects whose data buffers the HW has 1216 * filled. 1217 */ 1218 struct sk_buff **netbufs_ring; 1219 /* 1220 * Ring of buffer addresses - 1221 * This ring holds the "physical" device address of the 1222 * rx buffers the host SW provides for the MAC HW to 1223 * fill. 1224 */ 1225 __le32 *paddrs_ring; 1226 1227 /* 1228 * Base address of ring, as a "physical" device address 1229 * rather than a CPU address. 1230 */ 1231 dma_addr_t base_paddr; 1232 1233 /* how many elems in the ring (power of 2) */ 1234 int size; 1235 1236 /* size - 1 */ 1237 unsigned size_mask; 1238 1239 /* how many rx buffers to keep in the ring */ 1240 int fill_level; 1241 1242 /* how many rx buffers (full+empty) are in the ring */ 1243 int fill_cnt; 1244 1245 /* 1246 * alloc_idx - where HTT SW has deposited empty buffers 1247 * This is allocated in consistent mem, so that the FW can 1248 * read this variable, and program the HW's FW_IDX reg with 1249 * the value of this shadow register. 1250 */ 1251 struct { 1252 __le32 *vaddr; 1253 dma_addr_t paddr; 1254 } alloc_idx; 1255 1256 /* where HTT SW has processed bufs filled by rx MAC DMA */ 1257 struct { 1258 unsigned msdu_payld; 1259 } sw_rd_idx; 1260 1261 /* 1262 * refill_retry_timer - timer triggered when the ring is 1263 * not refilled to the level expected 1264 */ 1265 struct timer_list refill_retry_timer; 1266 1267 /* Protects access to all rx ring buffer state variables */ 1268 spinlock_t lock; 1269 } rx_ring; 1270 1271 unsigned int prefetch_len; 1272 1273 /* Protects access to %pending_tx, %used_msdu_ids */ 1274 spinlock_t tx_lock; 1275 int max_num_pending_tx; 1276 int num_pending_tx; 1277 struct sk_buff **pending_tx; 1278 unsigned long *used_msdu_ids; /* bitmap */ 1279 wait_queue_head_t empty_tx_wq; 1280 struct dma_pool *tx_pool; 1281 1282 /* set if host-fw communication goes haywire 1283 * used to avoid further failures */ 1284 bool rx_confused; 1285 struct tasklet_struct rx_replenish_task; 1286 1287 /* This is used to group tx/rx completions separately and process them 1288 * in batches to reduce cache stalls */ 1289 struct tasklet_struct txrx_compl_task; 1290 struct sk_buff_head tx_compl_q; 1291 struct sk_buff_head rx_compl_q; 1292 }; 1293 1294 #define RX_HTT_HDR_STATUS_LEN 64 1295 1296 /* This structure layout is programmed via rx ring setup 1297 * so that FW knows how to transfer the rx descriptor to the host. 1298 * Buffers like this are placed on the rx ring. */ 1299 struct htt_rx_desc { 1300 union { 1301 /* This field is filled on the host using the msdu buffer 1302 * from htt_rx_indication */ 1303 struct fw_rx_desc_base fw_desc; 1304 u32 pad; 1305 } __packed; 1306 struct { 1307 struct rx_attention attention; 1308 struct rx_frag_info frag_info; 1309 struct rx_mpdu_start mpdu_start; 1310 struct rx_msdu_start msdu_start; 1311 struct rx_msdu_end msdu_end; 1312 struct rx_mpdu_end mpdu_end; 1313 struct rx_ppdu_start ppdu_start; 1314 struct rx_ppdu_end ppdu_end; 1315 } __packed; 1316 u8 rx_hdr_status[RX_HTT_HDR_STATUS_LEN]; 1317 u8 msdu_payload[0]; 1318 }; 1319 1320 #define HTT_RX_DESC_ALIGN 8 1321 1322 #define HTT_MAC_ADDR_LEN 6 1323 1324 /* 1325 * FIX THIS 1326 * Should be: sizeof(struct htt_host_rx_desc) + max rx MSDU size, 1327 * rounded up to a cache line size. 1328 */ 1329 #define HTT_RX_BUF_SIZE 1920 1330 #define HTT_RX_MSDU_SIZE (HTT_RX_BUF_SIZE - (int)sizeof(struct htt_rx_desc)) 1331 1332 /* Refill a bunch of RX buffers for each refill round so that FW/HW can handle 1333 * aggregated traffic more nicely. */ 1334 #define ATH10K_HTT_MAX_NUM_REFILL 16 1335 1336 /* 1337 * DMA_MAP expects the buffer to be an integral number of cache lines. 1338 * Rather than checking the actual cache line size, this code makes a 1339 * conservative estimate of what the cache line size could be. 1340 */ 1341 #define HTT_LOG2_MAX_CACHE_LINE_SIZE 7 /* 2^7 = 128 */ 1342 #define HTT_MAX_CACHE_LINE_SIZE_MASK ((1 << HTT_LOG2_MAX_CACHE_LINE_SIZE) - 1) 1343 1344 int ath10k_htt_attach(struct ath10k *ar); 1345 int ath10k_htt_attach_target(struct ath10k_htt *htt); 1346 void ath10k_htt_detach(struct ath10k_htt *htt); 1347 1348 int ath10k_htt_tx_attach(struct ath10k_htt *htt); 1349 void ath10k_htt_tx_detach(struct ath10k_htt *htt); 1350 int ath10k_htt_rx_attach(struct ath10k_htt *htt); 1351 void ath10k_htt_rx_detach(struct ath10k_htt *htt); 1352 void ath10k_htt_htc_tx_complete(struct ath10k *ar, struct sk_buff *skb); 1353 void ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb); 1354 int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt); 1355 int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u8 mask, u64 cookie); 1356 int ath10k_htt_send_rx_ring_cfg_ll(struct ath10k_htt *htt); 1357 1358 void __ath10k_htt_tx_dec_pending(struct ath10k_htt *htt); 1359 int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt); 1360 void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id); 1361 int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *); 1362 int ath10k_htt_tx(struct ath10k_htt *htt, struct sk_buff *); 1363 1364 #endif 1365