1 /* 2 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. 3 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #include "coredump.h" 19 20 #include <linux/devcoredump.h> 21 #include <linux/kernel.h> 22 #include <linux/types.h> 23 #include <linux/utsname.h> 24 25 #include "debug.h" 26 #include "hw.h" 27 28 static const struct ath10k_mem_section qca6174_hw21_register_sections[] = { 29 {0x800, 0x810}, 30 {0x820, 0x82C}, 31 {0x830, 0x8F4}, 32 {0x90C, 0x91C}, 33 {0xA14, 0xA18}, 34 {0xA84, 0xA94}, 35 {0xAA8, 0xAD4}, 36 {0xADC, 0xB40}, 37 {0x1000, 0x10A4}, 38 {0x10BC, 0x111C}, 39 {0x1134, 0x1138}, 40 {0x1144, 0x114C}, 41 {0x1150, 0x115C}, 42 {0x1160, 0x1178}, 43 {0x1240, 0x1260}, 44 {0x2000, 0x207C}, 45 {0x3000, 0x3014}, 46 {0x4000, 0x4014}, 47 {0x5000, 0x5124}, 48 {0x6000, 0x6040}, 49 {0x6080, 0x60CC}, 50 {0x6100, 0x611C}, 51 {0x6140, 0x61D8}, 52 {0x6200, 0x6238}, 53 {0x6240, 0x628C}, 54 {0x62C0, 0x62EC}, 55 {0x6380, 0x63E8}, 56 {0x6400, 0x6440}, 57 {0x6480, 0x64CC}, 58 {0x6500, 0x651C}, 59 {0x6540, 0x6580}, 60 {0x6600, 0x6638}, 61 {0x6640, 0x668C}, 62 {0x66C0, 0x66EC}, 63 {0x6780, 0x67E8}, 64 {0x7080, 0x708C}, 65 {0x70C0, 0x70C8}, 66 {0x7400, 0x741C}, 67 {0x7440, 0x7454}, 68 {0x7800, 0x7818}, 69 {0x8000, 0x8004}, 70 {0x8010, 0x8064}, 71 {0x8080, 0x8084}, 72 {0x80A0, 0x80A4}, 73 {0x80C0, 0x80C4}, 74 {0x80E0, 0x80F4}, 75 {0x8100, 0x8104}, 76 {0x8110, 0x812C}, 77 {0x9000, 0x9004}, 78 {0x9800, 0x982C}, 79 {0x9830, 0x9838}, 80 {0x9840, 0x986C}, 81 {0x9870, 0x9898}, 82 {0x9A00, 0x9C00}, 83 {0xD580, 0xD59C}, 84 {0xF000, 0xF0E0}, 85 {0xF140, 0xF190}, 86 {0xF250, 0xF25C}, 87 {0xF260, 0xF268}, 88 {0xF26C, 0xF2A8}, 89 {0x10008, 0x1000C}, 90 {0x10014, 0x10018}, 91 {0x1001C, 0x10020}, 92 {0x10024, 0x10028}, 93 {0x10030, 0x10034}, 94 {0x10040, 0x10054}, 95 {0x10058, 0x1007C}, 96 {0x10080, 0x100C4}, 97 {0x100C8, 0x10114}, 98 {0x1012C, 0x10130}, 99 {0x10138, 0x10144}, 100 {0x10200, 0x10220}, 101 {0x10230, 0x10250}, 102 {0x10260, 0x10280}, 103 {0x10290, 0x102B0}, 104 {0x102C0, 0x102DC}, 105 {0x102E0, 0x102F4}, 106 {0x102FC, 0x1037C}, 107 {0x10380, 0x10390}, 108 {0x10800, 0x10828}, 109 {0x10840, 0x10844}, 110 {0x10880, 0x10884}, 111 {0x108C0, 0x108E8}, 112 {0x10900, 0x10928}, 113 {0x10940, 0x10944}, 114 {0x10980, 0x10984}, 115 {0x109C0, 0x109E8}, 116 {0x10A00, 0x10A28}, 117 {0x10A40, 0x10A50}, 118 {0x11000, 0x11028}, 119 {0x11030, 0x11034}, 120 {0x11038, 0x11068}, 121 {0x11070, 0x11074}, 122 {0x11078, 0x110A8}, 123 {0x110B0, 0x110B4}, 124 {0x110B8, 0x110E8}, 125 {0x110F0, 0x110F4}, 126 {0x110F8, 0x11128}, 127 {0x11138, 0x11144}, 128 {0x11178, 0x11180}, 129 {0x111B8, 0x111C0}, 130 {0x111F8, 0x11200}, 131 {0x11238, 0x1123C}, 132 {0x11270, 0x11274}, 133 {0x11278, 0x1127C}, 134 {0x112B0, 0x112B4}, 135 {0x112B8, 0x112BC}, 136 {0x112F0, 0x112F4}, 137 {0x112F8, 0x112FC}, 138 {0x11338, 0x1133C}, 139 {0x11378, 0x1137C}, 140 {0x113B8, 0x113BC}, 141 {0x113F8, 0x113FC}, 142 {0x11438, 0x11440}, 143 {0x11478, 0x11480}, 144 {0x114B8, 0x114BC}, 145 {0x114F8, 0x114FC}, 146 {0x11538, 0x1153C}, 147 {0x11578, 0x1157C}, 148 {0x115B8, 0x115BC}, 149 {0x115F8, 0x115FC}, 150 {0x11638, 0x1163C}, 151 {0x11678, 0x1167C}, 152 {0x116B8, 0x116BC}, 153 {0x116F8, 0x116FC}, 154 {0x11738, 0x1173C}, 155 {0x11778, 0x1177C}, 156 {0x117B8, 0x117BC}, 157 {0x117F8, 0x117FC}, 158 {0x17000, 0x1701C}, 159 {0x17020, 0x170AC}, 160 {0x18000, 0x18050}, 161 {0x18054, 0x18074}, 162 {0x18080, 0x180D4}, 163 {0x180DC, 0x18104}, 164 {0x18108, 0x1813C}, 165 {0x18144, 0x18148}, 166 {0x18168, 0x18174}, 167 {0x18178, 0x18180}, 168 {0x181C8, 0x181E0}, 169 {0x181E4, 0x181E8}, 170 {0x181EC, 0x1820C}, 171 {0x1825C, 0x18280}, 172 {0x18284, 0x18290}, 173 {0x18294, 0x182A0}, 174 {0x18300, 0x18304}, 175 {0x18314, 0x18320}, 176 {0x18328, 0x18350}, 177 {0x1835C, 0x1836C}, 178 {0x18370, 0x18390}, 179 {0x18398, 0x183AC}, 180 {0x183BC, 0x183D8}, 181 {0x183DC, 0x183F4}, 182 {0x18400, 0x186F4}, 183 {0x186F8, 0x1871C}, 184 {0x18720, 0x18790}, 185 {0x19800, 0x19830}, 186 {0x19834, 0x19840}, 187 {0x19880, 0x1989C}, 188 {0x198A4, 0x198B0}, 189 {0x198BC, 0x19900}, 190 {0x19C00, 0x19C88}, 191 {0x19D00, 0x19D20}, 192 {0x19E00, 0x19E7C}, 193 {0x19E80, 0x19E94}, 194 {0x19E98, 0x19EAC}, 195 {0x19EB0, 0x19EBC}, 196 {0x19F70, 0x19F74}, 197 {0x19F80, 0x19F8C}, 198 {0x19FA0, 0x19FB4}, 199 {0x19FC0, 0x19FD8}, 200 {0x1A000, 0x1A200}, 201 {0x1A204, 0x1A210}, 202 {0x1A228, 0x1A22C}, 203 {0x1A230, 0x1A248}, 204 {0x1A250, 0x1A270}, 205 {0x1A280, 0x1A290}, 206 {0x1A2A0, 0x1A2A4}, 207 {0x1A2C0, 0x1A2EC}, 208 {0x1A300, 0x1A3BC}, 209 {0x1A3F0, 0x1A3F4}, 210 {0x1A3F8, 0x1A434}, 211 {0x1A438, 0x1A444}, 212 {0x1A448, 0x1A468}, 213 {0x1A580, 0x1A58C}, 214 {0x1A644, 0x1A654}, 215 {0x1A670, 0x1A698}, 216 {0x1A6AC, 0x1A6B0}, 217 {0x1A6D0, 0x1A6D4}, 218 {0x1A6EC, 0x1A70C}, 219 {0x1A710, 0x1A738}, 220 {0x1A7C0, 0x1A7D0}, 221 {0x1A7D4, 0x1A7D8}, 222 {0x1A7DC, 0x1A7E4}, 223 {0x1A7F0, 0x1A7F8}, 224 {0x1A888, 0x1A89C}, 225 {0x1A8A8, 0x1A8AC}, 226 {0x1A8C0, 0x1A8DC}, 227 {0x1A8F0, 0x1A8FC}, 228 {0x1AE04, 0x1AE08}, 229 {0x1AE18, 0x1AE24}, 230 {0x1AF80, 0x1AF8C}, 231 {0x1AFA0, 0x1AFB4}, 232 {0x1B000, 0x1B200}, 233 {0x1B284, 0x1B288}, 234 {0x1B2D0, 0x1B2D8}, 235 {0x1B2DC, 0x1B2EC}, 236 {0x1B300, 0x1B340}, 237 {0x1B374, 0x1B378}, 238 {0x1B380, 0x1B384}, 239 {0x1B388, 0x1B38C}, 240 {0x1B404, 0x1B408}, 241 {0x1B420, 0x1B428}, 242 {0x1B440, 0x1B444}, 243 {0x1B448, 0x1B44C}, 244 {0x1B450, 0x1B458}, 245 {0x1B45C, 0x1B468}, 246 {0x1B584, 0x1B58C}, 247 {0x1B68C, 0x1B690}, 248 {0x1B6AC, 0x1B6B0}, 249 {0x1B7F0, 0x1B7F8}, 250 {0x1C800, 0x1CC00}, 251 {0x1CE00, 0x1CE04}, 252 {0x1CF80, 0x1CF84}, 253 {0x1D200, 0x1D800}, 254 {0x1E000, 0x20014}, 255 {0x20100, 0x20124}, 256 {0x21400, 0x217A8}, 257 {0x21800, 0x21BA8}, 258 {0x21C00, 0x21FA8}, 259 {0x22000, 0x223A8}, 260 {0x22400, 0x227A8}, 261 {0x22800, 0x22BA8}, 262 {0x22C00, 0x22FA8}, 263 {0x23000, 0x233A8}, 264 {0x24000, 0x24034}, 265 {0x26000, 0x26064}, 266 {0x27000, 0x27024}, 267 {0x34000, 0x3400C}, 268 {0x34400, 0x3445C}, 269 {0x34800, 0x3485C}, 270 {0x34C00, 0x34C5C}, 271 {0x35000, 0x3505C}, 272 {0x35400, 0x3545C}, 273 {0x35800, 0x3585C}, 274 {0x35C00, 0x35C5C}, 275 {0x36000, 0x3605C}, 276 {0x38000, 0x38064}, 277 {0x38070, 0x380E0}, 278 {0x3A000, 0x3A064}, 279 {0x40000, 0x400A4}, 280 {0x80000, 0x8000C}, 281 {0x80010, 0x80020}, 282 }; 283 284 static const struct ath10k_mem_section qca6174_hw30_register_sections[] = { 285 {0x800, 0x810}, 286 {0x820, 0x82C}, 287 {0x830, 0x8F4}, 288 {0x90C, 0x91C}, 289 {0xA14, 0xA18}, 290 {0xA84, 0xA94}, 291 {0xAA8, 0xAD4}, 292 {0xADC, 0xB40}, 293 {0x1000, 0x10A4}, 294 {0x10BC, 0x111C}, 295 {0x1134, 0x1138}, 296 {0x1144, 0x114C}, 297 {0x1150, 0x115C}, 298 {0x1160, 0x1178}, 299 {0x1240, 0x1260}, 300 {0x2000, 0x207C}, 301 {0x3000, 0x3014}, 302 {0x4000, 0x4014}, 303 {0x5000, 0x5124}, 304 {0x6000, 0x6040}, 305 {0x6080, 0x60CC}, 306 {0x6100, 0x611C}, 307 {0x6140, 0x61D8}, 308 {0x6200, 0x6238}, 309 {0x6240, 0x628C}, 310 {0x62C0, 0x62EC}, 311 {0x6380, 0x63E8}, 312 {0x6400, 0x6440}, 313 {0x6480, 0x64CC}, 314 {0x6500, 0x651C}, 315 {0x6540, 0x6580}, 316 {0x6600, 0x6638}, 317 {0x6640, 0x668C}, 318 {0x66C0, 0x66EC}, 319 {0x6780, 0x67E8}, 320 {0x7080, 0x708C}, 321 {0x70C0, 0x70C8}, 322 {0x7400, 0x741C}, 323 {0x7440, 0x7454}, 324 {0x7800, 0x7818}, 325 {0x8000, 0x8004}, 326 {0x8010, 0x8064}, 327 {0x8080, 0x8084}, 328 {0x80A0, 0x80A4}, 329 {0x80C0, 0x80C4}, 330 {0x80E0, 0x80F4}, 331 {0x8100, 0x8104}, 332 {0x8110, 0x812C}, 333 {0x9000, 0x9004}, 334 {0x9800, 0x982C}, 335 {0x9830, 0x9838}, 336 {0x9840, 0x986C}, 337 {0x9870, 0x9898}, 338 {0x9A00, 0x9C00}, 339 {0xD580, 0xD59C}, 340 {0xF000, 0xF0E0}, 341 {0xF140, 0xF190}, 342 {0xF250, 0xF25C}, 343 {0xF260, 0xF268}, 344 {0xF26C, 0xF2A8}, 345 {0x10008, 0x1000C}, 346 {0x10014, 0x10018}, 347 {0x1001C, 0x10020}, 348 {0x10024, 0x10028}, 349 {0x10030, 0x10034}, 350 {0x10040, 0x10054}, 351 {0x10058, 0x1007C}, 352 {0x10080, 0x100C4}, 353 {0x100C8, 0x10114}, 354 {0x1012C, 0x10130}, 355 {0x10138, 0x10144}, 356 {0x10200, 0x10220}, 357 {0x10230, 0x10250}, 358 {0x10260, 0x10280}, 359 {0x10290, 0x102B0}, 360 {0x102C0, 0x102DC}, 361 {0x102E0, 0x102F4}, 362 {0x102FC, 0x1037C}, 363 {0x10380, 0x10390}, 364 {0x10800, 0x10828}, 365 {0x10840, 0x10844}, 366 {0x10880, 0x10884}, 367 {0x108C0, 0x108E8}, 368 {0x10900, 0x10928}, 369 {0x10940, 0x10944}, 370 {0x10980, 0x10984}, 371 {0x109C0, 0x109E8}, 372 {0x10A00, 0x10A28}, 373 {0x10A40, 0x10A50}, 374 {0x11000, 0x11028}, 375 {0x11030, 0x11034}, 376 {0x11038, 0x11068}, 377 {0x11070, 0x11074}, 378 {0x11078, 0x110A8}, 379 {0x110B0, 0x110B4}, 380 {0x110B8, 0x110E8}, 381 {0x110F0, 0x110F4}, 382 {0x110F8, 0x11128}, 383 {0x11138, 0x11144}, 384 {0x11178, 0x11180}, 385 {0x111B8, 0x111C0}, 386 {0x111F8, 0x11200}, 387 {0x11238, 0x1123C}, 388 {0x11270, 0x11274}, 389 {0x11278, 0x1127C}, 390 {0x112B0, 0x112B4}, 391 {0x112B8, 0x112BC}, 392 {0x112F0, 0x112F4}, 393 {0x112F8, 0x112FC}, 394 {0x11338, 0x1133C}, 395 {0x11378, 0x1137C}, 396 {0x113B8, 0x113BC}, 397 {0x113F8, 0x113FC}, 398 {0x11438, 0x11440}, 399 {0x11478, 0x11480}, 400 {0x114B8, 0x114BC}, 401 {0x114F8, 0x114FC}, 402 {0x11538, 0x1153C}, 403 {0x11578, 0x1157C}, 404 {0x115B8, 0x115BC}, 405 {0x115F8, 0x115FC}, 406 {0x11638, 0x1163C}, 407 {0x11678, 0x1167C}, 408 {0x116B8, 0x116BC}, 409 {0x116F8, 0x116FC}, 410 {0x11738, 0x1173C}, 411 {0x11778, 0x1177C}, 412 {0x117B8, 0x117BC}, 413 {0x117F8, 0x117FC}, 414 {0x17000, 0x1701C}, 415 {0x17020, 0x170AC}, 416 {0x18000, 0x18050}, 417 {0x18054, 0x18074}, 418 {0x18080, 0x180D4}, 419 {0x180DC, 0x18104}, 420 {0x18108, 0x1813C}, 421 {0x18144, 0x18148}, 422 {0x18168, 0x18174}, 423 {0x18178, 0x18180}, 424 {0x181C8, 0x181E0}, 425 {0x181E4, 0x181E8}, 426 {0x181EC, 0x1820C}, 427 {0x1825C, 0x18280}, 428 {0x18284, 0x18290}, 429 {0x18294, 0x182A0}, 430 {0x18300, 0x18304}, 431 {0x18314, 0x18320}, 432 {0x18328, 0x18350}, 433 {0x1835C, 0x1836C}, 434 {0x18370, 0x18390}, 435 {0x18398, 0x183AC}, 436 {0x183BC, 0x183D8}, 437 {0x183DC, 0x183F4}, 438 {0x18400, 0x186F4}, 439 {0x186F8, 0x1871C}, 440 {0x18720, 0x18790}, 441 {0x19800, 0x19830}, 442 {0x19834, 0x19840}, 443 {0x19880, 0x1989C}, 444 {0x198A4, 0x198B0}, 445 {0x198BC, 0x19900}, 446 {0x19C00, 0x19C88}, 447 {0x19D00, 0x19D20}, 448 {0x19E00, 0x19E7C}, 449 {0x19E80, 0x19E94}, 450 {0x19E98, 0x19EAC}, 451 {0x19EB0, 0x19EBC}, 452 {0x19F70, 0x19F74}, 453 {0x19F80, 0x19F8C}, 454 {0x19FA0, 0x19FB4}, 455 {0x19FC0, 0x19FD8}, 456 {0x1A000, 0x1A200}, 457 {0x1A204, 0x1A210}, 458 {0x1A228, 0x1A22C}, 459 {0x1A230, 0x1A248}, 460 {0x1A250, 0x1A270}, 461 {0x1A280, 0x1A290}, 462 {0x1A2A0, 0x1A2A4}, 463 {0x1A2C0, 0x1A2EC}, 464 {0x1A300, 0x1A3BC}, 465 {0x1A3F0, 0x1A3F4}, 466 {0x1A3F8, 0x1A434}, 467 {0x1A438, 0x1A444}, 468 {0x1A448, 0x1A468}, 469 {0x1A580, 0x1A58C}, 470 {0x1A644, 0x1A654}, 471 {0x1A670, 0x1A698}, 472 {0x1A6AC, 0x1A6B0}, 473 {0x1A6D0, 0x1A6D4}, 474 {0x1A6EC, 0x1A70C}, 475 {0x1A710, 0x1A738}, 476 {0x1A7C0, 0x1A7D0}, 477 {0x1A7D4, 0x1A7D8}, 478 {0x1A7DC, 0x1A7E4}, 479 {0x1A7F0, 0x1A7F8}, 480 {0x1A888, 0x1A89C}, 481 {0x1A8A8, 0x1A8AC}, 482 {0x1A8C0, 0x1A8DC}, 483 {0x1A8F0, 0x1A8FC}, 484 {0x1AE04, 0x1AE08}, 485 {0x1AE18, 0x1AE24}, 486 {0x1AF80, 0x1AF8C}, 487 {0x1AFA0, 0x1AFB4}, 488 {0x1B000, 0x1B200}, 489 {0x1B284, 0x1B288}, 490 {0x1B2D0, 0x1B2D8}, 491 {0x1B2DC, 0x1B2EC}, 492 {0x1B300, 0x1B340}, 493 {0x1B374, 0x1B378}, 494 {0x1B380, 0x1B384}, 495 {0x1B388, 0x1B38C}, 496 {0x1B404, 0x1B408}, 497 {0x1B420, 0x1B428}, 498 {0x1B440, 0x1B444}, 499 {0x1B448, 0x1B44C}, 500 {0x1B450, 0x1B458}, 501 {0x1B45C, 0x1B468}, 502 {0x1B584, 0x1B58C}, 503 {0x1B68C, 0x1B690}, 504 {0x1B6AC, 0x1B6B0}, 505 {0x1B7F0, 0x1B7F8}, 506 {0x1C800, 0x1CC00}, 507 {0x1CE00, 0x1CE04}, 508 {0x1CF80, 0x1CF84}, 509 {0x1D200, 0x1D800}, 510 {0x1E000, 0x20014}, 511 {0x20100, 0x20124}, 512 {0x21400, 0x217A8}, 513 {0x21800, 0x21BA8}, 514 {0x21C00, 0x21FA8}, 515 {0x22000, 0x223A8}, 516 {0x22400, 0x227A8}, 517 {0x22800, 0x22BA8}, 518 {0x22C00, 0x22FA8}, 519 {0x23000, 0x233A8}, 520 {0x24000, 0x24034}, 521 {0x26000, 0x26064}, 522 {0x27000, 0x27024}, 523 {0x34000, 0x3400C}, 524 {0x34400, 0x3445C}, 525 {0x34800, 0x3485C}, 526 {0x34C00, 0x34C5C}, 527 {0x35000, 0x3505C}, 528 {0x35400, 0x3545C}, 529 {0x35800, 0x3585C}, 530 {0x35C00, 0x35C5C}, 531 {0x36000, 0x3605C}, 532 {0x38000, 0x38064}, 533 {0x38070, 0x380E0}, 534 {0x3A000, 0x3A074}, 535 {0x40000, 0x400A4}, 536 {0x80000, 0x8000C}, 537 {0x80010, 0x80020}, 538 }; 539 540 static const struct ath10k_mem_region qca6174_hw10_mem_regions[] = { 541 { 542 .type = ATH10K_MEM_REGION_TYPE_DRAM, 543 .start = 0x400000, 544 .len = 0x70000, 545 .name = "DRAM", 546 .section_table = { 547 .sections = NULL, 548 .size = 0, 549 }, 550 }, 551 { 552 .type = ATH10K_MEM_REGION_TYPE_REG, 553 554 /* RTC_SOC_BASE_ADDRESS */ 555 .start = 0x0, 556 557 /* WLAN_MBOX_BASE_ADDRESS - RTC_SOC_BASE_ADDRESS */ 558 .len = 0x800 - 0x0, 559 560 .name = "REG_PART1", 561 .section_table = { 562 .sections = NULL, 563 .size = 0, 564 }, 565 }, 566 { 567 .type = ATH10K_MEM_REGION_TYPE_REG, 568 569 /* STEREO_BASE_ADDRESS */ 570 .start = 0x27000, 571 572 /* USB_BASE_ADDRESS - STEREO_BASE_ADDRESS */ 573 .len = 0x60000 - 0x27000, 574 575 .name = "REG_PART2", 576 .section_table = { 577 .sections = NULL, 578 .size = 0, 579 }, 580 }, 581 }; 582 583 static const struct ath10k_mem_region qca6174_hw21_mem_regions[] = { 584 { 585 .type = ATH10K_MEM_REGION_TYPE_DRAM, 586 .start = 0x400000, 587 .len = 0x70000, 588 .name = "DRAM", 589 .section_table = { 590 .sections = NULL, 591 .size = 0, 592 }, 593 }, 594 { 595 .type = ATH10K_MEM_REGION_TYPE_AXI, 596 .start = 0xa0000, 597 .len = 0x18000, 598 .name = "AXI", 599 .section_table = { 600 .sections = NULL, 601 .size = 0, 602 }, 603 }, 604 { 605 .type = ATH10K_MEM_REGION_TYPE_REG, 606 .start = 0x800, 607 .len = 0x80020 - 0x800, 608 .name = "REG_TOTAL", 609 .section_table = { 610 .sections = qca6174_hw21_register_sections, 611 .size = ARRAY_SIZE(qca6174_hw21_register_sections), 612 }, 613 }, 614 }; 615 616 static const struct ath10k_mem_region qca6174_hw30_mem_regions[] = { 617 { 618 .type = ATH10K_MEM_REGION_TYPE_DRAM, 619 .start = 0x400000, 620 .len = 0xa8000, 621 .name = "DRAM", 622 .section_table = { 623 .sections = NULL, 624 .size = 0, 625 }, 626 }, 627 { 628 .type = ATH10K_MEM_REGION_TYPE_AXI, 629 .start = 0xa0000, 630 .len = 0x18000, 631 .name = "AXI", 632 .section_table = { 633 .sections = NULL, 634 .size = 0, 635 }, 636 }, 637 { 638 .type = ATH10K_MEM_REGION_TYPE_REG, 639 .start = 0x800, 640 .len = 0x80020 - 0x800, 641 .name = "REG_TOTAL", 642 .section_table = { 643 .sections = qca6174_hw30_register_sections, 644 .size = ARRAY_SIZE(qca6174_hw30_register_sections), 645 }, 646 }, 647 648 /* IRAM dump must be put last */ 649 { 650 .type = ATH10K_MEM_REGION_TYPE_IRAM1, 651 .start = 0x00980000, 652 .len = 0x00080000, 653 .name = "IRAM1", 654 .section_table = { 655 .sections = NULL, 656 .size = 0, 657 }, 658 }, 659 { 660 .type = ATH10K_MEM_REGION_TYPE_IRAM2, 661 .start = 0x00a00000, 662 .len = 0x00040000, 663 .name = "IRAM2", 664 .section_table = { 665 .sections = NULL, 666 .size = 0, 667 }, 668 }, 669 }; 670 671 static const struct ath10k_mem_region qca988x_hw20_mem_regions[] = { 672 { 673 .type = ATH10K_MEM_REGION_TYPE_DRAM, 674 .start = 0x400000, 675 .len = 0x50000, 676 .name = "DRAM", 677 .section_table = { 678 .sections = NULL, 679 .size = 0, 680 }, 681 }, 682 { 683 .type = ATH10K_MEM_REGION_TYPE_REG, 684 .start = 0x4000, 685 .len = 0x2000, 686 .name = "REG_PART1", 687 .section_table = { 688 .sections = NULL, 689 .size = 0, 690 }, 691 }, 692 { 693 .type = ATH10K_MEM_REGION_TYPE_REG, 694 .start = 0x8000, 695 .len = 0x58000, 696 .name = "REG_PART2", 697 .section_table = { 698 .sections = NULL, 699 .size = 0, 700 }, 701 }, 702 }; 703 704 static const struct ath10k_mem_region qca99x0_hw20_mem_regions[] = { 705 { 706 .type = ATH10K_MEM_REGION_TYPE_DRAM, 707 .start = 0x400000, 708 .len = 0x60000, 709 .name = "DRAM", 710 .section_table = { 711 .sections = NULL, 712 .size = 0, 713 }, 714 }, 715 { 716 .type = ATH10K_MEM_REGION_TYPE_REG, 717 .start = 0x98000, 718 .len = 0x50000, 719 .name = "IRAM", 720 .section_table = { 721 .sections = NULL, 722 .size = 0, 723 }, 724 }, 725 { 726 .type = ATH10K_MEM_REGION_TYPE_IOSRAM, 727 .start = 0xC0000, 728 .len = 0x40000, 729 .name = "SRAM", 730 .section_table = { 731 .sections = NULL, 732 .size = 0, 733 }, 734 }, 735 { 736 .type = ATH10K_MEM_REGION_TYPE_IOREG, 737 .start = 0x30000, 738 .len = 0x7000, 739 .name = "APB REG 1", 740 .section_table = { 741 .sections = NULL, 742 .size = 0, 743 }, 744 }, 745 { 746 .type = ATH10K_MEM_REGION_TYPE_IOREG, 747 .start = 0x3f000, 748 .len = 0x3000, 749 .name = "APB REG 2", 750 .section_table = { 751 .sections = NULL, 752 .size = 0, 753 }, 754 }, 755 { 756 .type = ATH10K_MEM_REGION_TYPE_IOREG, 757 .start = 0x43000, 758 .len = 0x3000, 759 .name = "WIFI REG", 760 .section_table = { 761 .sections = NULL, 762 .size = 0, 763 }, 764 }, 765 { 766 .type = ATH10K_MEM_REGION_TYPE_IOREG, 767 .start = 0x4A000, 768 .len = 0x5000, 769 .name = "CE REG", 770 .section_table = { 771 .sections = NULL, 772 .size = 0, 773 }, 774 }, 775 { 776 .type = ATH10K_MEM_REGION_TYPE_IOREG, 777 .start = 0x80000, 778 .len = 0x6000, 779 .name = "SOC REG", 780 .section_table = { 781 .sections = NULL, 782 .size = 0, 783 }, 784 }, 785 }; 786 787 static const struct ath10k_mem_region qca9984_hw10_mem_regions[] = { 788 { 789 .type = ATH10K_MEM_REGION_TYPE_DRAM, 790 .start = 0x400000, 791 .len = 0x80000, 792 .name = "DRAM", 793 .section_table = { 794 .sections = NULL, 795 .size = 0, 796 }, 797 }, 798 { 799 .type = ATH10K_MEM_REGION_TYPE_REG, 800 .start = 0x98000, 801 .len = 0x50000, 802 .name = "IRAM", 803 .section_table = { 804 .sections = NULL, 805 .size = 0, 806 }, 807 }, 808 { 809 .type = ATH10K_MEM_REGION_TYPE_IOSRAM, 810 .start = 0xC0000, 811 .len = 0x40000, 812 .name = "SRAM", 813 .section_table = { 814 .sections = NULL, 815 .size = 0, 816 }, 817 }, 818 { 819 .type = ATH10K_MEM_REGION_TYPE_IOREG, 820 .start = 0x30000, 821 .len = 0x7000, 822 .name = "APB REG 1", 823 .section_table = { 824 .sections = NULL, 825 .size = 0, 826 }, 827 }, 828 { 829 .type = ATH10K_MEM_REGION_TYPE_IOREG, 830 .start = 0x3f000, 831 .len = 0x3000, 832 .name = "APB REG 2", 833 .section_table = { 834 .sections = NULL, 835 .size = 0, 836 }, 837 }, 838 { 839 .type = ATH10K_MEM_REGION_TYPE_IOREG, 840 .start = 0x43000, 841 .len = 0x3000, 842 .name = "WIFI REG", 843 .section_table = { 844 .sections = NULL, 845 .size = 0, 846 }, 847 }, 848 { 849 .type = ATH10K_MEM_REGION_TYPE_IOREG, 850 .start = 0x4A000, 851 .len = 0x5000, 852 .name = "CE REG", 853 .section_table = { 854 .sections = NULL, 855 .size = 0, 856 }, 857 }, 858 { 859 .type = ATH10K_MEM_REGION_TYPE_IOREG, 860 .start = 0x80000, 861 .len = 0x6000, 862 .name = "SOC REG", 863 .section_table = { 864 .sections = NULL, 865 .size = 0, 866 }, 867 }, 868 }; 869 870 static const struct ath10k_mem_section ipq4019_soc_reg_range[] = { 871 {0x080000, 0x080004}, 872 {0x080020, 0x080024}, 873 {0x080028, 0x080050}, 874 {0x0800d4, 0x0800ec}, 875 {0x08010c, 0x080118}, 876 {0x080284, 0x080290}, 877 {0x0802a8, 0x0802b8}, 878 {0x0802dc, 0x08030c}, 879 {0x082000, 0x083fff} 880 }; 881 882 static const struct ath10k_mem_region qca4019_hw10_mem_regions[] = { 883 { 884 .type = ATH10K_MEM_REGION_TYPE_DRAM, 885 .start = 0x400000, 886 .len = 0x68000, 887 .name = "DRAM", 888 .section_table = { 889 .sections = NULL, 890 .size = 0, 891 }, 892 }, 893 { 894 .type = ATH10K_MEM_REGION_TYPE_REG, 895 .start = 0xC0000, 896 .len = 0x40000, 897 .name = "SRAM", 898 .section_table = { 899 .sections = NULL, 900 .size = 0, 901 }, 902 }, 903 { 904 .type = ATH10K_MEM_REGION_TYPE_REG, 905 .start = 0x98000, 906 .len = 0x50000, 907 .name = "IRAM", 908 .section_table = { 909 .sections = NULL, 910 .size = 0, 911 }, 912 }, 913 { 914 .type = ATH10K_MEM_REGION_TYPE_IOREG, 915 .start = 0x30000, 916 .len = 0x7000, 917 .name = "APB REG 1", 918 .section_table = { 919 .sections = NULL, 920 .size = 0, 921 }, 922 }, 923 { 924 .type = ATH10K_MEM_REGION_TYPE_IOREG, 925 .start = 0x3f000, 926 .len = 0x3000, 927 .name = "APB REG 2", 928 .section_table = { 929 .sections = NULL, 930 .size = 0, 931 }, 932 }, 933 { 934 .type = ATH10K_MEM_REGION_TYPE_IOREG, 935 .start = 0x43000, 936 .len = 0x3000, 937 .name = "WIFI REG", 938 .section_table = { 939 .sections = NULL, 940 .size = 0, 941 }, 942 }, 943 { 944 .type = ATH10K_MEM_REGION_TYPE_IOREG, 945 .start = 0x4A000, 946 .len = 0x5000, 947 .name = "CE REG", 948 .section_table = { 949 .sections = NULL, 950 .size = 0, 951 }, 952 }, 953 { 954 .type = ATH10K_MEM_REGION_TYPE_REG, 955 .start = 0x080000, 956 .len = 0x083fff - 0x080000, 957 .name = "REG_TOTAL", 958 .section_table = { 959 .sections = ipq4019_soc_reg_range, 960 .size = ARRAY_SIZE(ipq4019_soc_reg_range), 961 }, 962 }, 963 }; 964 965 static const struct ath10k_hw_mem_layout hw_mem_layouts[] = { 966 { 967 .hw_id = QCA6174_HW_1_0_VERSION, 968 .hw_rev = ATH10K_HW_QCA6174, 969 .region_table = { 970 .regions = qca6174_hw10_mem_regions, 971 .size = ARRAY_SIZE(qca6174_hw10_mem_regions), 972 }, 973 }, 974 { 975 .hw_id = QCA6174_HW_1_1_VERSION, 976 .hw_rev = ATH10K_HW_QCA6174, 977 .region_table = { 978 .regions = qca6174_hw10_mem_regions, 979 .size = ARRAY_SIZE(qca6174_hw10_mem_regions), 980 }, 981 }, 982 { 983 .hw_id = QCA6174_HW_1_3_VERSION, 984 .hw_rev = ATH10K_HW_QCA6174, 985 .region_table = { 986 .regions = qca6174_hw10_mem_regions, 987 .size = ARRAY_SIZE(qca6174_hw10_mem_regions), 988 }, 989 }, 990 { 991 .hw_id = QCA6174_HW_2_1_VERSION, 992 .hw_rev = ATH10K_HW_QCA6174, 993 .region_table = { 994 .regions = qca6174_hw21_mem_regions, 995 .size = ARRAY_SIZE(qca6174_hw21_mem_regions), 996 }, 997 }, 998 { 999 .hw_id = QCA6174_HW_3_0_VERSION, 1000 .hw_rev = ATH10K_HW_QCA6174, 1001 .region_table = { 1002 .regions = qca6174_hw30_mem_regions, 1003 .size = ARRAY_SIZE(qca6174_hw30_mem_regions), 1004 }, 1005 }, 1006 { 1007 .hw_id = QCA6174_HW_3_2_VERSION, 1008 .hw_rev = ATH10K_HW_QCA6174, 1009 .region_table = { 1010 .regions = qca6174_hw30_mem_regions, 1011 .size = ARRAY_SIZE(qca6174_hw30_mem_regions), 1012 }, 1013 }, 1014 { 1015 .hw_id = QCA9377_HW_1_1_DEV_VERSION, 1016 .hw_rev = ATH10K_HW_QCA9377, 1017 .region_table = { 1018 .regions = qca6174_hw30_mem_regions, 1019 .size = ARRAY_SIZE(qca6174_hw30_mem_regions), 1020 }, 1021 }, 1022 { 1023 .hw_id = QCA988X_HW_2_0_VERSION, 1024 .hw_rev = ATH10K_HW_QCA988X, 1025 .region_table = { 1026 .regions = qca988x_hw20_mem_regions, 1027 .size = ARRAY_SIZE(qca988x_hw20_mem_regions), 1028 }, 1029 }, 1030 { 1031 .hw_id = QCA9984_HW_1_0_DEV_VERSION, 1032 .hw_rev = ATH10K_HW_QCA9984, 1033 .region_table = { 1034 .regions = qca9984_hw10_mem_regions, 1035 .size = ARRAY_SIZE(qca9984_hw10_mem_regions), 1036 }, 1037 }, 1038 { 1039 .hw_id = QCA9888_HW_2_0_DEV_VERSION, 1040 .hw_rev = ATH10K_HW_QCA9888, 1041 .region_table = { 1042 .regions = qca9984_hw10_mem_regions, 1043 .size = ARRAY_SIZE(qca9984_hw10_mem_regions), 1044 }, 1045 }, 1046 { 1047 .hw_id = QCA99X0_HW_2_0_DEV_VERSION, 1048 .hw_rev = ATH10K_HW_QCA99X0, 1049 .region_table = { 1050 .regions = qca99x0_hw20_mem_regions, 1051 .size = ARRAY_SIZE(qca99x0_hw20_mem_regions), 1052 }, 1053 }, 1054 { 1055 .hw_id = QCA4019_HW_1_0_DEV_VERSION, 1056 .hw_rev = ATH10K_HW_QCA4019, 1057 .region_table = { 1058 .regions = qca4019_hw10_mem_regions, 1059 .size = ARRAY_SIZE(qca4019_hw10_mem_regions), 1060 }, 1061 }, 1062 }; 1063 1064 static u32 ath10k_coredump_get_ramdump_size(struct ath10k *ar) 1065 { 1066 const struct ath10k_hw_mem_layout *hw; 1067 const struct ath10k_mem_region *mem_region; 1068 size_t size = 0; 1069 int i; 1070 1071 hw = ath10k_coredump_get_mem_layout(ar); 1072 1073 if (!hw) 1074 return 0; 1075 1076 mem_region = &hw->region_table.regions[0]; 1077 1078 for (i = 0; i < hw->region_table.size; i++) { 1079 size += mem_region->len; 1080 mem_region++; 1081 } 1082 1083 /* reserve space for the headers */ 1084 size += hw->region_table.size * sizeof(struct ath10k_dump_ram_data_hdr); 1085 1086 /* make sure it is aligned 16 bytes for debug message print out */ 1087 size = ALIGN(size, 16); 1088 1089 return size; 1090 } 1091 1092 const struct ath10k_hw_mem_layout *ath10k_coredump_get_mem_layout(struct ath10k *ar) 1093 { 1094 int i; 1095 1096 if (!test_bit(ATH10K_FW_CRASH_DUMP_RAM_DATA, &ath10k_coredump_mask)) 1097 return NULL; 1098 1099 if (WARN_ON(ar->target_version == 0)) 1100 return NULL; 1101 1102 for (i = 0; i < ARRAY_SIZE(hw_mem_layouts); i++) { 1103 if (ar->target_version == hw_mem_layouts[i].hw_id && 1104 ar->hw_rev == hw_mem_layouts[i].hw_rev) 1105 return &hw_mem_layouts[i]; 1106 } 1107 1108 return NULL; 1109 } 1110 EXPORT_SYMBOL(ath10k_coredump_get_mem_layout); 1111 1112 struct ath10k_fw_crash_data *ath10k_coredump_new(struct ath10k *ar) 1113 { 1114 struct ath10k_fw_crash_data *crash_data = ar->coredump.fw_crash_data; 1115 1116 lockdep_assert_held(&ar->data_lock); 1117 1118 if (ath10k_coredump_mask == 0) 1119 /* coredump disabled */ 1120 return NULL; 1121 1122 guid_gen(&crash_data->guid); 1123 ktime_get_real_ts64(&crash_data->timestamp); 1124 1125 return crash_data; 1126 } 1127 EXPORT_SYMBOL(ath10k_coredump_new); 1128 1129 static struct ath10k_dump_file_data *ath10k_coredump_build(struct ath10k *ar) 1130 { 1131 struct ath10k_fw_crash_data *crash_data = ar->coredump.fw_crash_data; 1132 struct ath10k_ce_crash_hdr *ce_hdr; 1133 struct ath10k_dump_file_data *dump_data; 1134 struct ath10k_tlv_dump_data *dump_tlv; 1135 size_t hdr_len = sizeof(*dump_data); 1136 size_t len, sofar = 0; 1137 unsigned char *buf; 1138 1139 len = hdr_len; 1140 1141 if (test_bit(ATH10K_FW_CRASH_DUMP_REGISTERS, &ath10k_coredump_mask)) 1142 len += sizeof(*dump_tlv) + sizeof(crash_data->registers); 1143 1144 if (test_bit(ATH10K_FW_CRASH_DUMP_CE_DATA, &ath10k_coredump_mask)) 1145 len += sizeof(*dump_tlv) + sizeof(*ce_hdr) + 1146 CE_COUNT * sizeof(ce_hdr->entries[0]); 1147 1148 if (test_bit(ATH10K_FW_CRASH_DUMP_RAM_DATA, &ath10k_coredump_mask)) 1149 len += sizeof(*dump_tlv) + crash_data->ramdump_buf_len; 1150 1151 sofar += hdr_len; 1152 1153 /* This is going to get big when we start dumping FW RAM and such, 1154 * so go ahead and use vmalloc. 1155 */ 1156 buf = vzalloc(len); 1157 if (!buf) 1158 return NULL; 1159 1160 spin_lock_bh(&ar->data_lock); 1161 1162 dump_data = (struct ath10k_dump_file_data *)(buf); 1163 strlcpy(dump_data->df_magic, "ATH10K-FW-DUMP", 1164 sizeof(dump_data->df_magic)); 1165 dump_data->len = cpu_to_le32(len); 1166 1167 dump_data->version = cpu_to_le32(ATH10K_FW_CRASH_DUMP_VERSION); 1168 1169 guid_copy(&dump_data->guid, &crash_data->guid); 1170 dump_data->chip_id = cpu_to_le32(ar->chip_id); 1171 dump_data->bus_type = cpu_to_le32(0); 1172 dump_data->target_version = cpu_to_le32(ar->target_version); 1173 dump_data->fw_version_major = cpu_to_le32(ar->fw_version_major); 1174 dump_data->fw_version_minor = cpu_to_le32(ar->fw_version_minor); 1175 dump_data->fw_version_release = cpu_to_le32(ar->fw_version_release); 1176 dump_data->fw_version_build = cpu_to_le32(ar->fw_version_build); 1177 dump_data->phy_capability = cpu_to_le32(ar->phy_capability); 1178 dump_data->hw_min_tx_power = cpu_to_le32(ar->hw_min_tx_power); 1179 dump_data->hw_max_tx_power = cpu_to_le32(ar->hw_max_tx_power); 1180 dump_data->ht_cap_info = cpu_to_le32(ar->ht_cap_info); 1181 dump_data->vht_cap_info = cpu_to_le32(ar->vht_cap_info); 1182 dump_data->num_rf_chains = cpu_to_le32(ar->num_rf_chains); 1183 1184 strlcpy(dump_data->fw_ver, ar->hw->wiphy->fw_version, 1185 sizeof(dump_data->fw_ver)); 1186 1187 dump_data->kernel_ver_code = 0; 1188 strlcpy(dump_data->kernel_ver, init_utsname()->release, 1189 sizeof(dump_data->kernel_ver)); 1190 1191 dump_data->tv_sec = cpu_to_le64(crash_data->timestamp.tv_sec); 1192 dump_data->tv_nsec = cpu_to_le64(crash_data->timestamp.tv_nsec); 1193 1194 if (test_bit(ATH10K_FW_CRASH_DUMP_REGISTERS, &ath10k_coredump_mask)) { 1195 dump_tlv = (struct ath10k_tlv_dump_data *)(buf + sofar); 1196 dump_tlv->type = cpu_to_le32(ATH10K_FW_CRASH_DUMP_REGISTERS); 1197 dump_tlv->tlv_len = cpu_to_le32(sizeof(crash_data->registers)); 1198 memcpy(dump_tlv->tlv_data, &crash_data->registers, 1199 sizeof(crash_data->registers)); 1200 sofar += sizeof(*dump_tlv) + sizeof(crash_data->registers); 1201 } 1202 1203 if (test_bit(ATH10K_FW_CRASH_DUMP_CE_DATA, &ath10k_coredump_mask)) { 1204 dump_tlv = (struct ath10k_tlv_dump_data *)(buf + sofar); 1205 dump_tlv->type = cpu_to_le32(ATH10K_FW_CRASH_DUMP_CE_DATA); 1206 dump_tlv->tlv_len = cpu_to_le32(sizeof(*ce_hdr) + 1207 CE_COUNT * sizeof(ce_hdr->entries[0])); 1208 ce_hdr = (struct ath10k_ce_crash_hdr *)(dump_tlv->tlv_data); 1209 ce_hdr->ce_count = cpu_to_le32(CE_COUNT); 1210 memset(ce_hdr->reserved, 0, sizeof(ce_hdr->reserved)); 1211 memcpy(ce_hdr->entries, crash_data->ce_crash_data, 1212 CE_COUNT * sizeof(ce_hdr->entries[0])); 1213 sofar += sizeof(*dump_tlv) + sizeof(*ce_hdr) + 1214 CE_COUNT * sizeof(ce_hdr->entries[0]); 1215 } 1216 1217 /* Gather ram dump */ 1218 if (test_bit(ATH10K_FW_CRASH_DUMP_RAM_DATA, &ath10k_coredump_mask)) { 1219 dump_tlv = (struct ath10k_tlv_dump_data *)(buf + sofar); 1220 dump_tlv->type = cpu_to_le32(ATH10K_FW_CRASH_DUMP_RAM_DATA); 1221 dump_tlv->tlv_len = cpu_to_le32(crash_data->ramdump_buf_len); 1222 memcpy(dump_tlv->tlv_data, crash_data->ramdump_buf, 1223 crash_data->ramdump_buf_len); 1224 sofar += sizeof(*dump_tlv) + crash_data->ramdump_buf_len; 1225 } 1226 1227 spin_unlock_bh(&ar->data_lock); 1228 1229 return dump_data; 1230 } 1231 1232 int ath10k_coredump_submit(struct ath10k *ar) 1233 { 1234 struct ath10k_dump_file_data *dump; 1235 1236 if (ath10k_coredump_mask == 0) 1237 /* coredump disabled */ 1238 return 0; 1239 1240 dump = ath10k_coredump_build(ar); 1241 if (!dump) { 1242 ath10k_warn(ar, "no crash dump data found for devcoredump"); 1243 return -ENODATA; 1244 } 1245 1246 dev_coredumpv(ar->dev, dump, le32_to_cpu(dump->len), GFP_KERNEL); 1247 1248 return 0; 1249 } 1250 1251 int ath10k_coredump_create(struct ath10k *ar) 1252 { 1253 if (ath10k_coredump_mask == 0) 1254 /* coredump disabled */ 1255 return 0; 1256 1257 ar->coredump.fw_crash_data = vzalloc(sizeof(*ar->coredump.fw_crash_data)); 1258 if (!ar->coredump.fw_crash_data) 1259 return -ENOMEM; 1260 1261 return 0; 1262 } 1263 1264 int ath10k_coredump_register(struct ath10k *ar) 1265 { 1266 struct ath10k_fw_crash_data *crash_data = ar->coredump.fw_crash_data; 1267 1268 if (test_bit(ATH10K_FW_CRASH_DUMP_RAM_DATA, &ath10k_coredump_mask)) { 1269 crash_data->ramdump_buf_len = ath10k_coredump_get_ramdump_size(ar); 1270 1271 crash_data->ramdump_buf = vzalloc(crash_data->ramdump_buf_len); 1272 if (!crash_data->ramdump_buf) 1273 return -ENOMEM; 1274 } 1275 1276 return 0; 1277 } 1278 1279 void ath10k_coredump_unregister(struct ath10k *ar) 1280 { 1281 struct ath10k_fw_crash_data *crash_data = ar->coredump.fw_crash_data; 1282 1283 vfree(crash_data->ramdump_buf); 1284 } 1285 1286 void ath10k_coredump_destroy(struct ath10k *ar) 1287 { 1288 if (ar->coredump.fw_crash_data->ramdump_buf) { 1289 vfree(ar->coredump.fw_crash_data->ramdump_buf); 1290 ar->coredump.fw_crash_data->ramdump_buf = NULL; 1291 ar->coredump.fw_crash_data->ramdump_buf_len = 0; 1292 } 1293 1294 vfree(ar->coredump.fw_crash_data); 1295 ar->coredump.fw_crash_data = NULL; 1296 } 1297