1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. 4 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 5 */ 6 7 #include "coredump.h" 8 9 #include <linux/devcoredump.h> 10 #include <linux/kernel.h> 11 #include <linux/types.h> 12 #include <linux/utsname.h> 13 14 #include "debug.h" 15 #include "hw.h" 16 17 static const struct ath10k_mem_section qca6174_hw21_register_sections[] = { 18 {0x800, 0x810}, 19 {0x820, 0x82C}, 20 {0x830, 0x8F4}, 21 {0x90C, 0x91C}, 22 {0xA14, 0xA18}, 23 {0xA84, 0xA94}, 24 {0xAA8, 0xAD4}, 25 {0xADC, 0xB40}, 26 {0x1000, 0x10A4}, 27 {0x10BC, 0x111C}, 28 {0x1134, 0x1138}, 29 {0x1144, 0x114C}, 30 {0x1150, 0x115C}, 31 {0x1160, 0x1178}, 32 {0x1240, 0x1260}, 33 {0x2000, 0x207C}, 34 {0x3000, 0x3014}, 35 {0x4000, 0x4014}, 36 {0x5000, 0x5124}, 37 {0x6000, 0x6040}, 38 {0x6080, 0x60CC}, 39 {0x6100, 0x611C}, 40 {0x6140, 0x61D8}, 41 {0x6200, 0x6238}, 42 {0x6240, 0x628C}, 43 {0x62C0, 0x62EC}, 44 {0x6380, 0x63E8}, 45 {0x6400, 0x6440}, 46 {0x6480, 0x64CC}, 47 {0x6500, 0x651C}, 48 {0x6540, 0x6580}, 49 {0x6600, 0x6638}, 50 {0x6640, 0x668C}, 51 {0x66C0, 0x66EC}, 52 {0x6780, 0x67E8}, 53 {0x7080, 0x708C}, 54 {0x70C0, 0x70C8}, 55 {0x7400, 0x741C}, 56 {0x7440, 0x7454}, 57 {0x7800, 0x7818}, 58 {0x8000, 0x8004}, 59 {0x8010, 0x8064}, 60 {0x8080, 0x8084}, 61 {0x80A0, 0x80A4}, 62 {0x80C0, 0x80C4}, 63 {0x80E0, 0x80F4}, 64 {0x8100, 0x8104}, 65 {0x8110, 0x812C}, 66 {0x9000, 0x9004}, 67 {0x9800, 0x982C}, 68 {0x9830, 0x9838}, 69 {0x9840, 0x986C}, 70 {0x9870, 0x9898}, 71 {0x9A00, 0x9C00}, 72 {0xD580, 0xD59C}, 73 {0xF000, 0xF0E0}, 74 {0xF140, 0xF190}, 75 {0xF250, 0xF25C}, 76 {0xF260, 0xF268}, 77 {0xF26C, 0xF2A8}, 78 {0x10008, 0x1000C}, 79 {0x10014, 0x10018}, 80 {0x1001C, 0x10020}, 81 {0x10024, 0x10028}, 82 {0x10030, 0x10034}, 83 {0x10040, 0x10054}, 84 {0x10058, 0x1007C}, 85 {0x10080, 0x100C4}, 86 {0x100C8, 0x10114}, 87 {0x1012C, 0x10130}, 88 {0x10138, 0x10144}, 89 {0x10200, 0x10220}, 90 {0x10230, 0x10250}, 91 {0x10260, 0x10280}, 92 {0x10290, 0x102B0}, 93 {0x102C0, 0x102DC}, 94 {0x102E0, 0x102F4}, 95 {0x102FC, 0x1037C}, 96 {0x10380, 0x10390}, 97 {0x10800, 0x10828}, 98 {0x10840, 0x10844}, 99 {0x10880, 0x10884}, 100 {0x108C0, 0x108E8}, 101 {0x10900, 0x10928}, 102 {0x10940, 0x10944}, 103 {0x10980, 0x10984}, 104 {0x109C0, 0x109E8}, 105 {0x10A00, 0x10A28}, 106 {0x10A40, 0x10A50}, 107 {0x11000, 0x11028}, 108 {0x11030, 0x11034}, 109 {0x11038, 0x11068}, 110 {0x11070, 0x11074}, 111 {0x11078, 0x110A8}, 112 {0x110B0, 0x110B4}, 113 {0x110B8, 0x110E8}, 114 {0x110F0, 0x110F4}, 115 {0x110F8, 0x11128}, 116 {0x11138, 0x11144}, 117 {0x11178, 0x11180}, 118 {0x111B8, 0x111C0}, 119 {0x111F8, 0x11200}, 120 {0x11238, 0x1123C}, 121 {0x11270, 0x11274}, 122 {0x11278, 0x1127C}, 123 {0x112B0, 0x112B4}, 124 {0x112B8, 0x112BC}, 125 {0x112F0, 0x112F4}, 126 {0x112F8, 0x112FC}, 127 {0x11338, 0x1133C}, 128 {0x11378, 0x1137C}, 129 {0x113B8, 0x113BC}, 130 {0x113F8, 0x113FC}, 131 {0x11438, 0x11440}, 132 {0x11478, 0x11480}, 133 {0x114B8, 0x114BC}, 134 {0x114F8, 0x114FC}, 135 {0x11538, 0x1153C}, 136 {0x11578, 0x1157C}, 137 {0x115B8, 0x115BC}, 138 {0x115F8, 0x115FC}, 139 {0x11638, 0x1163C}, 140 {0x11678, 0x1167C}, 141 {0x116B8, 0x116BC}, 142 {0x116F8, 0x116FC}, 143 {0x11738, 0x1173C}, 144 {0x11778, 0x1177C}, 145 {0x117B8, 0x117BC}, 146 {0x117F8, 0x117FC}, 147 {0x17000, 0x1701C}, 148 {0x17020, 0x170AC}, 149 {0x18000, 0x18050}, 150 {0x18054, 0x18074}, 151 {0x18080, 0x180D4}, 152 {0x180DC, 0x18104}, 153 {0x18108, 0x1813C}, 154 {0x18144, 0x18148}, 155 {0x18168, 0x18174}, 156 {0x18178, 0x18180}, 157 {0x181C8, 0x181E0}, 158 {0x181E4, 0x181E8}, 159 {0x181EC, 0x1820C}, 160 {0x1825C, 0x18280}, 161 {0x18284, 0x18290}, 162 {0x18294, 0x182A0}, 163 {0x18300, 0x18304}, 164 {0x18314, 0x18320}, 165 {0x18328, 0x18350}, 166 {0x1835C, 0x1836C}, 167 {0x18370, 0x18390}, 168 {0x18398, 0x183AC}, 169 {0x183BC, 0x183D8}, 170 {0x183DC, 0x183F4}, 171 {0x18400, 0x186F4}, 172 {0x186F8, 0x1871C}, 173 {0x18720, 0x18790}, 174 {0x19800, 0x19830}, 175 {0x19834, 0x19840}, 176 {0x19880, 0x1989C}, 177 {0x198A4, 0x198B0}, 178 {0x198BC, 0x19900}, 179 {0x19C00, 0x19C88}, 180 {0x19D00, 0x19D20}, 181 {0x19E00, 0x19E7C}, 182 {0x19E80, 0x19E94}, 183 {0x19E98, 0x19EAC}, 184 {0x19EB0, 0x19EBC}, 185 {0x19F70, 0x19F74}, 186 {0x19F80, 0x19F8C}, 187 {0x19FA0, 0x19FB4}, 188 {0x19FC0, 0x19FD8}, 189 {0x1A000, 0x1A200}, 190 {0x1A204, 0x1A210}, 191 {0x1A228, 0x1A22C}, 192 {0x1A230, 0x1A248}, 193 {0x1A250, 0x1A270}, 194 {0x1A280, 0x1A290}, 195 {0x1A2A0, 0x1A2A4}, 196 {0x1A2C0, 0x1A2EC}, 197 {0x1A300, 0x1A3BC}, 198 {0x1A3F0, 0x1A3F4}, 199 {0x1A3F8, 0x1A434}, 200 {0x1A438, 0x1A444}, 201 {0x1A448, 0x1A468}, 202 {0x1A580, 0x1A58C}, 203 {0x1A644, 0x1A654}, 204 {0x1A670, 0x1A698}, 205 {0x1A6AC, 0x1A6B0}, 206 {0x1A6D0, 0x1A6D4}, 207 {0x1A6EC, 0x1A70C}, 208 {0x1A710, 0x1A738}, 209 {0x1A7C0, 0x1A7D0}, 210 {0x1A7D4, 0x1A7D8}, 211 {0x1A7DC, 0x1A7E4}, 212 {0x1A7F0, 0x1A7F8}, 213 {0x1A888, 0x1A89C}, 214 {0x1A8A8, 0x1A8AC}, 215 {0x1A8C0, 0x1A8DC}, 216 {0x1A8F0, 0x1A8FC}, 217 {0x1AE04, 0x1AE08}, 218 {0x1AE18, 0x1AE24}, 219 {0x1AF80, 0x1AF8C}, 220 {0x1AFA0, 0x1AFB4}, 221 {0x1B000, 0x1B200}, 222 {0x1B284, 0x1B288}, 223 {0x1B2D0, 0x1B2D8}, 224 {0x1B2DC, 0x1B2EC}, 225 {0x1B300, 0x1B340}, 226 {0x1B374, 0x1B378}, 227 {0x1B380, 0x1B384}, 228 {0x1B388, 0x1B38C}, 229 {0x1B404, 0x1B408}, 230 {0x1B420, 0x1B428}, 231 {0x1B440, 0x1B444}, 232 {0x1B448, 0x1B44C}, 233 {0x1B450, 0x1B458}, 234 {0x1B45C, 0x1B468}, 235 {0x1B584, 0x1B58C}, 236 {0x1B68C, 0x1B690}, 237 {0x1B6AC, 0x1B6B0}, 238 {0x1B7F0, 0x1B7F8}, 239 {0x1C800, 0x1CC00}, 240 {0x1CE00, 0x1CE04}, 241 {0x1CF80, 0x1CF84}, 242 {0x1D200, 0x1D800}, 243 {0x1E000, 0x20014}, 244 {0x20100, 0x20124}, 245 {0x21400, 0x217A8}, 246 {0x21800, 0x21BA8}, 247 {0x21C00, 0x21FA8}, 248 {0x22000, 0x223A8}, 249 {0x22400, 0x227A8}, 250 {0x22800, 0x22BA8}, 251 {0x22C00, 0x22FA8}, 252 {0x23000, 0x233A8}, 253 {0x24000, 0x24034}, 254 {0x26000, 0x26064}, 255 {0x27000, 0x27024}, 256 {0x34000, 0x3400C}, 257 {0x34400, 0x3445C}, 258 {0x34800, 0x3485C}, 259 {0x34C00, 0x34C5C}, 260 {0x35000, 0x3505C}, 261 {0x35400, 0x3545C}, 262 {0x35800, 0x3585C}, 263 {0x35C00, 0x35C5C}, 264 {0x36000, 0x3605C}, 265 {0x38000, 0x38064}, 266 {0x38070, 0x380E0}, 267 {0x3A000, 0x3A064}, 268 {0x40000, 0x400A4}, 269 {0x80000, 0x8000C}, 270 {0x80010, 0x80020}, 271 }; 272 273 static const struct ath10k_mem_section qca6174_hw30_register_sections[] = { 274 {0x800, 0x810}, 275 {0x820, 0x82C}, 276 {0x830, 0x8F4}, 277 {0x90C, 0x91C}, 278 {0xA14, 0xA18}, 279 {0xA84, 0xA94}, 280 {0xAA8, 0xAD4}, 281 {0xADC, 0xB40}, 282 {0x1000, 0x10A4}, 283 {0x10BC, 0x111C}, 284 {0x1134, 0x1138}, 285 {0x1144, 0x114C}, 286 {0x1150, 0x115C}, 287 {0x1160, 0x1178}, 288 {0x1240, 0x1260}, 289 {0x2000, 0x207C}, 290 {0x3000, 0x3014}, 291 {0x4000, 0x4014}, 292 {0x5000, 0x5124}, 293 {0x6000, 0x6040}, 294 {0x6080, 0x60CC}, 295 {0x6100, 0x611C}, 296 {0x6140, 0x61D8}, 297 {0x6200, 0x6238}, 298 {0x6240, 0x628C}, 299 {0x62C0, 0x62EC}, 300 {0x6380, 0x63E8}, 301 {0x6400, 0x6440}, 302 {0x6480, 0x64CC}, 303 {0x6500, 0x651C}, 304 {0x6540, 0x6580}, 305 {0x6600, 0x6638}, 306 {0x6640, 0x668C}, 307 {0x66C0, 0x66EC}, 308 {0x6780, 0x67E8}, 309 {0x7080, 0x708C}, 310 {0x70C0, 0x70C8}, 311 {0x7400, 0x741C}, 312 {0x7440, 0x7454}, 313 {0x7800, 0x7818}, 314 {0x8000, 0x8004}, 315 {0x8010, 0x8064}, 316 {0x8080, 0x8084}, 317 {0x80A0, 0x80A4}, 318 {0x80C0, 0x80C4}, 319 {0x80E0, 0x80F4}, 320 {0x8100, 0x8104}, 321 {0x8110, 0x812C}, 322 {0x9000, 0x9004}, 323 {0x9800, 0x982C}, 324 {0x9830, 0x9838}, 325 {0x9840, 0x986C}, 326 {0x9870, 0x9898}, 327 {0x9A00, 0x9C00}, 328 {0xD580, 0xD59C}, 329 {0xF000, 0xF0E0}, 330 {0xF140, 0xF190}, 331 {0xF250, 0xF25C}, 332 {0xF260, 0xF268}, 333 {0xF26C, 0xF2A8}, 334 {0x10008, 0x1000C}, 335 {0x10014, 0x10018}, 336 {0x1001C, 0x10020}, 337 {0x10024, 0x10028}, 338 {0x10030, 0x10034}, 339 {0x10040, 0x10054}, 340 {0x10058, 0x1007C}, 341 {0x10080, 0x100C4}, 342 {0x100C8, 0x10114}, 343 {0x1012C, 0x10130}, 344 {0x10138, 0x10144}, 345 {0x10200, 0x10220}, 346 {0x10230, 0x10250}, 347 {0x10260, 0x10280}, 348 {0x10290, 0x102B0}, 349 {0x102C0, 0x102DC}, 350 {0x102E0, 0x102F4}, 351 {0x102FC, 0x1037C}, 352 {0x10380, 0x10390}, 353 {0x10800, 0x10828}, 354 {0x10840, 0x10844}, 355 {0x10880, 0x10884}, 356 {0x108C0, 0x108E8}, 357 {0x10900, 0x10928}, 358 {0x10940, 0x10944}, 359 {0x10980, 0x10984}, 360 {0x109C0, 0x109E8}, 361 {0x10A00, 0x10A28}, 362 {0x10A40, 0x10A50}, 363 {0x11000, 0x11028}, 364 {0x11030, 0x11034}, 365 {0x11038, 0x11068}, 366 {0x11070, 0x11074}, 367 {0x11078, 0x110A8}, 368 {0x110B0, 0x110B4}, 369 {0x110B8, 0x110E8}, 370 {0x110F0, 0x110F4}, 371 {0x110F8, 0x11128}, 372 {0x11138, 0x11144}, 373 {0x11178, 0x11180}, 374 {0x111B8, 0x111C0}, 375 {0x111F8, 0x11200}, 376 {0x11238, 0x1123C}, 377 {0x11270, 0x11274}, 378 {0x11278, 0x1127C}, 379 {0x112B0, 0x112B4}, 380 {0x112B8, 0x112BC}, 381 {0x112F0, 0x112F4}, 382 {0x112F8, 0x112FC}, 383 {0x11338, 0x1133C}, 384 {0x11378, 0x1137C}, 385 {0x113B8, 0x113BC}, 386 {0x113F8, 0x113FC}, 387 {0x11438, 0x11440}, 388 {0x11478, 0x11480}, 389 {0x114B8, 0x114BC}, 390 {0x114F8, 0x114FC}, 391 {0x11538, 0x1153C}, 392 {0x11578, 0x1157C}, 393 {0x115B8, 0x115BC}, 394 {0x115F8, 0x115FC}, 395 {0x11638, 0x1163C}, 396 {0x11678, 0x1167C}, 397 {0x116B8, 0x116BC}, 398 {0x116F8, 0x116FC}, 399 {0x11738, 0x1173C}, 400 {0x11778, 0x1177C}, 401 {0x117B8, 0x117BC}, 402 {0x117F8, 0x117FC}, 403 {0x17000, 0x1701C}, 404 {0x17020, 0x170AC}, 405 {0x18000, 0x18050}, 406 {0x18054, 0x18074}, 407 {0x18080, 0x180D4}, 408 {0x180DC, 0x18104}, 409 {0x18108, 0x1813C}, 410 {0x18144, 0x18148}, 411 {0x18168, 0x18174}, 412 {0x18178, 0x18180}, 413 {0x181C8, 0x181E0}, 414 {0x181E4, 0x181E8}, 415 {0x181EC, 0x1820C}, 416 {0x1825C, 0x18280}, 417 {0x18284, 0x18290}, 418 {0x18294, 0x182A0}, 419 {0x18300, 0x18304}, 420 {0x18314, 0x18320}, 421 {0x18328, 0x18350}, 422 {0x1835C, 0x1836C}, 423 {0x18370, 0x18390}, 424 {0x18398, 0x183AC}, 425 {0x183BC, 0x183D8}, 426 {0x183DC, 0x183F4}, 427 {0x18400, 0x186F4}, 428 {0x186F8, 0x1871C}, 429 {0x18720, 0x18790}, 430 {0x19800, 0x19830}, 431 {0x19834, 0x19840}, 432 {0x19880, 0x1989C}, 433 {0x198A4, 0x198B0}, 434 {0x198BC, 0x19900}, 435 {0x19C00, 0x19C88}, 436 {0x19D00, 0x19D20}, 437 {0x19E00, 0x19E7C}, 438 {0x19E80, 0x19E94}, 439 {0x19E98, 0x19EAC}, 440 {0x19EB0, 0x19EBC}, 441 {0x19F70, 0x19F74}, 442 {0x19F80, 0x19F8C}, 443 {0x19FA0, 0x19FB4}, 444 {0x19FC0, 0x19FD8}, 445 {0x1A000, 0x1A200}, 446 {0x1A204, 0x1A210}, 447 {0x1A228, 0x1A22C}, 448 {0x1A230, 0x1A248}, 449 {0x1A250, 0x1A270}, 450 {0x1A280, 0x1A290}, 451 {0x1A2A0, 0x1A2A4}, 452 {0x1A2C0, 0x1A2EC}, 453 {0x1A300, 0x1A3BC}, 454 {0x1A3F0, 0x1A3F4}, 455 {0x1A3F8, 0x1A434}, 456 {0x1A438, 0x1A444}, 457 {0x1A448, 0x1A468}, 458 {0x1A580, 0x1A58C}, 459 {0x1A644, 0x1A654}, 460 {0x1A670, 0x1A698}, 461 {0x1A6AC, 0x1A6B0}, 462 {0x1A6D0, 0x1A6D4}, 463 {0x1A6EC, 0x1A70C}, 464 {0x1A710, 0x1A738}, 465 {0x1A7C0, 0x1A7D0}, 466 {0x1A7D4, 0x1A7D8}, 467 {0x1A7DC, 0x1A7E4}, 468 {0x1A7F0, 0x1A7F8}, 469 {0x1A888, 0x1A89C}, 470 {0x1A8A8, 0x1A8AC}, 471 {0x1A8C0, 0x1A8DC}, 472 {0x1A8F0, 0x1A8FC}, 473 {0x1AE04, 0x1AE08}, 474 {0x1AE18, 0x1AE24}, 475 {0x1AF80, 0x1AF8C}, 476 {0x1AFA0, 0x1AFB4}, 477 {0x1B000, 0x1B200}, 478 {0x1B284, 0x1B288}, 479 {0x1B2D0, 0x1B2D8}, 480 {0x1B2DC, 0x1B2EC}, 481 {0x1B300, 0x1B340}, 482 {0x1B374, 0x1B378}, 483 {0x1B380, 0x1B384}, 484 {0x1B388, 0x1B38C}, 485 {0x1B404, 0x1B408}, 486 {0x1B420, 0x1B428}, 487 {0x1B440, 0x1B444}, 488 {0x1B448, 0x1B44C}, 489 {0x1B450, 0x1B458}, 490 {0x1B45C, 0x1B468}, 491 {0x1B584, 0x1B58C}, 492 {0x1B68C, 0x1B690}, 493 {0x1B6AC, 0x1B6B0}, 494 {0x1B7F0, 0x1B7F8}, 495 {0x1C800, 0x1CC00}, 496 {0x1CE00, 0x1CE04}, 497 {0x1CF80, 0x1CF84}, 498 {0x1D200, 0x1D800}, 499 {0x1E000, 0x20014}, 500 {0x20100, 0x20124}, 501 {0x21400, 0x217A8}, 502 {0x21800, 0x21BA8}, 503 {0x21C00, 0x21FA8}, 504 {0x22000, 0x223A8}, 505 {0x22400, 0x227A8}, 506 {0x22800, 0x22BA8}, 507 {0x22C00, 0x22FA8}, 508 {0x23000, 0x233A8}, 509 {0x24000, 0x24034}, 510 {0x26000, 0x26064}, 511 {0x27000, 0x27024}, 512 {0x34000, 0x3400C}, 513 {0x34400, 0x3445C}, 514 {0x34800, 0x3485C}, 515 {0x34C00, 0x34C5C}, 516 {0x35000, 0x3505C}, 517 {0x35400, 0x3545C}, 518 {0x35800, 0x3585C}, 519 {0x35C00, 0x35C5C}, 520 {0x36000, 0x3605C}, 521 {0x38000, 0x38064}, 522 {0x38070, 0x380E0}, 523 {0x3A000, 0x3A074}, 524 {0x40000, 0x400A4}, 525 {0x80000, 0x8000C}, 526 {0x80010, 0x80020}, 527 }; 528 529 static const struct ath10k_mem_region qca6174_hw10_mem_regions[] = { 530 { 531 .type = ATH10K_MEM_REGION_TYPE_DRAM, 532 .start = 0x400000, 533 .len = 0x70000, 534 .name = "DRAM", 535 .section_table = { 536 .sections = NULL, 537 .size = 0, 538 }, 539 }, 540 { 541 .type = ATH10K_MEM_REGION_TYPE_REG, 542 543 /* RTC_SOC_BASE_ADDRESS */ 544 .start = 0x0, 545 546 /* WLAN_MBOX_BASE_ADDRESS - RTC_SOC_BASE_ADDRESS */ 547 .len = 0x800 - 0x0, 548 549 .name = "REG_PART1", 550 .section_table = { 551 .sections = NULL, 552 .size = 0, 553 }, 554 }, 555 { 556 .type = ATH10K_MEM_REGION_TYPE_REG, 557 558 /* STEREO_BASE_ADDRESS */ 559 .start = 0x27000, 560 561 /* USB_BASE_ADDRESS - STEREO_BASE_ADDRESS */ 562 .len = 0x60000 - 0x27000, 563 564 .name = "REG_PART2", 565 .section_table = { 566 .sections = NULL, 567 .size = 0, 568 }, 569 }, 570 }; 571 572 static const struct ath10k_mem_region qca6174_hw21_mem_regions[] = { 573 { 574 .type = ATH10K_MEM_REGION_TYPE_DRAM, 575 .start = 0x400000, 576 .len = 0x70000, 577 .name = "DRAM", 578 .section_table = { 579 .sections = NULL, 580 .size = 0, 581 }, 582 }, 583 { 584 .type = ATH10K_MEM_REGION_TYPE_AXI, 585 .start = 0xa0000, 586 .len = 0x18000, 587 .name = "AXI", 588 .section_table = { 589 .sections = NULL, 590 .size = 0, 591 }, 592 }, 593 { 594 .type = ATH10K_MEM_REGION_TYPE_REG, 595 .start = 0x800, 596 .len = 0x80020 - 0x800, 597 .name = "REG_TOTAL", 598 .section_table = { 599 .sections = qca6174_hw21_register_sections, 600 .size = ARRAY_SIZE(qca6174_hw21_register_sections), 601 }, 602 }, 603 }; 604 605 static const struct ath10k_mem_region qca6174_hw30_mem_regions[] = { 606 { 607 .type = ATH10K_MEM_REGION_TYPE_DRAM, 608 .start = 0x400000, 609 .len = 0xa8000, 610 .name = "DRAM", 611 .section_table = { 612 .sections = NULL, 613 .size = 0, 614 }, 615 }, 616 { 617 .type = ATH10K_MEM_REGION_TYPE_AXI, 618 .start = 0xa0000, 619 .len = 0x18000, 620 .name = "AXI", 621 .section_table = { 622 .sections = NULL, 623 .size = 0, 624 }, 625 }, 626 { 627 .type = ATH10K_MEM_REGION_TYPE_REG, 628 .start = 0x800, 629 .len = 0x80020 - 0x800, 630 .name = "REG_TOTAL", 631 .section_table = { 632 .sections = qca6174_hw30_register_sections, 633 .size = ARRAY_SIZE(qca6174_hw30_register_sections), 634 }, 635 }, 636 637 /* IRAM dump must be put last */ 638 { 639 .type = ATH10K_MEM_REGION_TYPE_IRAM1, 640 .start = 0x00980000, 641 .len = 0x00080000, 642 .name = "IRAM1", 643 .section_table = { 644 .sections = NULL, 645 .size = 0, 646 }, 647 }, 648 { 649 .type = ATH10K_MEM_REGION_TYPE_IRAM2, 650 .start = 0x00a00000, 651 .len = 0x00040000, 652 .name = "IRAM2", 653 .section_table = { 654 .sections = NULL, 655 .size = 0, 656 }, 657 }, 658 }; 659 660 static const struct ath10k_mem_region qca988x_hw20_mem_regions[] = { 661 { 662 .type = ATH10K_MEM_REGION_TYPE_DRAM, 663 .start = 0x400000, 664 .len = 0x50000, 665 .name = "DRAM", 666 .section_table = { 667 .sections = NULL, 668 .size = 0, 669 }, 670 }, 671 { 672 .type = ATH10K_MEM_REGION_TYPE_REG, 673 .start = 0x4000, 674 .len = 0x2000, 675 .name = "REG_PART1", 676 .section_table = { 677 .sections = NULL, 678 .size = 0, 679 }, 680 }, 681 { 682 .type = ATH10K_MEM_REGION_TYPE_REG, 683 .start = 0x8000, 684 .len = 0x58000, 685 .name = "REG_PART2", 686 .section_table = { 687 .sections = NULL, 688 .size = 0, 689 }, 690 }, 691 }; 692 693 static const struct ath10k_mem_region qca99x0_hw20_mem_regions[] = { 694 { 695 .type = ATH10K_MEM_REGION_TYPE_DRAM, 696 .start = 0x400000, 697 .len = 0x60000, 698 .name = "DRAM", 699 .section_table = { 700 .sections = NULL, 701 .size = 0, 702 }, 703 }, 704 { 705 .type = ATH10K_MEM_REGION_TYPE_REG, 706 .start = 0x980000, 707 .len = 0x50000, 708 .name = "IRAM", 709 .section_table = { 710 .sections = NULL, 711 .size = 0, 712 }, 713 }, 714 { 715 .type = ATH10K_MEM_REGION_TYPE_IOSRAM, 716 .start = 0xC0000, 717 .len = 0x40000, 718 .name = "SRAM", 719 .section_table = { 720 .sections = NULL, 721 .size = 0, 722 }, 723 }, 724 { 725 .type = ATH10K_MEM_REGION_TYPE_IOREG, 726 .start = 0x30000, 727 .len = 0x7000, 728 .name = "APB REG 1", 729 .section_table = { 730 .sections = NULL, 731 .size = 0, 732 }, 733 }, 734 { 735 .type = ATH10K_MEM_REGION_TYPE_IOREG, 736 .start = 0x3f000, 737 .len = 0x3000, 738 .name = "APB REG 2", 739 .section_table = { 740 .sections = NULL, 741 .size = 0, 742 }, 743 }, 744 { 745 .type = ATH10K_MEM_REGION_TYPE_IOREG, 746 .start = 0x43000, 747 .len = 0x3000, 748 .name = "WIFI REG", 749 .section_table = { 750 .sections = NULL, 751 .size = 0, 752 }, 753 }, 754 { 755 .type = ATH10K_MEM_REGION_TYPE_IOREG, 756 .start = 0x4A000, 757 .len = 0x5000, 758 .name = "CE REG", 759 .section_table = { 760 .sections = NULL, 761 .size = 0, 762 }, 763 }, 764 { 765 .type = ATH10K_MEM_REGION_TYPE_IOREG, 766 .start = 0x80000, 767 .len = 0x6000, 768 .name = "SOC REG", 769 .section_table = { 770 .sections = NULL, 771 .size = 0, 772 }, 773 }, 774 }; 775 776 static const struct ath10k_mem_region qca9984_hw10_mem_regions[] = { 777 { 778 .type = ATH10K_MEM_REGION_TYPE_DRAM, 779 .start = 0x400000, 780 .len = 0x80000, 781 .name = "DRAM", 782 .section_table = { 783 .sections = NULL, 784 .size = 0, 785 }, 786 }, 787 { 788 .type = ATH10K_MEM_REGION_TYPE_REG, 789 .start = 0x980000, 790 .len = 0x50000, 791 .name = "IRAM", 792 .section_table = { 793 .sections = NULL, 794 .size = 0, 795 }, 796 }, 797 { 798 .type = ATH10K_MEM_REGION_TYPE_IOSRAM, 799 .start = 0xC0000, 800 .len = 0x40000, 801 .name = "SRAM", 802 .section_table = { 803 .sections = NULL, 804 .size = 0, 805 }, 806 }, 807 { 808 .type = ATH10K_MEM_REGION_TYPE_IOREG, 809 .start = 0x30000, 810 .len = 0x7000, 811 .name = "APB REG 1", 812 .section_table = { 813 .sections = NULL, 814 .size = 0, 815 }, 816 }, 817 { 818 .type = ATH10K_MEM_REGION_TYPE_IOREG, 819 .start = 0x3f000, 820 .len = 0x3000, 821 .name = "APB REG 2", 822 .section_table = { 823 .sections = NULL, 824 .size = 0, 825 }, 826 }, 827 { 828 .type = ATH10K_MEM_REGION_TYPE_IOREG, 829 .start = 0x43000, 830 .len = 0x3000, 831 .name = "WIFI REG", 832 .section_table = { 833 .sections = NULL, 834 .size = 0, 835 }, 836 }, 837 { 838 .type = ATH10K_MEM_REGION_TYPE_IOREG, 839 .start = 0x4A000, 840 .len = 0x5000, 841 .name = "CE REG", 842 .section_table = { 843 .sections = NULL, 844 .size = 0, 845 }, 846 }, 847 { 848 .type = ATH10K_MEM_REGION_TYPE_IOREG, 849 .start = 0x80000, 850 .len = 0x6000, 851 .name = "SOC REG", 852 .section_table = { 853 .sections = NULL, 854 .size = 0, 855 }, 856 }, 857 }; 858 859 static const struct ath10k_mem_section ipq4019_soc_reg_range[] = { 860 {0x080000, 0x080004}, 861 {0x080020, 0x080024}, 862 {0x080028, 0x080050}, 863 {0x0800d4, 0x0800ec}, 864 {0x08010c, 0x080118}, 865 {0x080284, 0x080290}, 866 {0x0802a8, 0x0802b8}, 867 {0x0802dc, 0x08030c}, 868 {0x082000, 0x083fff} 869 }; 870 871 static const struct ath10k_mem_region qca4019_hw10_mem_regions[] = { 872 { 873 .type = ATH10K_MEM_REGION_TYPE_DRAM, 874 .start = 0x400000, 875 .len = 0x68000, 876 .name = "DRAM", 877 .section_table = { 878 .sections = NULL, 879 .size = 0, 880 }, 881 }, 882 { 883 .type = ATH10K_MEM_REGION_TYPE_REG, 884 .start = 0xC0000, 885 .len = 0x40000, 886 .name = "SRAM", 887 .section_table = { 888 .sections = NULL, 889 .size = 0, 890 }, 891 }, 892 { 893 .type = ATH10K_MEM_REGION_TYPE_REG, 894 .start = 0x980000, 895 .len = 0x50000, 896 .name = "IRAM", 897 .section_table = { 898 .sections = NULL, 899 .size = 0, 900 }, 901 }, 902 { 903 .type = ATH10K_MEM_REGION_TYPE_IOREG, 904 .start = 0x30000, 905 .len = 0x7000, 906 .name = "APB REG 1", 907 .section_table = { 908 .sections = NULL, 909 .size = 0, 910 }, 911 }, 912 { 913 .type = ATH10K_MEM_REGION_TYPE_IOREG, 914 .start = 0x3f000, 915 .len = 0x3000, 916 .name = "APB REG 2", 917 .section_table = { 918 .sections = NULL, 919 .size = 0, 920 }, 921 }, 922 { 923 .type = ATH10K_MEM_REGION_TYPE_IOREG, 924 .start = 0x43000, 925 .len = 0x3000, 926 .name = "WIFI REG", 927 .section_table = { 928 .sections = NULL, 929 .size = 0, 930 }, 931 }, 932 { 933 .type = ATH10K_MEM_REGION_TYPE_IOREG, 934 .start = 0x4A000, 935 .len = 0x5000, 936 .name = "CE REG", 937 .section_table = { 938 .sections = NULL, 939 .size = 0, 940 }, 941 }, 942 { 943 .type = ATH10K_MEM_REGION_TYPE_REG, 944 .start = 0x080000, 945 .len = 0x083fff - 0x080000, 946 .name = "REG_TOTAL", 947 .section_table = { 948 .sections = ipq4019_soc_reg_range, 949 .size = ARRAY_SIZE(ipq4019_soc_reg_range), 950 }, 951 }, 952 }; 953 954 static const struct ath10k_mem_region wcn399x_hw10_mem_regions[] = { 955 { 956 /* MSA region start is not fixed, hence it is assigned at runtime */ 957 .type = ATH10K_MEM_REGION_TYPE_MSA, 958 .len = 0x100000, 959 .name = "DRAM", 960 .section_table = { 961 .sections = NULL, 962 .size = 0, 963 }, 964 }, 965 }; 966 967 static const struct ath10k_hw_mem_layout hw_mem_layouts[] = { 968 { 969 .hw_id = QCA6174_HW_1_0_VERSION, 970 .hw_rev = ATH10K_HW_QCA6174, 971 .region_table = { 972 .regions = qca6174_hw10_mem_regions, 973 .size = ARRAY_SIZE(qca6174_hw10_mem_regions), 974 }, 975 }, 976 { 977 .hw_id = QCA6174_HW_1_1_VERSION, 978 .hw_rev = ATH10K_HW_QCA6174, 979 .region_table = { 980 .regions = qca6174_hw10_mem_regions, 981 .size = ARRAY_SIZE(qca6174_hw10_mem_regions), 982 }, 983 }, 984 { 985 .hw_id = QCA6174_HW_1_3_VERSION, 986 .hw_rev = ATH10K_HW_QCA6174, 987 .region_table = { 988 .regions = qca6174_hw10_mem_regions, 989 .size = ARRAY_SIZE(qca6174_hw10_mem_regions), 990 }, 991 }, 992 { 993 .hw_id = QCA6174_HW_2_1_VERSION, 994 .hw_rev = ATH10K_HW_QCA6174, 995 .region_table = { 996 .regions = qca6174_hw21_mem_regions, 997 .size = ARRAY_SIZE(qca6174_hw21_mem_regions), 998 }, 999 }, 1000 { 1001 .hw_id = QCA6174_HW_3_0_VERSION, 1002 .hw_rev = ATH10K_HW_QCA6174, 1003 .region_table = { 1004 .regions = qca6174_hw30_mem_regions, 1005 .size = ARRAY_SIZE(qca6174_hw30_mem_regions), 1006 }, 1007 }, 1008 { 1009 .hw_id = QCA6174_HW_3_2_VERSION, 1010 .hw_rev = ATH10K_HW_QCA6174, 1011 .region_table = { 1012 .regions = qca6174_hw30_mem_regions, 1013 .size = ARRAY_SIZE(qca6174_hw30_mem_regions), 1014 }, 1015 }, 1016 { 1017 .hw_id = QCA9377_HW_1_1_DEV_VERSION, 1018 .hw_rev = ATH10K_HW_QCA9377, 1019 .region_table = { 1020 .regions = qca6174_hw30_mem_regions, 1021 .size = ARRAY_SIZE(qca6174_hw30_mem_regions), 1022 }, 1023 }, 1024 { 1025 .hw_id = QCA988X_HW_2_0_VERSION, 1026 .hw_rev = ATH10K_HW_QCA988X, 1027 .region_table = { 1028 .regions = qca988x_hw20_mem_regions, 1029 .size = ARRAY_SIZE(qca988x_hw20_mem_regions), 1030 }, 1031 }, 1032 { 1033 .hw_id = QCA9984_HW_1_0_DEV_VERSION, 1034 .hw_rev = ATH10K_HW_QCA9984, 1035 .region_table = { 1036 .regions = qca9984_hw10_mem_regions, 1037 .size = ARRAY_SIZE(qca9984_hw10_mem_regions), 1038 }, 1039 }, 1040 { 1041 .hw_id = QCA9888_HW_2_0_DEV_VERSION, 1042 .hw_rev = ATH10K_HW_QCA9888, 1043 .region_table = { 1044 .regions = qca9984_hw10_mem_regions, 1045 .size = ARRAY_SIZE(qca9984_hw10_mem_regions), 1046 }, 1047 }, 1048 { 1049 .hw_id = QCA99X0_HW_2_0_DEV_VERSION, 1050 .hw_rev = ATH10K_HW_QCA99X0, 1051 .region_table = { 1052 .regions = qca99x0_hw20_mem_regions, 1053 .size = ARRAY_SIZE(qca99x0_hw20_mem_regions), 1054 }, 1055 }, 1056 { 1057 .hw_id = QCA4019_HW_1_0_DEV_VERSION, 1058 .hw_rev = ATH10K_HW_QCA4019, 1059 .region_table = { 1060 .regions = qca4019_hw10_mem_regions, 1061 .size = ARRAY_SIZE(qca4019_hw10_mem_regions), 1062 }, 1063 }, 1064 { 1065 .hw_id = WCN3990_HW_1_0_DEV_VERSION, 1066 .hw_rev = ATH10K_HW_WCN3990, 1067 .region_table = { 1068 .regions = wcn399x_hw10_mem_regions, 1069 .size = ARRAY_SIZE(wcn399x_hw10_mem_regions), 1070 }, 1071 }, 1072 }; 1073 1074 static u32 ath10k_coredump_get_ramdump_size(struct ath10k *ar) 1075 { 1076 const struct ath10k_hw_mem_layout *hw; 1077 const struct ath10k_mem_region *mem_region; 1078 size_t size = 0; 1079 int i; 1080 1081 hw = ath10k_coredump_get_mem_layout(ar); 1082 1083 if (!hw) 1084 return 0; 1085 1086 mem_region = &hw->region_table.regions[0]; 1087 1088 for (i = 0; i < hw->region_table.size; i++) { 1089 size += mem_region->len; 1090 mem_region++; 1091 } 1092 1093 /* reserve space for the headers */ 1094 size += hw->region_table.size * sizeof(struct ath10k_dump_ram_data_hdr); 1095 1096 /* make sure it is aligned 16 bytes for debug message print out */ 1097 size = ALIGN(size, 16); 1098 1099 return size; 1100 } 1101 1102 const struct ath10k_hw_mem_layout *ath10k_coredump_get_mem_layout(struct ath10k *ar) 1103 { 1104 int i; 1105 1106 if (!test_bit(ATH10K_FW_CRASH_DUMP_RAM_DATA, &ath10k_coredump_mask)) 1107 return NULL; 1108 1109 if (WARN_ON(ar->target_version == 0)) 1110 return NULL; 1111 1112 for (i = 0; i < ARRAY_SIZE(hw_mem_layouts); i++) { 1113 if (ar->target_version == hw_mem_layouts[i].hw_id && 1114 ar->hw_rev == hw_mem_layouts[i].hw_rev) 1115 return &hw_mem_layouts[i]; 1116 } 1117 1118 return NULL; 1119 } 1120 EXPORT_SYMBOL(ath10k_coredump_get_mem_layout); 1121 1122 struct ath10k_fw_crash_data *ath10k_coredump_new(struct ath10k *ar) 1123 { 1124 struct ath10k_fw_crash_data *crash_data = ar->coredump.fw_crash_data; 1125 1126 lockdep_assert_held(&ar->dump_mutex); 1127 1128 if (ath10k_coredump_mask == 0) 1129 /* coredump disabled */ 1130 return NULL; 1131 1132 guid_gen(&crash_data->guid); 1133 ktime_get_real_ts64(&crash_data->timestamp); 1134 1135 return crash_data; 1136 } 1137 EXPORT_SYMBOL(ath10k_coredump_new); 1138 1139 static struct ath10k_dump_file_data *ath10k_coredump_build(struct ath10k *ar) 1140 { 1141 struct ath10k_fw_crash_data *crash_data = ar->coredump.fw_crash_data; 1142 struct ath10k_ce_crash_hdr *ce_hdr; 1143 struct ath10k_dump_file_data *dump_data; 1144 struct ath10k_tlv_dump_data *dump_tlv; 1145 size_t hdr_len = sizeof(*dump_data); 1146 size_t len, sofar = 0; 1147 unsigned char *buf; 1148 1149 len = hdr_len; 1150 1151 if (test_bit(ATH10K_FW_CRASH_DUMP_REGISTERS, &ath10k_coredump_mask)) 1152 len += sizeof(*dump_tlv) + sizeof(crash_data->registers); 1153 1154 if (test_bit(ATH10K_FW_CRASH_DUMP_CE_DATA, &ath10k_coredump_mask)) 1155 len += sizeof(*dump_tlv) + sizeof(*ce_hdr) + 1156 CE_COUNT * sizeof(ce_hdr->entries[0]); 1157 1158 if (test_bit(ATH10K_FW_CRASH_DUMP_RAM_DATA, &ath10k_coredump_mask)) 1159 len += sizeof(*dump_tlv) + crash_data->ramdump_buf_len; 1160 1161 sofar += hdr_len; 1162 1163 /* This is going to get big when we start dumping FW RAM and such, 1164 * so go ahead and use vmalloc. 1165 */ 1166 buf = vzalloc(len); 1167 if (!buf) 1168 return NULL; 1169 1170 mutex_lock(&ar->dump_mutex); 1171 1172 dump_data = (struct ath10k_dump_file_data *)(buf); 1173 strlcpy(dump_data->df_magic, "ATH10K-FW-DUMP", 1174 sizeof(dump_data->df_magic)); 1175 dump_data->len = cpu_to_le32(len); 1176 1177 dump_data->version = cpu_to_le32(ATH10K_FW_CRASH_DUMP_VERSION); 1178 1179 guid_copy(&dump_data->guid, &crash_data->guid); 1180 dump_data->chip_id = cpu_to_le32(ar->bus_param.chip_id); 1181 dump_data->bus_type = cpu_to_le32(0); 1182 dump_data->target_version = cpu_to_le32(ar->target_version); 1183 dump_data->fw_version_major = cpu_to_le32(ar->fw_version_major); 1184 dump_data->fw_version_minor = cpu_to_le32(ar->fw_version_minor); 1185 dump_data->fw_version_release = cpu_to_le32(ar->fw_version_release); 1186 dump_data->fw_version_build = cpu_to_le32(ar->fw_version_build); 1187 dump_data->phy_capability = cpu_to_le32(ar->phy_capability); 1188 dump_data->hw_min_tx_power = cpu_to_le32(ar->hw_min_tx_power); 1189 dump_data->hw_max_tx_power = cpu_to_le32(ar->hw_max_tx_power); 1190 dump_data->ht_cap_info = cpu_to_le32(ar->ht_cap_info); 1191 dump_data->vht_cap_info = cpu_to_le32(ar->vht_cap_info); 1192 dump_data->num_rf_chains = cpu_to_le32(ar->num_rf_chains); 1193 1194 strlcpy(dump_data->fw_ver, ar->hw->wiphy->fw_version, 1195 sizeof(dump_data->fw_ver)); 1196 1197 dump_data->kernel_ver_code = 0; 1198 strlcpy(dump_data->kernel_ver, init_utsname()->release, 1199 sizeof(dump_data->kernel_ver)); 1200 1201 dump_data->tv_sec = cpu_to_le64(crash_data->timestamp.tv_sec); 1202 dump_data->tv_nsec = cpu_to_le64(crash_data->timestamp.tv_nsec); 1203 1204 if (test_bit(ATH10K_FW_CRASH_DUMP_REGISTERS, &ath10k_coredump_mask)) { 1205 dump_tlv = (struct ath10k_tlv_dump_data *)(buf + sofar); 1206 dump_tlv->type = cpu_to_le32(ATH10K_FW_CRASH_DUMP_REGISTERS); 1207 dump_tlv->tlv_len = cpu_to_le32(sizeof(crash_data->registers)); 1208 memcpy(dump_tlv->tlv_data, &crash_data->registers, 1209 sizeof(crash_data->registers)); 1210 sofar += sizeof(*dump_tlv) + sizeof(crash_data->registers); 1211 } 1212 1213 if (test_bit(ATH10K_FW_CRASH_DUMP_CE_DATA, &ath10k_coredump_mask)) { 1214 dump_tlv = (struct ath10k_tlv_dump_data *)(buf + sofar); 1215 dump_tlv->type = cpu_to_le32(ATH10K_FW_CRASH_DUMP_CE_DATA); 1216 dump_tlv->tlv_len = cpu_to_le32(struct_size(ce_hdr, entries, 1217 CE_COUNT)); 1218 ce_hdr = (struct ath10k_ce_crash_hdr *)(dump_tlv->tlv_data); 1219 ce_hdr->ce_count = cpu_to_le32(CE_COUNT); 1220 memset(ce_hdr->reserved, 0, sizeof(ce_hdr->reserved)); 1221 memcpy(ce_hdr->entries, crash_data->ce_crash_data, 1222 CE_COUNT * sizeof(ce_hdr->entries[0])); 1223 sofar += sizeof(*dump_tlv) + sizeof(*ce_hdr) + 1224 CE_COUNT * sizeof(ce_hdr->entries[0]); 1225 } 1226 1227 /* Gather ram dump */ 1228 if (test_bit(ATH10K_FW_CRASH_DUMP_RAM_DATA, &ath10k_coredump_mask)) { 1229 dump_tlv = (struct ath10k_tlv_dump_data *)(buf + sofar); 1230 dump_tlv->type = cpu_to_le32(ATH10K_FW_CRASH_DUMP_RAM_DATA); 1231 dump_tlv->tlv_len = cpu_to_le32(crash_data->ramdump_buf_len); 1232 if (crash_data->ramdump_buf_len) { 1233 memcpy(dump_tlv->tlv_data, crash_data->ramdump_buf, 1234 crash_data->ramdump_buf_len); 1235 sofar += sizeof(*dump_tlv) + crash_data->ramdump_buf_len; 1236 } 1237 } 1238 1239 mutex_unlock(&ar->dump_mutex); 1240 1241 return dump_data; 1242 } 1243 1244 int ath10k_coredump_submit(struct ath10k *ar) 1245 { 1246 struct ath10k_dump_file_data *dump; 1247 1248 if (ath10k_coredump_mask == 0) 1249 /* coredump disabled */ 1250 return 0; 1251 1252 dump = ath10k_coredump_build(ar); 1253 if (!dump) { 1254 ath10k_warn(ar, "no crash dump data found for devcoredump"); 1255 return -ENODATA; 1256 } 1257 1258 dev_coredumpv(ar->dev, dump, le32_to_cpu(dump->len), GFP_KERNEL); 1259 1260 return 0; 1261 } 1262 1263 int ath10k_coredump_create(struct ath10k *ar) 1264 { 1265 if (ath10k_coredump_mask == 0) 1266 /* coredump disabled */ 1267 return 0; 1268 1269 ar->coredump.fw_crash_data = vzalloc(sizeof(*ar->coredump.fw_crash_data)); 1270 if (!ar->coredump.fw_crash_data) 1271 return -ENOMEM; 1272 1273 return 0; 1274 } 1275 1276 int ath10k_coredump_register(struct ath10k *ar) 1277 { 1278 struct ath10k_fw_crash_data *crash_data = ar->coredump.fw_crash_data; 1279 1280 if (test_bit(ATH10K_FW_CRASH_DUMP_RAM_DATA, &ath10k_coredump_mask)) { 1281 crash_data->ramdump_buf_len = ath10k_coredump_get_ramdump_size(ar); 1282 1283 if (!crash_data->ramdump_buf_len) 1284 return 0; 1285 1286 crash_data->ramdump_buf = vzalloc(crash_data->ramdump_buf_len); 1287 if (!crash_data->ramdump_buf) 1288 return -ENOMEM; 1289 } 1290 1291 return 0; 1292 } 1293 1294 void ath10k_coredump_unregister(struct ath10k *ar) 1295 { 1296 struct ath10k_fw_crash_data *crash_data = ar->coredump.fw_crash_data; 1297 1298 vfree(crash_data->ramdump_buf); 1299 } 1300 1301 void ath10k_coredump_destroy(struct ath10k *ar) 1302 { 1303 if (ar->coredump.fw_crash_data->ramdump_buf) { 1304 vfree(ar->coredump.fw_crash_data->ramdump_buf); 1305 ar->coredump.fw_crash_data->ramdump_buf = NULL; 1306 ar->coredump.fw_crash_data->ramdump_buf_len = 0; 1307 } 1308 1309 vfree(ar->coredump.fw_crash_data); 1310 ar->coredump.fw_crash_data = NULL; 1311 } 1312