1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (c) 2005-2011 Atheros Communications Inc. 4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. 5 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. 6 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. 7 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 8 */ 9 10 #include <linux/export.h> 11 #include <linux/module.h> 12 #include <linux/firmware.h> 13 #include <linux/of.h> 14 #include <linux/property.h> 15 #include <linux/dmi.h> 16 #include <linux/ctype.h> 17 #include <linux/pm_qos.h> 18 #include <linux/nvmem-consumer.h> 19 #include <asm/byteorder.h> 20 21 #include "core.h" 22 #include "mac.h" 23 #include "htc.h" 24 #include "hif.h" 25 #include "wmi.h" 26 #include "bmi.h" 27 #include "debug.h" 28 #include "htt.h" 29 #include "testmode.h" 30 #include "wmi-ops.h" 31 #include "coredump.h" 32 #include "leds.h" 33 34 unsigned int ath10k_debug_mask; 35 EXPORT_SYMBOL(ath10k_debug_mask); 36 37 static unsigned int ath10k_cryptmode_param; 38 static bool uart_print; 39 static bool skip_otp; 40 static bool fw_diag_log; 41 42 /* frame mode values are mapped as per enum ath10k_hw_txrx_mode */ 43 unsigned int ath10k_frame_mode = ATH10K_HW_TXRX_NATIVE_WIFI; 44 45 unsigned long ath10k_coredump_mask = BIT(ATH10K_FW_CRASH_DUMP_REGISTERS) | 46 BIT(ATH10K_FW_CRASH_DUMP_CE_DATA); 47 48 /* FIXME: most of these should be readonly */ 49 module_param_named(debug_mask, ath10k_debug_mask, uint, 0644); 50 module_param_named(cryptmode, ath10k_cryptmode_param, uint, 0644); 51 module_param(uart_print, bool, 0644); 52 module_param(skip_otp, bool, 0644); 53 module_param(fw_diag_log, bool, 0644); 54 module_param_named(frame_mode, ath10k_frame_mode, uint, 0644); 55 module_param_named(coredump_mask, ath10k_coredump_mask, ulong, 0444); 56 57 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 58 MODULE_PARM_DESC(uart_print, "Uart target debugging"); 59 MODULE_PARM_DESC(skip_otp, "Skip otp failure for calibration in testmode"); 60 MODULE_PARM_DESC(cryptmode, "Crypto mode: 0-hardware, 1-software"); 61 MODULE_PARM_DESC(frame_mode, 62 "Datapath frame mode (0: raw, 1: native wifi (default), 2: ethernet)"); 63 MODULE_PARM_DESC(coredump_mask, "Bitfield of what to include in firmware crash file"); 64 MODULE_PARM_DESC(fw_diag_log, "Diag based fw log debugging"); 65 66 static const struct ath10k_hw_params ath10k_hw_params_list[] = { 67 { 68 .id = QCA988X_HW_2_0_VERSION, 69 .dev_id = QCA988X_2_0_DEVICE_ID, 70 .bus = ATH10K_BUS_PCI, 71 .name = "qca988x hw2.0", 72 .patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR, 73 .uart_pin = 7, 74 .led_pin = 1, 75 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL, 76 .otp_exe_param = 0, 77 .channel_counters_freq_hz = 88000, 78 .max_probe_resp_desc_thres = 0, 79 .cal_data_len = 2116, 80 .fw = { 81 .dir = QCA988X_HW_2_0_FW_DIR, 82 .board_size = QCA988X_BOARD_DATA_SZ, 83 .board_ext_size = QCA988X_BOARD_EXT_DATA_SZ, 84 }, 85 .rx_desc_ops = &qca988x_rx_desc_ops, 86 .hw_ops = &qca988x_ops, 87 .decap_align_bytes = 4, 88 .spectral_bin_discard = 0, 89 .spectral_bin_offset = 0, 90 .vht160_mcs_rx_highest = 0, 91 .vht160_mcs_tx_highest = 0, 92 .n_cipher_suites = 8, 93 .ast_skid_limit = 0x10, 94 .num_wds_entries = 0x20, 95 .target_64bit = false, 96 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 97 .shadow_reg_support = false, 98 .rri_on_ddr = false, 99 .hw_filter_reset_required = true, 100 .fw_diag_ce_download = false, 101 .credit_size_workaround = false, 102 .tx_stats_over_pktlog = true, 103 .dynamic_sar_support = false, 104 .hw_restart_disconnect = false, 105 .use_fw_tx_credits = true, 106 .delay_unmap_buffer = false, 107 .mcast_frame_registration = false, 108 }, 109 { 110 .id = QCA988X_HW_2_0_VERSION, 111 .dev_id = QCA988X_2_0_DEVICE_ID_UBNT, 112 .name = "qca988x hw2.0 ubiquiti", 113 .patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR, 114 .uart_pin = 7, 115 .led_pin = 0, 116 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL, 117 .otp_exe_param = 0, 118 .channel_counters_freq_hz = 88000, 119 .max_probe_resp_desc_thres = 0, 120 .cal_data_len = 2116, 121 .fw = { 122 .dir = QCA988X_HW_2_0_FW_DIR, 123 .board_size = QCA988X_BOARD_DATA_SZ, 124 .board_ext_size = QCA988X_BOARD_EXT_DATA_SZ, 125 }, 126 .rx_desc_ops = &qca988x_rx_desc_ops, 127 .hw_ops = &qca988x_ops, 128 .decap_align_bytes = 4, 129 .spectral_bin_discard = 0, 130 .spectral_bin_offset = 0, 131 .vht160_mcs_rx_highest = 0, 132 .vht160_mcs_tx_highest = 0, 133 .n_cipher_suites = 8, 134 .ast_skid_limit = 0x10, 135 .num_wds_entries = 0x20, 136 .target_64bit = false, 137 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 138 .shadow_reg_support = false, 139 .rri_on_ddr = false, 140 .hw_filter_reset_required = true, 141 .fw_diag_ce_download = false, 142 .credit_size_workaround = false, 143 .tx_stats_over_pktlog = true, 144 .dynamic_sar_support = false, 145 .hw_restart_disconnect = false, 146 .use_fw_tx_credits = true, 147 .delay_unmap_buffer = false, 148 .mcast_frame_registration = false, 149 }, 150 { 151 .id = QCA9887_HW_1_0_VERSION, 152 .dev_id = QCA9887_1_0_DEVICE_ID, 153 .bus = ATH10K_BUS_PCI, 154 .name = "qca9887 hw1.0", 155 .patch_load_addr = QCA9887_HW_1_0_PATCH_LOAD_ADDR, 156 .uart_pin = 7, 157 .led_pin = 1, 158 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL, 159 .otp_exe_param = 0, 160 .channel_counters_freq_hz = 88000, 161 .max_probe_resp_desc_thres = 0, 162 .cal_data_len = 2116, 163 .fw = { 164 .dir = QCA9887_HW_1_0_FW_DIR, 165 .board_size = QCA9887_BOARD_DATA_SZ, 166 .board_ext_size = QCA9887_BOARD_EXT_DATA_SZ, 167 }, 168 .rx_desc_ops = &qca988x_rx_desc_ops, 169 .hw_ops = &qca988x_ops, 170 .decap_align_bytes = 4, 171 .spectral_bin_discard = 0, 172 .spectral_bin_offset = 0, 173 .vht160_mcs_rx_highest = 0, 174 .vht160_mcs_tx_highest = 0, 175 .n_cipher_suites = 8, 176 .ast_skid_limit = 0x10, 177 .num_wds_entries = 0x20, 178 .target_64bit = false, 179 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 180 .shadow_reg_support = false, 181 .rri_on_ddr = false, 182 .hw_filter_reset_required = true, 183 .fw_diag_ce_download = false, 184 .credit_size_workaround = false, 185 .tx_stats_over_pktlog = false, 186 .dynamic_sar_support = false, 187 .hw_restart_disconnect = false, 188 .use_fw_tx_credits = true, 189 .delay_unmap_buffer = false, 190 .mcast_frame_registration = false, 191 }, 192 { 193 .id = QCA6174_HW_3_2_VERSION, 194 .dev_id = QCA6174_3_2_DEVICE_ID, 195 .bus = ATH10K_BUS_SDIO, 196 .name = "qca6174 hw3.2 sdio", 197 .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR, 198 .uart_pin = 19, 199 .led_pin = 0, 200 .otp_exe_param = 0, 201 .channel_counters_freq_hz = 88000, 202 .max_probe_resp_desc_thres = 0, 203 .cal_data_len = 0, 204 .fw = { 205 .dir = QCA6174_HW_3_0_FW_DIR, 206 .board_size = QCA6174_BOARD_DATA_SZ, 207 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, 208 }, 209 .rx_desc_ops = &qca988x_rx_desc_ops, 210 .hw_ops = &qca6174_sdio_ops, 211 .hw_clk = qca6174_clk, 212 .target_cpu_freq = 176000000, 213 .decap_align_bytes = 4, 214 .n_cipher_suites = 8, 215 .num_peers = 10, 216 .ast_skid_limit = 0x10, 217 .num_wds_entries = 0x20, 218 .uart_pin_workaround = true, 219 .tx_stats_over_pktlog = false, 220 .credit_size_workaround = false, 221 .bmi_large_size_download = true, 222 .supports_peer_stats_info = true, 223 .dynamic_sar_support = true, 224 .hw_restart_disconnect = false, 225 .use_fw_tx_credits = true, 226 .delay_unmap_buffer = false, 227 .mcast_frame_registration = false, 228 }, 229 { 230 .id = QCA6174_HW_2_1_VERSION, 231 .dev_id = QCA6164_2_1_DEVICE_ID, 232 .bus = ATH10K_BUS_PCI, 233 .name = "qca6164 hw2.1", 234 .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR, 235 .uart_pin = 6, 236 .led_pin = 0, 237 .otp_exe_param = 0, 238 .channel_counters_freq_hz = 88000, 239 .max_probe_resp_desc_thres = 0, 240 .cal_data_len = 8124, 241 .fw = { 242 .dir = QCA6174_HW_2_1_FW_DIR, 243 .board_size = QCA6174_BOARD_DATA_SZ, 244 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, 245 }, 246 .rx_desc_ops = &qca988x_rx_desc_ops, 247 .hw_ops = &qca988x_ops, 248 .decap_align_bytes = 4, 249 .spectral_bin_discard = 0, 250 .spectral_bin_offset = 0, 251 .vht160_mcs_rx_highest = 0, 252 .vht160_mcs_tx_highest = 0, 253 .n_cipher_suites = 8, 254 .ast_skid_limit = 0x10, 255 .num_wds_entries = 0x20, 256 .target_64bit = false, 257 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 258 .shadow_reg_support = false, 259 .rri_on_ddr = false, 260 .hw_filter_reset_required = true, 261 .fw_diag_ce_download = false, 262 .credit_size_workaround = false, 263 .tx_stats_over_pktlog = false, 264 .dynamic_sar_support = false, 265 .hw_restart_disconnect = false, 266 .use_fw_tx_credits = true, 267 .delay_unmap_buffer = false, 268 .mcast_frame_registration = false, 269 }, 270 { 271 .id = QCA6174_HW_2_1_VERSION, 272 .dev_id = QCA6174_2_1_DEVICE_ID, 273 .bus = ATH10K_BUS_PCI, 274 .name = "qca6174 hw2.1", 275 .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR, 276 .uart_pin = 6, 277 .led_pin = 0, 278 .otp_exe_param = 0, 279 .channel_counters_freq_hz = 88000, 280 .max_probe_resp_desc_thres = 0, 281 .cal_data_len = 8124, 282 .fw = { 283 .dir = QCA6174_HW_2_1_FW_DIR, 284 .board_size = QCA6174_BOARD_DATA_SZ, 285 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, 286 }, 287 .rx_desc_ops = &qca988x_rx_desc_ops, 288 .hw_ops = &qca988x_ops, 289 .decap_align_bytes = 4, 290 .spectral_bin_discard = 0, 291 .spectral_bin_offset = 0, 292 .vht160_mcs_rx_highest = 0, 293 .vht160_mcs_tx_highest = 0, 294 .n_cipher_suites = 8, 295 .ast_skid_limit = 0x10, 296 .num_wds_entries = 0x20, 297 .target_64bit = false, 298 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 299 .shadow_reg_support = false, 300 .rri_on_ddr = false, 301 .hw_filter_reset_required = true, 302 .fw_diag_ce_download = false, 303 .credit_size_workaround = false, 304 .tx_stats_over_pktlog = false, 305 .dynamic_sar_support = false, 306 .hw_restart_disconnect = false, 307 .use_fw_tx_credits = true, 308 .delay_unmap_buffer = false, 309 .mcast_frame_registration = false, 310 }, 311 { 312 .id = QCA6174_HW_3_0_VERSION, 313 .dev_id = QCA6174_2_1_DEVICE_ID, 314 .bus = ATH10K_BUS_PCI, 315 .name = "qca6174 hw3.0", 316 .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR, 317 .uart_pin = 6, 318 .led_pin = 0, 319 .otp_exe_param = 0, 320 .channel_counters_freq_hz = 88000, 321 .max_probe_resp_desc_thres = 0, 322 .cal_data_len = 8124, 323 .fw = { 324 .dir = QCA6174_HW_3_0_FW_DIR, 325 .board_size = QCA6174_BOARD_DATA_SZ, 326 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, 327 }, 328 .rx_desc_ops = &qca988x_rx_desc_ops, 329 .hw_ops = &qca988x_ops, 330 .decap_align_bytes = 4, 331 .spectral_bin_discard = 0, 332 .spectral_bin_offset = 0, 333 .vht160_mcs_rx_highest = 0, 334 .vht160_mcs_tx_highest = 0, 335 .n_cipher_suites = 8, 336 .ast_skid_limit = 0x10, 337 .num_wds_entries = 0x20, 338 .target_64bit = false, 339 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 340 .shadow_reg_support = false, 341 .rri_on_ddr = false, 342 .hw_filter_reset_required = true, 343 .fw_diag_ce_download = false, 344 .credit_size_workaround = false, 345 .tx_stats_over_pktlog = false, 346 .dynamic_sar_support = false, 347 .hw_restart_disconnect = false, 348 .use_fw_tx_credits = true, 349 .delay_unmap_buffer = false, 350 .mcast_frame_registration = false, 351 }, 352 { 353 .id = QCA6174_HW_3_2_VERSION, 354 .dev_id = QCA6174_2_1_DEVICE_ID, 355 .bus = ATH10K_BUS_PCI, 356 .name = "qca6174 hw3.2", 357 .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR, 358 .uart_pin = 6, 359 .led_pin = 0, 360 .otp_exe_param = 0, 361 .channel_counters_freq_hz = 88000, 362 .max_probe_resp_desc_thres = 0, 363 .cal_data_len = 8124, 364 .fw = { 365 /* uses same binaries as hw3.0 */ 366 .dir = QCA6174_HW_3_0_FW_DIR, 367 .board_size = QCA6174_BOARD_DATA_SZ, 368 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, 369 }, 370 .rx_desc_ops = &qca988x_rx_desc_ops, 371 .hw_ops = &qca6174_ops, 372 .hw_clk = qca6174_clk, 373 .target_cpu_freq = 176000000, 374 .decap_align_bytes = 4, 375 .spectral_bin_discard = 0, 376 .spectral_bin_offset = 0, 377 .vht160_mcs_rx_highest = 0, 378 .vht160_mcs_tx_highest = 0, 379 .n_cipher_suites = 8, 380 .ast_skid_limit = 0x10, 381 .num_wds_entries = 0x20, 382 .target_64bit = false, 383 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 384 .shadow_reg_support = false, 385 .rri_on_ddr = false, 386 .hw_filter_reset_required = true, 387 .fw_diag_ce_download = true, 388 .credit_size_workaround = false, 389 .tx_stats_over_pktlog = false, 390 .supports_peer_stats_info = true, 391 .dynamic_sar_support = true, 392 .hw_restart_disconnect = false, 393 .use_fw_tx_credits = true, 394 .delay_unmap_buffer = false, 395 .mcast_frame_registration = true, 396 }, 397 { 398 .id = QCA99X0_HW_2_0_DEV_VERSION, 399 .dev_id = QCA99X0_2_0_DEVICE_ID, 400 .bus = ATH10K_BUS_PCI, 401 .name = "qca99x0 hw2.0", 402 .patch_load_addr = QCA99X0_HW_2_0_PATCH_LOAD_ADDR, 403 .uart_pin = 7, 404 .led_pin = 17, 405 .otp_exe_param = 0x00000700, 406 .continuous_frag_desc = true, 407 .cck_rate_map_rev2 = true, 408 .channel_counters_freq_hz = 150000, 409 .max_probe_resp_desc_thres = 24, 410 .tx_chain_mask = 0xf, 411 .rx_chain_mask = 0xf, 412 .max_spatial_stream = 4, 413 .cal_data_len = 12064, 414 .fw = { 415 .dir = QCA99X0_HW_2_0_FW_DIR, 416 .board_size = QCA99X0_BOARD_DATA_SZ, 417 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ, 418 }, 419 .sw_decrypt_mcast_mgmt = true, 420 .rx_desc_ops = &qca99x0_rx_desc_ops, 421 .hw_ops = &qca99x0_ops, 422 .decap_align_bytes = 1, 423 .spectral_bin_discard = 4, 424 .spectral_bin_offset = 0, 425 .vht160_mcs_rx_highest = 0, 426 .vht160_mcs_tx_highest = 0, 427 .n_cipher_suites = 11, 428 .ast_skid_limit = 0x10, 429 .num_wds_entries = 0x20, 430 .target_64bit = false, 431 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 432 .shadow_reg_support = false, 433 .rri_on_ddr = false, 434 .hw_filter_reset_required = true, 435 .fw_diag_ce_download = false, 436 .credit_size_workaround = false, 437 .tx_stats_over_pktlog = false, 438 .dynamic_sar_support = false, 439 .hw_restart_disconnect = false, 440 .use_fw_tx_credits = true, 441 .delay_unmap_buffer = false, 442 .mcast_frame_registration = false, 443 }, 444 { 445 .id = QCA9984_HW_1_0_DEV_VERSION, 446 .dev_id = QCA9984_1_0_DEVICE_ID, 447 .bus = ATH10K_BUS_PCI, 448 .name = "qca9984/qca9994 hw1.0", 449 .patch_load_addr = QCA9984_HW_1_0_PATCH_LOAD_ADDR, 450 .uart_pin = 7, 451 .led_pin = 17, 452 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH, 453 .otp_exe_param = 0x00000700, 454 .continuous_frag_desc = true, 455 .cck_rate_map_rev2 = true, 456 .channel_counters_freq_hz = 150000, 457 .max_probe_resp_desc_thres = 24, 458 .tx_chain_mask = 0xf, 459 .rx_chain_mask = 0xf, 460 .max_spatial_stream = 4, 461 .cal_data_len = 12064, 462 .fw = { 463 .dir = QCA9984_HW_1_0_FW_DIR, 464 .board_size = QCA99X0_BOARD_DATA_SZ, 465 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ, 466 .ext_board_size = QCA99X0_EXT_BOARD_DATA_SZ, 467 }, 468 .sw_decrypt_mcast_mgmt = true, 469 .rx_desc_ops = &qca99x0_rx_desc_ops, 470 .hw_ops = &qca99x0_ops, 471 .decap_align_bytes = 1, 472 .spectral_bin_discard = 12, 473 .spectral_bin_offset = 8, 474 475 /* Can do only 2x2 VHT160 or 80+80. 1560Mbps is 4x4 80Mhz 476 * or 2x2 160Mhz, long-guard-interval. 477 */ 478 .vht160_mcs_rx_highest = 1560, 479 .vht160_mcs_tx_highest = 1560, 480 .n_cipher_suites = 11, 481 .ast_skid_limit = 0x10, 482 .num_wds_entries = 0x20, 483 .target_64bit = false, 484 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 485 .shadow_reg_support = false, 486 .rri_on_ddr = false, 487 .hw_filter_reset_required = true, 488 .fw_diag_ce_download = false, 489 .credit_size_workaround = false, 490 .tx_stats_over_pktlog = false, 491 .dynamic_sar_support = false, 492 .hw_restart_disconnect = false, 493 .use_fw_tx_credits = true, 494 .delay_unmap_buffer = false, 495 .mcast_frame_registration = false, 496 }, 497 { 498 .id = QCA9888_HW_2_0_DEV_VERSION, 499 .dev_id = QCA9888_2_0_DEVICE_ID, 500 .bus = ATH10K_BUS_PCI, 501 .name = "qca9888 hw2.0", 502 .patch_load_addr = QCA9888_HW_2_0_PATCH_LOAD_ADDR, 503 .uart_pin = 7, 504 .led_pin = 17, 505 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH, 506 .otp_exe_param = 0x00000700, 507 .continuous_frag_desc = true, 508 .channel_counters_freq_hz = 150000, 509 .max_probe_resp_desc_thres = 24, 510 .tx_chain_mask = 3, 511 .rx_chain_mask = 3, 512 .max_spatial_stream = 2, 513 .cal_data_len = 12064, 514 .fw = { 515 .dir = QCA9888_HW_2_0_FW_DIR, 516 .board_size = QCA99X0_BOARD_DATA_SZ, 517 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ, 518 }, 519 .sw_decrypt_mcast_mgmt = true, 520 .rx_desc_ops = &qca99x0_rx_desc_ops, 521 .hw_ops = &qca99x0_ops, 522 .decap_align_bytes = 1, 523 .spectral_bin_discard = 12, 524 .spectral_bin_offset = 8, 525 526 /* Can do only 1x1 VHT160 or 80+80. 780Mbps is 2x2 80Mhz or 527 * 1x1 160Mhz, long-guard-interval. 528 */ 529 .vht160_mcs_rx_highest = 780, 530 .vht160_mcs_tx_highest = 780, 531 .n_cipher_suites = 11, 532 .ast_skid_limit = 0x10, 533 .num_wds_entries = 0x20, 534 .target_64bit = false, 535 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 536 .shadow_reg_support = false, 537 .rri_on_ddr = false, 538 .hw_filter_reset_required = true, 539 .fw_diag_ce_download = false, 540 .credit_size_workaround = false, 541 .tx_stats_over_pktlog = false, 542 .dynamic_sar_support = false, 543 .hw_restart_disconnect = false, 544 .use_fw_tx_credits = true, 545 .delay_unmap_buffer = false, 546 .mcast_frame_registration = false, 547 }, 548 { 549 .id = QCA9377_HW_1_0_DEV_VERSION, 550 .dev_id = QCA9377_1_0_DEVICE_ID, 551 .bus = ATH10K_BUS_PCI, 552 .name = "qca9377 hw1.0", 553 .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR, 554 .uart_pin = 6, 555 .led_pin = 0, 556 .otp_exe_param = 0, 557 .channel_counters_freq_hz = 88000, 558 .max_probe_resp_desc_thres = 0, 559 .cal_data_len = 8124, 560 .fw = { 561 .dir = QCA9377_HW_1_0_FW_DIR, 562 .board_size = QCA9377_BOARD_DATA_SZ, 563 .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ, 564 }, 565 .rx_desc_ops = &qca988x_rx_desc_ops, 566 .hw_ops = &qca988x_ops, 567 .decap_align_bytes = 4, 568 .spectral_bin_discard = 0, 569 .spectral_bin_offset = 0, 570 .vht160_mcs_rx_highest = 0, 571 .vht160_mcs_tx_highest = 0, 572 .n_cipher_suites = 8, 573 .ast_skid_limit = 0x10, 574 .num_wds_entries = 0x20, 575 .target_64bit = false, 576 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 577 .shadow_reg_support = false, 578 .rri_on_ddr = false, 579 .hw_filter_reset_required = true, 580 .fw_diag_ce_download = false, 581 .credit_size_workaround = false, 582 .tx_stats_over_pktlog = false, 583 .dynamic_sar_support = false, 584 .hw_restart_disconnect = false, 585 .use_fw_tx_credits = true, 586 .delay_unmap_buffer = false, 587 .mcast_frame_registration = false, 588 }, 589 { 590 .id = QCA9377_HW_1_1_DEV_VERSION, 591 .dev_id = QCA9377_1_0_DEVICE_ID, 592 .bus = ATH10K_BUS_PCI, 593 .name = "qca9377 hw1.1", 594 .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR, 595 .uart_pin = 6, 596 .led_pin = 0, 597 .otp_exe_param = 0, 598 .channel_counters_freq_hz = 88000, 599 .max_probe_resp_desc_thres = 0, 600 .cal_data_len = 8124, 601 .fw = { 602 .dir = QCA9377_HW_1_0_FW_DIR, 603 .board_size = QCA9377_BOARD_DATA_SZ, 604 .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ, 605 }, 606 .rx_desc_ops = &qca988x_rx_desc_ops, 607 .hw_ops = &qca6174_ops, 608 .hw_clk = qca6174_clk, 609 .target_cpu_freq = 176000000, 610 .decap_align_bytes = 4, 611 .spectral_bin_discard = 0, 612 .spectral_bin_offset = 0, 613 .vht160_mcs_rx_highest = 0, 614 .vht160_mcs_tx_highest = 0, 615 .n_cipher_suites = 8, 616 .ast_skid_limit = 0x10, 617 .num_wds_entries = 0x20, 618 .target_64bit = false, 619 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 620 .shadow_reg_support = false, 621 .rri_on_ddr = false, 622 .hw_filter_reset_required = true, 623 .fw_diag_ce_download = true, 624 .credit_size_workaround = false, 625 .tx_stats_over_pktlog = false, 626 .dynamic_sar_support = false, 627 .hw_restart_disconnect = false, 628 .use_fw_tx_credits = true, 629 .delay_unmap_buffer = false, 630 .mcast_frame_registration = false, 631 }, 632 { 633 .id = QCA9377_HW_1_1_DEV_VERSION, 634 .dev_id = QCA9377_1_0_DEVICE_ID, 635 .bus = ATH10K_BUS_SDIO, 636 .name = "qca9377 hw1.1 sdio", 637 .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR, 638 .uart_pin = 19, 639 .led_pin = 0, 640 .otp_exe_param = 0, 641 .channel_counters_freq_hz = 88000, 642 .max_probe_resp_desc_thres = 0, 643 .cal_data_len = 8124, 644 .fw = { 645 .dir = QCA9377_HW_1_0_FW_DIR, 646 .board_size = QCA9377_BOARD_DATA_SZ, 647 .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ, 648 }, 649 .rx_desc_ops = &qca988x_rx_desc_ops, 650 .hw_ops = &qca6174_ops, 651 .hw_clk = qca6174_clk, 652 .target_cpu_freq = 176000000, 653 .decap_align_bytes = 4, 654 .n_cipher_suites = 8, 655 .num_peers = TARGET_QCA9377_HL_NUM_PEERS, 656 .ast_skid_limit = 0x10, 657 .num_wds_entries = 0x20, 658 .uart_pin_workaround = true, 659 .credit_size_workaround = true, 660 .dynamic_sar_support = false, 661 .hw_restart_disconnect = false, 662 .use_fw_tx_credits = true, 663 .delay_unmap_buffer = false, 664 .mcast_frame_registration = false, 665 }, 666 { 667 .id = QCA4019_HW_1_0_DEV_VERSION, 668 .dev_id = 0, 669 .bus = ATH10K_BUS_AHB, 670 .name = "qca4019 hw1.0", 671 .patch_load_addr = QCA4019_HW_1_0_PATCH_LOAD_ADDR, 672 .uart_pin = 7, 673 .led_pin = 0, 674 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH, 675 .otp_exe_param = 0x0010000, 676 .continuous_frag_desc = true, 677 .cck_rate_map_rev2 = true, 678 .channel_counters_freq_hz = 125000, 679 .max_probe_resp_desc_thres = 24, 680 .tx_chain_mask = 0x3, 681 .rx_chain_mask = 0x3, 682 .max_spatial_stream = 2, 683 .cal_data_len = 12064, 684 .fw = { 685 .dir = QCA4019_HW_1_0_FW_DIR, 686 .board_size = QCA4019_BOARD_DATA_SZ, 687 .board_ext_size = QCA4019_BOARD_EXT_DATA_SZ, 688 }, 689 .sw_decrypt_mcast_mgmt = true, 690 .rx_desc_ops = &qca99x0_rx_desc_ops, 691 .hw_ops = &qca99x0_ops, 692 .decap_align_bytes = 1, 693 .spectral_bin_discard = 4, 694 .spectral_bin_offset = 0, 695 .vht160_mcs_rx_highest = 0, 696 .vht160_mcs_tx_highest = 0, 697 .n_cipher_suites = 11, 698 .ast_skid_limit = 0x10, 699 .num_wds_entries = 0x20, 700 .target_64bit = false, 701 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 702 .shadow_reg_support = false, 703 .rri_on_ddr = false, 704 .hw_filter_reset_required = true, 705 .fw_diag_ce_download = false, 706 .credit_size_workaround = false, 707 .tx_stats_over_pktlog = false, 708 .dynamic_sar_support = false, 709 .hw_restart_disconnect = false, 710 .use_fw_tx_credits = true, 711 .delay_unmap_buffer = false, 712 .mcast_frame_registration = false, 713 }, 714 { 715 .id = WCN3990_HW_1_0_DEV_VERSION, 716 .dev_id = 0, 717 .bus = ATH10K_BUS_SNOC, 718 .name = "wcn3990 hw1.0", 719 .led_pin = 0, 720 .continuous_frag_desc = true, 721 .tx_chain_mask = 0x7, 722 .rx_chain_mask = 0x7, 723 .max_spatial_stream = 4, 724 .fw = { 725 .dir = WCN3990_HW_1_0_FW_DIR, 726 .board_size = WCN3990_BOARD_DATA_SZ, 727 .board_ext_size = WCN3990_BOARD_EXT_DATA_SZ, 728 }, 729 .sw_decrypt_mcast_mgmt = true, 730 .rx_desc_ops = &wcn3990_rx_desc_ops, 731 .hw_ops = &wcn3990_ops, 732 .decap_align_bytes = 1, 733 .num_peers = TARGET_HL_TLV_NUM_PEERS, 734 .n_cipher_suites = 11, 735 .ast_skid_limit = TARGET_HL_TLV_AST_SKID_LIMIT, 736 .num_wds_entries = TARGET_HL_TLV_NUM_WDS_ENTRIES, 737 .target_64bit = true, 738 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL_DUAL_MAC, 739 .shadow_reg_support = true, 740 .rri_on_ddr = true, 741 .hw_filter_reset_required = false, 742 .fw_diag_ce_download = false, 743 .credit_size_workaround = false, 744 .tx_stats_over_pktlog = false, 745 .dynamic_sar_support = true, 746 .hw_restart_disconnect = true, 747 .use_fw_tx_credits = false, 748 .delay_unmap_buffer = true, 749 .mcast_frame_registration = false, 750 }, 751 }; 752 753 static const char *const ath10k_core_fw_feature_str[] = { 754 [ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX] = "wmi-mgmt-rx", 755 [ATH10K_FW_FEATURE_WMI_10X] = "wmi-10.x", 756 [ATH10K_FW_FEATURE_HAS_WMI_MGMT_TX] = "has-wmi-mgmt-tx", 757 [ATH10K_FW_FEATURE_NO_P2P] = "no-p2p", 758 [ATH10K_FW_FEATURE_WMI_10_2] = "wmi-10.2", 759 [ATH10K_FW_FEATURE_MULTI_VIF_PS_SUPPORT] = "multi-vif-ps", 760 [ATH10K_FW_FEATURE_WOWLAN_SUPPORT] = "wowlan", 761 [ATH10K_FW_FEATURE_IGNORE_OTP_RESULT] = "ignore-otp", 762 [ATH10K_FW_FEATURE_NO_NWIFI_DECAP_4ADDR_PADDING] = "no-4addr-pad", 763 [ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT] = "skip-clock-init", 764 [ATH10K_FW_FEATURE_RAW_MODE_SUPPORT] = "raw-mode", 765 [ATH10K_FW_FEATURE_SUPPORTS_ADAPTIVE_CCA] = "adaptive-cca", 766 [ATH10K_FW_FEATURE_MFP_SUPPORT] = "mfp", 767 [ATH10K_FW_FEATURE_PEER_FLOW_CONTROL] = "peer-flow-ctrl", 768 [ATH10K_FW_FEATURE_BTCOEX_PARAM] = "btcoex-param", 769 [ATH10K_FW_FEATURE_SKIP_NULL_FUNC_WAR] = "skip-null-func-war", 770 [ATH10K_FW_FEATURE_ALLOWS_MESH_BCAST] = "allows-mesh-bcast", 771 [ATH10K_FW_FEATURE_NO_PS] = "no-ps", 772 [ATH10K_FW_FEATURE_MGMT_TX_BY_REF] = "mgmt-tx-by-reference", 773 [ATH10K_FW_FEATURE_NON_BMI] = "non-bmi", 774 [ATH10K_FW_FEATURE_SINGLE_CHAN_INFO_PER_CHANNEL] = "single-chan-info-per-channel", 775 [ATH10K_FW_FEATURE_PEER_FIXED_RATE] = "peer-fixed-rate", 776 [ATH10K_FW_FEATURE_IRAM_RECOVERY] = "iram-recovery", 777 }; 778 779 static unsigned int ath10k_core_get_fw_feature_str(char *buf, 780 size_t buf_len, 781 enum ath10k_fw_features feat) 782 { 783 /* make sure that ath10k_core_fw_feature_str[] gets updated */ 784 BUILD_BUG_ON(ARRAY_SIZE(ath10k_core_fw_feature_str) != 785 ATH10K_FW_FEATURE_COUNT); 786 787 if (feat >= ARRAY_SIZE(ath10k_core_fw_feature_str) || 788 WARN_ON(!ath10k_core_fw_feature_str[feat])) { 789 return scnprintf(buf, buf_len, "bit%d", feat); 790 } 791 792 return scnprintf(buf, buf_len, "%s", ath10k_core_fw_feature_str[feat]); 793 } 794 795 void ath10k_core_get_fw_features_str(struct ath10k *ar, 796 char *buf, 797 size_t buf_len) 798 { 799 size_t len = 0; 800 int i; 801 802 for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) { 803 if (test_bit(i, ar->normal_mode_fw.fw_file.fw_features)) { 804 if (len > 0) 805 len += scnprintf(buf + len, buf_len - len, ","); 806 807 len += ath10k_core_get_fw_feature_str(buf + len, 808 buf_len - len, 809 i); 810 } 811 } 812 } 813 814 static void ath10k_send_suspend_complete(struct ath10k *ar) 815 { 816 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot suspend complete\n"); 817 818 complete(&ar->target_suspend); 819 } 820 821 static int ath10k_init_sdio(struct ath10k *ar, enum ath10k_firmware_mode mode) 822 { 823 bool mtu_workaround = ar->hw_params.credit_size_workaround; 824 int ret; 825 u32 param = 0; 826 827 ret = ath10k_bmi_write32(ar, hi_mbox_io_block_sz, 256); 828 if (ret) 829 return ret; 830 831 ret = ath10k_bmi_write32(ar, hi_mbox_isr_yield_limit, 99); 832 if (ret) 833 return ret; 834 835 ret = ath10k_bmi_read32(ar, hi_acs_flags, ¶m); 836 if (ret) 837 return ret; 838 839 param |= HI_ACS_FLAGS_SDIO_REDUCE_TX_COMPL_SET; 840 841 if (mode == ATH10K_FIRMWARE_MODE_NORMAL && !mtu_workaround) 842 param |= HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE; 843 else 844 param &= ~HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE; 845 846 if (mode == ATH10K_FIRMWARE_MODE_UTF) 847 param &= ~HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_SET; 848 else 849 param |= HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_SET; 850 851 ret = ath10k_bmi_write32(ar, hi_acs_flags, param); 852 if (ret) 853 return ret; 854 855 ret = ath10k_bmi_read32(ar, hi_option_flag2, ¶m); 856 if (ret) 857 return ret; 858 859 param |= HI_OPTION_SDIO_CRASH_DUMP_ENHANCEMENT_HOST; 860 861 ret = ath10k_bmi_write32(ar, hi_option_flag2, param); 862 if (ret) 863 return ret; 864 865 return 0; 866 } 867 868 static int ath10k_init_configure_target(struct ath10k *ar) 869 { 870 u32 param_host; 871 int ret; 872 873 /* tell target which HTC version it is used*/ 874 ret = ath10k_bmi_write32(ar, hi_app_host_interest, 875 HTC_PROTOCOL_VERSION); 876 if (ret) { 877 ath10k_err(ar, "settings HTC version failed\n"); 878 return ret; 879 } 880 881 /* set the firmware mode to STA/IBSS/AP */ 882 ret = ath10k_bmi_read32(ar, hi_option_flag, ¶m_host); 883 if (ret) { 884 ath10k_err(ar, "setting firmware mode (1/2) failed\n"); 885 return ret; 886 } 887 888 /* TODO following parameters need to be re-visited. */ 889 /* num_device */ 890 param_host |= (1 << HI_OPTION_NUM_DEV_SHIFT); 891 /* Firmware mode */ 892 /* FIXME: Why FW_MODE_AP ??.*/ 893 param_host |= (HI_OPTION_FW_MODE_AP << HI_OPTION_FW_MODE_SHIFT); 894 /* mac_addr_method */ 895 param_host |= (1 << HI_OPTION_MAC_ADDR_METHOD_SHIFT); 896 /* firmware_bridge */ 897 param_host |= (0 << HI_OPTION_FW_BRIDGE_SHIFT); 898 /* fwsubmode */ 899 param_host |= (0 << HI_OPTION_FW_SUBMODE_SHIFT); 900 901 ret = ath10k_bmi_write32(ar, hi_option_flag, param_host); 902 if (ret) { 903 ath10k_err(ar, "setting firmware mode (2/2) failed\n"); 904 return ret; 905 } 906 907 /* We do all byte-swapping on the host */ 908 ret = ath10k_bmi_write32(ar, hi_be, 0); 909 if (ret) { 910 ath10k_err(ar, "setting host CPU BE mode failed\n"); 911 return ret; 912 } 913 914 /* FW descriptor/Data swap flags */ 915 ret = ath10k_bmi_write32(ar, hi_fw_swap, 0); 916 917 if (ret) { 918 ath10k_err(ar, "setting FW data/desc swap flags failed\n"); 919 return ret; 920 } 921 922 /* Some devices have a special sanity check that verifies the PCI 923 * Device ID is written to this host interest var. It is known to be 924 * required to boot QCA6164. 925 */ 926 ret = ath10k_bmi_write32(ar, hi_hci_uart_pwr_mgmt_params_ext, 927 ar->dev_id); 928 if (ret) { 929 ath10k_err(ar, "failed to set pwr_mgmt_params: %d\n", ret); 930 return ret; 931 } 932 933 return 0; 934 } 935 936 static const struct firmware *ath10k_fetch_fw_file(struct ath10k *ar, 937 const char *dir, 938 const char *file) 939 { 940 char filename[100]; 941 const struct firmware *fw; 942 int ret; 943 944 if (file == NULL) 945 return ERR_PTR(-ENOENT); 946 947 if (dir == NULL) 948 dir = "."; 949 950 if (ar->board_name) { 951 snprintf(filename, sizeof(filename), "%s/%s/%s", 952 dir, ar->board_name, file); 953 ret = firmware_request_nowarn(&fw, filename, ar->dev); 954 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot fw request '%s': %d\n", 955 filename, ret); 956 if (!ret) 957 return fw; 958 } 959 960 snprintf(filename, sizeof(filename), "%s/%s", dir, file); 961 ret = firmware_request_nowarn(&fw, filename, ar->dev); 962 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot fw request '%s': %d\n", 963 filename, ret); 964 if (ret) 965 return ERR_PTR(ret); 966 967 return fw; 968 } 969 970 static int ath10k_push_board_ext_data(struct ath10k *ar, const void *data, 971 size_t data_len) 972 { 973 u32 board_data_size = ar->hw_params.fw.board_size; 974 u32 board_ext_data_size = ar->hw_params.fw.board_ext_size; 975 u32 board_ext_data_addr; 976 int ret; 977 978 ret = ath10k_bmi_read32(ar, hi_board_ext_data, &board_ext_data_addr); 979 if (ret) { 980 ath10k_err(ar, "could not read board ext data addr (%d)\n", 981 ret); 982 return ret; 983 } 984 985 ath10k_dbg(ar, ATH10K_DBG_BOOT, 986 "boot push board extended data addr 0x%x\n", 987 board_ext_data_addr); 988 989 if (board_ext_data_addr == 0) 990 return 0; 991 992 if (data_len != (board_data_size + board_ext_data_size)) { 993 ath10k_err(ar, "invalid board (ext) data sizes %zu != %d+%d\n", 994 data_len, board_data_size, board_ext_data_size); 995 return -EINVAL; 996 } 997 998 ret = ath10k_bmi_write_memory(ar, board_ext_data_addr, 999 data + board_data_size, 1000 board_ext_data_size); 1001 if (ret) { 1002 ath10k_err(ar, "could not write board ext data (%d)\n", ret); 1003 return ret; 1004 } 1005 1006 ret = ath10k_bmi_write32(ar, hi_board_ext_data_config, 1007 (board_ext_data_size << 16) | 1); 1008 if (ret) { 1009 ath10k_err(ar, "could not write board ext data bit (%d)\n", 1010 ret); 1011 return ret; 1012 } 1013 1014 return 0; 1015 } 1016 1017 static int ath10k_core_get_board_id_from_otp(struct ath10k *ar) 1018 { 1019 u32 result, address; 1020 u8 board_id, chip_id; 1021 bool ext_bid_support; 1022 int ret, bmi_board_id_param; 1023 1024 address = ar->hw_params.patch_load_addr; 1025 1026 if (!ar->normal_mode_fw.fw_file.otp_data || 1027 !ar->normal_mode_fw.fw_file.otp_len) { 1028 ath10k_warn(ar, 1029 "failed to retrieve board id because of invalid otp\n"); 1030 return -ENODATA; 1031 } 1032 1033 if (ar->id.bmi_ids_valid) { 1034 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1035 "boot already acquired valid otp board id,skip download, board_id %d chip_id %d\n", 1036 ar->id.bmi_board_id, ar->id.bmi_chip_id); 1037 goto skip_otp_download; 1038 } 1039 1040 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1041 "boot upload otp to 0x%x len %zd for board id\n", 1042 address, ar->normal_mode_fw.fw_file.otp_len); 1043 1044 ret = ath10k_bmi_fast_download(ar, address, 1045 ar->normal_mode_fw.fw_file.otp_data, 1046 ar->normal_mode_fw.fw_file.otp_len); 1047 if (ret) { 1048 ath10k_err(ar, "could not write otp for board id check: %d\n", 1049 ret); 1050 return ret; 1051 } 1052 1053 if (ar->cal_mode == ATH10K_PRE_CAL_MODE_DT || 1054 ar->cal_mode == ATH10K_PRE_CAL_MODE_FILE || 1055 ar->cal_mode == ATH10K_PRE_CAL_MODE_NVMEM) 1056 bmi_board_id_param = BMI_PARAM_GET_FLASH_BOARD_ID; 1057 else 1058 bmi_board_id_param = BMI_PARAM_GET_EEPROM_BOARD_ID; 1059 1060 ret = ath10k_bmi_execute(ar, address, bmi_board_id_param, &result); 1061 if (ret) { 1062 ath10k_err(ar, "could not execute otp for board id check: %d\n", 1063 ret); 1064 return ret; 1065 } 1066 1067 board_id = MS(result, ATH10K_BMI_BOARD_ID_FROM_OTP); 1068 chip_id = MS(result, ATH10K_BMI_CHIP_ID_FROM_OTP); 1069 ext_bid_support = (result & ATH10K_BMI_EXT_BOARD_ID_SUPPORT); 1070 1071 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1072 "boot get otp board id result 0x%08x board_id %d chip_id %d ext_bid_support %d\n", 1073 result, board_id, chip_id, ext_bid_support); 1074 1075 ar->id.ext_bid_supported = ext_bid_support; 1076 1077 if ((result & ATH10K_BMI_BOARD_ID_STATUS_MASK) != 0 || 1078 (board_id == 0)) { 1079 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1080 "board id does not exist in otp, ignore it\n"); 1081 return -EOPNOTSUPP; 1082 } 1083 1084 ar->id.bmi_ids_valid = true; 1085 ar->id.bmi_board_id = board_id; 1086 ar->id.bmi_chip_id = chip_id; 1087 1088 skip_otp_download: 1089 1090 return 0; 1091 } 1092 1093 static void ath10k_core_check_bdfext(const struct dmi_header *hdr, void *data) 1094 { 1095 struct ath10k *ar = data; 1096 const char *bdf_ext; 1097 const char *magic = ATH10K_SMBIOS_BDF_EXT_MAGIC; 1098 u8 bdf_enabled; 1099 int i; 1100 1101 if (hdr->type != ATH10K_SMBIOS_BDF_EXT_TYPE) 1102 return; 1103 1104 if (hdr->length != ATH10K_SMBIOS_BDF_EXT_LENGTH) { 1105 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1106 "wrong smbios bdf ext type length (%d).\n", 1107 hdr->length); 1108 return; 1109 } 1110 1111 bdf_enabled = *((u8 *)hdr + ATH10K_SMBIOS_BDF_EXT_OFFSET); 1112 if (!bdf_enabled) { 1113 ath10k_dbg(ar, ATH10K_DBG_BOOT, "bdf variant name not found.\n"); 1114 return; 1115 } 1116 1117 /* Only one string exists (per spec) */ 1118 bdf_ext = (char *)hdr + hdr->length; 1119 1120 if (memcmp(bdf_ext, magic, strlen(magic)) != 0) { 1121 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1122 "bdf variant magic does not match.\n"); 1123 return; 1124 } 1125 1126 for (i = 0; i < strlen(bdf_ext); i++) { 1127 if (!isascii(bdf_ext[i]) || !isprint(bdf_ext[i])) { 1128 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1129 "bdf variant name contains non ascii chars.\n"); 1130 return; 1131 } 1132 } 1133 1134 /* Copy extension name without magic suffix */ 1135 if (strscpy(ar->id.bdf_ext, bdf_ext + strlen(magic), 1136 sizeof(ar->id.bdf_ext)) < 0) { 1137 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1138 "bdf variant string is longer than the buffer can accommodate (variant: %s)\n", 1139 bdf_ext); 1140 return; 1141 } 1142 1143 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1144 "found and validated bdf variant smbios_type 0x%x bdf %s\n", 1145 ATH10K_SMBIOS_BDF_EXT_TYPE, bdf_ext); 1146 } 1147 1148 static int ath10k_core_check_smbios(struct ath10k *ar) 1149 { 1150 ar->id.bdf_ext[0] = '\0'; 1151 dmi_walk(ath10k_core_check_bdfext, ar); 1152 1153 if (ar->id.bdf_ext[0] == '\0') 1154 return -ENODATA; 1155 1156 return 0; 1157 } 1158 1159 int ath10k_core_check_dt(struct ath10k *ar) 1160 { 1161 struct device_node *node; 1162 const char *variant = NULL; 1163 1164 node = ar->dev->of_node; 1165 if (!node) 1166 return -ENOENT; 1167 1168 of_property_read_string(node, "qcom,calibration-variant", 1169 &variant); 1170 if (!variant) 1171 of_property_read_string(node, "qcom,ath10k-calibration-variant", 1172 &variant); 1173 if (!variant) 1174 return -ENODATA; 1175 1176 if (strscpy(ar->id.bdf_ext, variant, sizeof(ar->id.bdf_ext)) < 0) 1177 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1178 "bdf variant string is longer than the buffer can accommodate (variant: %s)\n", 1179 variant); 1180 1181 return 0; 1182 } 1183 EXPORT_SYMBOL(ath10k_core_check_dt); 1184 1185 static int ath10k_download_fw(struct ath10k *ar) 1186 { 1187 u32 address, data_len; 1188 const void *data; 1189 int ret; 1190 struct pm_qos_request latency_qos; 1191 1192 address = ar->hw_params.patch_load_addr; 1193 1194 data = ar->running_fw->fw_file.firmware_data; 1195 data_len = ar->running_fw->fw_file.firmware_len; 1196 1197 ret = ath10k_swap_code_seg_configure(ar, &ar->running_fw->fw_file); 1198 if (ret) { 1199 ath10k_err(ar, "failed to configure fw code swap: %d\n", 1200 ret); 1201 return ret; 1202 } 1203 1204 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1205 "boot uploading firmware image %p len %d\n", 1206 data, data_len); 1207 1208 /* Check if device supports to download firmware via 1209 * diag copy engine. Downloading firmware via diag CE 1210 * greatly reduces the time to download firmware. 1211 */ 1212 if (ar->hw_params.fw_diag_ce_download) { 1213 ret = ath10k_hw_diag_fast_download(ar, address, 1214 data, data_len); 1215 if (ret == 0) 1216 /* firmware upload via diag ce was successful */ 1217 return 0; 1218 1219 ath10k_warn(ar, 1220 "failed to upload firmware via diag ce, trying BMI: %d", 1221 ret); 1222 } 1223 1224 memset(&latency_qos, 0, sizeof(latency_qos)); 1225 cpu_latency_qos_add_request(&latency_qos, 0); 1226 1227 ret = ath10k_bmi_fast_download(ar, address, data, data_len); 1228 1229 cpu_latency_qos_remove_request(&latency_qos); 1230 1231 return ret; 1232 } 1233 1234 void ath10k_core_free_board_files(struct ath10k *ar) 1235 { 1236 if (!IS_ERR(ar->normal_mode_fw.board)) 1237 release_firmware(ar->normal_mode_fw.board); 1238 1239 if (!IS_ERR(ar->normal_mode_fw.ext_board)) 1240 release_firmware(ar->normal_mode_fw.ext_board); 1241 1242 ar->normal_mode_fw.board = NULL; 1243 ar->normal_mode_fw.board_data = NULL; 1244 ar->normal_mode_fw.board_len = 0; 1245 ar->normal_mode_fw.ext_board = NULL; 1246 ar->normal_mode_fw.ext_board_data = NULL; 1247 ar->normal_mode_fw.ext_board_len = 0; 1248 } 1249 EXPORT_SYMBOL(ath10k_core_free_board_files); 1250 1251 static void ath10k_core_free_firmware_files(struct ath10k *ar) 1252 { 1253 if (!IS_ERR(ar->normal_mode_fw.fw_file.firmware)) 1254 release_firmware(ar->normal_mode_fw.fw_file.firmware); 1255 1256 if (!IS_ERR(ar->cal_file)) 1257 release_firmware(ar->cal_file); 1258 1259 if (!IS_ERR(ar->pre_cal_file)) 1260 release_firmware(ar->pre_cal_file); 1261 1262 ath10k_swap_code_seg_release(ar, &ar->normal_mode_fw.fw_file); 1263 1264 ar->normal_mode_fw.fw_file.otp_data = NULL; 1265 ar->normal_mode_fw.fw_file.otp_len = 0; 1266 1267 ar->normal_mode_fw.fw_file.firmware = NULL; 1268 ar->normal_mode_fw.fw_file.firmware_data = NULL; 1269 ar->normal_mode_fw.fw_file.firmware_len = 0; 1270 1271 ar->cal_file = NULL; 1272 ar->pre_cal_file = NULL; 1273 } 1274 1275 static int ath10k_fetch_cal_file(struct ath10k *ar) 1276 { 1277 char filename[100]; 1278 1279 /* pre-cal-<bus>-<id>.bin */ 1280 scnprintf(filename, sizeof(filename), "pre-cal-%s-%s.bin", 1281 ath10k_bus_str(ar->hif.bus), dev_name(ar->dev)); 1282 1283 ar->pre_cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename); 1284 if (!IS_ERR(ar->pre_cal_file)) 1285 goto success; 1286 1287 /* cal-<bus>-<id>.bin */ 1288 scnprintf(filename, sizeof(filename), "cal-%s-%s.bin", 1289 ath10k_bus_str(ar->hif.bus), dev_name(ar->dev)); 1290 1291 ar->cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename); 1292 if (IS_ERR(ar->cal_file)) 1293 /* calibration file is optional, don't print any warnings */ 1294 return PTR_ERR(ar->cal_file); 1295 success: 1296 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found calibration file %s/%s\n", 1297 ATH10K_FW_DIR, filename); 1298 1299 return 0; 1300 } 1301 1302 static int ath10k_core_fetch_board_data_api_1(struct ath10k *ar, int bd_ie_type) 1303 { 1304 const struct firmware *fw; 1305 char boardname[100]; 1306 1307 if (bd_ie_type == ATH10K_BD_IE_BOARD) { 1308 scnprintf(boardname, sizeof(boardname), "board-%s-%s.bin", 1309 ath10k_bus_str(ar->hif.bus), dev_name(ar->dev)); 1310 1311 ar->normal_mode_fw.board = ath10k_fetch_fw_file(ar, 1312 ar->hw_params.fw.dir, 1313 boardname); 1314 if (IS_ERR(ar->normal_mode_fw.board)) { 1315 fw = ath10k_fetch_fw_file(ar, 1316 ar->hw_params.fw.dir, 1317 ATH10K_BOARD_DATA_FILE); 1318 ar->normal_mode_fw.board = fw; 1319 } 1320 1321 if (IS_ERR(ar->normal_mode_fw.board)) 1322 return PTR_ERR(ar->normal_mode_fw.board); 1323 1324 ar->normal_mode_fw.board_data = ar->normal_mode_fw.board->data; 1325 ar->normal_mode_fw.board_len = ar->normal_mode_fw.board->size; 1326 } else if (bd_ie_type == ATH10K_BD_IE_BOARD_EXT) { 1327 fw = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir, 1328 ATH10K_EBOARD_DATA_FILE); 1329 ar->normal_mode_fw.ext_board = fw; 1330 if (IS_ERR(ar->normal_mode_fw.ext_board)) 1331 return PTR_ERR(ar->normal_mode_fw.ext_board); 1332 1333 ar->normal_mode_fw.ext_board_data = ar->normal_mode_fw.ext_board->data; 1334 ar->normal_mode_fw.ext_board_len = ar->normal_mode_fw.ext_board->size; 1335 } 1336 1337 return 0; 1338 } 1339 1340 static int ath10k_core_parse_bd_ie_board(struct ath10k *ar, 1341 const void *buf, size_t buf_len, 1342 const char *boardname, 1343 int bd_ie_type) 1344 { 1345 const struct ath10k_fw_ie *hdr; 1346 bool name_match_found; 1347 int ret, board_ie_id; 1348 size_t board_ie_len; 1349 const void *board_ie_data; 1350 1351 name_match_found = false; 1352 1353 /* go through ATH10K_BD_IE_BOARD_ elements */ 1354 while (buf_len > sizeof(struct ath10k_fw_ie)) { 1355 hdr = buf; 1356 board_ie_id = le32_to_cpu(hdr->id); 1357 board_ie_len = le32_to_cpu(hdr->len); 1358 board_ie_data = hdr->data; 1359 1360 buf_len -= sizeof(*hdr); 1361 buf += sizeof(*hdr); 1362 1363 if (buf_len < ALIGN(board_ie_len, 4)) { 1364 ath10k_err(ar, "invalid ATH10K_BD_IE_BOARD length: %zu < %zu\n", 1365 buf_len, ALIGN(board_ie_len, 4)); 1366 ret = -EINVAL; 1367 goto out; 1368 } 1369 1370 switch (board_ie_id) { 1371 case ATH10K_BD_IE_BOARD_NAME: 1372 ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "board name", "", 1373 board_ie_data, board_ie_len); 1374 1375 if (board_ie_len != strlen(boardname)) 1376 break; 1377 1378 ret = memcmp(board_ie_data, boardname, strlen(boardname)); 1379 if (ret) 1380 break; 1381 1382 name_match_found = true; 1383 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1384 "boot found match for name '%s'", 1385 boardname); 1386 break; 1387 case ATH10K_BD_IE_BOARD_DATA: 1388 if (!name_match_found) 1389 /* no match found */ 1390 break; 1391 1392 if (bd_ie_type == ATH10K_BD_IE_BOARD) { 1393 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1394 "boot found board data for '%s'", 1395 boardname); 1396 1397 ar->normal_mode_fw.board_data = board_ie_data; 1398 ar->normal_mode_fw.board_len = board_ie_len; 1399 } else if (bd_ie_type == ATH10K_BD_IE_BOARD_EXT) { 1400 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1401 "boot found eboard data for '%s'", 1402 boardname); 1403 1404 ar->normal_mode_fw.ext_board_data = board_ie_data; 1405 ar->normal_mode_fw.ext_board_len = board_ie_len; 1406 } 1407 1408 ret = 0; 1409 goto out; 1410 default: 1411 ath10k_warn(ar, "unknown ATH10K_BD_IE_BOARD found: %d\n", 1412 board_ie_id); 1413 break; 1414 } 1415 1416 /* jump over the padding */ 1417 board_ie_len = ALIGN(board_ie_len, 4); 1418 1419 buf_len -= board_ie_len; 1420 buf += board_ie_len; 1421 } 1422 1423 /* no match found */ 1424 ret = -ENOENT; 1425 1426 out: 1427 return ret; 1428 } 1429 1430 static int ath10k_core_search_bd(struct ath10k *ar, 1431 const char *boardname, 1432 const u8 *data, 1433 size_t len) 1434 { 1435 size_t ie_len; 1436 struct ath10k_fw_ie *hdr; 1437 int ret = -ENOENT, ie_id; 1438 1439 while (len > sizeof(struct ath10k_fw_ie)) { 1440 hdr = (struct ath10k_fw_ie *)data; 1441 ie_id = le32_to_cpu(hdr->id); 1442 ie_len = le32_to_cpu(hdr->len); 1443 1444 len -= sizeof(*hdr); 1445 data = hdr->data; 1446 1447 if (len < ALIGN(ie_len, 4)) { 1448 ath10k_err(ar, "invalid length for board ie_id %d ie_len %zu len %zu\n", 1449 ie_id, ie_len, len); 1450 return -EINVAL; 1451 } 1452 1453 switch (ie_id) { 1454 case ATH10K_BD_IE_BOARD: 1455 ret = ath10k_core_parse_bd_ie_board(ar, data, ie_len, 1456 boardname, 1457 ATH10K_BD_IE_BOARD); 1458 if (ret == -ENOENT) 1459 /* no match found, continue */ 1460 break; 1461 1462 /* either found or error, so stop searching */ 1463 goto out; 1464 case ATH10K_BD_IE_BOARD_EXT: 1465 ret = ath10k_core_parse_bd_ie_board(ar, data, ie_len, 1466 boardname, 1467 ATH10K_BD_IE_BOARD_EXT); 1468 if (ret == -ENOENT) 1469 /* no match found, continue */ 1470 break; 1471 1472 /* either found or error, so stop searching */ 1473 goto out; 1474 } 1475 1476 /* jump over the padding */ 1477 ie_len = ALIGN(ie_len, 4); 1478 1479 len -= ie_len; 1480 data += ie_len; 1481 } 1482 1483 out: 1484 /* return result of parse_bd_ie_board() or -ENOENT */ 1485 return ret; 1486 } 1487 1488 static int ath10k_core_fetch_board_data_api_n(struct ath10k *ar, 1489 const char *boardname, 1490 const char *fallback_boardname1, 1491 const char *fallback_boardname2, 1492 const char *filename) 1493 { 1494 size_t len, magic_len; 1495 const u8 *data; 1496 int ret; 1497 1498 /* Skip if already fetched during board data download */ 1499 if (!ar->normal_mode_fw.board) 1500 ar->normal_mode_fw.board = ath10k_fetch_fw_file(ar, 1501 ar->hw_params.fw.dir, 1502 filename); 1503 if (IS_ERR(ar->normal_mode_fw.board)) 1504 return PTR_ERR(ar->normal_mode_fw.board); 1505 1506 data = ar->normal_mode_fw.board->data; 1507 len = ar->normal_mode_fw.board->size; 1508 1509 /* magic has extra null byte padded */ 1510 magic_len = strlen(ATH10K_BOARD_MAGIC) + 1; 1511 if (len < magic_len) { 1512 ath10k_err(ar, "failed to find magic value in %s/%s, file too short: %zu\n", 1513 ar->hw_params.fw.dir, filename, len); 1514 ret = -EINVAL; 1515 goto err; 1516 } 1517 1518 if (memcmp(data, ATH10K_BOARD_MAGIC, magic_len)) { 1519 ath10k_err(ar, "found invalid board magic\n"); 1520 ret = -EINVAL; 1521 goto err; 1522 } 1523 1524 /* magic is padded to 4 bytes */ 1525 magic_len = ALIGN(magic_len, 4); 1526 if (len < magic_len) { 1527 ath10k_err(ar, "failed: %s/%s too small to contain board data, len: %zu\n", 1528 ar->hw_params.fw.dir, filename, len); 1529 ret = -EINVAL; 1530 goto err; 1531 } 1532 1533 data += magic_len; 1534 len -= magic_len; 1535 1536 /* attempt to find boardname in the IE list */ 1537 ret = ath10k_core_search_bd(ar, boardname, data, len); 1538 1539 /* if we didn't find it and have a fallback name, try that */ 1540 if (ret == -ENOENT && fallback_boardname1) 1541 ret = ath10k_core_search_bd(ar, fallback_boardname1, data, len); 1542 1543 if (ret == -ENOENT && fallback_boardname2) 1544 ret = ath10k_core_search_bd(ar, fallback_boardname2, data, len); 1545 1546 if (ret == -ENOENT) { 1547 ath10k_err(ar, 1548 "failed to fetch board data for %s from %s/%s\n", 1549 boardname, ar->hw_params.fw.dir, filename); 1550 ret = -ENODATA; 1551 } 1552 1553 if (ret) 1554 goto err; 1555 1556 return 0; 1557 1558 err: 1559 ath10k_core_free_board_files(ar); 1560 return ret; 1561 } 1562 1563 static int ath10k_core_create_board_name(struct ath10k *ar, char *name, 1564 size_t name_len, bool with_variant, 1565 bool with_chip_id) 1566 { 1567 /* strlen(',variant=') + strlen(ar->id.bdf_ext) */ 1568 char variant[9 + ATH10K_SMBIOS_BDF_EXT_STR_LENGTH] = {}; 1569 1570 if (with_variant && ar->id.bdf_ext[0] != '\0') 1571 scnprintf(variant, sizeof(variant), ",variant=%s", 1572 ar->id.bdf_ext); 1573 1574 if (ar->id.bmi_ids_valid) { 1575 scnprintf(name, name_len, 1576 "bus=%s,bmi-chip-id=%d,bmi-board-id=%d%s", 1577 ath10k_bus_str(ar->hif.bus), 1578 ar->id.bmi_chip_id, 1579 ar->id.bmi_board_id, variant); 1580 goto out; 1581 } 1582 1583 if (ar->id.qmi_ids_valid) { 1584 if (with_chip_id) 1585 scnprintf(name, name_len, 1586 "bus=%s,qmi-board-id=%x,qmi-chip-id=%x%s", 1587 ath10k_bus_str(ar->hif.bus), 1588 ar->id.qmi_board_id, ar->id.qmi_chip_id, 1589 variant); 1590 else 1591 scnprintf(name, name_len, 1592 "bus=%s,qmi-board-id=%x", 1593 ath10k_bus_str(ar->hif.bus), 1594 ar->id.qmi_board_id); 1595 goto out; 1596 } 1597 1598 scnprintf(name, name_len, 1599 "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x%s", 1600 ath10k_bus_str(ar->hif.bus), 1601 ar->id.vendor, ar->id.device, 1602 ar->id.subsystem_vendor, ar->id.subsystem_device, variant); 1603 out: 1604 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using board name '%s'\n", name); 1605 1606 return 0; 1607 } 1608 1609 static int ath10k_core_create_eboard_name(struct ath10k *ar, char *name, 1610 size_t name_len) 1611 { 1612 if (ar->id.bmi_ids_valid) { 1613 scnprintf(name, name_len, 1614 "bus=%s,bmi-chip-id=%d,bmi-eboard-id=%d", 1615 ath10k_bus_str(ar->hif.bus), 1616 ar->id.bmi_chip_id, 1617 ar->id.bmi_eboard_id); 1618 1619 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using eboard name '%s'\n", name); 1620 return 0; 1621 } 1622 /* Fallback if returned board id is zero */ 1623 return -1; 1624 } 1625 1626 int ath10k_core_fetch_board_file(struct ath10k *ar, int bd_ie_type) 1627 { 1628 char boardname[100], fallback_boardname1[100], fallback_boardname2[100]; 1629 int ret; 1630 1631 if (bd_ie_type == ATH10K_BD_IE_BOARD) { 1632 /* With variant and chip id */ 1633 ret = ath10k_core_create_board_name(ar, boardname, 1634 sizeof(boardname), true, 1635 true); 1636 if (ret) { 1637 ath10k_err(ar, "failed to create board name: %d", ret); 1638 return ret; 1639 } 1640 1641 /* Without variant and only chip-id */ 1642 ret = ath10k_core_create_board_name(ar, fallback_boardname1, 1643 sizeof(boardname), false, 1644 true); 1645 if (ret) { 1646 ath10k_err(ar, "failed to create 1st fallback board name: %d", 1647 ret); 1648 return ret; 1649 } 1650 1651 /* Without variant and without chip-id */ 1652 ret = ath10k_core_create_board_name(ar, fallback_boardname2, 1653 sizeof(boardname), false, 1654 false); 1655 if (ret) { 1656 ath10k_err(ar, "failed to create 2nd fallback board name: %d", 1657 ret); 1658 return ret; 1659 } 1660 } else if (bd_ie_type == ATH10K_BD_IE_BOARD_EXT) { 1661 ret = ath10k_core_create_eboard_name(ar, boardname, 1662 sizeof(boardname)); 1663 if (ret) { 1664 ath10k_err(ar, "fallback to eboard.bin since board id 0"); 1665 goto fallback; 1666 } 1667 } 1668 1669 ar->bd_api = 2; 1670 ret = ath10k_core_fetch_board_data_api_n(ar, boardname, 1671 fallback_boardname1, 1672 fallback_boardname2, 1673 ATH10K_BOARD_API2_FILE); 1674 if (!ret) 1675 goto success; 1676 1677 fallback: 1678 ar->bd_api = 1; 1679 ret = ath10k_core_fetch_board_data_api_1(ar, bd_ie_type); 1680 if (ret) { 1681 ath10k_err(ar, "failed to fetch board-2.bin or board.bin from %s\n", 1682 ar->hw_params.fw.dir); 1683 return ret; 1684 } 1685 1686 success: 1687 ath10k_dbg(ar, ATH10K_DBG_BOOT, "using board api %d\n", ar->bd_api); 1688 return 0; 1689 } 1690 EXPORT_SYMBOL(ath10k_core_fetch_board_file); 1691 1692 static int ath10k_core_get_ext_board_id_from_otp(struct ath10k *ar) 1693 { 1694 u32 result, address; 1695 u8 ext_board_id; 1696 int ret; 1697 1698 address = ar->hw_params.patch_load_addr; 1699 1700 if (!ar->normal_mode_fw.fw_file.otp_data || 1701 !ar->normal_mode_fw.fw_file.otp_len) { 1702 ath10k_warn(ar, 1703 "failed to retrieve extended board id due to otp binary missing\n"); 1704 return -ENODATA; 1705 } 1706 1707 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1708 "boot upload otp to 0x%x len %zd for ext board id\n", 1709 address, ar->normal_mode_fw.fw_file.otp_len); 1710 1711 ret = ath10k_bmi_fast_download(ar, address, 1712 ar->normal_mode_fw.fw_file.otp_data, 1713 ar->normal_mode_fw.fw_file.otp_len); 1714 if (ret) { 1715 ath10k_err(ar, "could not write otp for ext board id check: %d\n", 1716 ret); 1717 return ret; 1718 } 1719 1720 ret = ath10k_bmi_execute(ar, address, BMI_PARAM_GET_EXT_BOARD_ID, &result); 1721 if (ret) { 1722 ath10k_err(ar, "could not execute otp for ext board id check: %d\n", 1723 ret); 1724 return ret; 1725 } 1726 1727 if (!result) { 1728 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1729 "ext board id does not exist in otp, ignore it\n"); 1730 return -EOPNOTSUPP; 1731 } 1732 1733 ext_board_id = result & ATH10K_BMI_EBOARD_ID_STATUS_MASK; 1734 1735 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1736 "boot get otp ext board id result 0x%08x ext_board_id %d\n", 1737 result, ext_board_id); 1738 1739 ar->id.bmi_eboard_id = ext_board_id; 1740 1741 return 0; 1742 } 1743 1744 static int ath10k_download_board_data(struct ath10k *ar, const void *data, 1745 size_t data_len) 1746 { 1747 u32 board_data_size = ar->hw_params.fw.board_size; 1748 u32 eboard_data_size = ar->hw_params.fw.ext_board_size; 1749 u32 board_address; 1750 u32 ext_board_address; 1751 int ret; 1752 1753 ret = ath10k_push_board_ext_data(ar, data, data_len); 1754 if (ret) { 1755 ath10k_err(ar, "could not push board ext data (%d)\n", ret); 1756 goto exit; 1757 } 1758 1759 ret = ath10k_bmi_read32(ar, hi_board_data, &board_address); 1760 if (ret) { 1761 ath10k_err(ar, "could not read board data addr (%d)\n", ret); 1762 goto exit; 1763 } 1764 1765 ret = ath10k_bmi_write_memory(ar, board_address, data, 1766 min_t(u32, board_data_size, 1767 data_len)); 1768 if (ret) { 1769 ath10k_err(ar, "could not write board data (%d)\n", ret); 1770 goto exit; 1771 } 1772 1773 ret = ath10k_bmi_write32(ar, hi_board_data_initialized, 1); 1774 if (ret) { 1775 ath10k_err(ar, "could not write board data bit (%d)\n", ret); 1776 goto exit; 1777 } 1778 1779 if (!ar->id.ext_bid_supported) 1780 goto exit; 1781 1782 /* Extended board data download */ 1783 ret = ath10k_core_get_ext_board_id_from_otp(ar); 1784 if (ret == -EOPNOTSUPP) { 1785 /* Not fetching ext_board_data if ext board id is 0 */ 1786 ath10k_dbg(ar, ATH10K_DBG_BOOT, "otp returned ext board id 0\n"); 1787 return 0; 1788 } else if (ret) { 1789 ath10k_err(ar, "failed to get extended board id: %d\n", ret); 1790 goto exit; 1791 } 1792 1793 ret = ath10k_core_fetch_board_file(ar, ATH10K_BD_IE_BOARD_EXT); 1794 if (ret) 1795 goto exit; 1796 1797 if (ar->normal_mode_fw.ext_board_data) { 1798 ext_board_address = board_address + EXT_BOARD_ADDRESS_OFFSET; 1799 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1800 "boot writing ext board data to addr 0x%x", 1801 ext_board_address); 1802 ret = ath10k_bmi_write_memory(ar, ext_board_address, 1803 ar->normal_mode_fw.ext_board_data, 1804 min_t(u32, eboard_data_size, data_len)); 1805 if (ret) 1806 ath10k_err(ar, "failed to write ext board data: %d\n", ret); 1807 } 1808 1809 exit: 1810 return ret; 1811 } 1812 1813 static int ath10k_download_and_run_otp(struct ath10k *ar) 1814 { 1815 u32 result, address = ar->hw_params.patch_load_addr; 1816 u32 bmi_otp_exe_param = ar->hw_params.otp_exe_param; 1817 int ret; 1818 1819 ret = ath10k_download_board_data(ar, 1820 ar->running_fw->board_data, 1821 ar->running_fw->board_len); 1822 if (ret) { 1823 ath10k_err(ar, "failed to download board data: %d\n", ret); 1824 return ret; 1825 } 1826 1827 /* OTP is optional */ 1828 1829 if (!ar->running_fw->fw_file.otp_data || 1830 !ar->running_fw->fw_file.otp_len) { 1831 ath10k_warn(ar, "Not running otp, calibration will be incorrect (otp-data %p otp_len %zd)!\n", 1832 ar->running_fw->fw_file.otp_data, 1833 ar->running_fw->fw_file.otp_len); 1834 return 0; 1835 } 1836 1837 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot upload otp to 0x%x len %zd\n", 1838 address, ar->running_fw->fw_file.otp_len); 1839 1840 ret = ath10k_bmi_fast_download(ar, address, 1841 ar->running_fw->fw_file.otp_data, 1842 ar->running_fw->fw_file.otp_len); 1843 if (ret) { 1844 ath10k_err(ar, "could not write otp (%d)\n", ret); 1845 return ret; 1846 } 1847 1848 /* As of now pre-cal is valid for 10_4 variants */ 1849 if (ar->cal_mode == ATH10K_PRE_CAL_MODE_DT || 1850 ar->cal_mode == ATH10K_PRE_CAL_MODE_FILE || 1851 ar->cal_mode == ATH10K_PRE_CAL_MODE_NVMEM) 1852 bmi_otp_exe_param = BMI_PARAM_FLASH_SECTION_ALL; 1853 1854 ret = ath10k_bmi_execute(ar, address, bmi_otp_exe_param, &result); 1855 if (ret) { 1856 ath10k_err(ar, "could not execute otp (%d)\n", ret); 1857 return ret; 1858 } 1859 1860 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot otp execute result %d\n", result); 1861 1862 if (!(skip_otp || test_bit(ATH10K_FW_FEATURE_IGNORE_OTP_RESULT, 1863 ar->running_fw->fw_file.fw_features)) && 1864 result != 0) { 1865 ath10k_err(ar, "otp calibration failed: %d", result); 1866 return -EINVAL; 1867 } 1868 1869 return 0; 1870 } 1871 1872 static int ath10k_download_cal_file(struct ath10k *ar, 1873 const struct firmware *file) 1874 { 1875 int ret; 1876 1877 if (!file) 1878 return -ENOENT; 1879 1880 if (IS_ERR(file)) 1881 return PTR_ERR(file); 1882 1883 ret = ath10k_download_board_data(ar, file->data, file->size); 1884 if (ret) { 1885 ath10k_err(ar, "failed to download cal_file data: %d\n", ret); 1886 return ret; 1887 } 1888 1889 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cal file downloaded\n"); 1890 1891 return 0; 1892 } 1893 1894 static int ath10k_download_cal_dt(struct ath10k *ar, const char *dt_name) 1895 { 1896 struct device_node *node; 1897 int data_len; 1898 void *data; 1899 int ret; 1900 1901 node = ar->dev->of_node; 1902 if (!node) 1903 /* Device Tree is optional, don't print any warnings if 1904 * there's no node for ath10k. 1905 */ 1906 return -ENOENT; 1907 1908 if (!of_get_property(node, dt_name, &data_len)) { 1909 /* The calibration data node is optional */ 1910 return -ENOENT; 1911 } 1912 1913 if (data_len != ar->hw_params.cal_data_len) { 1914 ath10k_warn(ar, "invalid calibration data length in DT: %d\n", 1915 data_len); 1916 ret = -EMSGSIZE; 1917 goto out; 1918 } 1919 1920 data = kmalloc(data_len, GFP_KERNEL); 1921 if (!data) { 1922 ret = -ENOMEM; 1923 goto out; 1924 } 1925 1926 ret = of_property_read_u8_array(node, dt_name, data, data_len); 1927 if (ret) { 1928 ath10k_warn(ar, "failed to read calibration data from DT: %d\n", 1929 ret); 1930 goto out_free; 1931 } 1932 1933 ret = ath10k_download_board_data(ar, data, data_len); 1934 if (ret) { 1935 ath10k_warn(ar, "failed to download calibration data from Device Tree: %d\n", 1936 ret); 1937 goto out_free; 1938 } 1939 1940 ret = 0; 1941 1942 out_free: 1943 kfree(data); 1944 1945 out: 1946 return ret; 1947 } 1948 1949 static int ath10k_download_cal_eeprom(struct ath10k *ar) 1950 { 1951 size_t data_len; 1952 void *data = NULL; 1953 int ret; 1954 1955 ret = ath10k_hif_fetch_cal_eeprom(ar, &data, &data_len); 1956 if (ret) { 1957 if (ret != -EOPNOTSUPP) 1958 ath10k_warn(ar, "failed to read calibration data from EEPROM: %d\n", 1959 ret); 1960 goto out_free; 1961 } 1962 1963 ret = ath10k_download_board_data(ar, data, data_len); 1964 if (ret) { 1965 ath10k_warn(ar, "failed to download calibration data from EEPROM: %d\n", 1966 ret); 1967 goto out_free; 1968 } 1969 1970 ret = 0; 1971 1972 out_free: 1973 kfree(data); 1974 1975 return ret; 1976 } 1977 1978 static int ath10k_download_cal_nvmem(struct ath10k *ar, const char *cell_name) 1979 { 1980 struct nvmem_cell *cell; 1981 void *buf; 1982 size_t len; 1983 int ret; 1984 1985 cell = devm_nvmem_cell_get(ar->dev, cell_name); 1986 if (IS_ERR(cell)) { 1987 ret = PTR_ERR(cell); 1988 return ret; 1989 } 1990 1991 buf = nvmem_cell_read(cell, &len); 1992 if (IS_ERR(buf)) 1993 return PTR_ERR(buf); 1994 1995 if (ar->hw_params.cal_data_len != len) { 1996 kfree(buf); 1997 ath10k_warn(ar, "invalid calibration data length in nvmem-cell '%s': %zu != %u\n", 1998 cell_name, len, ar->hw_params.cal_data_len); 1999 return -EMSGSIZE; 2000 } 2001 2002 ret = ath10k_download_board_data(ar, buf, len); 2003 kfree(buf); 2004 if (ret) 2005 ath10k_warn(ar, "failed to download calibration data from nvmem-cell '%s': %d\n", 2006 cell_name, ret); 2007 2008 return ret; 2009 } 2010 2011 int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name, 2012 struct ath10k_fw_file *fw_file) 2013 { 2014 size_t magic_len, len, ie_len; 2015 int ie_id, i, index, bit, ret; 2016 struct ath10k_fw_ie *hdr; 2017 const u8 *data; 2018 __le32 *timestamp, *version; 2019 2020 /* first fetch the firmware file (firmware-*.bin) */ 2021 fw_file->firmware = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir, 2022 name); 2023 if (IS_ERR(fw_file->firmware)) 2024 return PTR_ERR(fw_file->firmware); 2025 2026 data = fw_file->firmware->data; 2027 len = fw_file->firmware->size; 2028 2029 /* magic also includes the null byte, check that as well */ 2030 magic_len = strlen(ATH10K_FIRMWARE_MAGIC) + 1; 2031 2032 if (len < magic_len) { 2033 ath10k_err(ar, "firmware file '%s/%s' too small to contain magic: %zu\n", 2034 ar->hw_params.fw.dir, name, len); 2035 ret = -EINVAL; 2036 goto err; 2037 } 2038 2039 if (memcmp(data, ATH10K_FIRMWARE_MAGIC, magic_len) != 0) { 2040 ath10k_err(ar, "invalid firmware magic\n"); 2041 ret = -EINVAL; 2042 goto err; 2043 } 2044 2045 /* jump over the padding */ 2046 magic_len = ALIGN(magic_len, 4); 2047 2048 len -= magic_len; 2049 data += magic_len; 2050 2051 /* loop elements */ 2052 while (len > sizeof(struct ath10k_fw_ie)) { 2053 hdr = (struct ath10k_fw_ie *)data; 2054 2055 ie_id = le32_to_cpu(hdr->id); 2056 ie_len = le32_to_cpu(hdr->len); 2057 2058 len -= sizeof(*hdr); 2059 data += sizeof(*hdr); 2060 2061 if (len < ie_len) { 2062 ath10k_err(ar, "invalid length for FW IE %d (%zu < %zu)\n", 2063 ie_id, len, ie_len); 2064 ret = -EINVAL; 2065 goto err; 2066 } 2067 2068 switch (ie_id) { 2069 case ATH10K_FW_IE_FW_VERSION: 2070 if (ie_len > sizeof(fw_file->fw_version) - 1) 2071 break; 2072 2073 memcpy(fw_file->fw_version, data, ie_len); 2074 fw_file->fw_version[ie_len] = '\0'; 2075 2076 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2077 "found fw version %s\n", 2078 fw_file->fw_version); 2079 break; 2080 case ATH10K_FW_IE_TIMESTAMP: 2081 if (ie_len != sizeof(u32)) 2082 break; 2083 2084 timestamp = (__le32 *)data; 2085 2086 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw timestamp %d\n", 2087 le32_to_cpup(timestamp)); 2088 break; 2089 case ATH10K_FW_IE_FEATURES: 2090 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2091 "found firmware features ie (%zd B)\n", 2092 ie_len); 2093 2094 for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) { 2095 index = i / 8; 2096 bit = i % 8; 2097 2098 if (index == ie_len) 2099 break; 2100 2101 if (data[index] & (1 << bit)) { 2102 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2103 "Enabling feature bit: %i\n", 2104 i); 2105 __set_bit(i, fw_file->fw_features); 2106 } 2107 } 2108 2109 ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "features", "", 2110 fw_file->fw_features, 2111 sizeof(fw_file->fw_features)); 2112 break; 2113 case ATH10K_FW_IE_FW_IMAGE: 2114 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2115 "found fw image ie (%zd B)\n", 2116 ie_len); 2117 2118 fw_file->firmware_data = data; 2119 fw_file->firmware_len = ie_len; 2120 2121 break; 2122 case ATH10K_FW_IE_OTP_IMAGE: 2123 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2124 "found otp image ie (%zd B)\n", 2125 ie_len); 2126 2127 fw_file->otp_data = data; 2128 fw_file->otp_len = ie_len; 2129 2130 break; 2131 case ATH10K_FW_IE_WMI_OP_VERSION: 2132 if (ie_len != sizeof(u32)) 2133 break; 2134 2135 version = (__le32 *)data; 2136 2137 fw_file->wmi_op_version = le32_to_cpup(version); 2138 2139 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie wmi op version %d\n", 2140 fw_file->wmi_op_version); 2141 break; 2142 case ATH10K_FW_IE_HTT_OP_VERSION: 2143 if (ie_len != sizeof(u32)) 2144 break; 2145 2146 version = (__le32 *)data; 2147 2148 fw_file->htt_op_version = le32_to_cpup(version); 2149 2150 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie htt op version %d\n", 2151 fw_file->htt_op_version); 2152 break; 2153 case ATH10K_FW_IE_FW_CODE_SWAP_IMAGE: 2154 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2155 "found fw code swap image ie (%zd B)\n", 2156 ie_len); 2157 fw_file->codeswap_data = data; 2158 fw_file->codeswap_len = ie_len; 2159 break; 2160 default: 2161 ath10k_warn(ar, "Unknown FW IE: %u\n", 2162 le32_to_cpu(hdr->id)); 2163 break; 2164 } 2165 2166 /* jump over the padding */ 2167 ie_len = ALIGN(ie_len, 4); 2168 2169 len -= ie_len; 2170 data += ie_len; 2171 } 2172 2173 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, fw_file->fw_features) && 2174 (!fw_file->firmware_data || !fw_file->firmware_len)) { 2175 ath10k_warn(ar, "No ATH10K_FW_IE_FW_IMAGE found from '%s/%s', skipping\n", 2176 ar->hw_params.fw.dir, name); 2177 ret = -ENOMEDIUM; 2178 goto err; 2179 } 2180 2181 return 0; 2182 2183 err: 2184 ath10k_core_free_firmware_files(ar); 2185 return ret; 2186 } 2187 2188 static void ath10k_core_get_fw_name(struct ath10k *ar, char *fw_name, 2189 size_t fw_name_len, int fw_api) 2190 { 2191 switch (ar->hif.bus) { 2192 case ATH10K_BUS_SDIO: 2193 case ATH10K_BUS_USB: 2194 scnprintf(fw_name, fw_name_len, "%s-%s-%d.bin", 2195 ATH10K_FW_FILE_BASE, ath10k_bus_str(ar->hif.bus), 2196 fw_api); 2197 break; 2198 case ATH10K_BUS_PCI: 2199 case ATH10K_BUS_AHB: 2200 case ATH10K_BUS_SNOC: 2201 scnprintf(fw_name, fw_name_len, "%s-%d.bin", 2202 ATH10K_FW_FILE_BASE, fw_api); 2203 break; 2204 } 2205 } 2206 2207 static int ath10k_core_fetch_firmware_files(struct ath10k *ar) 2208 { 2209 int ret, i; 2210 char fw_name[100]; 2211 2212 /* calibration file is optional, don't check for any errors */ 2213 ath10k_fetch_cal_file(ar); 2214 2215 for (i = ATH10K_FW_API_MAX; i >= ATH10K_FW_API_MIN; i--) { 2216 ar->fw_api = i; 2217 ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", 2218 ar->fw_api); 2219 2220 ath10k_core_get_fw_name(ar, fw_name, sizeof(fw_name), ar->fw_api); 2221 ret = ath10k_core_fetch_firmware_api_n(ar, fw_name, 2222 &ar->normal_mode_fw.fw_file); 2223 if (!ret) 2224 goto success; 2225 } 2226 2227 /* we end up here if we couldn't fetch any firmware */ 2228 2229 ath10k_err(ar, "Failed to find firmware-N.bin (N between %d and %d) from %s: %d", 2230 ATH10K_FW_API_MIN, ATH10K_FW_API_MAX, ar->hw_params.fw.dir, 2231 ret); 2232 2233 return ret; 2234 2235 success: 2236 ath10k_dbg(ar, ATH10K_DBG_BOOT, "using fw api %d\n", ar->fw_api); 2237 2238 return 0; 2239 } 2240 2241 static int ath10k_core_pre_cal_download(struct ath10k *ar) 2242 { 2243 int ret; 2244 2245 ret = ath10k_download_cal_nvmem(ar, "pre-calibration"); 2246 if (ret == 0) { 2247 ar->cal_mode = ATH10K_PRE_CAL_MODE_NVMEM; 2248 goto success; 2249 } else if (ret == -EPROBE_DEFER) { 2250 return ret; 2251 } 2252 2253 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2254 "boot did not find a pre-calibration nvmem-cell, try file next: %d\n", 2255 ret); 2256 2257 ret = ath10k_download_cal_file(ar, ar->pre_cal_file); 2258 if (ret == 0) { 2259 ar->cal_mode = ATH10K_PRE_CAL_MODE_FILE; 2260 goto success; 2261 } 2262 2263 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2264 "boot did not find a pre calibration file, try DT next: %d\n", 2265 ret); 2266 2267 ret = ath10k_download_cal_dt(ar, "qcom,pre-calibration-data"); 2268 if (ret == -ENOENT) 2269 ret = ath10k_download_cal_dt(ar, "qcom,ath10k-pre-calibration-data"); 2270 if (ret) { 2271 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2272 "unable to load pre cal data from DT: %d\n", ret); 2273 return ret; 2274 } 2275 ar->cal_mode = ATH10K_PRE_CAL_MODE_DT; 2276 2277 success: 2278 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n", 2279 ath10k_cal_mode_str(ar->cal_mode)); 2280 2281 return 0; 2282 } 2283 2284 static int ath10k_core_pre_cal_config(struct ath10k *ar) 2285 { 2286 int ret; 2287 2288 ret = ath10k_core_pre_cal_download(ar); 2289 if (ret) { 2290 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2291 "failed to load pre cal data: %d\n", ret); 2292 return ret; 2293 } 2294 2295 ret = ath10k_core_get_board_id_from_otp(ar); 2296 if (ret) { 2297 ath10k_err(ar, "failed to get board id: %d\n", ret); 2298 return ret; 2299 } 2300 2301 ret = ath10k_download_and_run_otp(ar); 2302 if (ret) { 2303 ath10k_err(ar, "failed to run otp: %d\n", ret); 2304 return ret; 2305 } 2306 2307 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2308 "pre cal configuration done successfully\n"); 2309 2310 return 0; 2311 } 2312 2313 static int ath10k_download_cal_data(struct ath10k *ar) 2314 { 2315 int ret; 2316 2317 ret = ath10k_core_pre_cal_config(ar); 2318 if (ret == 0) 2319 return 0; 2320 2321 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2322 "pre cal download procedure failed, try cal file: %d\n", 2323 ret); 2324 2325 ret = ath10k_download_cal_nvmem(ar, "calibration"); 2326 if (ret == 0) { 2327 ar->cal_mode = ATH10K_CAL_MODE_NVMEM; 2328 goto done; 2329 } else if (ret == -EPROBE_DEFER) { 2330 return ret; 2331 } 2332 2333 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2334 "boot did not find a calibration nvmem-cell, try file next: %d\n", 2335 ret); 2336 2337 ret = ath10k_download_cal_file(ar, ar->cal_file); 2338 if (ret == 0) { 2339 ar->cal_mode = ATH10K_CAL_MODE_FILE; 2340 goto done; 2341 } 2342 2343 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2344 "boot did not find a calibration file, try DT next: %d\n", 2345 ret); 2346 2347 ret = ath10k_download_cal_dt(ar, "qcom,calibration-data"); 2348 if (ret == -ENOENT) 2349 ret = ath10k_download_cal_dt(ar, "qcom,ath10k-calibration-data"); 2350 if (ret == 0) { 2351 ar->cal_mode = ATH10K_CAL_MODE_DT; 2352 goto done; 2353 } 2354 2355 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2356 "boot did not find DT entry, try target EEPROM next: %d\n", 2357 ret); 2358 2359 ret = ath10k_download_cal_eeprom(ar); 2360 if (ret == 0) { 2361 ar->cal_mode = ATH10K_CAL_MODE_EEPROM; 2362 goto done; 2363 } 2364 2365 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2366 "boot did not find target EEPROM entry, try OTP next: %d\n", 2367 ret); 2368 2369 ret = ath10k_download_and_run_otp(ar); 2370 if (ret) { 2371 ath10k_err(ar, "failed to run otp: %d\n", ret); 2372 return ret; 2373 } 2374 2375 ar->cal_mode = ATH10K_CAL_MODE_OTP; 2376 2377 done: 2378 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n", 2379 ath10k_cal_mode_str(ar->cal_mode)); 2380 return 0; 2381 } 2382 2383 static void ath10k_core_fetch_btcoex_dt(struct ath10k *ar) 2384 { 2385 struct device_node *node; 2386 u8 coex_support = 0; 2387 int ret; 2388 2389 node = ar->dev->of_node; 2390 if (!node) 2391 goto out; 2392 2393 ret = of_property_read_u8(node, "qcom,coexist-support", &coex_support); 2394 if (ret) { 2395 ar->coex_support = true; 2396 goto out; 2397 } 2398 2399 if (coex_support) { 2400 ar->coex_support = true; 2401 } else { 2402 ar->coex_support = false; 2403 ar->coex_gpio_pin = -1; 2404 goto out; 2405 } 2406 2407 ret = of_property_read_u32(node, "qcom,coexist-gpio-pin", 2408 &ar->coex_gpio_pin); 2409 if (ret) 2410 ar->coex_gpio_pin = -1; 2411 2412 out: 2413 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot coex_support %d coex_gpio_pin %d\n", 2414 ar->coex_support, ar->coex_gpio_pin); 2415 } 2416 2417 static int ath10k_init_uart(struct ath10k *ar) 2418 { 2419 int ret; 2420 2421 /* 2422 * Explicitly setting UART prints to zero as target turns it on 2423 * based on scratch registers. 2424 */ 2425 ret = ath10k_bmi_write32(ar, hi_serial_enable, 0); 2426 if (ret) { 2427 ath10k_warn(ar, "could not disable UART prints (%d)\n", ret); 2428 return ret; 2429 } 2430 2431 if (!uart_print) { 2432 if (ar->hw_params.uart_pin_workaround) { 2433 ret = ath10k_bmi_write32(ar, hi_dbg_uart_txpin, 2434 ar->hw_params.uart_pin); 2435 if (ret) { 2436 ath10k_warn(ar, "failed to set UART TX pin: %d", 2437 ret); 2438 return ret; 2439 } 2440 } 2441 2442 return 0; 2443 } 2444 2445 ret = ath10k_bmi_write32(ar, hi_dbg_uart_txpin, ar->hw_params.uart_pin); 2446 if (ret) { 2447 ath10k_warn(ar, "could not enable UART prints (%d)\n", ret); 2448 return ret; 2449 } 2450 2451 ret = ath10k_bmi_write32(ar, hi_serial_enable, 1); 2452 if (ret) { 2453 ath10k_warn(ar, "could not enable UART prints (%d)\n", ret); 2454 return ret; 2455 } 2456 2457 /* Set the UART baud rate to 19200. */ 2458 ret = ath10k_bmi_write32(ar, hi_desired_baud_rate, 19200); 2459 if (ret) { 2460 ath10k_warn(ar, "could not set the baud rate (%d)\n", ret); 2461 return ret; 2462 } 2463 2464 ath10k_info(ar, "UART prints enabled\n"); 2465 return 0; 2466 } 2467 2468 static int ath10k_init_hw_params(struct ath10k *ar) 2469 { 2470 const struct ath10k_hw_params *hw_params; 2471 int i; 2472 2473 for (i = 0; i < ARRAY_SIZE(ath10k_hw_params_list); i++) { 2474 hw_params = &ath10k_hw_params_list[i]; 2475 2476 if (hw_params->bus == ar->hif.bus && 2477 hw_params->id == ar->target_version && 2478 hw_params->dev_id == ar->dev_id) 2479 break; 2480 } 2481 2482 if (i == ARRAY_SIZE(ath10k_hw_params_list)) { 2483 ath10k_err(ar, "Unsupported hardware version: 0x%x\n", 2484 ar->target_version); 2485 return -EINVAL; 2486 } 2487 2488 ar->hw_params = *hw_params; 2489 2490 ath10k_dbg(ar, ATH10K_DBG_BOOT, "Hardware name %s version 0x%x\n", 2491 ar->hw_params.name, ar->target_version); 2492 2493 return 0; 2494 } 2495 2496 static bool ath10k_core_needs_recovery(struct ath10k *ar) 2497 { 2498 long time_left; 2499 2500 /* Sometimes the recovery will fail and then the next all recovery fail, 2501 * so avoid infinite recovery. 2502 */ 2503 if (atomic_read(&ar->fail_cont_count) >= ATH10K_RECOVERY_MAX_FAIL_COUNT) { 2504 ath10k_err(ar, "consecutive fail %d times, will shutdown driver!", 2505 atomic_read(&ar->fail_cont_count)); 2506 ar->state = ATH10K_STATE_WEDGED; 2507 return false; 2508 } 2509 2510 ath10k_dbg(ar, ATH10K_DBG_BOOT, "total recovery count: %d", ++ar->recovery_count); 2511 2512 if (atomic_read(&ar->pending_recovery)) { 2513 /* Sometimes it happened another recovery work before the previous one 2514 * completed, then the second recovery work will destroy the previous 2515 * one, thus below is to avoid that. 2516 */ 2517 time_left = wait_for_completion_timeout(&ar->driver_recovery, 2518 ATH10K_RECOVERY_TIMEOUT_HZ); 2519 if (time_left) { 2520 ath10k_warn(ar, "previous recovery succeeded, skip this!\n"); 2521 return false; 2522 } 2523 2524 /* Record the continuous recovery fail count when recovery failed. */ 2525 atomic_inc(&ar->fail_cont_count); 2526 2527 /* Avoid having multiple recoveries at the same time. */ 2528 return false; 2529 } 2530 2531 atomic_inc(&ar->pending_recovery); 2532 2533 return true; 2534 } 2535 2536 void ath10k_core_start_recovery(struct ath10k *ar) 2537 { 2538 if (!ath10k_core_needs_recovery(ar)) 2539 return; 2540 2541 queue_work(ar->workqueue, &ar->restart_work); 2542 } 2543 EXPORT_SYMBOL(ath10k_core_start_recovery); 2544 2545 void ath10k_core_napi_enable(struct ath10k *ar) 2546 { 2547 lockdep_assert_held(&ar->conf_mutex); 2548 2549 if (test_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags)) 2550 return; 2551 2552 napi_enable(&ar->napi); 2553 set_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags); 2554 } 2555 EXPORT_SYMBOL(ath10k_core_napi_enable); 2556 2557 void ath10k_core_napi_sync_disable(struct ath10k *ar) 2558 { 2559 lockdep_assert_held(&ar->conf_mutex); 2560 2561 if (!test_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags)) 2562 return; 2563 2564 napi_synchronize(&ar->napi); 2565 napi_disable(&ar->napi); 2566 clear_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags); 2567 } 2568 EXPORT_SYMBOL(ath10k_core_napi_sync_disable); 2569 2570 static void ath10k_core_restart(struct work_struct *work) 2571 { 2572 struct ath10k *ar = container_of(work, struct ath10k, restart_work); 2573 int ret; 2574 2575 reinit_completion(&ar->driver_recovery); 2576 2577 set_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags); 2578 2579 /* Place a barrier to make sure the compiler doesn't reorder 2580 * CRASH_FLUSH and calling other functions. 2581 */ 2582 barrier(); 2583 2584 ieee80211_stop_queues(ar->hw); 2585 ath10k_drain_tx(ar); 2586 complete(&ar->scan.started); 2587 complete(&ar->scan.completed); 2588 complete(&ar->scan.on_channel); 2589 complete(&ar->offchan_tx_completed); 2590 complete(&ar->install_key_done); 2591 complete(&ar->vdev_setup_done); 2592 complete(&ar->vdev_delete_done); 2593 complete(&ar->thermal.wmi_sync); 2594 complete(&ar->bss_survey_done); 2595 wake_up(&ar->htt.empty_tx_wq); 2596 wake_up(&ar->wmi.tx_credits_wq); 2597 wake_up(&ar->peer_mapping_wq); 2598 2599 /* TODO: We can have one instance of cancelling coverage_class_work by 2600 * moving it to ath10k_halt(), so that both stop() and restart() would 2601 * call that but it takes conf_mutex() and if we call cancel_work_sync() 2602 * with conf_mutex it will deadlock. 2603 */ 2604 cancel_work_sync(&ar->set_coverage_class_work); 2605 2606 mutex_lock(&ar->conf_mutex); 2607 2608 switch (ar->state) { 2609 case ATH10K_STATE_ON: 2610 ar->state = ATH10K_STATE_RESTARTING; 2611 ath10k_halt(ar); 2612 ath10k_scan_finish(ar); 2613 ieee80211_restart_hw(ar->hw); 2614 break; 2615 case ATH10K_STATE_OFF: 2616 /* this can happen if driver is being unloaded 2617 * or if the crash happens during FW probing 2618 */ 2619 ath10k_warn(ar, "cannot restart a device that hasn't been started\n"); 2620 break; 2621 case ATH10K_STATE_RESTARTING: 2622 /* hw restart might be requested from multiple places */ 2623 break; 2624 case ATH10K_STATE_RESTARTED: 2625 ar->state = ATH10K_STATE_WEDGED; 2626 fallthrough; 2627 case ATH10K_STATE_WEDGED: 2628 ath10k_warn(ar, "device is wedged, will not restart\n"); 2629 break; 2630 case ATH10K_STATE_UTF: 2631 ath10k_warn(ar, "firmware restart in UTF mode not supported\n"); 2632 break; 2633 } 2634 2635 mutex_unlock(&ar->conf_mutex); 2636 2637 ret = ath10k_coredump_submit(ar); 2638 if (ret) 2639 ath10k_warn(ar, "failed to send firmware crash dump via devcoredump: %d", 2640 ret); 2641 } 2642 2643 static void ath10k_core_set_coverage_class_work(struct work_struct *work) 2644 { 2645 struct ath10k *ar = container_of(work, struct ath10k, 2646 set_coverage_class_work); 2647 2648 if (ar->hw_params.hw_ops->set_coverage_class) 2649 ar->hw_params.hw_ops->set_coverage_class(ar, -1, -1); 2650 } 2651 2652 static int ath10k_core_init_firmware_features(struct ath10k *ar) 2653 { 2654 struct ath10k_fw_file *fw_file = &ar->normal_mode_fw.fw_file; 2655 int max_num_peers; 2656 2657 if (test_bit(ATH10K_FW_FEATURE_WMI_10_2, fw_file->fw_features) && 2658 !test_bit(ATH10K_FW_FEATURE_WMI_10X, fw_file->fw_features)) { 2659 ath10k_err(ar, "feature bits corrupted: 10.2 feature requires 10.x feature to be set as well"); 2660 return -EINVAL; 2661 } 2662 2663 if (fw_file->wmi_op_version >= ATH10K_FW_WMI_OP_VERSION_MAX) { 2664 ath10k_err(ar, "unsupported WMI OP version (max %d): %d\n", 2665 ATH10K_FW_WMI_OP_VERSION_MAX, fw_file->wmi_op_version); 2666 return -EINVAL; 2667 } 2668 2669 ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_NATIVE_WIFI; 2670 switch (ath10k_cryptmode_param) { 2671 case ATH10K_CRYPT_MODE_HW: 2672 clear_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags); 2673 clear_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags); 2674 break; 2675 case ATH10K_CRYPT_MODE_SW: 2676 if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT, 2677 fw_file->fw_features)) { 2678 ath10k_err(ar, "cryptmode > 0 requires raw mode support from firmware"); 2679 return -EINVAL; 2680 } 2681 2682 set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags); 2683 set_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags); 2684 break; 2685 default: 2686 ath10k_info(ar, "invalid cryptmode: %d\n", 2687 ath10k_cryptmode_param); 2688 return -EINVAL; 2689 } 2690 2691 ar->htt.max_num_amsdu = ATH10K_HTT_MAX_NUM_AMSDU_DEFAULT; 2692 ar->htt.max_num_ampdu = ATH10K_HTT_MAX_NUM_AMPDU_DEFAULT; 2693 2694 if (ath10k_frame_mode == ATH10K_HW_TXRX_RAW) { 2695 if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT, 2696 fw_file->fw_features)) { 2697 ath10k_err(ar, "rawmode = 1 requires support from firmware"); 2698 return -EINVAL; 2699 } 2700 set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags); 2701 } 2702 2703 if (test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) { 2704 ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_RAW; 2705 2706 /* Workaround: 2707 * 2708 * Firmware A-MSDU aggregation breaks with RAW Tx encap mode 2709 * and causes enormous performance issues (malformed frames, 2710 * etc). 2711 * 2712 * Disabling A-MSDU makes RAW mode stable with heavy traffic 2713 * albeit a bit slower compared to regular operation. 2714 */ 2715 ar->htt.max_num_amsdu = 1; 2716 } 2717 2718 /* Backwards compatibility for firmwares without 2719 * ATH10K_FW_IE_WMI_OP_VERSION. 2720 */ 2721 if (fw_file->wmi_op_version == ATH10K_FW_WMI_OP_VERSION_UNSET) { 2722 if (test_bit(ATH10K_FW_FEATURE_WMI_10X, fw_file->fw_features)) { 2723 if (test_bit(ATH10K_FW_FEATURE_WMI_10_2, 2724 fw_file->fw_features)) 2725 fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_10_2; 2726 else 2727 fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_10_1; 2728 } else { 2729 fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_MAIN; 2730 } 2731 } 2732 2733 switch (fw_file->wmi_op_version) { 2734 case ATH10K_FW_WMI_OP_VERSION_MAIN: 2735 max_num_peers = TARGET_NUM_PEERS; 2736 ar->max_num_stations = TARGET_NUM_STATIONS; 2737 ar->max_num_vdevs = TARGET_NUM_VDEVS; 2738 ar->htt.max_num_pending_tx = TARGET_NUM_MSDU_DESC; 2739 ar->fw_stats_req_mask = WMI_STAT_PDEV | WMI_STAT_VDEV | 2740 WMI_STAT_PEER; 2741 ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM; 2742 break; 2743 case ATH10K_FW_WMI_OP_VERSION_10_1: 2744 case ATH10K_FW_WMI_OP_VERSION_10_2: 2745 case ATH10K_FW_WMI_OP_VERSION_10_2_4: 2746 if (ath10k_peer_stats_enabled(ar)) { 2747 max_num_peers = TARGET_10X_TX_STATS_NUM_PEERS; 2748 ar->max_num_stations = TARGET_10X_TX_STATS_NUM_STATIONS; 2749 } else { 2750 max_num_peers = TARGET_10X_NUM_PEERS; 2751 ar->max_num_stations = TARGET_10X_NUM_STATIONS; 2752 } 2753 ar->max_num_vdevs = TARGET_10X_NUM_VDEVS; 2754 ar->htt.max_num_pending_tx = TARGET_10X_NUM_MSDU_DESC; 2755 ar->fw_stats_req_mask = WMI_STAT_PEER; 2756 ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM; 2757 break; 2758 case ATH10K_FW_WMI_OP_VERSION_TLV: 2759 max_num_peers = TARGET_TLV_NUM_PEERS; 2760 ar->max_num_stations = TARGET_TLV_NUM_STATIONS; 2761 ar->max_num_vdevs = TARGET_TLV_NUM_VDEVS; 2762 ar->max_num_tdls_vdevs = TARGET_TLV_NUM_TDLS_VDEVS; 2763 if (ar->hif.bus == ATH10K_BUS_SDIO) 2764 ar->htt.max_num_pending_tx = 2765 TARGET_TLV_NUM_MSDU_DESC_HL; 2766 else 2767 ar->htt.max_num_pending_tx = TARGET_TLV_NUM_MSDU_DESC; 2768 ar->wow.max_num_patterns = TARGET_TLV_NUM_WOW_PATTERNS; 2769 ar->fw_stats_req_mask = WMI_TLV_STAT_PDEV | WMI_TLV_STAT_VDEV | 2770 WMI_TLV_STAT_PEER | WMI_TLV_STAT_PEER_EXTD; 2771 ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM; 2772 ar->wmi.mgmt_max_num_pending_tx = TARGET_TLV_MGMT_NUM_MSDU_DESC; 2773 break; 2774 case ATH10K_FW_WMI_OP_VERSION_10_4: 2775 max_num_peers = TARGET_10_4_NUM_PEERS; 2776 ar->max_num_stations = TARGET_10_4_NUM_STATIONS; 2777 ar->num_active_peers = TARGET_10_4_ACTIVE_PEERS; 2778 ar->max_num_vdevs = TARGET_10_4_NUM_VDEVS; 2779 ar->num_tids = TARGET_10_4_TGT_NUM_TIDS; 2780 ar->fw_stats_req_mask = WMI_10_4_STAT_PEER | 2781 WMI_10_4_STAT_PEER_EXTD | 2782 WMI_10_4_STAT_VDEV_EXTD; 2783 ar->max_spatial_stream = ar->hw_params.max_spatial_stream; 2784 ar->max_num_tdls_vdevs = TARGET_10_4_NUM_TDLS_VDEVS; 2785 2786 if (test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, 2787 fw_file->fw_features)) 2788 ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC_PFC; 2789 else 2790 ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC; 2791 break; 2792 case ATH10K_FW_WMI_OP_VERSION_UNSET: 2793 case ATH10K_FW_WMI_OP_VERSION_MAX: 2794 default: 2795 WARN_ON(1); 2796 return -EINVAL; 2797 } 2798 2799 if (ar->hw_params.num_peers) 2800 ar->max_num_peers = ar->hw_params.num_peers; 2801 else 2802 ar->max_num_peers = max_num_peers; 2803 2804 /* Backwards compatibility for firmwares without 2805 * ATH10K_FW_IE_HTT_OP_VERSION. 2806 */ 2807 if (fw_file->htt_op_version == ATH10K_FW_HTT_OP_VERSION_UNSET) { 2808 switch (fw_file->wmi_op_version) { 2809 case ATH10K_FW_WMI_OP_VERSION_MAIN: 2810 fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_MAIN; 2811 break; 2812 case ATH10K_FW_WMI_OP_VERSION_10_1: 2813 case ATH10K_FW_WMI_OP_VERSION_10_2: 2814 case ATH10K_FW_WMI_OP_VERSION_10_2_4: 2815 fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_10_1; 2816 break; 2817 case ATH10K_FW_WMI_OP_VERSION_TLV: 2818 fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_TLV; 2819 break; 2820 case ATH10K_FW_WMI_OP_VERSION_10_4: 2821 case ATH10K_FW_WMI_OP_VERSION_UNSET: 2822 case ATH10K_FW_WMI_OP_VERSION_MAX: 2823 ath10k_err(ar, "htt op version not found from fw meta data"); 2824 return -EINVAL; 2825 } 2826 } 2827 2828 return 0; 2829 } 2830 2831 static int ath10k_core_reset_rx_filter(struct ath10k *ar) 2832 { 2833 int ret; 2834 int vdev_id; 2835 int vdev_type; 2836 int vdev_subtype; 2837 const u8 *vdev_addr; 2838 2839 vdev_id = 0; 2840 vdev_type = WMI_VDEV_TYPE_STA; 2841 vdev_subtype = ath10k_wmi_get_vdev_subtype(ar, WMI_VDEV_SUBTYPE_NONE); 2842 vdev_addr = ar->mac_addr; 2843 2844 ret = ath10k_wmi_vdev_create(ar, vdev_id, vdev_type, vdev_subtype, 2845 vdev_addr); 2846 if (ret) { 2847 ath10k_err(ar, "failed to create dummy vdev: %d\n", ret); 2848 return ret; 2849 } 2850 2851 ret = ath10k_wmi_vdev_delete(ar, vdev_id); 2852 if (ret) { 2853 ath10k_err(ar, "failed to delete dummy vdev: %d\n", ret); 2854 return ret; 2855 } 2856 2857 /* WMI and HTT may use separate HIF pipes and are not guaranteed to be 2858 * serialized properly implicitly. 2859 * 2860 * Moreover (most) WMI commands have no explicit acknowledges. It is 2861 * possible to infer it implicitly by poking firmware with echo 2862 * command - getting a reply means all preceding comments have been 2863 * (mostly) processed. 2864 * 2865 * In case of vdev create/delete this is sufficient. 2866 * 2867 * Without this it's possible to end up with a race when HTT Rx ring is 2868 * started before vdev create/delete hack is complete allowing a short 2869 * window of opportunity to receive (and Tx ACK) a bunch of frames. 2870 */ 2871 ret = ath10k_wmi_barrier(ar); 2872 if (ret) { 2873 ath10k_err(ar, "failed to ping firmware: %d\n", ret); 2874 return ret; 2875 } 2876 2877 return 0; 2878 } 2879 2880 static int ath10k_core_compat_services(struct ath10k *ar) 2881 { 2882 struct ath10k_fw_file *fw_file = &ar->normal_mode_fw.fw_file; 2883 2884 /* all 10.x firmware versions support thermal throttling but don't 2885 * advertise the support via service flags so we have to hardcode 2886 * it here 2887 */ 2888 switch (fw_file->wmi_op_version) { 2889 case ATH10K_FW_WMI_OP_VERSION_10_1: 2890 case ATH10K_FW_WMI_OP_VERSION_10_2: 2891 case ATH10K_FW_WMI_OP_VERSION_10_2_4: 2892 case ATH10K_FW_WMI_OP_VERSION_10_4: 2893 set_bit(WMI_SERVICE_THERM_THROT, ar->wmi.svc_map); 2894 break; 2895 default: 2896 break; 2897 } 2898 2899 return 0; 2900 } 2901 2902 #define TGT_IRAM_READ_PER_ITR (8 * 1024) 2903 2904 static int ath10k_core_copy_target_iram(struct ath10k *ar) 2905 { 2906 const struct ath10k_hw_mem_layout *hw_mem; 2907 const struct ath10k_mem_region *tmp, *mem_region = NULL; 2908 dma_addr_t paddr; 2909 void *vaddr = NULL; 2910 u8 num_read_itr; 2911 int i, ret; 2912 u32 len, remaining_len; 2913 2914 /* copy target iram feature must work also when 2915 * ATH10K_FW_CRASH_DUMP_RAM_DATA is disabled, so 2916 * _ath10k_coredump_get_mem_layout() to accomplist that 2917 */ 2918 hw_mem = _ath10k_coredump_get_mem_layout(ar); 2919 if (!hw_mem) 2920 /* if CONFIG_DEV_COREDUMP is disabled we get NULL, then 2921 * just silently disable the feature by doing nothing 2922 */ 2923 return 0; 2924 2925 for (i = 0; i < hw_mem->region_table.size; i++) { 2926 tmp = &hw_mem->region_table.regions[i]; 2927 if (tmp->type == ATH10K_MEM_REGION_TYPE_REG) { 2928 mem_region = tmp; 2929 break; 2930 } 2931 } 2932 2933 if (!mem_region) 2934 return -ENOMEM; 2935 2936 for (i = 0; i < ar->wmi.num_mem_chunks; i++) { 2937 if (ar->wmi.mem_chunks[i].req_id == 2938 WMI_IRAM_RECOVERY_HOST_MEM_REQ_ID) { 2939 vaddr = ar->wmi.mem_chunks[i].vaddr; 2940 len = ar->wmi.mem_chunks[i].len; 2941 break; 2942 } 2943 } 2944 2945 if (!vaddr || !len) { 2946 ath10k_warn(ar, "No allocated memory for IRAM back up"); 2947 return -ENOMEM; 2948 } 2949 2950 len = (len < mem_region->len) ? len : mem_region->len; 2951 paddr = mem_region->start; 2952 num_read_itr = len / TGT_IRAM_READ_PER_ITR; 2953 remaining_len = len % TGT_IRAM_READ_PER_ITR; 2954 for (i = 0; i < num_read_itr; i++) { 2955 ret = ath10k_hif_diag_read(ar, paddr, vaddr, 2956 TGT_IRAM_READ_PER_ITR); 2957 if (ret) { 2958 ath10k_warn(ar, "failed to copy firmware IRAM contents: %d", 2959 ret); 2960 return ret; 2961 } 2962 2963 paddr += TGT_IRAM_READ_PER_ITR; 2964 vaddr += TGT_IRAM_READ_PER_ITR; 2965 } 2966 2967 if (remaining_len) { 2968 ret = ath10k_hif_diag_read(ar, paddr, vaddr, remaining_len); 2969 if (ret) { 2970 ath10k_warn(ar, "failed to copy firmware IRAM contents: %d", 2971 ret); 2972 return ret; 2973 } 2974 } 2975 2976 ath10k_dbg(ar, ATH10K_DBG_BOOT, "target IRAM back up completed\n"); 2977 2978 return 0; 2979 } 2980 2981 int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode, 2982 const struct ath10k_fw_components *fw) 2983 { 2984 int status; 2985 u32 val; 2986 2987 lockdep_assert_held(&ar->conf_mutex); 2988 2989 clear_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags); 2990 2991 ar->running_fw = fw; 2992 2993 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, 2994 ar->running_fw->fw_file.fw_features)) { 2995 ath10k_bmi_start(ar); 2996 2997 /* Enable hardware clock to speed up firmware download */ 2998 if (ar->hw_params.hw_ops->enable_pll_clk) { 2999 status = ar->hw_params.hw_ops->enable_pll_clk(ar); 3000 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot enable pll ret %d\n", 3001 status); 3002 } 3003 3004 if (ath10k_init_configure_target(ar)) { 3005 status = -EINVAL; 3006 goto err; 3007 } 3008 3009 status = ath10k_download_cal_data(ar); 3010 if (status) 3011 goto err; 3012 3013 /* Some of qca988x solutions are having global reset issue 3014 * during target initialization. Bypassing PLL setting before 3015 * downloading firmware and letting the SoC run on REF_CLK is 3016 * fixing the problem. Corresponding firmware change is also 3017 * needed to set the clock source once the target is 3018 * initialized. 3019 */ 3020 if (test_bit(ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT, 3021 ar->running_fw->fw_file.fw_features)) { 3022 status = ath10k_bmi_write32(ar, hi_skip_clock_init, 1); 3023 if (status) { 3024 ath10k_err(ar, "could not write to skip_clock_init: %d\n", 3025 status); 3026 goto err; 3027 } 3028 } 3029 3030 status = ath10k_download_fw(ar); 3031 if (status) 3032 goto err; 3033 3034 status = ath10k_init_uart(ar); 3035 if (status) 3036 goto err; 3037 3038 if (ar->hif.bus == ATH10K_BUS_SDIO) { 3039 status = ath10k_init_sdio(ar, mode); 3040 if (status) { 3041 ath10k_err(ar, "failed to init SDIO: %d\n", status); 3042 goto err; 3043 } 3044 } 3045 } 3046 3047 ar->htc.htc_ops.target_send_suspend_complete = 3048 ath10k_send_suspend_complete; 3049 3050 status = ath10k_htc_init(ar); 3051 if (status) { 3052 ath10k_err(ar, "could not init HTC (%d)\n", status); 3053 goto err; 3054 } 3055 3056 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, 3057 ar->running_fw->fw_file.fw_features)) { 3058 status = ath10k_bmi_done(ar); 3059 if (status) 3060 goto err; 3061 } 3062 3063 status = ath10k_wmi_attach(ar); 3064 if (status) { 3065 ath10k_err(ar, "WMI attach failed: %d\n", status); 3066 goto err; 3067 } 3068 3069 status = ath10k_htt_init(ar); 3070 if (status) { 3071 ath10k_err(ar, "failed to init htt: %d\n", status); 3072 goto err_wmi_detach; 3073 } 3074 3075 status = ath10k_htt_tx_start(&ar->htt); 3076 if (status) { 3077 ath10k_err(ar, "failed to alloc htt tx: %d\n", status); 3078 goto err_wmi_detach; 3079 } 3080 3081 /* If firmware indicates Full Rx Reorder support it must be used in a 3082 * slightly different manner. Let HTT code know. 3083 */ 3084 ar->htt.rx_ring.in_ord_rx = !!(test_bit(WMI_SERVICE_RX_FULL_REORDER, 3085 ar->wmi.svc_map)); 3086 3087 status = ath10k_htt_rx_alloc(&ar->htt); 3088 if (status) { 3089 ath10k_err(ar, "failed to alloc htt rx: %d\n", status); 3090 goto err_htt_tx_detach; 3091 } 3092 3093 status = ath10k_hif_start(ar); 3094 if (status) { 3095 ath10k_err(ar, "could not start HIF: %d\n", status); 3096 goto err_htt_rx_detach; 3097 } 3098 3099 status = ath10k_htc_wait_target(&ar->htc); 3100 if (status) { 3101 ath10k_err(ar, "failed to connect to HTC: %d\n", status); 3102 goto err_hif_stop; 3103 } 3104 3105 status = ath10k_hif_start_post(ar); 3106 if (status) { 3107 ath10k_err(ar, "failed to swap mailbox: %d\n", status); 3108 goto err_hif_stop; 3109 } 3110 3111 if (mode == ATH10K_FIRMWARE_MODE_NORMAL) { 3112 status = ath10k_htt_connect(&ar->htt); 3113 if (status) { 3114 ath10k_err(ar, "failed to connect htt (%d)\n", status); 3115 goto err_hif_stop; 3116 } 3117 } 3118 3119 status = ath10k_wmi_connect(ar); 3120 if (status) { 3121 ath10k_err(ar, "could not connect wmi: %d\n", status); 3122 goto err_hif_stop; 3123 } 3124 3125 status = ath10k_htc_start(&ar->htc); 3126 if (status) { 3127 ath10k_err(ar, "failed to start htc: %d\n", status); 3128 goto err_hif_stop; 3129 } 3130 3131 if (mode == ATH10K_FIRMWARE_MODE_NORMAL) { 3132 status = ath10k_wmi_wait_for_service_ready(ar); 3133 if (status) { 3134 ath10k_warn(ar, "wmi service ready event not received"); 3135 goto err_hif_stop; 3136 } 3137 } 3138 3139 ath10k_dbg(ar, ATH10K_DBG_BOOT, "firmware %s booted\n", 3140 ar->hw->wiphy->fw_version); 3141 3142 if (test_bit(ATH10K_FW_FEATURE_IRAM_RECOVERY, 3143 ar->running_fw->fw_file.fw_features)) { 3144 status = ath10k_core_copy_target_iram(ar); 3145 if (status) { 3146 ath10k_warn(ar, "failed to copy target iram contents: %d", 3147 status); 3148 goto err_hif_stop; 3149 } 3150 } 3151 3152 if (test_bit(WMI_SERVICE_EXT_RES_CFG_SUPPORT, ar->wmi.svc_map) && 3153 mode == ATH10K_FIRMWARE_MODE_NORMAL) { 3154 val = 0; 3155 if (ath10k_peer_stats_enabled(ar)) 3156 val = WMI_10_4_PEER_STATS; 3157 3158 /* Enable vdev stats by default */ 3159 val |= WMI_10_4_VDEV_STATS; 3160 3161 if (test_bit(WMI_SERVICE_BSS_CHANNEL_INFO_64, ar->wmi.svc_map)) 3162 val |= WMI_10_4_BSS_CHANNEL_INFO_64; 3163 3164 ath10k_core_fetch_btcoex_dt(ar); 3165 3166 /* 10.4 firmware supports BT-Coex without reloading firmware 3167 * via pdev param. To support Bluetooth coexistence pdev param, 3168 * WMI_COEX_GPIO_SUPPORT of extended resource config should be 3169 * enabled always. 3170 * 3171 * We can still enable BTCOEX if firmware has the support 3172 * even though btceox_support value is 3173 * ATH10K_DT_BTCOEX_NOT_FOUND 3174 */ 3175 3176 if (test_bit(WMI_SERVICE_COEX_GPIO, ar->wmi.svc_map) && 3177 test_bit(ATH10K_FW_FEATURE_BTCOEX_PARAM, 3178 ar->running_fw->fw_file.fw_features) && 3179 ar->coex_support) 3180 val |= WMI_10_4_COEX_GPIO_SUPPORT; 3181 3182 if (test_bit(WMI_SERVICE_TDLS_EXPLICIT_MODE_ONLY, 3183 ar->wmi.svc_map)) 3184 val |= WMI_10_4_TDLS_EXPLICIT_MODE_ONLY; 3185 3186 if (test_bit(WMI_SERVICE_TDLS_UAPSD_BUFFER_STA, 3187 ar->wmi.svc_map)) 3188 val |= WMI_10_4_TDLS_UAPSD_BUFFER_STA; 3189 3190 if (test_bit(WMI_SERVICE_TX_DATA_ACK_RSSI, 3191 ar->wmi.svc_map)) 3192 val |= WMI_10_4_TX_DATA_ACK_RSSI; 3193 3194 if (test_bit(WMI_SERVICE_REPORT_AIRTIME, ar->wmi.svc_map)) 3195 val |= WMI_10_4_REPORT_AIRTIME; 3196 3197 if (test_bit(WMI_SERVICE_EXT_PEER_TID_CONFIGS_SUPPORT, 3198 ar->wmi.svc_map)) 3199 val |= WMI_10_4_EXT_PEER_TID_CONFIGS_SUPPORT; 3200 3201 status = ath10k_mac_ext_resource_config(ar, val); 3202 if (status) { 3203 ath10k_err(ar, 3204 "failed to send ext resource cfg command : %d\n", 3205 status); 3206 goto err_hif_stop; 3207 } 3208 } 3209 3210 status = ath10k_wmi_cmd_init(ar); 3211 if (status) { 3212 ath10k_err(ar, "could not send WMI init command (%d)\n", 3213 status); 3214 goto err_hif_stop; 3215 } 3216 3217 status = ath10k_wmi_wait_for_unified_ready(ar); 3218 if (status) { 3219 ath10k_err(ar, "wmi unified ready event not received\n"); 3220 goto err_hif_stop; 3221 } 3222 3223 status = ath10k_core_compat_services(ar); 3224 if (status) { 3225 ath10k_err(ar, "compat services failed: %d\n", status); 3226 goto err_hif_stop; 3227 } 3228 3229 status = ath10k_wmi_pdev_set_base_macaddr(ar, ar->mac_addr); 3230 if (status && status != -EOPNOTSUPP) { 3231 ath10k_err(ar, 3232 "failed to set base mac address: %d\n", status); 3233 goto err_hif_stop; 3234 } 3235 3236 /* Some firmware revisions do not properly set up hardware rx filter 3237 * registers. 3238 * 3239 * A known example from QCA9880 and 10.2.4 is that MAC_PCU_ADDR1_MASK 3240 * is filled with 0s instead of 1s allowing HW to respond with ACKs to 3241 * any frames that matches MAC_PCU_RX_FILTER which is also 3242 * misconfigured to accept anything. 3243 * 3244 * The ADDR1 is programmed using internal firmware structure field and 3245 * can't be (easily/sanely) reached from the driver explicitly. It is 3246 * possible to implicitly make it correct by creating a dummy vdev and 3247 * then deleting it. 3248 */ 3249 if (ar->hw_params.hw_filter_reset_required && 3250 mode == ATH10K_FIRMWARE_MODE_NORMAL) { 3251 status = ath10k_core_reset_rx_filter(ar); 3252 if (status) { 3253 ath10k_err(ar, 3254 "failed to reset rx filter: %d\n", status); 3255 goto err_hif_stop; 3256 } 3257 } 3258 3259 status = ath10k_htt_rx_ring_refill(ar); 3260 if (status) { 3261 ath10k_err(ar, "failed to refill htt rx ring: %d\n", status); 3262 goto err_hif_stop; 3263 } 3264 3265 if (ar->max_num_vdevs >= 64) 3266 ar->free_vdev_map = 0xFFFFFFFFFFFFFFFFLL; 3267 else 3268 ar->free_vdev_map = (1LL << ar->max_num_vdevs) - 1; 3269 3270 INIT_LIST_HEAD(&ar->arvifs); 3271 3272 /* we don't care about HTT in UTF mode */ 3273 if (mode == ATH10K_FIRMWARE_MODE_NORMAL) { 3274 status = ath10k_htt_setup(&ar->htt); 3275 if (status) { 3276 ath10k_err(ar, "failed to setup htt: %d\n", status); 3277 goto err_hif_stop; 3278 } 3279 } 3280 3281 status = ath10k_debug_start(ar); 3282 if (status) 3283 goto err_hif_stop; 3284 3285 status = ath10k_hif_set_target_log_mode(ar, fw_diag_log); 3286 if (status && status != -EOPNOTSUPP) { 3287 ath10k_warn(ar, "set target log mode failed: %d\n", status); 3288 goto err_hif_stop; 3289 } 3290 3291 status = ath10k_leds_start(ar); 3292 if (status) 3293 goto err_hif_stop; 3294 3295 return 0; 3296 3297 err_hif_stop: 3298 ath10k_hif_stop(ar); 3299 err_htt_rx_detach: 3300 ath10k_htt_rx_free(&ar->htt); 3301 err_htt_tx_detach: 3302 ath10k_htt_tx_free(&ar->htt); 3303 err_wmi_detach: 3304 ath10k_wmi_detach(ar); 3305 err: 3306 return status; 3307 } 3308 EXPORT_SYMBOL(ath10k_core_start); 3309 3310 int ath10k_wait_for_suspend(struct ath10k *ar, u32 suspend_opt) 3311 { 3312 int ret; 3313 unsigned long time_left; 3314 3315 reinit_completion(&ar->target_suspend); 3316 3317 ret = ath10k_wmi_pdev_suspend_target(ar, suspend_opt); 3318 if (ret) { 3319 ath10k_warn(ar, "could not suspend target (%d)\n", ret); 3320 return ret; 3321 } 3322 3323 time_left = wait_for_completion_timeout(&ar->target_suspend, 1 * HZ); 3324 3325 if (!time_left) { 3326 ath10k_warn(ar, "suspend timed out - target pause event never came\n"); 3327 return -ETIMEDOUT; 3328 } 3329 3330 return 0; 3331 } 3332 3333 void ath10k_core_stop(struct ath10k *ar) 3334 { 3335 lockdep_assert_held(&ar->conf_mutex); 3336 ath10k_debug_stop(ar); 3337 3338 /* try to suspend target */ 3339 if (ar->state != ATH10K_STATE_RESTARTING && 3340 ar->state != ATH10K_STATE_UTF) 3341 ath10k_wait_for_suspend(ar, WMI_PDEV_SUSPEND_AND_DISABLE_INTR); 3342 3343 ath10k_hif_stop(ar); 3344 ath10k_htt_tx_stop(&ar->htt); 3345 ath10k_htt_rx_free(&ar->htt); 3346 ath10k_wmi_detach(ar); 3347 3348 ar->id.bmi_ids_valid = false; 3349 } 3350 EXPORT_SYMBOL(ath10k_core_stop); 3351 3352 /* mac80211 manages fw/hw initialization through start/stop hooks. However in 3353 * order to know what hw capabilities should be advertised to mac80211 it is 3354 * necessary to load the firmware (and tear it down immediately since start 3355 * hook will try to init it again) before registering 3356 */ 3357 static int ath10k_core_probe_fw(struct ath10k *ar) 3358 { 3359 struct bmi_target_info target_info; 3360 int ret = 0; 3361 3362 ret = ath10k_hif_power_up(ar, ATH10K_FIRMWARE_MODE_NORMAL); 3363 if (ret) { 3364 ath10k_err(ar, "could not power on hif bus (%d)\n", ret); 3365 return ret; 3366 } 3367 3368 switch (ar->hif.bus) { 3369 case ATH10K_BUS_SDIO: 3370 memset(&target_info, 0, sizeof(target_info)); 3371 ret = ath10k_bmi_get_target_info_sdio(ar, &target_info); 3372 if (ret) { 3373 ath10k_err(ar, "could not get target info (%d)\n", ret); 3374 goto err_power_down; 3375 } 3376 ar->target_version = target_info.version; 3377 ar->hw->wiphy->hw_version = target_info.version; 3378 break; 3379 case ATH10K_BUS_PCI: 3380 case ATH10K_BUS_AHB: 3381 case ATH10K_BUS_USB: 3382 memset(&target_info, 0, sizeof(target_info)); 3383 ret = ath10k_bmi_get_target_info(ar, &target_info); 3384 if (ret) { 3385 ath10k_err(ar, "could not get target info (%d)\n", ret); 3386 goto err_power_down; 3387 } 3388 ar->target_version = target_info.version; 3389 ar->hw->wiphy->hw_version = target_info.version; 3390 break; 3391 case ATH10K_BUS_SNOC: 3392 memset(&target_info, 0, sizeof(target_info)); 3393 ret = ath10k_hif_get_target_info(ar, &target_info); 3394 if (ret) { 3395 ath10k_err(ar, "could not get target info (%d)\n", ret); 3396 goto err_power_down; 3397 } 3398 ar->target_version = target_info.version; 3399 ar->hw->wiphy->hw_version = target_info.version; 3400 break; 3401 default: 3402 ath10k_err(ar, "incorrect hif bus type: %d\n", ar->hif.bus); 3403 } 3404 3405 ret = ath10k_init_hw_params(ar); 3406 if (ret) { 3407 ath10k_err(ar, "could not get hw params (%d)\n", ret); 3408 goto err_power_down; 3409 } 3410 3411 ret = ath10k_core_fetch_firmware_files(ar); 3412 if (ret) { 3413 ath10k_err(ar, "could not fetch firmware files (%d)\n", ret); 3414 goto err_power_down; 3415 } 3416 3417 BUILD_BUG_ON(sizeof(ar->hw->wiphy->fw_version) != 3418 sizeof(ar->normal_mode_fw.fw_file.fw_version)); 3419 memcpy(ar->hw->wiphy->fw_version, ar->normal_mode_fw.fw_file.fw_version, 3420 sizeof(ar->hw->wiphy->fw_version)); 3421 3422 ath10k_debug_print_hwfw_info(ar); 3423 3424 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, 3425 ar->normal_mode_fw.fw_file.fw_features)) { 3426 ret = ath10k_core_pre_cal_download(ar); 3427 if (ret) { 3428 /* pre calibration data download is not necessary 3429 * for all the chipsets. Ignore failures and continue. 3430 */ 3431 ath10k_dbg(ar, ATH10K_DBG_BOOT, 3432 "could not load pre cal data: %d\n", ret); 3433 } 3434 3435 ret = ath10k_core_get_board_id_from_otp(ar); 3436 if (ret && ret != -EOPNOTSUPP) { 3437 ath10k_err(ar, "failed to get board id from otp: %d\n", 3438 ret); 3439 goto err_free_firmware_files; 3440 } 3441 3442 ret = ath10k_core_check_smbios(ar); 3443 if (ret) 3444 ath10k_dbg(ar, ATH10K_DBG_BOOT, "SMBIOS bdf variant name not set.\n"); 3445 3446 ret = ath10k_core_check_dt(ar); 3447 if (ret) 3448 ath10k_dbg(ar, ATH10K_DBG_BOOT, "DT bdf variant name not set.\n"); 3449 3450 ret = ath10k_core_fetch_board_file(ar, ATH10K_BD_IE_BOARD); 3451 if (ret) { 3452 ath10k_err(ar, "failed to fetch board file: %d\n", ret); 3453 goto err_free_firmware_files; 3454 } 3455 3456 ath10k_debug_print_board_info(ar); 3457 } 3458 3459 device_get_mac_address(ar->dev, ar->mac_addr); 3460 3461 ret = ath10k_core_init_firmware_features(ar); 3462 if (ret) { 3463 ath10k_err(ar, "fatal problem with firmware features: %d\n", 3464 ret); 3465 goto err_free_firmware_files; 3466 } 3467 3468 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, 3469 ar->normal_mode_fw.fw_file.fw_features)) { 3470 ret = ath10k_swap_code_seg_init(ar, 3471 &ar->normal_mode_fw.fw_file); 3472 if (ret) { 3473 ath10k_err(ar, "failed to initialize code swap segment: %d\n", 3474 ret); 3475 goto err_free_firmware_files; 3476 } 3477 } 3478 3479 mutex_lock(&ar->conf_mutex); 3480 3481 ret = ath10k_core_start(ar, ATH10K_FIRMWARE_MODE_NORMAL, 3482 &ar->normal_mode_fw); 3483 if (ret) { 3484 ath10k_err(ar, "could not init core (%d)\n", ret); 3485 goto err_unlock; 3486 } 3487 3488 ath10k_debug_print_boot_info(ar); 3489 ath10k_core_stop(ar); 3490 3491 mutex_unlock(&ar->conf_mutex); 3492 3493 ath10k_hif_power_down(ar); 3494 return 0; 3495 3496 err_unlock: 3497 mutex_unlock(&ar->conf_mutex); 3498 3499 err_free_firmware_files: 3500 ath10k_core_free_firmware_files(ar); 3501 3502 err_power_down: 3503 ath10k_hif_power_down(ar); 3504 3505 return ret; 3506 } 3507 3508 static void ath10k_core_register_work(struct work_struct *work) 3509 { 3510 struct ath10k *ar = container_of(work, struct ath10k, register_work); 3511 int status; 3512 3513 /* peer stats are enabled by default */ 3514 set_bit(ATH10K_FLAG_PEER_STATS, &ar->dev_flags); 3515 3516 status = ath10k_core_probe_fw(ar); 3517 if (status) { 3518 ath10k_err(ar, "could not probe fw (%d)\n", status); 3519 goto err; 3520 } 3521 3522 status = ath10k_mac_register(ar); 3523 if (status) { 3524 ath10k_err(ar, "could not register to mac80211 (%d)\n", status); 3525 goto err_release_fw; 3526 } 3527 3528 status = ath10k_coredump_register(ar); 3529 if (status) { 3530 ath10k_err(ar, "unable to register coredump\n"); 3531 goto err_unregister_mac; 3532 } 3533 3534 status = ath10k_debug_register(ar); 3535 if (status) { 3536 ath10k_err(ar, "unable to initialize debugfs\n"); 3537 goto err_unregister_coredump; 3538 } 3539 3540 status = ath10k_spectral_create(ar); 3541 if (status) { 3542 ath10k_err(ar, "failed to initialize spectral\n"); 3543 goto err_debug_destroy; 3544 } 3545 3546 status = ath10k_thermal_register(ar); 3547 if (status) { 3548 ath10k_err(ar, "could not register thermal device: %d\n", 3549 status); 3550 goto err_spectral_destroy; 3551 } 3552 3553 status = ath10k_leds_register(ar); 3554 if (status) { 3555 ath10k_err(ar, "could not register leds: %d\n", 3556 status); 3557 goto err_thermal_unregister; 3558 } 3559 3560 set_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags); 3561 return; 3562 3563 err_thermal_unregister: 3564 ath10k_thermal_unregister(ar); 3565 err_spectral_destroy: 3566 ath10k_spectral_destroy(ar); 3567 err_debug_destroy: 3568 ath10k_debug_destroy(ar); 3569 err_unregister_coredump: 3570 ath10k_coredump_unregister(ar); 3571 err_unregister_mac: 3572 ath10k_mac_unregister(ar); 3573 err_release_fw: 3574 ath10k_core_free_firmware_files(ar); 3575 err: 3576 /* TODO: It's probably a good idea to release device from the driver 3577 * but calling device_release_driver() here will cause a deadlock. 3578 */ 3579 return; 3580 } 3581 3582 int ath10k_core_register(struct ath10k *ar, 3583 const struct ath10k_bus_params *bus_params) 3584 { 3585 ar->bus_param = *bus_params; 3586 3587 queue_work(ar->workqueue, &ar->register_work); 3588 3589 return 0; 3590 } 3591 EXPORT_SYMBOL(ath10k_core_register); 3592 3593 void ath10k_core_unregister(struct ath10k *ar) 3594 { 3595 cancel_work_sync(&ar->register_work); 3596 3597 if (!test_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags)) 3598 return; 3599 3600 ath10k_leds_unregister(ar); 3601 3602 ath10k_thermal_unregister(ar); 3603 /* Stop spectral before unregistering from mac80211 to remove the 3604 * relayfs debugfs file cleanly. Otherwise the parent debugfs tree 3605 * would be already be free'd recursively, leading to a double free. 3606 */ 3607 ath10k_spectral_destroy(ar); 3608 3609 /* We must unregister from mac80211 before we stop HTC and HIF. 3610 * Otherwise we will fail to submit commands to FW and mac80211 will be 3611 * unhappy about callback failures. 3612 */ 3613 ath10k_mac_unregister(ar); 3614 3615 ath10k_testmode_destroy(ar); 3616 3617 ath10k_core_free_firmware_files(ar); 3618 ath10k_core_free_board_files(ar); 3619 3620 ath10k_debug_unregister(ar); 3621 } 3622 EXPORT_SYMBOL(ath10k_core_unregister); 3623 3624 struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev, 3625 enum ath10k_bus bus, 3626 enum ath10k_hw_rev hw_rev, 3627 const struct ath10k_hif_ops *hif_ops) 3628 { 3629 struct ath10k *ar; 3630 int ret; 3631 3632 ar = ath10k_mac_create(priv_size); 3633 if (!ar) 3634 return NULL; 3635 3636 ar->ath_common.priv = ar; 3637 ar->ath_common.hw = ar->hw; 3638 ar->dev = dev; 3639 ar->hw_rev = hw_rev; 3640 ar->hif.ops = hif_ops; 3641 ar->hif.bus = bus; 3642 3643 switch (hw_rev) { 3644 case ATH10K_HW_QCA988X: 3645 case ATH10K_HW_QCA9887: 3646 ar->regs = &qca988x_regs; 3647 ar->hw_ce_regs = &qcax_ce_regs; 3648 ar->hw_values = &qca988x_values; 3649 break; 3650 case ATH10K_HW_QCA6174: 3651 case ATH10K_HW_QCA9377: 3652 ar->regs = &qca6174_regs; 3653 ar->hw_ce_regs = &qcax_ce_regs; 3654 ar->hw_values = &qca6174_values; 3655 break; 3656 case ATH10K_HW_QCA99X0: 3657 case ATH10K_HW_QCA9984: 3658 ar->regs = &qca99x0_regs; 3659 ar->hw_ce_regs = &qcax_ce_regs; 3660 ar->hw_values = &qca99x0_values; 3661 break; 3662 case ATH10K_HW_QCA9888: 3663 ar->regs = &qca99x0_regs; 3664 ar->hw_ce_regs = &qcax_ce_regs; 3665 ar->hw_values = &qca9888_values; 3666 break; 3667 case ATH10K_HW_QCA4019: 3668 ar->regs = &qca4019_regs; 3669 ar->hw_ce_regs = &qcax_ce_regs; 3670 ar->hw_values = &qca4019_values; 3671 break; 3672 case ATH10K_HW_WCN3990: 3673 ar->regs = &wcn3990_regs; 3674 ar->hw_ce_regs = &wcn3990_ce_regs; 3675 ar->hw_values = &wcn3990_values; 3676 break; 3677 default: 3678 ath10k_err(ar, "unsupported core hardware revision %d\n", 3679 hw_rev); 3680 ret = -EOPNOTSUPP; 3681 goto err_free_mac; 3682 } 3683 3684 init_completion(&ar->scan.started); 3685 init_completion(&ar->scan.completed); 3686 init_completion(&ar->scan.on_channel); 3687 init_completion(&ar->target_suspend); 3688 init_completion(&ar->driver_recovery); 3689 init_completion(&ar->wow.wakeup_completed); 3690 3691 init_completion(&ar->install_key_done); 3692 init_completion(&ar->vdev_setup_done); 3693 init_completion(&ar->vdev_delete_done); 3694 init_completion(&ar->thermal.wmi_sync); 3695 init_completion(&ar->bss_survey_done); 3696 init_completion(&ar->peer_delete_done); 3697 init_completion(&ar->peer_stats_info_complete); 3698 3699 INIT_DELAYED_WORK(&ar->scan.timeout, ath10k_scan_timeout_work); 3700 3701 ar->workqueue = create_singlethread_workqueue("ath10k_wq"); 3702 if (!ar->workqueue) 3703 goto err_free_mac; 3704 3705 ar->workqueue_aux = create_singlethread_workqueue("ath10k_aux_wq"); 3706 if (!ar->workqueue_aux) 3707 goto err_free_wq; 3708 3709 ar->workqueue_tx_complete = 3710 create_singlethread_workqueue("ath10k_tx_complete_wq"); 3711 if (!ar->workqueue_tx_complete) 3712 goto err_free_aux_wq; 3713 3714 mutex_init(&ar->conf_mutex); 3715 mutex_init(&ar->dump_mutex); 3716 spin_lock_init(&ar->data_lock); 3717 3718 for (int ac = 0; ac < IEEE80211_NUM_ACS; ac++) 3719 spin_lock_init(&ar->queue_lock[ac]); 3720 3721 INIT_LIST_HEAD(&ar->peers); 3722 init_waitqueue_head(&ar->peer_mapping_wq); 3723 init_waitqueue_head(&ar->htt.empty_tx_wq); 3724 init_waitqueue_head(&ar->wmi.tx_credits_wq); 3725 3726 skb_queue_head_init(&ar->htt.rx_indication_head); 3727 3728 init_completion(&ar->offchan_tx_completed); 3729 INIT_WORK(&ar->offchan_tx_work, ath10k_offchan_tx_work); 3730 skb_queue_head_init(&ar->offchan_tx_queue); 3731 3732 INIT_WORK(&ar->wmi_mgmt_tx_work, ath10k_mgmt_over_wmi_tx_work); 3733 skb_queue_head_init(&ar->wmi_mgmt_tx_queue); 3734 3735 INIT_WORK(&ar->register_work, ath10k_core_register_work); 3736 INIT_WORK(&ar->restart_work, ath10k_core_restart); 3737 INIT_WORK(&ar->set_coverage_class_work, 3738 ath10k_core_set_coverage_class_work); 3739 3740 ar->napi_dev = alloc_netdev_dummy(0); 3741 if (!ar->napi_dev) 3742 goto err_free_tx_complete; 3743 3744 ret = ath10k_coredump_create(ar); 3745 if (ret) 3746 goto err_free_netdev; 3747 3748 ret = ath10k_debug_create(ar); 3749 if (ret) 3750 goto err_free_coredump; 3751 3752 return ar; 3753 3754 err_free_coredump: 3755 ath10k_coredump_destroy(ar); 3756 err_free_netdev: 3757 free_netdev(ar->napi_dev); 3758 err_free_tx_complete: 3759 destroy_workqueue(ar->workqueue_tx_complete); 3760 err_free_aux_wq: 3761 destroy_workqueue(ar->workqueue_aux); 3762 err_free_wq: 3763 destroy_workqueue(ar->workqueue); 3764 err_free_mac: 3765 ath10k_mac_destroy(ar); 3766 3767 return NULL; 3768 } 3769 EXPORT_SYMBOL(ath10k_core_create); 3770 3771 void ath10k_core_destroy(struct ath10k *ar) 3772 { 3773 destroy_workqueue(ar->workqueue); 3774 3775 destroy_workqueue(ar->workqueue_aux); 3776 3777 destroy_workqueue(ar->workqueue_tx_complete); 3778 3779 free_netdev(ar->napi_dev); 3780 ath10k_debug_destroy(ar); 3781 ath10k_coredump_destroy(ar); 3782 ath10k_htt_tx_destroy(&ar->htt); 3783 ath10k_wmi_free_host_mem(ar); 3784 ath10k_mac_destroy(ar); 3785 } 3786 EXPORT_SYMBOL(ath10k_core_destroy); 3787 3788 MODULE_AUTHOR("Qualcomm Atheros"); 3789 MODULE_DESCRIPTION("Core module for Qualcomm Atheros 802.11ac wireless LAN cards."); 3790 MODULE_LICENSE("Dual BSD/GPL"); 3791